Apparatus including plurality of integrated circuits and methods of assembling and packaging integrated circuits

Abstract

The invention relates to an apparatus including a plurality of integrated circuits and methods of assembling and packaging integrated circuits. A first layer of a resin compatible with direct laser structuring (LDS) is formed on the substrate and encapsulates the first integrated circuit. The substrate includes a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal covered by the first layer. A first via is formed using LDS, the first via passing through the first layer and forming an electrical connection with the second connection terminal. A second integrated circuit is mounted over the first integrated circuit. A second layer of a resin compatible with the LDS is formed to encapsulate a second integrated circuit. A second via is formed using LDS, the second via passing through the second layer and forming an electrical connection with the first via.

Description

[0001] Priority Claim

[0002] This application claims the priority benefit of a French application with patent number No. 2400206 filed on January 10, 2024, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure generally relates to devices including multiple integrated circuits and methods of manufacturing such devices. Background Art

[0004] In microelectronics, the trend is towards miniaturization in order to consume less raw material and reduce production costs, or to be able to add new functionality to a product without increasing its size. Keeping this in mind, it is advantageous to stack integrated circuits on the same substrate so that they take up less space. The electrical connections between the first integrated circuits mounted on the substrate can be formed by direct connections between metal pads, and wire bonding provides a solution for forming electrical connections between second integrated circuits mounted on the first integrated circuits. However, using wires requires significant space around the integrated circuits to be connected.

[0005] Therefore, there is a need for a method of assembling multiple circuits stacked on top of each other on the same substrate, which enables the dimensions of the final device to be reduced. Summary of the Invention

[0006] Embodiments provide a method that includes: forming a first layer of resin compatible with direct laser structuring (LDS) on a substrate, wherein a first integrated circuit mounted on the substrate is incorporated (e.g., encapsulated) in the first layer, the substrate including a first connection terminal coupled to the first integrated circuit and a second connection terminal coupled to the first connection terminal and covered by the first layer; forming a first via hole by LDS, the first via hole passing through the first layer and making electrical contact with the second connection terminal; mounting a second integrated circuit on the first integrated circuit; forming a second layer of resin compatible with LDS on the substrate, wherein the second integrated circuit is incorporated (e.g., encapsulated) in the second layer; and forming a second via hole by LDS, the second via hole passing through the second layer and making electrical contact with the first via hole.

[0007] According to an embodiment, forming the first layer includes depositing an initial resin layer and thinning the initial resin layer to obtain the first layer.

[0008] According to an embodiment, forming the second layer includes depositing an initial resin layer and thinning the initial resin layer to obtain the second layer.

[0009] According to an embodiment, the method further includes adding a device on the second layer, the device being coupled to the second via.

[0010] According to an embodiment, the method further includes depositing a third layer made of resin on the second layer.

[0011] According to an embodiment, the first integrated circuit and the second integrated circuit each have a first surface and a second surface opposite the first surface, the first surface including a metallization portion including one or more connection terminals, and the first integrated circuit and the second integrated circuit are mounted in such a manner that their second surfaces face each other.

[0012] According to an embodiment, the via is formed by autocatalytic growth or electroless plating.

[0013] According to an embodiment, the second via is laterally offset with respect to the first via.

[0014] According to an embodiment, the height of the first layer is at least equal to the distance separating the second connection terminal from the upper surface of the first integrated circuit.

[0015] According to an embodiment, the height of the second layer is at least equal to the distance separating the first via from the upper surface of the second integrated circuit.

[0016] Another embodiment provides a microelectronic device, comprising: a substrate; a first integrated circuit mounted on the substrate; a first layer of resin, compatible with direct laser structuring (LDS), deposited on the substrate and in which the first integrated circuit is incorporated (e.g., encapsulated); in the substrate, a first connection terminal coupled to the first integrated circuit and a second connection terminal coupled to the first connection terminal and covered by the first layer; a first via formed by LDS, the first via passing through the first layer and making electrical contact with the second connection terminal; a second integrated circuit mounted on the first integrated circuit; a second layer of resin compatible with LDS, the second integrated circuit being incorporated (e.g., encapsulated) in the second layer; and a second via formed by LDS, the second via passing through the second layer and making electrical contact with the first via. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features and advantages, as well as others, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, in the accompanying drawings in which:

[0018] Figure 1 is a cross-sectional view of a device including two integrated circuits connected to each other and to the same substrate according to an embodiment of the present disclosure;

[0019] Figures 2A to 2I is a method of manufacturing according to an embodiment of the present disclosure Figure 1 successive steps of a cross-sectional view of the method of the device;

[0020] Figure 3A and Figure 3B are cross-sectional views of successive steps of a method of manufacturing a device that can be applied to Figure 1 ; and

[0021] Figure 4A and Figure 4B are partial cross-sectional views showing successive steps of a panel-embedded packaging (PEP) method of an integrated circuit. DETAILED DESCRIPTION

[0022] Like features are denoted by like reference numerals in the various figures. In particular, structural and / or functional features common to the various embodiments may have the same reference numeral and may have the same structure, dimensions, and material properties deployed.

[0023] For clarity, only the steps and elements useful for understanding the embodiments are shown and described in detail. In particular, the steps of manufacturing the laminated substrate and the integrated circuit are common and not described in detail.

[0024] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection with no intervening elements other than conductors, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements.

[0025] In the following description, when referring to absolute position qualifiers such as "front", "rear", "top", "bottom", "left", "right", etc. or relative position qualifiers such as "top", "bottom", "upper", "lower", etc. or orientation qualifiers such as "horizontal", "vertical", etc., unless otherwise stated, the orientation of the drawings is referred to.

[0026] Unless otherwise stated, the expressions "about", "approximate", "substantially", and "around" mean plus or minus 10%, preferably plus or minus 5%.

[0027] Figure 1 is a cross-sectional view of a device 100 according to an embodiment of the present disclosure, the device 100 including two integrated circuits 101, 102 that are connected to each other and connected to the same substrate 104.

[0028] In Figure 1In the example, two integrated circuits 101 and 102 are stacked and mounted on each other through a bonding layer 126 and encapsulated in a resin 106. The integrated circuit 101 is mounted on a substrate 104 through a dielectric layer 105, for example. The integrated circuits 101 and 102 are electrically connected to each other and to the substrate 104 through a set of vias 112, 117, 118, 112', 117', 118' formed in the resin 106, the substrate 104, and / or the dielectric layer 105, and a set of metal traces 114, 119, 124, 114', 119', 124'.

[0029] The substrate 104 and the dielectric layer 105 are made of, for example, Ajinomoto Build-up Film (ABF) or are made of a polymer, for example. The substrate 104 has a thickness of at least 50 μm, for example. The dielectric layer 105 has a thickness of at least 10 μm, for example.

[0030] Each of the integrated circuits 101 and 102 has a metallization portion that includes one or more connection terminals 123, 130, 123', 130' on the first surface of each of the integrated circuits 101, 102, and does not have a metallization portion or connection terminals on the second surface opposite the first surface, for example. The second integrated circuit 102 is mounted on the first integrated circuit 101 such that the second surfaces of the integrated circuits 101 and 102 face each other and the connection terminals present on their first surfaces remain accessible.

[0031] The connection terminals 123 of the integrated circuit 101 are located on its lower surface, for example, and are connected to the connection terminals 125 on the upper surface of the substrate 104 through one or more metal traces 124. The metal traces 124 are made of, for example, copper, gold, tin, silver, or an alloy of multiple materials among these materials.

[0032] In some embodiments, the connection terminals 123 and 125 are also connected to the connection terminals 128 through the metal traces 124, thereby enabling the device 100 to be coupled to an external electronic device (not shown). The connection terminals 128 are present on the lower surface of the substrate 104, for example.

[0033] The connection terminals 130 of the integrated circuit 102 are located on its upper surface, for example. The connection terminals 125 and 130 are connected to each other through the via 112 and the via 118. In Figure 1 the example, the via 112 has a height of at least equal to the sum of the height of the first integrated circuit 101 and the height of the dielectric layer 105. In general, the via 112 has a height of at least equal to the distance separating the connection terminals 125 from the upper surface of the integrated circuit 101. In Figure 1In the example shown, the height of the through - hole 118 is at least equal to the sum of the height of the second integrated circuit 102 and the height of the bonding layer 126. In general, the through - hole 118 has a height that is at least equal to the distance separating the through - hole 112 from the upper surface of the integrated circuit 102.

[0034] According to an embodiment, the through - holes 112 and 118 are laterally offset, i.e., they are offset from each other by a distance δ in a direction parallel to the plane of the substrate 104. The through - holes 112 and 118 are connected to each other, for example, by metal tracks 114.

[0035] The through - hole 117 is connected on the one hand to the connection terminal 130 of the integrated circuit 102 and on the other hand to the through - hole 118 via one or more metal tracks 119.

[0036] The resin 106 for encapsulating the integrated circuit 101 is, for example, a specific resin compatible with direct laser structuring (LDS), which is manifested in that the resin includes additives or particulate matter that can be activated by laser treatment at the positions of the desired through - holes and tracks. The thickness of the resin layer 106 is, for example, at least equal to the sum of the heights of the through - holes 112 and 118. In Figure 1 the example, the thickness of the resin layer 106 is sufficient to cover the metal track 119.

[0037] In Figure 1 the example, a second set of connection terminals 123', 125', 128' and 130' and a second set of through - holes 112', 117', 118' and metal tracks 114', 119', 124' are shown, and similar to those described above, they will not be described in detail. In other embodiments, one or more than two sets of connection terminals, through - holes and metal tracks may be provided.

[0038] Figures 2A to 2I is a cross - sectional view of successive steps of a method for manufacturing Figure 1 the device 100 according to an embodiment of the present disclosure.

[0039] Figures 2A to 2I certain elements of Figure 1 are the same as the elements of

[0040] In the following description of Figures 2A to 2I only the formation of the metal tracks 114 and 119 and the through - holes 112, 117 and 118 will be described. For example, the same steps are used to form the metal tracks 114' and 119' and the through - holes 112', 117' and 118'.

[0041] Figure 2A shows an example of the device 200, providing a starting point for the method of manufacturing Figure 1 the device 100 ofFigure 1 Compared with the device 100, the device 200 also does not include the second integrated circuit 102 or the vias 112, 118 for connecting the circuits 101 and 102 to each other and to the substrate 104.

[0042] Figure 2A The device 200 is, for example, obtained according to the manufacturing steps of the panel embedded packaging (PEP) method detailed in Figure 4A and Figure 4B and

[0043] In the example of Figure 2A the device 200 includes a first integrated circuit 101 encapsulated in a resin layer 106A, and the first integrated circuit 101 is face-down so that the connection terminals 123, 123' on the front face face and are connected to the substrate 104. The height h1 of the resin layer 106A is, for example, sufficient to cover the integrated circuit 101 and the connection terminals 125.

[0044] Figure 2B Shows the Figure 2A device after an optional step of thinning the resin layer 106A. According to an embodiment, the thickness of the resin layer is reduced to expose the back surface of the integrated circuit 101. For example, this step is useful when it is expected to bond the second integrated circuit 102 to the first integrated circuit 101.

[0045] In Figure 2B the example of

[0046] the final height h1' of the resin layer 106A' is at least equal to the sum of the height d1 of the first integrated circuit 101 and the height d5 of the dielectric layer 105. In general, the height h1' is, for example, at least equal to the distance separating the connection terminals 125 from the upper surface of the integrated circuit 101. Figures 2C to 2I In the following description of Figure 2B it is considered that these steps are applicable to the device obtained at the step of Figure 2B However, in the case of omitting the step of Figures 2C to 2I those skilled in the art will know how to adjust the steps in

[0047] Figure 2C Shows the Figure 2B device after a laser ablation (or drilling) step. The resin layer 106A' is perforated by a laser beam to partially expose the connection terminals 125 present on the surface of the substrate 104. The perforations 110 performed correspond to the positions of the future metal vias.

[0048] During the laser ablation step, the laser beam used to perforate the resin 106A' interacts with the LDS additive present in the resin 106A' and locally activates the periphery of the perforations 110.

[0049] In addition, during this step, for example, the upper surface of the resin 106A', i.e., the surface farthest from the substrate 104, at the position where the metal tracks 114 are to be formed in the future, is irradiated with a laser beam to locally activate them.

[0050] Figure 2D Illustrated is, for example, the Figure 2C apparatus after the autocatalytic growth or electroless plating step. During this method, metal is deposited on the surface of the resin 106A' previously activated by the laser beam without using an electric current. The activation of the resin by the laser beam creates seeds at the positions where the resin surface is irradiated. For example, the vias 112 are created in the Figure 2C perforations 110 starting from the exposed connection terminals 125 and the periphery of the previously activated perforations 110. The metal tracks 114 are created, for example, on the previously activated portions of the surface of the resin 106A'.

[0051] Although Figure 2D illustrates an example of electroless plating to form the metal tracks 114 and the vias 112, an electroplating method can also be used. In this case, for example, temporary metal tracks (not shown) are created on the surface of the resin layer 106A' to allow the current for this electroplating to flow.

[0052] The vias 112 are made of, for example, copper, gold, tin, silver, or an alloy of multiple of these materials.

[0053] As described above in connection with Figure 2C and Figure 2D the steps correspond to an embodiment of the LDS method.

[0054] Figure 2E Illustrated is the Figure 2D apparatus after the second integrated circuit 102 is bonded to the first integrated circuit 101. As described with respect to Figure 1 , each of the integrated circuits 101 and 102 includes a first surface (or front side) and a second surface (or back side) opposite to the first surface. The first surface (or front side) includes a metallization portion containing one or more connection terminals, and the second surface (or back side) does not include, for example, a metallization portion or connection terminals. The second integrated circuit 102 is bonded, for example, such that the second surfaces of the two integrated circuits 101 and 102 are in contact, and the connection terminals of the second integrated circuit are located on its upper surface such that the connection terminals remain accessible after bonding. The two integrated circuits are bonded, for example, by using an epoxy-based glue that polymerizes during a heating step.

[0055] According to an embodiment, in the case where the thinning step of Figure 2B is omitted or a partial thinning is performed, there is a resin layer between the integrated circuits 101 and 102.

[0056] Figure 2F illustrates the device after the deposition of the second layer 106B of LDS-compatible resin Figure 2E .

[0057] The deposition of the resin layer 106B is performed, for example, by compression molding, and the resin is deposited, for example, Figure 2E on the surface of the device and pressed into the mold.

[0058] The thickness h2 of the layer 106B is, for example, at least equal to the height of the future through-hole 118, that is, for example, at least sufficient to cover the integrated circuit 102.

[0059] Figure 2G illustrates the device after an optional step of thinning the resin layer 106B Figure 2F .

[0060] Regarding the height h2, in the example shown in Figure 2G , the final height h2' of the resin layer 106B' is at least equal to the sum of the height d2 of the second integrated circuit 102 and the height d26 of the bonding layer 126. In general, the height h2' is, for example, greater than the distance separating the through-hole 112 from the upper surface of the integrated circuit 102 to cover the integrated circuit 102.

[0061] In the following description of Figures 2H to 2I , it is considered that these steps are applicable to the device obtained at the step of Figure 2G . However, in the case where the step of Figure 2G is omitted, those skilled in the art will know clearly how to adjust the steps in Figures 2H to 2I .

[0062] Figure 2H illustrates the device after the laser ablation (or drilling) step Figure 2G . The resin layer 106B is perforated by a laser beam to form perforations 116 and, for example, perforation 115, which corresponds to the position of the future through-hole. The perforation 116 exposes at least a part of the metal track 114, which is coupled to at least one connection terminal 123 of the integrated circuit 101 and at least one connection terminal 128 of the substrate 104. The perforation 115 exposes, for example, the connection terminal 130 of the integrated circuit 102.

[0063] After the laser ablation step, the peripheries of the perforations 115, 116 are activated.

[0064] In addition, during this step, the positions on the upper surface of the resin 106B' where the metal tracks 119 will be formed in the future are, for example, illuminated by a laser beam to locally activate them.

[0065] Figure 2I illustrates, for example, the device after the autocatalytic growth step Figure 2Hdevice. During this method, through-holes 118 are created in the perforations 116 of Figure 2H , starting from the exposed part of the metal track 114 and from the previously activated periphery of the perforation 116. For example, in Figure 2H , through-holes 117 are created in the perforations 115, starting from the exposed connection terminals of the integrated circuit 102 and from the previously activated periphery of the perforation 115. For example, on the surface of the resin 106B, metal tracks 119 are created on the previously activated parts. For example, the through-holes 118, 117 and the tracks 119 are made of copper, gold, tin, silver or alloys of several of these materials.

[0066] The above steps related to Figure 2H and Figure 2I correspond to the implementation of the LDS method. The LDS method is only possible on compatible resin layers.

[0067] According to an embodiment, the through-holes formed by autocatalytic growth in steps 2C and 2H are created by forming a metal layer on the walls of the perforations 110, 116, 115. The through-holes 112, 118, 117 created in this way form, for example, cones that are partially filled in their centers. The through-holes 112 and 118 are, for example, offset from each other by a distance δ and are connected by the metal track 114 to ensure a good connection.

[0068] Although Figure 2I shows an example of electroless plating to form the metal track 119 and the through-hole 114, an electroplating method can also be used. In this case, for example, temporary metal tracks (not shown) are created on the surface of the resin layer 106B' to allow the current for obtaining this electroplating to flow.

[0069] After the step of depositing a third resin layer (not shown) on the surface of the Figure 2I device, the Figure 1 device 100 is obtained. The assembly formed by the resin layers 106A', 106B' and the third resin layer corresponds to the Figure 1 resin layer 106.

[0070] Figure 3A and Figure 3B are cross-sectional views of successive steps of a manufacturing method that can be applied to the Figure 1 device.

[0071] Figure 3A and Figure 3B certain elements of Figure 1 and / or Figures 2A to 2I are the same as the elements of

[0072] Figure 3Ashown after an optional step of connecting a surface mount device (SMD) 120 to metal tracks 119 and 119' Figure 2I of the device. According to an embodiment, the surface mount component 120 is added to, for example, Figure 1 the device 100 and integrated during the encapsulation method. The component 120 is, for example, soldered or bonded with a conductive adhesive between the tracks 119 and 119'.

[0073] Figure 3B shown after an optional step of depositing a resin layer 106C to encapsulate the component 120 Figure 3A of the device. For example, a resin incompatible with LDS is used for this layer. The height of the resin layer 106C is, for example, at least as high as the component 120, and, for example, higher than the component 120 to cover the component 120 in order to protect the component 120 and insulate it.

[0074] According to Figure 3B an alternative embodiment of the embodiment shown in, for example, a series of layers is deposited on the surface of the metal track 119 by electroplating, for example including a nickel layer and / or a gold layer, to make it corrosion resistant, and the resin layer 106C is not deposited.

[0075] In Figure 1 , Figures 2A to 2I and Figure 3A and Figure 3B example, a dielectric layer 105 is present between the substrate 104 and the chip 101. However, in other embodiments, the layer 105 is omitted and the integrated circuit 101 is directly mounted on the substrate 104. Those skilled in the art will be clear on how to adjust these processes.

[0076] During the method thus described, two series of vias 112 and 118 are successively created. The advantage of creating these two series of vias instead of a single via is that the height of each via is reduced, thus making the final device more compact. In fact, the aspect ratio of the via is generally limited. For example, in the case of a via formed by LDS, the aspect ratio is limited to 1:1, that is, the height cannot exceed the diameter of the via. Therefore, creating two successive vias occupies less surface area than creating a single taller and thus wider via. For example, when it is desired to form a 300 μm high via, if the aspect ratio is limited to 1, then two vias with a height of 150 μm and a maximum diameter of 150 μm may be created, one on top of the other, with a total height of 300 μm and a maximum diameter of 150 μm. In contrast, a single 300 μm high via would require a 300 μm maximum diameter. Thus, the surface area required for the vias is effectively reduced.

[0077] Figure 4A and Figure 4BA partial cross-sectional view showing successive steps of a panel-embedded packaging (PEP) method for an integrated circuit 101 is presented.

[0078] Figure 4A and Figure 4B The components of Figure 1 and / or Figures 2A to 2I and / or Figures 3A to 3B are the same as those of

[0079] The PEP packaging process is used, for example, to obtain Figure 2A the device 200 of

[0080] In step A, a substrate (e.g., a wafer 301 of semiconductor material (e.g., silicon)) including an integrated circuit (not shown at step A) is covered with a dielectric layer 105. The dielectric layer 105 is, for example, an ABF or a polymer film.

[0081] In step B, after depositing the dielectric layer 105, layer 105 is locally opened, for example, by laser and / or plasma etching to create vias, for example, at the positions of the connection terminals 123 of the integrated circuit 101 of Figure 1 , Figures 2A to 2I and Figures 3A to 3B present on the wafer 301. The vias will be used to form conductive through-holes.

[0082] In step C, the wafer 301 of step B is then ground, for example, to remove the substrate thickness that is useless for the operation of the integrated circuit, and cut to separate the integrated circuit 101 into individual electronic chips.

[0083] In step D, after step C, the electronic chips are flipped and repositioned on a support plate made of, for example, stainless steel such that the dielectric layer 105 is bonded to the plate by a temporary bonding film 302.

[0084] In step E, after step D, the chips are separated, for example, with a sufficient spacing between the chips to create, for example, the future through-holes 112 in Figure 2D . The support plate is, for example, rectangular and, for example, larger than the silicon wafer, for example, 700 mm × 700 mm. A resin layer 106A is deposited to encapsulate the chips.

[0085] In step F, after depositing the resin layer 106A, it is thinned, for example, by abrasive polishing.

[0086] In step G, after step F, the chips encapsulated in the resin 106A are separated from the support plate, flipped to expose the dielectric layer 105, and its opposite surface is bonded to the support plate by a temporary bonding film 304. For example, an automatic optical inspection (AOI) is performed to detect defects on the chips.

[0087] In step H following step G, metal particles 306 such as copper and titanium are deposited on the surface of the encapsulated chip. These particles will serve as seeds for subsequent autocatalytic or electrocatalytic growth steps.

[0088] In step I, after depositing the metal particles 306, a photoresist layer 308 is deposited, for example.

[0089] In step J, after depositing layer 308, it is exposed and developed by laser direct imaging (LDI) to create openings in the dielectric layer. Using a laser instead of a mask for this lithography step allows adjustment of the illumination pattern of the dielectric layer. The position of the electronic chip on the support plate can vary from plate to plate, and LDI imaging enables adaptation to these variations.

[0090] In step K, after forming the openings, metal vias and tracks 124 are formed, for example, by electroplating.

[0091] In step L, after forming the metal tracks 124, a photoresist layer 310 is deposited, for example.

[0092] In step M, layer 310 is exposed by LDI and developed to create openings in the photoresist layer 310.

[0093] In step N following step M, metal tracks 128 made of, for example, copper are created on the metal tracks deposited at step K, for example, by electroplating according to the openings in layer 310. The tracks 128 form connection terminals, for example.

[0094] In step O following step N, layers 308 and 310 and the precursor particles 306 remaining below layers 308 and 310 are removed, for example, by etching.

[0095] In step P, after the etching step, a dielectric layer 104 is deposited to encapsulate the metal tracks and vias.

[0096] In step Q, after depositing the dielectric layer 104, it is thinned, for example, to expose the metal tracks 328, and successive layers, for example, including a nickel layer and / or a gold layer, are deposited, for example, by electroplating at the surface of the metal tracks 328 to make them corrosion-resistant. The structure including the two integrated circuits 101 is separated from the support plate.

[0097] By the combination Figure 4A and Figure 4B The method described by steps A to Q described in detail, for example, is used to encapsulate the integrated circuit 101 and obtain Figure 2A device 200. Then, the resin used to coat the integrated circuit is, for example, a specific resin compatible with LDS. In Figure 4A and Figure 4BIn the example, a structure including two integrated circuits 101 is formed. In other embodiments, a structure including one or more than two integrated circuits 101 arranged side by side can be formed by the same method. In combination with Figures 2A to 2I The described method is applied, for example, simultaneously to all the integrated circuits 101, and a plurality of individual devices 100 are obtained by separating the structure, for example, by laser cutting or mechanical sawing.

[0098] As a variant, after step Q, in step R, the electronic chip is separated into individual electronic chips, for example, by laser cutting or mechanical sawing. In this case, the method described with respect to Figures 2A to 2I is applied separately to each electronic chip.

[0099] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants can be combined, and other variants will occur to those skilled in the art. In particular, Figures 2A to 2I The method described in is illustrated for a single device 100, but the method can be performed simultaneously for a plurality of devices that are bonded to a common substrate and separated at the end of the method. The method has been detailed for two integrated circuits 101 and 102, but can be extended to a stack of at least three integrated circuits, in which case, for example, a set of vias is formed for each integrated circuit. Additionally, although the example of forming Figure 4A and Figure 4B the device 200 has been detailed in connection with the method of Figure 2A other methods can be used to obtain this device.

Claims

1. A method, comprising: forming a first layer of resin compatible with laser direct structuring (LDS) on a substrate, wherein a first integrated circuit is mounted on the substrate and incorporated in the first layer, the substrate including a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal electrically coupled to the first connection terminal and covered by the first layer; forming a first via hole by LDS processing, the first via hole passing through the first layer and forming an electrical coupling with the second connection terminal; mounting a second integrated circuit above the first integrated circuit; forming a second layer of resin compatible with LDS on the first layer, wherein the second integrated circuit is incorporated in the second layer; and forming a second via hole by LDS processing, the second via hole passing through the second layer and forming an electrical coupling with the first via hole.

2. The method according to claim 1, wherein, Forming the first layer includes depositing an initial resin layer having a first thickness and thinning the initial resin layer to obtain a first layer having a second thickness less than the first thickness.

3. The method according to claim 2, wherein Forming the second layer includes depositing an additional initial resin layer having a third thickness and thinning the additional initial resin layer to obtain a second layer having a fourth thickness less than the third thickness.

4. The method according to claim 1, further comprising adding a device on top of the upper surface of the second layer, wherein the device is electrically coupled to the second via hole.

5. The method according to claim 1, further comprising depositing a third layer made of resin on the second layer.

6. The method according to claim 1, wherein The first integrated circuit and the second integrated circuit each have a first surface and a second surface opposite the first surface, the first surface including a metallization portion comprising one or more connection terminals, and wherein the first integrated circuit and the second integrated circuit are mounted in such a way that their second surfaces face each other.

7. The method according to claim 1, wherein The first via hole and the second via hole are formed by one of autocatalytic growth or electroless plating in the LDS processing.

8. The method according to claim 1, wherein, The second via hole is laterally offset with respect to the first via hole and connected to each other by a conductive track.

9. The method according to claim 1, wherein The height of the first layer is at least equal to the distance separating the second connection terminal from the upper surface of the first integrated circuit.

10. The method according to claim 1, wherein, The height of the second layer is at least equal to the distance separating the first via hole from the upper surface of the second integrated circuit.

11. A microelectronic device, comprising: a substrate including a first connection terminal and a second connection terminal electrically coupled to the first connection terminal; a first integrated circuit mounted on the substrate and electrically coupled to the first connection terminal; a first layer of resin compatible with direct laser structuring (LDS) on the substrate, wherein the first integrated circuit is incorporated into the first layer and the first layer covers the second connection terminal; a first LDS via hole passing through the first layer and electrically coupled to the second connection terminal; a second integrated circuit mounted above the first integrated circuit; a second layer of resin compatible with LDS on the first layer, wherein the second integrated circuit is incorporated in the second layer; and a second LDS via hole passing through the second layer and electrically coupled to the first LDS via hole.

12. The device according to claim 11, further comprising an LDS metal track electrically coupling the second LDS via hole to the second integrated circuit.

13. The device according to claim 11, wherein, The second LDS via hole is laterally offset with respect to the first LDS via hole and connected thereto by an LDS metal track.

14. The device according to claim 11, wherein, The first integrated circuit and the second integrated circuit each have a first surface and a second surface opposite the first surface, the first surface including a metallization portion containing one or more connection terminals, and wherein the first integrated circuit and the second integrated circuit are mounted in such a manner that their second surfaces face each other.

15. The apparatus according to claim 11, further comprising an apparatus on the second layer, wherein the apparatus is electrically coupled to the second via.

16. The apparatus according to claim 11, further comprising a third layer made of resin, the third layer being on the second layer and covering the second LDS via.

Images