A packaging structure and forming method

Abstract

The present disclosure provides a packaging structure and a method for forming the same, wherein the packaging structure comprises: a plurality of first chips, a plurality of microfluidic chips, a plurality of first connecting structures, a plurality of glass flow channels, and a plurality of second chips; wherein the plurality of first chips are stacked layer by layer; in the stacking direction of the plurality of first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is disposed between every two adjacent first chips; the plurality of glass flow channels and the plurality of second chips are disposed around the sidewalls of the plurality of first chips; each glass flow channel is bonded to the sidewalls of the plurality of first chips and communicates with the plurality of microfluidic chips; each second chip is bonded to a corresponding glass flow channel; the first end of each connecting structure is bonded to the first chip located on top; and the second end of each first connecting structure is bonded to a corresponding second chip. Thus, the integration of the packaging structure can be further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] As modern electronic systems place increasing demands on chip performance, 2.5D packaging technology and 3D packaging technology have achieved high-bandwidth, low-latency communication and three-dimensional, high-density integration through interposer interconnection and through-silicon via (TSV) vertical stacking, respectively, promoting the development of high-performance computing and miniaturized devices.

[0003] However, current technology still faces core challenges such as insufficient integration, limited integration of heterogeneous modules, inflexible adaptability across application scenarios, and difficulty in meeting ultra-thin packaging requirements, which restrict its comprehensive application expansion in the diversified electronic ecosystem. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a packaging structure and a forming method to improve integration.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] An embodiment of the present disclosure provides a packaging structure, which includes: multiple first chips, multiple microfluidic chips, multiple first connecting structures, multiple glass flow channels and multiple second chips; wherein, the multiple first chips are stacked layer by layer; in the stacking direction of the multiple first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is arranged between every two adjacent first chips; the multiple glass flow channels and the multiple second chips are all arranged around the side walls of the multiple first chips; each of the glass flow channels is bonded to the side walls of the multiple first chips and is connected to the multiple microfluidic chips; each of the second chips is bonded to a corresponding one of the glass flow channels; the first end of each of the connecting structures is bonded to the first chip located at the top; the second end of each of the first connecting structures is bonded to a corresponding one of the second chips.

[0007] In the above scheme, the bonding structure of every two adjacent first chips includes: a first conductive plug, a second conductive plug and a first metal interconnection point; wherein, in the stacking direction, the microfluidic chip is bonded to the first surface of the two adjacent first chips respectively; the first metal interconnection point is arranged on the second surface of the two adjacent first chips; the first conductive plug or the second conductive plug passes through one of the two adjacent first chips, as well as the microfluidic chip between the two adjacent first chips; one of the first chips between every two adjacent first chips is connected to the first metal interconnection point through the first conductive plug; the other first chip between every two adjacent first chips is connected to the first metal interconnection point through the second conductive plug.

[0008] In the above scheme, the bonding structure of every two adjacent first chips includes: a third conductive plug, a fourth conductive plug and a second metal interconnection point; in the stacking direction, the third conductive plug or the fourth conductive plug passes through the microfluidic chip between the two adjacent first chips; the second metal interconnection point is located between the two adjacent first chips; one of the first chips in every two adjacent first chips is connected to the second metal interconnection point through the third conductive plug; the other first chip in every two adjacent first chips is connected to the second metal interconnection point through the fourth conductive plug.

[0009] In the above solution, each of the microfluidic chips includes: a plurality of cooling medium flow channels; and a conductive plug between every two adjacent first chips, penetrating the microfluidic chip at the protrusion between the two adjacent cooling medium flow channels.

[0010] In the above scheme, each of the glass flow channels includes: multiple first cooling medium flow channels and multiple second cooling medium flow channels; wherein, the multiple first cooling medium flow channels and the multiple second cooling medium flow channels all extend along the stacking direction; the lengths of the multiple first cooling medium flow channels in the stacking direction are all greater than the lengths of the multiple second cooling medium flow channels; the multiple first cooling medium flow channels and the multiple second cooling medium flow channels are alternately arranged in the first direction; the first direction is perpendicular to the stacking direction; the first direction is parallel to one of the side walls of the multiple first chips.

[0011] In the above solution, one or more of the plurality of first chips are cut into a plurality of third chips.

[0012] In the above solution, the packaging structure further includes: a plurality of third chips; wherein, in the stacking direction, the first chip located at the top is bonded to the plurality of third chips respectively.

[0013] An embodiment of the present disclosure provides a method for forming a packaging structure, which includes: providing a substrate; stacking a plurality of first chips and a plurality of microfluidic chips layer by layer on the substrate; wherein, in the stacking direction of the plurality of first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is arranged between every two adjacent first chips; bonding a plurality of glass flow channels to the side walls of the plurality of first chips; wherein the plurality of glass flow channels are arranged around the side walls of the plurality of first chips; each of the glass flow channels is bonded to the side walls of the plurality of first chips and is connected to the plurality of microfluidic chips; bonding a plurality of second chips to the side walls of the plurality of first chips; wherein the plurality of second chips are arranged around the side walls of the plurality of first chips; each of the second chips is bonded to a corresponding one of the glass flow channels; forming a plurality of first connection structures; wherein the first end of each first connection structure is bonded to the first chip located at the top; and the second end of each first connection structure is bonded to a corresponding one of the second chips.

[0014] In the above scheme, bonding every two adjacent first chips includes: bonding the two adjacent first chips, and the microfluidic chip between the two adjacent first chips; wherein the microfluidic chip is bonded to the first surface of the two adjacent first chips; forming a first conductive plug and a second conductive plug along the second surface of one of the two adjacent first chips; wherein the first conductive plug or the second conductive plug passes through one of the two adjacent first chips, and the microfluidic chip between the two adjacent first chips; forming a first metal connection point on the second surface of the first chip; wherein the first metal interconnection point connects the first conductive plug and the second conductive plug respectively.

[0015] In the above scheme, bonding every two adjacent first chips includes: bonding the microfluidic chip on one of the first chips and forming a third conductive plug and a second metal interconnection point; wherein the fourth conductive plug passes through the microfluidic chip and is connected to the second metal interconnection point; forming a fourth conductive plug on another first chip; bonding the fourth conductive plug and the second metal interconnection point; wherein the second metal interconnection point is located between two adjacent first chips.

[0016] The present disclosure provides a packaging structure, which includes: multiple first chips, multiple microfluidic chips, multiple first connection structures, multiple glass flow channels and multiple second chips; wherein the multiple first chips are stacked layer by layer; in the stacking direction of the multiple first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is arranged between every two adjacent first chips; multiple glass flow channels and multiple second chips are arranged around the side walls of the multiple first chips; each glass flow channel is bonded to the side walls of the multiple first chips and is connected to the multiple microfluidic chips; each second chip is bonded to a corresponding glass flow channel; the first end of each connection structure is bonded to the first chip located at the top; the second end of each first connection structure is bonded to a corresponding second chip. In this way, the present disclosure integrates the second chip on the side walls of the multiple stacked first chips, and the multiple second chips can reuse the glass flow channels for heat dissipation, thereby further improving the integration of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the packaging structure provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic diagram of the packaging structure provided in the embodiment of the present disclosure Figure 2 ;

[0019] Figure 3 A schematic diagram of the packaging structure provided in the embodiment of the present disclosure Figure 3 ;

[0020] Figure 4 Schematic diagram of the bonding structure provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 5 Schematic diagram of the bonding structure provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 6 A schematic diagram of the structure of a microfluidic chip provided in an embodiment of the present disclosure;

[0023] Figure 7 A schematic structural diagram of a glass flow channel provided in an embodiment of the present disclosure;

[0024] Figure 8 A schematic flow chart of a method for forming a packaging structure provided in an embodiment of the present disclosure;

[0025] Figure 9 A schematic diagram of the packaging structure forming process provided in the embodiment of the present disclosure Figure 1 ;

[0026] Figure 10A schematic diagram of the packaging structure forming process provided in the embodiment of the present disclosure Figure 2 ;

[0027] Figure 11 A schematic diagram of the packaging structure forming process provided in the embodiment of the present disclosure Figure 3 ;

[0028] Figure 12 A schematic diagram of the packaging structure forming process provided in the embodiment of the present disclosure Figure 4 . DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0030] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, package, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, package, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, package, article, or device comprising the element.

[0034] Figure 1is a schematic structural diagram of an optional packaging structure 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 1 Only three first chips 10 are shown as an example, and the package structure 100 may also include two or more first chips 10. The first chip 10 may be any of a logic computing chip, a memory chip, and a sensor chip. The functions and structures of the multiple first chips 10 may be the same or different, and are not limited here.

[0035] In the embodiments of the present disclosure, reference Figure 1 , multiple first chips 10 are stacked layer by layer. In the stacking direction Z, every two adjacent first chips 10 are bonded to each other. The multiple first chips 10 can be bonded using a W2W (Wafer to Wafer) bonding method or the like.

[0036] In the embodiments of the present disclosure, reference Figure 1 The package structure 100 includes multiple microfluidic chips 20. A microfluidic chip 20 is disposed between every two adjacent first chips 10. In this way, the cooling medium (such as water or gas) in the internal flow channels of the microfluidic chips 20 can absorb heat from the first chips 10, thereby reducing the temperature of the multiple first chips 10 and preventing the heat generated by the multi-layer stacking of the first chips 10 from adversely affecting the performance of the devices in the package structure 100.

[0037] In the embodiments of the present disclosure, reference Figure 1 , the packaging structure 100 includes a plurality of glass runners 30. Each glass runner 30 is bonded to the side walls of the plurality of first chips 10. The plurality of glass runners 30 are arranged around the side walls of the plurality of first chips 10. Each glass runner 30 is connected to a plurality of microfluidic chips 20. That is to say, each glass runner 30 is connected to a plurality of microfluidic chips 20, and the cooling medium can enter or leave the microfluidic chip 20 through the glass runner 30. In this way, the embodiment of the present disclosure can realize the input and output control of the cooling medium in the microfluidic chip 10 through the glass runner 30, so that the embodiment of the present disclosure can accurately control the flow rate and heat exchange efficiency of the cooling medium through the glass runner 30, and further improve the thermal management capability. In addition, the plurality of glass runners 30 are all surrounded and bonded to the side walls of the plurality of first chips 10, so that the plurality of first chips 10 can also dissipate heat through the glass runner 30, thereby increasing the heat dissipation area of the stacking structure of the plurality of first chips 10 and further improving the heat dissipation performance.

[0038] In the embodiments of the present disclosure, reference Figure 1, the packaging structure 100 also includes a plurality of second chips 40. The second chip 40 can be a chip of a type such as a radio frequency chip. The plurality of second chips 40 are arranged around the side walls of the plurality of first chips 10. Each second chip 40 is bonded to a corresponding glass flow channel 30. The plurality of second chips 40 are all parallel to the stacking direction Z. That is to say, the plurality of second chips 40 are integrated in a vertical integration manner and integrated on the side walls of the plurality of stacked first chips 10. In this way, the embodiment of the present disclosure makes full use of the vertical space of the packaging structure 100, and increases the number of chips integrated in the packaging structure 100 without occupying additional horizontal area; and, the plurality of second chips 40 can reuse the glass flow channel 30 for heat dissipation, thereby further improving the integration of the packaging structure 100.

[0039] In the embodiments of the present disclosure, reference Figure 1 The package structure 100 also includes multiple first connection structures 50. The first connection structure 50 can be a flexible board or a coated metal trace, etc. The flexible board can be bent and adapted to different spatial layouts. The coated metal trace can achieve complex connections in a smaller space. The first end of each first connection structure 50 is bonded to the first chip 10 located at the top. The second end of each first connection structure 50 is bonded to a corresponding second chip 40. In other words, the multiple second chips 40 can be electrically connected to the multiple first chips 10 through the first connection structure 50.

[0040] Figure 2 is a structural diagram of another optional semiconductor package structure 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 2 The insulating structure 12 between the two third chips 11 is used to prevent electrical short circuits between the third chips 11 , provide mechanical support and thermal management functions, and the like.

[0041] In some embodiments of the present disclosure, reference Figure 2 One or more of the plurality of first chips 10 are cut into a plurality of third chips 11 .

[0042] In the embodiments of the present disclosure, reference Figure 2 , the first chip 10 can be cut into multiple third chips 11. For example, the functions of the multiple third chips 11 can be the same. In this way, if a third chip 11 fails, it can be individually shielded or replaced to avoid the entire chip from being scrapped, thereby improving system reliability and fault tolerance. For another example, the functions of the multiple third chips 11 are different. In this way, the embodiment of the present disclosure can divide a single chip into multiple independent functional units, thereby being able to adapt to diverse scenario requirements.

[0043] Figure 3This is a structural diagram of another optional packaging structure provided by an embodiment of the present disclosure. It should be noted that the third chip 70 can be any type of logic computing chip, storage chip and sensor chip, and the functions and structures of multiple third chips 70 can be the same or different, and there is no limitation here.

[0044] In some embodiments of the present disclosure, reference Figure 3 The package structure 100 further includes multiple third chips 70. In the stacking direction Z, the first chip 10 located at the top is bonded to each of the multiple third chips 70. In other words, the disclosed embodiment integrates multiple third chips 70 on top of the stacked structure formed by the multiple first chips 10. Thus, the disclosed embodiment can further improve the integration level of the package structure 100.

[0045] Figure 4 is a schematic structural diagram of an optional bonding structure 60 between two adjacent first chips provided in an embodiment of the present disclosure. It should be noted that: Figure 4 110 a is the interconnect structure of the first chip 10 a , and 110 b is the interconnect structure of the first chip 10 b .

[0046] In some embodiments of the present disclosure, reference Figure 4 The bonding structure 60 of each two adjacent first chips includes a first conductive plug 61, a second conductive plug 62, and a first metal interconnection 63. The first conductive plug 61 and the second conductive plug 62 can be formed by filling a through-silicon via (TSV). The first metal interconnection 63 can be a pad (PAD).

[0047] In the embodiments of the present disclosure, reference Figure 4 In the stacking direction Z, the microfluidic chip 20 is bonded to the first surface of two adjacent first chips. The first metal interconnection point 63 is set on the second surface of the two adjacent first chips. For example, Figure 4 The first metal interconnection point 63 is provided on the second surface of the first chip 10 a , and the first surface of the first chip 10 a and the first surface of the first chip 10 b are bonded to the microfluidic chip 20 .

[0048] In the embodiment of the present disclosure, the first conductive plug or the second conductive plug passes through one of the two adjacent first chips, and the microfluidic chip between the two adjacent first chips. Figure 4 The second conductive plug 62 passes through the first chip 10 a and the microfluidic chip 20 and lands on the interconnection structure 110 b of the second chip 10 b .

[0049] In the embodiment of the present disclosure, Figure 1 and Figure 4 One of the first chips between every two adjacent first chips is connected to the first metal interconnection 63 via a first conductive plug 61. The other first chip between every two adjacent first chips is connected to the first metal interconnection 63 via a second conductive plug 62. For example, the first chip 10a is connected to the first metal interconnection 63 via the first conductive plug 61, and the second chip 10b is connected to the first metal interconnection 63 via the second conductive plug 62. Thus, the embodiment of the present disclosure achieves vertical interconnection between adjacent first chips through the bonding structure 60.

[0050] Figure 5 is a schematic structural diagram of another optional bonding structure between two adjacent first chips provided by an embodiment of the present disclosure. It should be noted that: Figure 5 The interconnect structures 110a and 110b can refer to Figure 4 The above is for understanding, I will not go into details here.

[0051] In some embodiments of the present disclosure, reference Figure 5 The bonding structure 60 of each two adjacent first chips includes a third conductive plug 64, a fourth conductive plug 65, and a second metal interconnection 66. The third conductive plug 64 and the fourth conductive plug 65 can be formed by filling a through-silicon via (TSV). The second metal interconnection 66 can be a pad (PAD).

[0052] In the embodiments of the present disclosure, reference Figure 5 , the second metal interconnection point 66 is located between two adjacent first chips. For example, the second metal interconnection point 66 is located between the first chips 10a and 10b. In the stacking direction Z, the third conductive plug 64 or the fourth conductive plug 65 passes through the microfluidic chip 20 between the two adjacent first chips. For example, Figure 5 Fourth conductive plug 65 extends through microfluidic chip 20 and connects to second metal interconnection 66. First chip 10a is connected to second metal interconnection 66 via third conductive plug 64, and second chip 10b is connected to second metal interconnection 66 via second conductive plug 65. Thus, the present embodiment achieves vertical interconnection between adjacent first chips through bonding structure 60.

[0053] It should be noted that Figure 1 、 Figure 2 and Figure 3 The bonding structure between the plurality of first chips 10 can be Figure 4 and Figure 5 One or more combinations of the bonding structures shown.

[0054] Figure 6 is a schematic structural diagram of an optional microfluidic chip 20 provided in an embodiment of the present disclosure. It should be noted that: Figure 6The conductive plug 610 in the embodiment may be any one of the first conductive plug 61, the second conductive plug 62, the third conductive plug 64 and the fourth conductive plug 65 in the above embodiment, and is not limited here.

[0055] In some embodiments of the present disclosure, reference Figure 6 Each microfluidic chip 20 includes a plurality of cooling medium channels 21. The conductive plug 610 between each two adjacent first chips penetrates the microfluidic chip 20 at the protrusion 22 between the two adjacent cooling medium channels 21.

[0056] Figure 7 This is a schematic structural diagram of an optional glass flow channel 30 provided in an embodiment of the present disclosure. It should be noted that: Figure 7 The glass flow channel 30 shown is parallel to the first direction X, which is perpendicular to the stacking direction Z. The first direction X is parallel to one of the side walls of the plurality of first chips 10. It should be noted that the glass flow channel 30 bonded in the second direction Y can refer to Figure 7 Shown for understanding.

[0057] It should also be noted that Figure 7 The multiple first cooling medium flow channels 31 shown in the figure are all used to input cooling medium, and the multiple second cooling medium flow channels 32 are all used to output cooling medium. The input or output of cooling medium of each first cooling medium flow channel 31 and each second cooling medium flow channel 32 can be set according to actual conditions and are not limited here.

[0058] In some embodiments of the present disclosure, reference Figure 5 Each glass flow channel 30 includes a plurality of first cooling medium flow channels 31 and a plurality of second cooling medium flow channels 32. The plurality of first cooling medium flow channels 31 and the plurality of second cooling medium flow channels 32 extend along the stacking direction Z. The plurality of first cooling medium flow channels 31 can communicate with the microfluidic chip 20b. The plurality of second cooling medium flow channels 32 can communicate with the microfluidic chip 20a.

[0059] In the embodiments of the present disclosure, reference Figure 5 The lengths of the multiple first cooling medium flow channels 31 in the stacking direction Z are all greater than the lengths of the multiple second cooling medium flow channels 32. The multiple first cooling medium flow channels 31 and the multiple second cooling medium flow channels 31 are arranged alternately in the first direction X. In this way, the first cooling medium flow channels 31 and the second cooling medium flow channels 32 are arranged alternately in the X direction, and the difference in their lengths in the Z direction forms a complementary structure, which effectively disperses thermal stress concentration, thereby reducing the interfacial stress caused by the difference in thermal expansion coefficients, improving the mechanical reliability of the packaging structure, and ensuring long-term stability under thermal cycling conditions.

[0060] Figure 8This is a flow chart of an optional method for forming a packaging structure provided by an embodiment of the present disclosure, which will be described in conjunction with the steps shown in the figure.

[0061] S101: Provide a substrate.

[0062] S102. Stacking a plurality of first chips and a plurality of microfluidic chips layer by layer on a substrate; wherein, in the stacking direction of the plurality of first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is provided between every two adjacent first chips.

[0063] Figure 9 and Figure 10 This is a structural diagram of the formation process of the optional packaging structure provided by the embodiment of the present disclosure. It should be noted that: Figure 9 Only the stacking method of two first chips 10a and the second chip 10b is illustrated. The stacking method of more first chips can refer to Figure 9 Shown for understanding. Figure 10 The third chip 70 is shown in the example. It should also be noted that Figure 9 and Figure 10 The substrate is not shown.

[0064] In the embodiments of the present disclosure, reference Figure 9 In the stacking direction Z, every two adjacent first chips are bonded to each other, and a microfluidic chip 20 is disposed between every two adjacent first chips. For example, before bonding the two adjacent first chips 10a and 10b, the microfluidic chip 20 can be secured to one surface (e.g., the top surface) of the first chip 10b via thermocompression bonding. The first chip 10b is then aligned with the surface of the bonded microfluidic chip 20 and melt-bonded. The first chip 10b and the first chip 10a can be bonded using a hybrid bonding process (HB).

[0065] In the embodiment of the present disclosure, Figure 9 and Figure 10 After stacking a plurality of first chips, a plurality of third chips 70 may be bonded on the first chip located on the top. Figure 9 A plurality of third chips 70 are bonded to the first chip 10a in the embodiment of the present invention. Each third chip 70 is bonded to the first chip 10a via a bonding structure 620. An insulating structure 12b fills the gap between the third chip 70 and the first chip 10a.

[0066] S103. Bonding multiple glass flow channels to the side walls of the multiple first chips; wherein the multiple glass flow channels are arranged around the side walls of the multiple first chips; each glass flow channel is bonded to the side walls of the multiple first chips and is connected to the multiple microfluidic chips.

[0067] S104 , bonding a plurality of second chips to the sidewalls of the plurality of first chips; wherein the plurality of second chips are disposed around the sidewalls of the plurality of first chips; and each second chip is bonded to a corresponding glass flow channel.

[0068] S105 , forming a plurality of first connection structures; wherein a first end of each first connection structure is bonded to the first chip located at the top; and a second end of each first connection structure is bonded to a corresponding second chip.

[0069] Figure 11 is a structural diagram of the formation process of an optional packaging structure provided by an embodiment of the present disclosure, Figure 11 The front glass flow channel is not shown. Figure 11 The glass flow channel 30, the second chip 40 and the first connection structure 50 are shown in the example. Figure 11 The first connection structure 50 exemplified is a plated metal trace, and the first connection structure 50 may also be connected by a flexible board or the like. Figure 11 The illustrated first connection structure 50 is bonded to the third chip 70 . The process of bonding the first connection structure 50 to the first chip can be understood with reference to the process of bonding the first connection structure 50 to the third chip 70 .

[0070] In the embodiments of the present disclosure, reference Figure 10 and Figure 11 , on the side walls of the multiple first chips, glass runners 30 and second chips 40 are bonded in sequence. The glass runners 30 and second chips 40 can cover all or part of the side walls of the multiple first chips. Then, through the multiple first connection structures 50, the multiple second chips 40 are electrically connected to the third chip 70 and the first chip. In this way, the embodiment of the present disclosure makes full use of the vertical space of the packaging structure 100, and increases the number of chips integrated in the packaging structure 100 without occupying additional horizontal area; and the multiple second chips 40 can reuse the glass runner 30 for heat dissipation, thereby further improving the integration of the packaging structure 100.

[0071] In some embodiments of the present disclosure, it is also possible to implement the following steps S201 to S203: Figure 8 S102 in the embodiment will be described in conjunction with each step.

[0072] S201 , bonding two adjacent first chips and a microfluidic chip between the two adjacent first chips; wherein the microfluidic chip is bonded to the first surfaces of the two adjacent first chips.

[0073] In the embodiments of the present disclosure, reference Figure 4 The microfluidic chip 20 can be formed by dry / wet etching the glass substrate. Figure 6 The cooling medium channel 21 of the microfluidic chip 20 is shown.

[0074] In the embodiments of the present disclosure, reference Figure 4 Before bonding the first chip 10a, the first chip 10b, and the microfluidic chip 20, the first chip 10a, the first chip 10b, and the microfluidic chip 20 are subjected to interface treatment. Interface treatment may include surface cleaning, planarization, and activation. The microfluidic chip 20 is then bonded to the first chip 10b, and the first chip 10a is bonded to the microfluidic chip 20, by methods such as melt bonding.

[0075] S202. Form a first conductive plug and a second conductive plug along the second surface of one of the two adjacent first chips; wherein the first conductive plug or the second conductive plug passes through one of the two adjacent first chips and the microfluidic chip between the two adjacent first chips.

[0076] S203 , forming a first metal connection point on the second surface of the first chip; wherein the first metal connection point is respectively connected to the first conductive plug and the second conductive plug.

[0077] In the embodiments of the present disclosure, reference Figure 4 , a first conductive plug 61 and a second conductive plug 62 are formed on the first chip 10a by through silicon via technology. The first conductive plug 61 passes through the first chip 10a and the microfluidic chip 20 and lands on the interconnection structure 110b of the first chip 10b. The second conductive plug 62 lands on the interconnection structure 110a of the first chip 10a. The first conductive plug 61 can refer to Figure 6 Then, a first metal connection point 63 is formed to connect the first conductive plug 61 and the second conductive plug 62.

[0078] In some embodiments of the present disclosure, it is also possible to implement the following steps S201 to S203: Figure 8 S102 in the embodiment will be described in conjunction with each step.

[0079] S301. Bond a microfluidic chip on a first chip, and form a third conductive plug and a second metal interconnection point; wherein the third conductive plug passes through the microfluidic chip and connects to the second metal interconnection point.

[0080] Figure 12This is a structural diagram of the formation process of the optional packaging structure provided by the embodiment of the present disclosure. It should be noted that: Figure 12 The example shows the bonding process between the first chip 10b and the microfluidic chip 20.

[0081] In the embodiments of the present disclosure, reference Figure 12 Before bonding the first chip 10 a and the microfluidic chip 20 , interface processing is performed on the first chip 10 a and the microfluidic chip 20 .

[0082] In the embodiments of the present disclosure, reference Figure 12 , a fourth conductive plug 65 is formed by through silicon via technology. The fourth conductive plug 65 passes through the microfluidic chip 20 and lands on the interconnection structure 110b of the first chip 10b.

[0083] S302 , forming a third conductive plug on another first chip.

[0084] S303 , bonding the third conductive plug to the second metal interconnection point; wherein the second metal interconnection point is located between two adjacent first chips.

[0085] In the embodiment of the present disclosure, Figure 12 and Figure 5 , third conductive plug 64 lands on interconnect structure 110b of first chip 10b. Second metal connection point 66 connects third conductive plug 64 and fourth conductive plug 65, bonding first chips 10a and 10b together. In other words, first chips 10b and 10a are bonded together using a hybrid bonding process (HB).

[0086] The above description of the forming method is similar to the description of the above-mentioned package structure embodiment, and has similar beneficial effects as the package structure embodiment. For technical details not disclosed in the forming method embodiment of the present disclosure, please refer to the description of the package structure embodiment of the present disclosure for understanding.

[0087] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, package, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, package, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, package, article, or device comprising the element.

[0088] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The packaging structures disclosed in the several packaging structure embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new packaging structure embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several packaging structure or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new packaging structure embodiments or device embodiments.

[0089] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: A plurality of first chips, a plurality of microfluidic chips, a plurality of first connection structures, a plurality of glass flow channels and a plurality of second chips; wherein, A plurality of the first chips are stacked layer by layer; in the stacking direction of the plurality of the first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is provided between every two adjacent first chips; The plurality of glass flow channels and the plurality of second chips are all arranged around the side walls of the plurality of first chips; each of the glass flow channels is bonded to the side walls of the plurality of first chips and is in communication with the plurality of microfluidic chips; each of the second chips is bonded to a corresponding one of the glass flow channels; The first end of each of the connection structures is bonded to the first chip located at the top; the second end of each of the first connection structures is bonded to a corresponding second chip.

2. The packaging structure according to claim 1, wherein: The bonding structure of each two adjacent first chips includes: a first conductive plug, a second conductive plug and a first metal interconnection point; wherein, In the stacking direction, the microfluidic chip is bonded to the first surfaces of two adjacent first chips respectively; the first metal interconnection point is provided on the second surfaces of the two adjacent first chips; The first conductive plug or the second conductive plug passes through one of the two adjacent first chips, and the microfluidic chip between the two adjacent first chips; One of the first chips between every two adjacent first chips is connected to the first metal interconnection point through the first conductive plug; another of the first chips between every two adjacent first chips is connected to the first metal interconnection point through the second conductive plug.

3. The packaging structure according to claim 1 or 2, characterized in that: The bonding structure of each two adjacent first chips includes: a third conductive plug, a fourth conductive plug, and a second metal interconnection point; In the stacking direction, the third conductive plug or the fourth conductive plug passes through the microfluidic chip between two adjacent first chips; the second metal interconnection point is located between two adjacent first chips; One of every two adjacent first chips is connected to the second metal interconnection point through the third conductive plug; the other of every two adjacent first chips is connected to the second metal interconnection point through the fourth conductive plug.

4. The packaging structure according to claim 3, wherein: Each of the microfluidic chips includes: a plurality of cooling medium flow channels; The conductive plug between every two adjacent first chips passes through the microfluidic chip at the protrusion between the two adjacent cooling medium flow channels.

5. The packaging structure according to claim 1, wherein: Each of the glass flow channels comprises: a plurality of first cooling medium flow channels and a plurality of second cooling medium flow channels; wherein, The plurality of first cooling medium flow channels and the plurality of second cooling medium flow channels all extend along the stacking direction; the lengths of the plurality of first cooling medium flow channels in the stacking direction are all greater than the lengths of the plurality of second cooling medium flow channels; The plurality of first cooling medium flow channels and the plurality of second cooling medium flow channels are alternately arranged in a first direction; the first direction is perpendicular to the stacking direction; and the first direction is parallel to one side wall of the plurality of first chips.

6. The packaging structure according to claim 1, wherein: One or more of the plurality of first chips are cut into a plurality of third chips.

7. The packaging structure according to claim 1, wherein: Also includes: A plurality of third chips; wherein, in the stacking direction, the first chip located at the top is bonded to the plurality of third chips respectively.

8. A method for forming a packaging structure, characterized in that: include: providing a substrate; On the substrate, a plurality of first chips and a plurality of microfluidic chips are stacked layer by layer; wherein, in the stacking direction of the plurality of first chips, every two adjacent first chips are bonded to each other, and a microfluidic chip is provided between every two adjacent first chips; A plurality of glass flow channels are bonded to the side walls of the plurality of first chips; wherein the plurality of glass flow channels are disposed around the side walls of the plurality of first chips; each of the glass flow channels is bonded to the side walls of the plurality of first chips and is in communication with the plurality of microfluidic chips; A plurality of second chips are bonded to the sidewalls of the plurality of first chips; wherein the plurality of second chips are disposed around the sidewalls of the plurality of first chips; and each second chip is bonded to a corresponding one of the glass flow channels; A plurality of first connection structures are formed; wherein a first end of each first connection structure is bonded to the first chip located at the top; and a second end of each first connection structure is bonded to a corresponding second chip.

9. The forming method according to claim 8, wherein: Bonding every two adjacent first chips, comprising: Bonding two adjacent first chips and the microfluidic chip between the two adjacent first chips; wherein the microfluidic chip is bonded to the first surfaces of the two adjacent first chips; forming a first conductive plug and a second conductive plug along the second surface of one of the two adjacent first chips; wherein the first conductive plug or the second conductive plug passes through one of the two adjacent first chips and the microfluidic chip between the two adjacent first chips; A first metal connection point is formed on the second surface of the first chip; wherein the first metal connection point is respectively connected to the first conductive plug and the second conductive plug.

10. The forming method according to claim 8, wherein: Bonding every two adjacent first chips, comprising: Bonding the microfluidic chip to one of the first chips and forming a fourth conductive plug and a second metal interconnection point; wherein the fourth conductive plug passes through the microfluidic chip and is connected to the second metal interconnection point; forming a third conductive plug on another first chip; The third conductive plug is bonded to the second metal interconnection point; wherein the second metal interconnection point is located between two adjacent first chips.

Images