Decision feedback equalizer sharing weight digital-to-analog converter

Abstract

The invention discloses a decision feedback equalizer sharing a weight digital-to-analog converter, which comprises a signal input branch, an odd channel, an even channel, an interlaced change-over switch and the weight digital-to-analog converter, and is characterized in that the signal input branch is used for accessing an original signal to be processed, and the signal input branch is accessed to an adder of the odd channel and the even channel; the odd channel and the even channel are respectively used for sampling at opposite clock phases, and the feedback signal input ends of the odd channel and the even channel are connected with a weight digital-to-analog converter. According to the scheme, the odd channel and the even channel share one group of weight digital-to-analog converters, the odd channel and the even channel respectively sample at different time, and the other side does not need to provide a feedback signal at the sampling moment at one side, so that the switching of feedback current between the odd channel and the even channel can be realized, and the switching efficiency is improved. The function that the decision feedback equalizer shares the weight digital-to-analog converter is achieved, and the area and power consumption of the whole structure are saved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a decision feedback equalizer sharing a weighted digital-to-analog converter. Background Art

[0002] With the rapid development of information technology, the communication rate of devices is getting faster and faster, and the impact of channel non-ideality on the transmitted data is becoming more and more serious. Due to reasons such as medium loss and skin effect of the channel, the attenuation of each frequency of the transmission channel is different, and the overall shows a low-pass characteristic. And in the time domain, the channel will cause the signal to have a tailing phenomenon, resulting in inter-symbol interference (ISI). ISI will cause the eye diagram to become smaller or even closed, leading to a sharp increase in the bit error rate (BER). It is often necessary to introduce an equalization technology to eliminate the influence caused by inter-symbol interference and obtain effective data.

[0003] For relatively high channel losses, linear equalizers such as CTLE / FFE have a certain upper limit and cannot handle non-linear distortion well. Therefore, it is necessary to introduce a decision feedback equalizer (DFE), which can eliminate the post-cursor component in ISI.

[0004] The working principle of DFE mainly includes three key steps:

[0005] 1. Symbol decision: A comparator (slicer) makes a hard decision on the current signal and outputs a decision result symbol d k ;

[0006] 2. Interference reconstruction: Using historical decision symbols d k-x and tap coefficients w x to generate an ISI compensation amount;

[0007] 3. Forward cancellation: Subtracting the compensation amount from the received signal y k in real time to achieve feedback closed-loop equalization;

[0008] The traditional DFE structure, as shown in Figure 1 , has an adder for adding the signal and the feedback, a comparison decision maker for making a decision on the signal, and a group of dynamic coefficient multipliers for multiplying the dynamic coefficients with the decision result using a digital-to-analog converter (DAC). It directly uses the same clk as the comparator sampling to delay the decision result to obtain the historical decision result. All circuit modules work under the data baud rate clock, and a complete equalization operation is completed every unit interval time (UI). This structure DFE is also called a full-rate decision feedback equalizer (Full-Rate DFE).

[0009] The full-rate DFE only requires the necessary modules to achieve the equalization effect, and has the advantage of a small area. However, it requires a clock frequency that is the same as the data frequency, consumes a large amount of power, and because it needs to complete equalization within 1UI, it needs to meet the timing constraints:

[0010] T clk ≥T slicer +T FB +T sum

[0011] T slicer represents the delay of the comparator, and T FB represents the propagation delay of the multiplier and the wiring delay, and T sum represents the time to subtract the compensation amount from the received signal yk in real time.

[0012] During high-speed signal communication, there is always a certain delay in the feedback critical path of the full-rate DFE, making it difficult to complete equalization within 1UI. Therefore, an improvement is made in the sampling rate, and there is a sub-rate decision feedback equalizer (Sub-Rate DFE).

[0013] According to the ratio of the sampling clock to the data rate, the sub-rate decision feedback equalizer (Sub-Rate DFE) can be subdivided into a half-rate decision feedback equalizer (Half-Rate DFE), a 1 / 4-rate decision feedback equalizer (Quad-Rate DFE), an 1 / 8-rate decision feedback equalizer (Oct-Rate DFE), etc.

[0014] The structure of the half-rate decision feedback equalizer (Half-Rate DFE) is as Figure 2 shown. The sampling clock of the half-rate structure is half of the data rate, that is, the Nyquist frequency clock frequency. It has two channels, odd and even. Each channel includes: an adder to add the signal and the feedback; a comparison discriminator to discriminate the signal; a group of delay elements to save the discrimination result as the historical discrimination result; a group of dynamic coefficient multipliers to multiply the dynamic coefficient with the discrimination / historical discrimination result using a digital-to-analog converter (DAC). The two channels alternately sample using clk and its inverted clock clkb respectively.

[0015] The structure of the 1 / 4-rate decision feedback equalizer (Quad-Rate DFE) is as Figure 3As shown, the frequency of the sampling clock of the 1 / 4-rate decision feedback equalizer structure is one-fourth of the data rate. It has four channels, and each channel includes: an adder for adding the signal and the feedback; a comparison discriminator for discriminating the signal; a group of delay elements for saving the discrimination result as a historical discrimination result; and a group of dynamic coefficient multipliers for multiplying the dynamic coefficient with the discrimination / historical discrimination result by using a digital-to-analog converter (DAC). The four channels are sampled and delayed using 0°, 90°, 180°, and 270° four-phase clocks respectively.

[0016] There is always a certain delay in the critical path of the Full-Rate DFE feedback, making it difficult to complete equalization within 1UI. The high-frequency clock also leads to high power consumption in the clock path.

[0017] While the Half-Rate DFE can reduce the clock frequency to the signal Nyquist frequency, each of its channels is similar to a complete DFE, and its area is approximately twice that of the Full-Rate DFE. Among them, the Sub-Rate DFE adopts a multi-channel independent DAC structure, and several DACs are required for several paths, and the area occupancy ratio of the DAC array ranks among the top. Summary of the Invention

[0018] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a decision feedback equalizer sharing a weighted digital-to-analog converter, which solves the problems of large occupied area and high system power consumption in the existing feedback equalization structure.

[0019] The present application discloses a decision feedback equalizer sharing a weighted digital-to-analog converter, including:

[0020] A signal input branch, an odd channel, an even channel, an interleaved switch, and a weighted digital-to-analog converter. The signal input branch is used to access the original signal to be processed. The signal input branch accesses the adders of the odd channel and the even channel through the interleaved switch. The odd channel and the even channel are sampled at opposite clock phases respectively. The feedback signal input ends of the odd channel and the even channel are both connected to the weighted digital-to-analog converter.

[0021] In some embodiments, the odd channel includes an odd-channel forward signal flow path and an odd-channel feedback signal flow path. An odd-channel discriminator and an odd-channel delay unit are arranged successively on the odd-channel forward signal flow path, and an odd-channel conduction switch is arranged on the odd-channel feedback signal flow path.

[0022] In some embodiments, the even channel includes an even-channel forward signal flow path and an even-channel feedback signal flow path. An even-channel decision device and an even-channel delay unit are arranged one after another on the even-channel forward signal flow path, and an even-channel conduction switch is arranged on the even-channel forward signal flow path.

[0023] In some embodiments, the odd channel further includes a first feedback branch, which is led out between the odd-channel decision device and the odd-channel delay unit and then fed back to the input end of the even-channel decision device.

[0024] In some embodiments, the even channel further includes a second feedback branch, which is led out between the even-channel decision device and the even-channel delay unit and then fed back to the input end of the odd-channel decision device.

[0025] In some embodiments, the odd channel further includes a first delay feedback branch, which is fed back from the output end of the odd-channel delay unit to the input end of the odd-channel decision device.

[0026] In some embodiments, the even channel further includes a second delay feedback branch, which is fed back from the output end of the even-channel delay unit to the input end of the even-channel decision device.

[0027] In some embodiments, the decision feedback equalizer further includes an output path of a weight digital-to-analog converter. One end of the output path is connected to the weight digital-to-analog converter, and the other end of the output path is connected to the interleaved switching switch.

[0028] In some embodiments, there are multiple odd-channel delay units, and the multiple odd-channel delay units are sequentially and spacedly arranged on the odd-channel forward signal flow path. A first delay feedback branch is arranged between adjacent two odd-channel delay units, and the first delay feedback branch is used to feed back a signal to the input end of the odd-channel decision device or to the input end of the even-channel decision device.

[0029] In some embodiments, there are multiple even-channel delay units, and the multiple even-channel delay units are sequentially and spacedly arranged on the even-channel forward signal flow path. A second delay feedback branch is arranged between adjacent two even-channel delay units, and the second delay feedback branch is used to feed back a signal to the input end of the even-channel decision device or to the input end of the odd-channel decision device.

[0030] The present solution includes, but is not limited to, the following beneficial effects: (1) The odd channels and even channels of this solution share a set of weight digital-to-analog converters. Since the odd channels and even channels sample at different times, at the moment of sampling on one side, the other side does not need to provide a feedback signal. Therefore, the switching of the feedback current between the odd channels and even channels can be realized, and the function of sharing the weight digital-to-analog converter by the decision feedback equalizer can be achieved, saving the area and power consumption of the entire structure; (2) In this case, under the control of the timing logic, only one switching transistor in one set of switches is always turned on. At the same time, there will be no situation where multiple switching transistors in two sets of switches are turned on simultaneously and require independent current sources for power supply. The two sets of switches for the odd channels and even channels can share a tail current source, which can effectively save the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art.

[0032] Figure 1 is the structural diagram of a traditional decision feedback equalizer;

[0033] Figure 2 is the structural diagram of a traditional half-rate decision feedback equalizer;

[0034] Figure 3 is the structural diagram of a traditional 1 / 4-rate decision feedback equalizer;

[0035] Figure 4 is the structural diagram of the decision feedback equalizer sharing a weight digital-to-analog converter according to an embodiment of the present application;

[0036] Figure 5 is the feedback control timing diagram of the decision feedback equalizer sharing a weight digital-to-analog converter according to an embodiment of the present application;

[0037] Figure 6 is the current switch circuit diagram of the decision feedback equalizer sharing a weight digital-to-analog converter according to an embodiment of the present application, where Figure 6 (a) is the structural diagram of the decision feedback equalizer current switch circuit, Figure 6 (b) is the sampling schematic diagram when entering the feedback sampling stage of the even channels, Figure 6 (c) is the sampling schematic diagram when entering the feedback sampling stage of the odd channels;

[0038] Figure 7 is the feedback control logic diagram of the decision feedback equalizer sharing a weight digital-to-analog converter according to an embodiment of the present application;

[0039] In the figure, 1 is the signal input branch, 2 is the interleaved switch, 3 is the weighted digital-to-analog converter, 4 is the odd-channel forward signal flow path, 5 is the odd-channel feedback signal flow path, 6 is the odd-channel decision maker, 7 is the odd-channel delay unit, 8 is the even-channel forward signal flow path, 9 is the even-channel feedback signal flow path, 10 is the even-channel decision maker, 11 is the even-channel delay unit, 12 is the odd-channel conduction switch, 13 is the even-channel conduction switch, 14 is the first feedback branch, 15 is the second feedback branch, 16 is the first delayed feedback branch, 17 is the second delayed feedback branch, 18 is the output path, Even represents the even channel, and Odd represents the odd channel. Detailed implementation

[0040] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] Specifically, as Figure 4 shown, a decision feedback equalizer sharing a weighted digital-to-analog converter is disclosed. Specifically, referring to Figure 4 the structure includes a signal input branch 1, an odd channel, an even channel, an interleaved switch 2, and a weighted digital-to-analog converter (Tap Weight DAC) 3. The signal input branch 1 is used to access the original signal to be processed. The signal input branch 1 is connected to the adder of the odd channel and the adder of the even channel through the interleaved switch 2. It can be understood that the odd channel and the even channel are sampled at opposite clock phases. Therefore, when the signal input branch 1 is connected to the adder of the odd channel through the interleaved switch 2 and an input signal is applied, the signal input branch 1 is disconnected from the interleaved switch 2. At this time, the input signal is not connected to the adder of the even channel. The feedback signal input ends of the odd channel and the even channel are both connected to the weighted digital-to-analog converter (Tap Weight DAC) 3. Among them, ck in the figure is used to represent the main clock signal, which is used to synchronize the operations of various modules in the circuit and provide a basic time reference for the circuit. In the circuit of this solution, it is used to control the timing of data decision making by the comparator in the even channel, as well as the reset and switching of related feedback switches, etc., to ensure that the signal processing in the even channel is carried out according to a specific timing. Ckb is used to represent the inverted clock signal of ck, that is, the level state is opposite to that of the ck clock signal. In this circuit, ckb is used to control the related operations of the odd channel, such as triggering the comparator in the odd channel to make a decision, and the reset and closing of switches in the odd channel, etc. It works in cooperation with the ck signal to enable the operations of the odd channel and the even channel to proceed in an orderly manner, realizing the alternating processing and path switching control of the input signal.

[0042] Further, the odd channel includes an odd-channel forward signal flow path 4 and an odd-channel feedback signal flow path 5. An odd-channel decision device 6 and an odd-channel delay unit 7 are arranged in sequence on the odd-channel forward signal flow path 4, and an odd-channel conduction switch 12 is arranged on the odd-channel feedback signal flow path 5. Specifically, as Figure 4 shown, the interleaved switching switch 2 includes a switch Odd_S0, and the odd-channel conduction switch 13 can be represented as Odd_S1. When the switch Odd_S0 and the switch Odd_S1 are turned on, Odd fb0, Odd fb1, and the signal input branch 1 are added together and input to the odd-channel decision device 6 for decision. The even channel includes an even-channel forward signal flow path 8 and an even-channel feedback signal flow path 9. An even-channel decision device 10 and an even-channel delay unit 11 are arranged in sequence on the even-channel forward signal flow path 8, and an even-channel conduction switch 13 is arranged on the even-channel feedback signal flow path 9. The interleaved switching switch 2 further includes a switch Even_S0, and the even-channel conduction switch 13 can be represented as Even_S1. When the switch Even_S0 and the switch Even_S1 are turned on, Even fb0, Even fb1, and the signal input branch 1 are added together and input to the even-channel decision device 10 for decision.

[0043] In some embodiments, the odd channel further includes a first feedback branch 14, which is led out between the odd-channel decision device 6 and the odd-channel delay unit 7 and fed back to the input end of the even-channel decision device 10.

[0044] In some embodiments, the even channel further includes a second feedback branch 15, which is led out between the even-channel decision device 10 and the even-channel delay unit 11 and fed back to the input end of the odd-channel decision device 6.

[0045] In some embodiments, the odd channel further includes a first delay feedback branch 16, which is fed back from the output end of the odd-channel delay unit 7 to the input end of the odd-channel decision device 6.

[0046] In some embodiments, the even channel further includes a second delay feedback branch 17, which is fed back from the output end of the even-channel delay unit 11 to the input end of the even-channel decision device 10.

[0047] Specifically, in combination with Figure 4 and Figure 7As shown: When the decision of the even channel (hereinafter referred to as the Even path) is completed, that is, when entering the sampling stage of the odd channel (hereinafter referred to as the odd channel), Odd_s0 / odd_s1 conducts. When Odd_s0 conducts, it multiplies the decision result Even_D0 of the even-channel decision maker 10 (Even slicer) by TAP1 of the weighted digital-to-analog converter (weight DAC) 3 and feeds it back to the odd-channel adder. The feedback signal is denoted as Odd fb0. When Odd_s1 conducts, it multiplies the historical decision result (delayed decision result) Odd_D1 of the odd-channel decision maker 6 (Odd slicer) by TAP2 of the weighted digital-to-analog converter 3 and feeds it back to the odd-channel adder. The feedback signal is denoted as Odd fb1. The odd-channel adder adds the original input signal Input, Odd fb0, Odd fb1, etc., and outputs it to the input end of the Odd slicer. After the rising edge of the Odd clk arrives, a decision is made to output Odd_D1.

[0048] Similarly, when the decision of the odd channel is completed, that is, when entering the sampling stage of the even channel, Even_s0 / Even_s1 conducts. When Even_s0 conducts, it multiplies the decision result Odd_D0 of the odd-channel decision maker 6 (Odd slicer) by TAP1 of the weighted digital-to-analog converter 3 and feeds it back to the even-channel adder. The feedback signal is denoted as Even fb0. When Even_s1 conducts, it multiplies the historical decision result (delayed decision result) Even_D1 of the even-channel decision maker 10 (Even slicer) by TAP2 of the weighted digital-to-analog converter 3 and feeds it back to the even-channel adder. The feedback signal is denoted as Even fb1. The even-channel adder adds the original input signal Input, Even fb0, Even fb1, etc., and outputs it to the input end of the Odd slicer. After the rising edge of the Odd clk arrives, a decision is made to output Odd_D1.

[0049] Further, the feedback control timing in the decision feedback equalizer sharing the weighted digital-to-analog converter is as Figure 5 shown. Among them, Even fb is the feedback signal of the even-channel path, Even sum is the sum signal of the even-channel path, which is used to represent the sum result of the even signals and is the combined result of the original signal and the even-channel feedback signal for subsequent processing. Even clk is the clock signal of the even-channel path, which is used to control the sampling and processing timing of the data; Odd fb is the feedback signal of the odd-channel path, Odd sum is the sum signal of the odd-channel path, which represents the sum result of the odd signals for subsequent processing, and Odd clk is the clock signal of the odd-channel path, which is used to control the sampling and processing timing of the odd signals.

[0050] Further, in this embodiment, the Tap Weight DAC 3 may include multiple taps to enable connection to different signals.

[0051] Further, in this embodiment, as Figure 6 shown, the current mirrored by the Tap Weight DAC 3 is connected to the sources of a total of four NMOS switching transistors in two groups (odd channels and even channels). The drains of the two groups of switching transistors are respectively connected to the positive and negative terminals of adders (not shown in the figure) of the even channel and the odd channel, and whether they are turned on or off, i.e., the gates, are logically controlled. The control logic is as follows:

[0052] When the rising edge of the Odd clk arrives, that is, after the odd channel makes a decision, it enters the even channel feedback sampling stage. In this stage, all switches (M3, M4) in the Odd group enter the reset-off state, that is, both On and On_b = 0. According to the sign of the previous decision result, the corresponding p-terminal or n-terminal switches (M1 or M2) of each TAP switch in the Even group are selectively turned on, that is, En = 1, En_b = 0 or vice versa. At this time, the feedback is connected to the Even path, and the adder on this path adds the signal and the feedback. When the rising edge of the Even clk arrives, the comparator on the Even path makes a decision on the data result of the Even path.

[0053] Conversely, when the rising edge of the Even clk arrives, that is, after the even channel makes a decision, it enters the odd channel feedback sampling stage. In this stage, all switches (M1, M2) in the Even group enter the reset-off state, that is, both En and En_b = 0. According to the sign of the previous decision result, the corresponding p-terminal or n-terminal switches (M3 or M4) of each TAP switch in the Odd group are selectively turned on, that is, On = 1, On_b = 0 or vice versa. At this time, the feedback is connected to the Odd path, and the adder on this path adds the signal and the feedback. When the rising edge of the Odd clk arrives, the comparator on the Odd path makes a decision on the data result of the Odd path.

[0054] Because through the timing logic control, always only one switching transistor in one group of switches is conducting, the two groups of switches can share a tail current source, further saving power consumption.

[0055] In some embodiments, the decision feedback equalizer further includes an output path 18 of the Tap Weight DAC. One end of the output path 18 is connected to the decision feedback equalizer 3, and the other end of the output path 18 is connected to the interleaved switch 2.

[0056] In some embodiments, there are multiple odd-channel delay units 7, and the multiple odd-channel delay units 7 are sequentially and spaced apart on the odd-channel forward signal flow path 4. A first delay feedback branch 16 is provided between every two adjacent odd-channel delay units 7, and the first delay feedback branch 16 is used to feed back a signal to the input end of the odd-channel decision maker 6 or to the input end of the even-channel decision maker 10.

[0057] In some embodiments, there are multiple even-channel delay units 11, and the multiple even-channel delay units 11 are sequentially and spaced apart on the even-channel forward signal flow path 8. A second delay feedback branch 17 is provided between every two adjacent even-channel delay units 11, and the second delay feedback branch 17 is used to feed back a signal to the input end of the even-channel decision maker 10 or to the input end of the odd-channel decision maker 6.

[0058] It can be understood that the odd-channel and even-channel of this solution share a set of weight digital-to-analog converters (Tap Weight DAC). Since the odd-channel and even-channel sample at different times, at the moment when one side samples, the other side does not need to provide a feedback signal. Therefore, the switching of the feedback current between the odd-channel and even-channel can be realized, and the function of sharing the weight digital-to-analog converter (Tap Weight DAC) can be achieved, saving the area and power consumption of the entire structure; further, in this case, due to the control of the timing logic, only one switching transistor in one group of switches is always turned on. At the same moment, there will not be a situation where multiple switching transistors in two groups of switches are turned on simultaneously and require independent current sources for power supply. The two groups of switches of the odd-channel and even-channel can share a tail current source, which can effectively save the circuit power consumption.

[0059] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification only illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements fall within the scope of the present invention claimed.

Claims

1. A decision feedback equalizer sharing a weighted digital-to-analog converter, characterized in that Including: A signal input branch (1), an odd channel, an even channel, an interleaved switch (2), and a weighted digital-to-analog converter (3). The signal input branch (1) is used to access the original signal to be processed. The signal input branch (1) accesses the adder of the odd channel and the even channel through the interleaved switch (2). The odd channel and the even channel sample at opposite clock phases respectively. The feedback signal input ends of the odd channel and the even channel are both connected to the weighted digital-to-analog converter (3).

2. The decision feedback equalizer of the shared weight digital-to-analog converter according to claim 1, characterized in that, The odd channel includes an odd-channel forward signal flow path (4) and an odd-channel feedback signal flow path (5). An odd-channel decision device (6) and an odd-channel delay unit (7) are arranged successively on the odd-channel forward signal flow path (4). An odd-channel conduction switch (12) is arranged on the odd-channel feedback signal flow path (5).

3. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 1, wherein The even channel includes an even-channel forward signal flow path (8) and an even-channel feedback signal flow path (9). An even-channel decision device (10) and an even-channel delay unit (11) are arranged successively on the even-channel forward signal flow path (8). An even-channel conduction switch (13) is arranged on the even-channel feedback signal flow path (9).

4. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 1 or 2, characterized in that The odd channel further includes a first feedback branch (14). The first feedback branch (14) is led out between the odd-channel decision device (6) and the odd-channel delay unit (7) and then fed back to the input end of the even-channel decision device (10).

5. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 1 or 3, characterized in that, The even channel further includes a second feedback branch (15). The second feedback branch (15) is led out between the even-channel decision device (10) and the even-channel delay unit (11) and then fed back to the input end of the odd-channel decision device (6).

6. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 4, characterized in that, The odd channel further includes a first delay feedback branch (16). The first delay feedback branch (16) is fed back from the output end of the odd-channel delay unit (7) to the input end of the odd-channel decision device (6).

7. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 5, characterized in that, The even channel further includes a second delay feedback branch (17). The second delay feedback branch (17) is fed back from the output end of the even-channel delay unit (11) to the input end of the even-channel decision device (10).

8. The decision feedback equalizer of the shared weight digital-to-analog converter according to claim 1, characterized in that, The decision feedback equalizer further includes an output path (18) of the weighted digital-to-analog converter. One end of the output path (18) is connected to the weighted digital-to-analog converter (3), and the other end of the output path (18) is connected to the interleaved switch (2).

9. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 2, wherein There are multiple odd-channel delay units (7). The multiple odd-channel delay units (7) are arranged at intervals successively on the odd-channel forward signal flow path (4). A first delay feedback branch (16) is arranged between every two adjacent odd-channel delay units (7). The first delay feedback branch (16) is used to feed back signals to the input end of the odd-channel decision device (6) or to the input end of the even-channel decision device (10).

10. The decision feedback equalizer of the shared-weight digital-to-analog converter according to claim 3, characterized in that, The even-channel delay units (11) are multiple, and the multiple even-channel delay units (11) are sequentially and spacedly arranged on the even-channel forward signal flow path (8). A second delay feedback branch (17) is provided between every two adjacent even-channel delay units (11), and the second delay feedback branch (17) is used to feed back a signal to the input end of the even-channel decision device (10) or to the input end of the odd-channel decision device (6).

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