LDPC partial parallel encoder and encoding method under DVB-S2 standard

Abstract

The invention discloses an LDPC partial parallel encoder and encoding method under a DVB-S2 standard, and the encoder comprises an ROM control module which is used for selecting a matrix column weight according to an input code rate, controlling a counter to count to a corresponding ROM address, and selecting a corresponding storage unit at the same time, so as to generate a read address signal and a read enable signal of the corresponding ROM; the ROM storage module is used for reading corresponding parity check matrix information according to the input information of the ROM control module; the check calculation module is used for completing iterative calculation of an intermediate value variable according to the parity check matrix information read from the ROM storage module, calculating a check bit at the same time, and finally outputting the check bit to the de-encapsulation module; the packaging module is used for splicing the input 8-bit data into 360-bit data and outputting the 360-bit data to the ROM control module and the check calculation module; and the de-encapsulation module is used for disassembling the output data into 8-bit data so as to keep the bit width of the 8-bit data consistent with the bit width of the input data. The method has the advantages of low resource consumption and high throughput, and can be used for satellite communication.

Description

Technical Field

[0001] The present invention belongs to the technical field of channel coding in wireless communication systems, and particularly relates to an LDPC partial parallel encoder and an encoding method under the DVB-S2 standard. Background Art

[0002] With the rapid development of global communication systems, traditional terrestrial networks can no longer fully meet people's needs for efficient information transmission and access to the network anytime and anywhere.

[0003] The second-generation DVB-S2 was first proposed as a draft in June 2004. As a new generation of DVB standard, its design goal is to meet the needs of broadband satellite communication. Compared with the previous standard, DVB-S2 has achieved a transmission capacity increase of about 30% under the same transmission conditions, and at the same time significantly improved the receiving performance while maintaining the spectral efficiency. With its excellent technical characteristics, DVB-S2 has quickly become the mainstream standard in the field of broadband satellite communication and has been widely used globally.

[0004] The DVB-S2 standard defines a normal frame LDPC code and a short frame LDPC code. The LDPC code corresponding to the normal frame has a code length of 64,800 and a total of 11 code rates, with the code rate range from 1 / 4 to 9 / 10; the LDPC code corresponding to the short frame has a code length of 16,200 and a total of 10 code rates, with the code rate range from 1 / 4 to 8 / 9.

[0005] In the DVB-S2 standard, the LDPC code is an irregular repeat-accumulate code. The standard takes every 360 columns of the parity-check matrix as a column block, and the compression information given in the appendix of the DVB-S2 standard is the row positions of the non-zero elements in the first column of each column block. And the number of each row in the compression information represents the degree of the variable nodes in the column block.

[0006] The encoding principle of the LDPC code in the DVB-S2 standard is as follows:

[0007] According to the equation for solving the parity-check bits with a double-diagonal structure, it can be obtained that:

[0008]

[0009] where p r represents the r-th parity-check bit, i z represents the z-th information bit, and a z,r represents the information in the r-th column and z-th row of the parity-check matrix.

[0010] The formula can be rewritten as:

[0011]

[0012] where:

[0013]

[0014] An intermediate variable used to represent the r-th parity check bit. Considering that the periodicity factor M of all DVB-S2 codes is 360, the partial parallel calculation of the parity check bits is thus performed, and the calculation formula is:

[0015]

[0016] Writing it in matrix form, denoted as S:

[0017]

[0018] Calculating the exclusive OR sum of all rows in matrix S, we can obtain:

[0019]

[0020] Subsequently, the vector s is obtained through the following matrix operations:

[0021]

[0022] where L is a lower triangular matrix of size 360×360, and the obtained result is then logically shifted right by 1 bit to obtain:

[0023]

[0024] Finally, the 360-bit parity check bit information can be calculated at once through the following formula:

[0025]

[0026] However, in practical applications, when a DVB-S2 standard LDPC code encoder performs partial parallel encoding, it takes a relatively long clock cycle to wait for the result of the exclusive OR sum operation of matrix S rows. At the same time, after the result calculation is completed, the encoder still needs 360 clocks to wait for the recursive calculation result of vector s. These operations will greatly reduce the throughput of the encoder; when storing the parity check matrix information, if no specific storage optimization scheme is adopted, it will lead to a large consumption of storage resources. Summary of the Invention

[0027] The object of the present invention is to reduce the use of storage resources in a partial parallel encoder architecture and at the same time reduce the idle waiting clocks during the encoding process, and propose an LDPC partial parallel encoder structure and encoding method conforming to the DVB-S2 standard, so as to reduce the consumption of storage resources, improve the throughput, and be compatible with all code rates of LDPC codes under the DVB-S2 standard.

[0028] The technical solution for achieving the object of the present invention is as follows:

[0029] An LDPC partial parallel encoder under the DVB-S2 standard, comprising: a ROM control module, a ROM storage module, a check calculation module, a packaging module and a decompression module. The ROM control module is used to select the matrix column weight according to the input code rate, control the counter to count to the corresponding ROM address, and at the same time select the corresponding storage unit to generate the read address signal and read enable signal of the corresponding ROM.

[0030] The ROM storage module is used to read the corresponding parity check matrix information according to the input information of the ROM control module.

[0031] The check calculation module is used to complete the iterative calculation of the intermediate value variable according to the parity check matrix information read from the ROM storage module, calculate the check bits at the same time, and finally output the check bits to the decompression module.

[0032] The packaging module is used to splice the input 8-bit data into 360-bit data and output it to the ROM control module and the check calculation module.

[0033] The decompression module is used to disassemble the output data into 8-bit data, keeping the same bit width as the input data.

[0034] An LDPC partial parallel encoding method under the DVB-S2 standard, comprising the steps of:

[0035] 1) After receiving the frame header signal and the code rate signal, the ROM control module selects the corresponding data matrix column weight and reads the corresponding ROM.

[0036] 2) Read the parity check matrix information corresponding to the code rate from the corresponding ROM storage module.

[0037] 3) The check calculation module calculates the check bit information according to the read parity check matrix information and the information bit information to complete the calculation of the intermediate variable information and the check information.

[0038] Compared with the prior art, the beneficial effects of the present invention are:

[0039] The LDPC partial parallel encoder under the DVB-S2 standard of the present invention makes a special storage plan for the parity check matrix information, reducing the BRAM resources required for storing the parity check matrix under each code rate. Some steps in the encoding calculation are preposed to reduce the delay caused by waiting for calculation in hardware implementation. At the same time, a recursive module with a parallelism of 8 is adopted to reduce the waiting recursive time required for calculating the vector s, improving the throughput of the encoder. Description of the Drawings

[0040] Figure 1 It is a schematic structural diagram of the LDPC encoder under the DVB-S2 standard of the present invention.

[0041] Figure 2 This is a schematic diagram of the matrix calculation unit of the parity check calculation module in the LDPC encoder of the present invention.

[0042] Figure 3 This is a schematic diagram of the structure of the recursive output unit of the parity check calculation module in the LDPC encoder of the present invention.

[0043] Figure 4 This is a simulation diagram of encoding using the LDPC encoder of the present invention.

[0044] Figure 5 This is a timing report diagram of the present invention under the 200Mhz clock of the FPGA development board. Detailed implementation manners

[0045] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention.

[0046] It should be noted that the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0047] The technical idea for achieving the objective of the present invention is: by preprocessing the data stored in the ROM, the encoder can perform encoding with less data storage; by advancing the matrix row XOR sum calculation and adopting partial parallel recursion, the idle waiting clocks during the encoding process are reduced, and the throughput of the encoder is improved.

[0048] An LDPC partial parallel encoder under the DVB-S2 standard mainly solves the problems of large resource consumption and low throughput of existing encoders. It includes the following modules: a ROM control module, a ROM storage module, and a parity check calculation module.

[0049] The ROM control module is used to select the matrix column weight according to the input code rate, control the counter to count to the corresponding ROM address, and select the corresponding storage unit at the same time to generate the read address signal and read enable signal of the corresponding ROM.

[0050] The ROM storage module is used to store the parity check matrix information of all code rates.

[0051] The parity check calculation module is used to update the intermediate value variable according to the read parity check matrix information and the intermediate value variable, calculate the parity check bits at the same time, and finally output the parity check bits.

[0052] Further, the input of the ROM control module is the code rate signal, input valid signal, frame header signal and switching column weight signal, and the output is the ROM address signal and enable signal; this control unit has 21 groups of ROM address signals and enable signals, corresponding to all code rates in the DVB-S2 standard. After detecting the frame header signal, the counter in the control module starts to work, selects the corresponding column weight through the code rate signal, and after every 360-bit information bits are input, the counting length of the counter is the corresponding column weight. After receiving the effective switching column weight signal, the matrix column weight is changed to 3, and counting starts again after receiving the new frame header signal. Due to the intermittent input of the encoder, it is necessary to use the input valid signal to determine whether to perform circular shift on the current input signal and whether to perform subsequent matrix calculations.

[0053] Further, the input of the ROM storage module is the ROM address signal and enable signal, and the output is the parity check matrix information and switching column weight signal. To reduce the consumption of hardware storage resources, the parity check matrix information is stored according to a specific scheme.

[0054] Further, the specific scheme is as follows: According to the compressed form of the parity check matrix corresponding to each code rate in the DVB-S2 standard, first determine the number of rows q of the matrix compression form. Use the initial value provided in the appendix of the DVB-S2 standard file as the dividend, and perform the remainder operation with the q value of each code rate as the divisor to obtain the corresponding row information. After obtaining the row information, perform the integer division operation on the initial value in the appendix, and use the row information as the benchmark to divide the initial value by the corresponding row information to obtain the column information of the parity check matrix. At the same time, in the parity check matrices of different code rates, the weight of each column is different, and a flag bit is added before the row and column information to determine whether to switch the column weight signal.

[0055] Except for the double diagonal sub-matrix part of the parity check matrix, it is divided into a larger column weight matrix H1 and a smaller column weight matrix H2 based on a threshold. Except for the last bit, the matrix flag bits of all columns in the H1 matrix are 0, and in the H2 matrix, except for the last bit, the matrix flag bits of all the remaining columns are 1. When the flag bit jumps from 0 to 1, it means that the calculation of the H1 part of the matrix is completed and the calculation of the H2 part is entered; when the flag bit jumps from 1 to 0, it means that the calculation of the H2 matrix is completed.

[0056] The threshold can be taken as 3. The matrix with a column weight greater than 3 is the larger column weight matrix H1, and the matrix with a column weight less than or equal to 3 is the smaller column weight matrix H2.

[0057] Further, the parity check calculation module includes a matrix calculation unit, a RAM read-write storage unit and a recursive output unit, which are used to update the intermediate value variable, calculate the parity check bit at the same time, and finally output the parity check bit.

[0058] Further, the matrix calculation unit cyclically shifts the matrix row data according to the column information in the parity check matrix information to ensure the correct correspondence between the input data and the matrix calculation. Since the result needs to be cyclically shifted and stored back in the RAM after the calculation of one row of data, the input data is directly cyclically shifted in the reverse direction. The core idea of this method is that through a single reverse cyclic shift operation, the position of the input data is pre-adjusted so that after the exclusive OR calculation with the intermediate variable row, the result can be stored in the RAM without having to cyclically shift the result again.

[0059] Further, the RAM read / write storage unit reads the corresponding intermediate variable through the row information in the parity check matrix information, sends it to the matrix calculation unit for update, and then sends the updated intermediate variable information back to the original address.

[0060] Further, the recursive output unit accelerates the recursive calculation speed and reduces the idle waiting time of the encoder by designing a recursive structure with a parallelism of 8. After the recursive calculation is completed, the recursive result is logically right-shifted and then exclusive ORed with the intermediate variable to obtain the parity bit information and output it.

[0061] A method for encoding using an LDPC partially parallel encoder under the DVB-S2 standard, comprising the following steps:

[0062] 1) After the encoder receives the frame header signal and the code rate signal, it selects the corresponding data matrix column weight and reads the corresponding ROM.

[0063] 2) Read the parity check matrix information corresponding to the code rate from the corresponding storage module.

[0064] 3) Calculate the parity bit information according to the read parity check matrix information and the information bit information to complete the calculation of the intermediate variable information and the parity information.

[0065] 6. The method according to claim 5, wherein: in step 1), the ROM control module controls the ROM corresponding to the code rate and its address, and the implementation is as follows:

[0066] 1a) After detecting the frame header signal, the counter in the control module starts to work, selects the corresponding column weight through the code rate signal, and after every 360 bits of information bit information are input, the counting length of the counter is the corresponding column weight, and when the effective column weight switching signal is received, the matrix column weight is changed to 3.

[0067] 1b) The ROM control module outputs the generated ROM read address signal and ROM enable signal to the ROM storage module to read the parity check matrix information.

[0068] 1c) The ROM control module determines whether to perform cyclic shift on the current input signal and whether to perform subsequent matrix calculations through valid signals.

[0069] In step 2), the ROM storage module stores each code rate with a maximum of only 1 BRAM resource.

[0070] In step 3), the check calculation module calculates the intermediate variable information and the check information as follows:

[0071] 3a) The check calculation module reads the intermediate variable information according to the read parity check matrix information, and at the same time writes the updated intermediate variable back to the original address.

[0072] 3b) According to the parity check matrix information, perform cyclic shift on the input information bit information, perform exclusive OR sum with the read intermediate variable information to obtain the updated intermediate variable information, and at the same time calculate the exclusive OR sum of the matrix rows.

[0073] 3c) After all the intermediate variable information is updated, perform recursive calculation on the exclusive OR sum of the matrix rows, and then read the intermediate variable information one by one to calculate the check information.

[0074] Embodiment 1

[0075] Refer to Figure 1 , the present invention provides an LDPC encoder under the DVB-S2 standard, including: a ROM control module, a ROM storage module, a check calculation module, a packaging module and a decompression module. The packaging module splices the input variable information into a 360-bit width. The ROM control module pulls up the corresponding ROM enable signal according to the input code rate signal, and at the same time reads the corresponding address in the ROM according to the counter in the ROM control module; the ROM storage module stores the check matrix information of all code rates, and reads the corresponding data according to the address information and enable information input by the control module; the check calculation module calculates the intermediate variable information and the check bit information according to the parity check matrix information and the input information bit information. The decompression module disassembles the output information into an 8-bit width.

[0076] The input of the packaging module is information bit information, information bit valid signal and frame header signal, and the output is packaged information, packaged valid signal and packaged frame header signal. The module contains a counter. When the input signal is detected to be valid, the module starts to read the input data and starts the counting process. When the counter reaches 90, its value will be automatically reset to zero, and the currently processed data will be passed to the next-level module. In the subsequent clock cycle, the counter restarts counting, indicating that the current input data has been successfully transmitted.

[0077] The input of the ROM control module is the encapsulation information, encapsulation valid signal, encapsulation frame header signal, and switching column weight signal, and the output is the ROM read enable and ROM read address. There is also a counter in this control module. After receiving the encapsulation frame header signal, the counter is cleared. After receiving the encapsulation valid signal, the counter starts counting. The count value is the column weight of the parity check matrix. After receiving the switching column weight signal, it means that the coding calculation enters the H2 matrix, so the count value of the counter changes. According to the code rate signal, the corresponding ROM read enable is pulled high, and at the same time, the corresponding data is read according to the value of the counter. Subsequently, the data is output to the parity check calculation module for circularly shifting the input signal and reading the corresponding address of matrix S.

[0078] The input of the ROM storage module is the ROM read enable and ROM read address, and the output is the matrix row information, matrix column information, and switching column weight signal. After reading out the matrix information, it is disassembled into row information, column information, and matrix header information. When the matrix header information changes from 0 to 1, it means that the coding calculation enters the H2 matrix, and the switching column weight signal is pulled high.

[0079] The ROM storage module stores the parity check matrix information corresponding to all code rates.

[0080] Since there are many parity check matrices in the DVB-S2 standard and there are remainder operations during the coding process, in order to meet the specific requirements of the parity check matrix under different code rates and reduce the hardware complexity of the encoder, it is necessary to preprocess the information in the appendix of the DVB-S2 standard file and adapt to the requirements of each code rate. According to the compressed form of the parity check matrix corresponding to each code rate in the DVB-S2 standard, first determine the number of rows q of the matrix compression form. Then, by performing a remainder operation on the initial value provided in the appendix of the DVB-S2 standard file and using the q value of each code rate as the divisor, the corresponding row information is obtained. After obtaining the row information, perform an integer division operation on the initial value in the appendix. Using the row information as a reference, divide the initial value by the corresponding row information to finally obtain the column information of the parity check matrix.

[0081] For example, the position data 23606 at a code rate of 1 / 4 given in the appendix of the DVB-S2 standard file. The number of rows q of the compression form at this code rate is 135. Therefore, the corresponding row information is 116, which is converted to the binary number 01110100, and the column information is 174, and its binary representation is 01110100. Since these information data belong to the parity check matrix H1, the prefix flag bit in the ROM is 0. In this case, the stored data is 001110100010101110.

[0082] The depth of each ROM varies according to the coding requirements of specific code rates, but their widths remain the same. The data width of all ROMs is 18 bits, which includes column frame headers, row information, and column information. Among them, the width of the frame header signal is 1 bit, the width of the row information signal is 8 bits, and the width of the column information signal is 9 bits. The maximum ROM depth is 648, so the maximum number of BRAM resources used for each code rate is 1. All code rates share 17.5 BRAM resources.

[0083] Combined with Figure 2 , the parity check calculation module includes a matrix calculation unit, a RAM read / write storage unit, and a recursive output unit to calculate the coding parity bit information.

[0084] The matrix calculation unit, with matrix row information, matrix column information, and information bit information as inputs, outputs intermediate variable update information and matrix row XOR sum information.

[0085] There is a barrel shifter in the matrix calculation unit for performing circular shift operations on the information bit information according to the matrix column information.

[0086] The RAM read / write storage unit, with matrix row information and intermediate variable update information as inputs, outputs intermediate variable information.

[0087] The RAM read / write storage unit reads the corresponding intermediate variable through the matrix row information, sends it to the matrix calculation unit for update, and then sends the updated intermediate variable information back to the original address. In the DVB-S2 standard, when the code rate is 1 / 4 and the code length is 64800, the storage requirement of the matrix reaches the maximum value. At this time, the length of the information bits is 16200, and the length of the parity bits is 48600. Therefore, the RAM depth for storing matrix S needs to be set to 135, and the width is 360. To adapt to the calculation requirements of all code rates under the standard, this application uniformly maximizes the bit widths of each parameter involved in the calculation process.

[0088] Refer to Figure 3 , the recursive output unit, with matrix row XOR sum information and intermediate value variable information as inputs, outputs parity bit information.

[0089] The recursive output unit can complete the recursive operation in 45 clock cycles through a partially parallel recursive structure after all intermediate value variable update operations on the input information bit information are completed. After the recursive operation is completed, the recursive result is logically shifted right by one bit, and then all intermediate value variable addresses are traversed to calculate the parity bit information.

[0090] The unpacking module uses the same counter as the packing module, but its function is the opposite of that of the packing module. To ensure the stability of data transmission in the unpacking module, a FIFO is nested in the module to temporarily store the generated parity bit information. The data width of the FIFO is set to 360 to adapt to the calculation requirements of matrix S. Considering that the maximum required FIFO depth is 135 in the scenario with a code rate of 1 / 4, the depth of the FIFO is set to 256 to ensure the flexibility and margin design of the system.

[0091] The effects of the present invention can be further illustrated by the following simulation experiments:

[0092] I. Simulation experiment conditions

[0093] This simulation uses Verilog code as the RTL code and Vivado2020.2, Matlab, and Modelsim as the simulation software;

[0094] Based on the VC709 development board, a simulation experiment is carried out at a 200 MHz clock, and the implementation process is as Figure 3 .

[0095] II. Simulation content

[0096] Figure 4 In a), it is the initial result of encoding one frame of data for the LDPC code with a long code rate of 1 / 4 under the DVB-S2 standard. Figure 4 In b), it is the final result of encoding one frame of data for the LDPC code with a long code rate of 1 / 4 under the DVB-S2 standard. Figure 4 In c), it is the overall result of encoding one frame of data for the LDPC code with a long code rate of 1 / 4 under the DVB-S2 standard. Figure 4 In d), it is the encoding result of the LDPC code with a short code rate of 1 / 4 under the DVB-S2 standard. Figure 4 In e), it is the encoding result of the LDPC code with a long code rate of 2 / 5 under the DVB-S2 standard. Figure 4 In f), it is the encoding result of the LDPC code with a long code where the first frame has a code rate of 1 / 4 and the second frame has a code rate of 2 / 5 under the DVB-S2 standard. As Figure 4 can be seen, the right_flag signal is fully pulled high, indicating that the encoding result is correct, demonstrating that the encoder design of the present invention is reasonable and can achieve the predetermined LDPC code encoding function for the full code rate under the DVB-S2 standard, and at the same time support the switching between code rates.

[0097] Simulation 1: The functions of the encoder of the present invention are implemented in the experimental platform through the Vivado2020.2 software, and the resource consumption results are shown in Table 1.

[0098] Table 1 Resource Consumption of the Present Invention on FPGA

[0099] Resources Usage Quantity Total Number of Chips Owned Percentage of Usage Slice 1737 108300 1.60％ SliceLUT 5627 433200 1.29％ SliceRegisters 3838 866400 0.44％ BRAM 22.5 1470 1.53％

[0100] Simulation 2. Implement the encoder of the present invention on the VC709 development board. When the working clock frequency is 200 MHz, the FPGA timing report reference Figure 5 , it can be obtained that the encoder meets the timing requirements. The maximum data throughput is 1.6 Gbps, indicating that the encoder of the present invention has a high throughput.

[0101] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An LDPC partial parallel encoder under the DVB-S2 standard, comprising: A ROM control module, a ROM storage module, a checksum calculation module, a packaging module, and a decompression module, characterized in that: The ROM control module is configured to select a matrix column weight according to an input code rate, control a counter to count to a corresponding ROM address, and simultaneously select a corresponding storage unit to generate a read address signal and a read enable signal for the corresponding ROM; The ROM storage module is configured to read corresponding parity check matrix information according to the input information of the ROM control module; The checksum calculation module is configured to complete iterative calculation of intermediate value variables according to the parity check matrix information read from the ROM storage module, calculate check bits at the same time, and finally output the check bits to the decompression module; The packaging module is configured to splice the input 8-bit data into 360-bit data and output it to the ROM control module and the checksum calculation module; The decompression module is configured to disassemble the output data into 8-bit data to be consistent with the input data bit width.

2. The encoder according to claim 1, characterized in that: The input of the ROM control module is a code rate signal, a valid signal, a frame header signal, and a switching column weight signal, and the output is a ROM address signal and an enable signal; the control unit includes 21 groups of ROM address signals and enable signals corresponding to all code rates in the DVB-S2 standard. After detecting the frame header signal, the counter in the control module starts to work, and the corresponding column weight is selected through the code rate signal; after every 360-bit information bit input, the counting length of the counter is the corresponding column weight. After receiving the effective switching column weight signal, the matrix column weight is changed to 3, and counting starts again after receiving the new frame header signal. The module determines whether to perform circular shift on the current input signal and whether to perform subsequent matrix calculations through the valid signal.

3. The encoder according to claim 1, characterized in that: The input of the ROM storage module is a ROM address signal and an enable signal, and the output is parity check matrix information and a switching column weight signal; the module stores parity check matrix information for all code rates, and the parity check matrix information is stored according to the design scheme.

4. The encoder according to claim 3, characterized in that: The design scheme is: According to the compressed form of the parity check matrix corresponding to each code rate in the DVB-S2 standard, first determine the number of rows q of the matrix compression form, use the initial value provided in the appendix of the DVB-S2 standard file as the dividend, and perform a remainder operation with the q value of each code rate as the divisor to obtain the corresponding row information; After obtaining the row information, perform an integer division operation on the initial value in the appendix. Using the row information as a reference, divide the initial value by the corresponding row information to obtain the column information of the parity check matrix. At the same time, in the parity check matrices of different code rates, the weight of each column is different, and a flag bit is added before the row and column information to determine whether to switch the column weight signal.

5. The encoder according to claim 4, characterized in that: The parity-check matrix is divided into a matrix H1 with a larger column weight and a matrix H2 with a smaller column weight based on a threshold. In the H1 matrix, except for the last bit, the matrix flag bits of all columns are 0. In the H2 matrix, except for the last bit, the matrix flag bits of all the remaining columns are 1. When the flag bit jumps from 0 to 1, it indicates that the calculation of the H1 part of the matrix is completed and the calculation enters the H2 part; when the flag bit jumps from 1 to 0, it indicates that the calculation of the H2 matrix is completed.

6. The encoder according to claim 1, wherein: The parity-check calculation module includes a matrix calculation unit, a RAM read-write storage unit, and a recursive output unit, wherein: The matrix calculation unit takes the parity-check matrix information, the information-bit information, and the intermediate variable information as inputs, and outputs the updated intermediate variable information and the matrix row XOR sum information; according to the row information in the matrix information, this unit reads the corresponding intermediate variable information from the RAM, performs barrel shifting on the information-bit information through the column information in the matrix information, and calculates the updated intermediate variable information. The RAM read-write storage unit takes the row information in the matrix information and the updated intermediate variable information as inputs, and outputs the intermediate variable information; it reads the corresponding intermediate variable information according to the row information, and after the intermediate variable information is updated, it writes it back to the original address. The recursive output unit takes the matrix row XOR sum information and the intermediate variable information as inputs, and outputs the parity-check information; after the intermediate variable is updated, it performs recursive calculation on the matrix row XOR sum information, and after the recursive calculation ends, it calculates the parity-check information.

7. The encoder according to claim 6, wherein: The recursive output unit adopts a recursive structure with a parallelism of 8.

8. A coding method using the encoder according to any one of claims 1-7, characterized in that, It includes the steps of: 1) After the ROM control module receives the frame header signal and the code rate signal, it selects the corresponding data matrix column weight and reads the corresponding ROM. 2) Read the parity-check matrix information corresponding to the code rate from the corresponding ROM storage module. 3) The parity-check calculation module calculates the parity-check bit information according to the read parity-check matrix information and the information-bit information to complete the calculation of the intermediate variable information and the parity-check information.

9. The method according to claim 8, wherein: Step 1) specifically includes: 1a) After detecting the frame header signal, the counter in the control module starts to work, selects the corresponding column weight through the code rate signal. After every 360-bit information-bit information is input, the counting length of the counter is the corresponding column weight. After receiving the valid switching column weight signal, the matrix column weight is changed to 3. 1b) The ROM control module outputs the generated ROM read address signal and ROM enable signal to the ROM storage module to read the parity-check matrix information. 1c) The ROM control module determines whether to perform circular shifting on the current input signal and whether to perform subsequent matrix calculations through the valid signal.

10. The method according to claim 8, characterized in that: In step 2), the ROM storage module stores at most only 1 BRAM resource for each code rate, and the implementation is as follows: According to the LDPC parity check matrix in the DVB-S2 standard, the systematic bit part in the matrix can be divided into 2 matrices, which have different column weights; except for the last bit in the previous matrix, the matrix flag bits of all columns are 0, while in the latter matrix, except for the last bit, the matrix flag bits of all columns are 1; When the flag bit jumps from 0 to 1, it means that the previous matrix part has been calculated, and it is necessary to switch the column weight to 3 for the counter in the ROM control module.

Images