Device and signal synchronization system

Abstract

The invention relates to a device and a signal synchronization system. For each device connected to the same bus, the device sends a device synchronization signal to the bus and detects a bus synchronization signal of the bus after the device synchronization signal is sent; wherein when the equipment synchronization signals of the equipment and the other equipment are low-level signals, the bus synchronization signal is a low-level signal; when the equipment synchronization signal of at least one of the equipment and the other equipment is a high-level signal, the bus synchronization signal is a high-level signal; then, under the condition that the detected bus synchronization signal is a low-level signal, performing signal synchronization processing on each device; wherein the signal synchronization comprises power frequency synchronization and carrier synchronization. Namely, all devices are connected to a synchronous bus, and power frequency and carrier synchronization is achieved at the same time. The master device and the slave device do not need to be distinguished, the defects of master-slave synchronization are overcome, the accuracy and stability of signal synchronization are improved, and the signal synchronization effect is improved; and the cost can be saved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technologies, and particularly to a device and a signal synchronization system. Background Art

[0002] The parallel operation performance of off-grid inverters mainly depends on the suppression effect of circulating current. One of the main factors affecting the circulating current is the consistency of the amplitudes, phases, and carriers of the output voltages of each inverter. Therefore, the performance of power frequency synchronization and carrier synchronization between inverters is crucial.

[0003] In traditional synchronization methods, a power frequency synchronization bus and a carrier synchronization bus are set between multiple parallel inverters, and the master inverter among the multiple inverters sends a power frequency synchronization signal to the power frequency synchronization bus and a carrier synchronization signal to the carrier synchronization bus, so that each slave inverter can correct its own power frequency phase angle and carrier according to the power frequency synchronization signal and the carrier synchronization signal.

[0004] However, in traditional synchronization methods, the master-slave synchronization strategy has the problem of poor synchronization effect. Summary of the Invention

[0005] Based on this, it is necessary to provide a device and a signal synchronization system that can improve the signal synchronization effect of a parallel system for the above technical problems.

[0006] In a first aspect, this application provides a device. The device and other devices are commonly connected to the same bus.

[0007] The device is configured to send a device synchronization signal to the bus and detect the bus synchronization signal after sending the device synchronization signal; wherein, when the device synchronization signals of the device and other devices are both low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device synchronization signal of the device and other devices that is a high-level signal, the bus synchronization signal is a high-level signal.

[0008] The device is further configured to perform signal synchronization processing when the detected bus synchronization signal is a low-level signal; wherein the signal synchronization includes power frequency synchronization and carrier synchronization.

[0009] In one embodiment, the device synchronization signal is generated by the device according to the power frequency signal and the carrier signal of the device.

[0010] In one embodiment, the device is further configured to

[0011] generate a first device synchronization signal if the power frequency phase angle of the power frequency signal corresponding to the device is 0° and the carrier count of the carrier signal is 0;

[0012] If the power frequency phase angle of the power frequency signal corresponding to the device is 180° and the carrier count of the carrier signal is 0, a second device synchronization signal is generated;

[0013] Among them, the first device synchronization signal is a low-level signal, and the second device synchronization signal is a high-level signal.

[0014] In one embodiment, the device is further configured to determine the device type of the device when the bus synchronization signal is a low-level signal;

[0015] When the device type is not the reference device, signal synchronization processing is performed on the device;

[0016] Among them, the reference device represents that the generation time of the low level of the device synchronization signal of the device is later than the generation time of the low level of the device synchronization signals of other devices.

[0017] In one embodiment, the device is further configured to

[0018] If the power frequency phase angle of the device is within a preset first power frequency phase angle range, the power frequency phase angle is reduced by a preset first phase step, and the carrier period of the device is increased by a preset period step; where the first phase step is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device; or,

[0019] If the power frequency phase angle of the device is within a preset second power frequency phase angle range, the power frequency phase angle is increased by a preset second phase step, and the carrier period of the device is reduced by a preset period step; where the second phase step is the difference between the preset power frequency phase angle period and the preset phase difference; the preset phase difference is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device; or,

[0020] If the power frequency phase angle of the device is within a preset third power frequency phase angle range, the power frequency phase angle is reduced by a preset third phase step, and the carrier period of the device remains unchanged; where the third phase step is less than the preset phase step threshold; or,

[0021] If the power frequency phase angle of the device is within a preset fourth power frequency phase angle range, the power frequency phase angle is increased by a preset fourth phase step, and the carrier period of the device remains unchanged; where the fourth phase step is less than the preset phase step threshold.

[0022] In one embodiment, the device is further configured to determine the delay duration between the device synchronization signal of the device and the bus synchronization signal;

[0023] If the delay duration is within a preset delay duration range, it is determined that the device type of the device is the reference device.

[0024] In one embodiment, the device and other devices are all inverters or rectifiers, and the devices are connected in parallel with each other.

[0025] In a second aspect, the present application further provides a signal synchronization system, which includes a plurality of devices connected in parallel, and each device is commonly connected to the same bus;

[0026] Each device is respectively configured to send a device synchronization signal to the bus;

[0027] The bus is configured to generate a bus synchronization signal according to the device synchronization signals sent by each device, so that each device can detect the bus synchronization signal; wherein, when the device synchronization signals of each device are all low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device among the devices whose device synchronization signal is a high-level signal, the bus synchronization signal is a high-level signal;

[0028] Each device is respectively further configured to detect the bus synchronization signal of the bus after sending the device synchronization signal, and in the case where the detected bus synchronization signal is a low-level signal, perform signal synchronization processing respectively; wherein, the signal synchronization includes power frequency synchronization and carrier synchronization.

[0029] In one embodiment, the device synchronization signal is generated according to the power frequency signal and carrier signal of each respective device.

[0030] In one embodiment, the plurality of devices connected in parallel are all inverters or rectifiers.

[0031] In the above-mentioned device and signal synchronization system, for each device connected to the same bus, the device sends a device synchronization signal to the bus and then detects the bus synchronization signal of the bus after sending the device synchronization signal. Then, when the detected bus synchronization signal is a low-level signal, each device performs signal synchronization processing; among them, when the device synchronization signals of the device and other devices are all low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device among the device and other devices whose device synchronization signal is a high-level signal, the bus synchronization signal is a high-level signal; signal synchronization includes power frequency synchronization and carrier synchronization. That is to say, in the embodiments of the present application, by connecting each device to the same synchronization bus, and each device separately sends a device synchronization signal to the bus, and when the device synchronization signals sent by each device are all low-level signals, the bus is triggered to generate a bus synchronization signal; thus, each device can synchronously correct the power frequency phase angle and carrier period of its own device when the bus synchronization signal is a low-level signal; compared with the traditional master-slave synchronization scheme, in the present application, there is no need to distinguish between the master device and the slave device connected to the same bus, but all devices send device synchronization signals to the bus to trigger the bus synchronization signal, which can avoid the problem of the loss or inaccuracy of the synchronization signal caused by the failure of the master device, improve the accuracy and stability of signal synchronization, improve the signal synchronization effect, and further improve the circulating current suppression effect. In addition, in the present application, only one synchronization bus needs to be set up to achieve the synchronization of the power frequency and carrier between each device connected in parallel. Compared with the traditional method of separately setting up a power frequency synchronization bus and a carrier synchronization bus, it can save costs and improve the comprehensive performance of the parallel system. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic structural diagram of a signal synchronization system in an embodiment;

[0034] Figure 2 It is a schematic diagram of the complete process of a device performing signal synchronization processing in an embodiment;

[0035] Figure 3 It is a schematic diagram of the output of a device synchronization signal in an embodiment;

[0036] Figure 4 It is a schematic diagram of the level logic of signal synchronization in an embodiment;

[0037] Figure 5 Schematic diagram of level logic for signal synchronization in another embodiment;

[0038] Figure 6 Schematic diagram of the structure of a signal synchronization system composed of inverters in one embodiment. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] With the continuous development of the power grid system, a single device can no longer meet the large-capacity requirements of the power grid. Instead, a large-capacity system composed of multiple devices in parallel is used. During the parallel operation of multiple devices, its parallel operation performance mainly depends on the suppression effect of circulating current. One of the main factors affecting the circulating current is the consistency of the amplitude, phase and carrier of the output voltages of each device. Therefore, the performance of power frequency synchronization and carrier synchronization between devices is crucial.

[0041] Exemplarily, for off-grid inverters, when synchronizing signals of multiple parallel off-grid inverters, a power frequency synchronization bus and a carrier synchronization bus are usually set between the multiple parallel inverters, and the main inverter among the multiple inverters sends a power frequency synchronization signal to the power frequency synchronization bus and a carrier synchronization signal to the carrier synchronization bus, so that each slave inverter can correct its own power frequency phase angle and carrier according to the power frequency synchronization signal and the carrier synchronization signal. That is, the currently relatively common synchronization scheme is that the inverters share the power frequency bus and the carrier bus, and one inverter sends an edge level signal with power frequency and carrier synchronization information to the bus, and all inverters receive the synchronization signal and correct their own power frequency phase angle and carrier according to the synchronization signal.

[0042] The main problems existing in this synchronization scheme include:

[0043] 1) There is a master-slave relationship between the inverters. After the master fails, a new master needs to be re-competed. During this period, the loss of the synchronization signal may cause an increase in the circulating current between the inverters, affecting the stable operation of the parallel system;

[0044] 2) Excessive dependence on the master. Once there is a problem with the synchronization signal sending circuit of the master, all slave devices will lose synchronization;

[0045] 3) A synchronization bus circuit is required for power frequency synchronization and carrier synchronization respectively, increasing the circuit cost and software resources.

[0046] To overcome the above problems, the present application proposes a device and a signal synchronization system. In this signal synchronization system, there is no distinction between master and slave devices, and the status of each device is equal. Moreover, the stable operation of the system is not affected even if new devices are added during system operation, improving the reliability. In addition, using this signal synchronization system reduces one synchronization bus. Only one synchronization bus can be used to achieve power frequency and carrier synchronization, and the synchronization accuracy is relatively high, the effect of suppressing circulating current is good, which can save costs and improve the parallel operation performance.

[0047] The signal synchronization system provided by the embodiment of the present application is shown as Figure 1 follows. Among them, multiple devices connected in parallel are respectively connected to the same synchronization bus. Each device connected to the synchronization bus sends a device synchronization signal (such as a synchronization level signal) to the bus through its respective output interface, and also detects the bus synchronization signal of the bus through its respective input interface. For the bus, when the device synchronization signals of each device are all low-level signals, a low-level bus synchronization signal is generated. This low-level bus synchronization signal is used to instruct each device connected to the bus to perform power frequency synchronization and carrier synchronization respectively; thereby realizing signal synchronization between the devices connected in parallel and suppressing circulating current.

[0048] Exemplarily, when the device synchronization signals of all devices are all low-level signals, the bus synchronization signal is low level; when there is at least one device whose device synchronization signal is high level, the bus synchronization signal is high level; wherein, when the bus synchronization signal is low level, it can be used to trigger each device to perform signal synchronization.

[0049] Exemplarily, the device may include, but is not limited to, any type of conversion device such as an inverter, a rectifier, or an energy storage device, etc. The type of the device is not specifically limited in this embodiment.

[0050] In an exemplary embodiment, for each device connected to the same bus, the device can be used to send a device synchronization signal to the bus and detect the bus synchronization signal of the bus after sending the device synchronization signal; wherein, when the device synchronization signals of the device and other devices are all low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device among the device and other devices whose device synchronization signal is a high-level signal, the bus synchronization signal is a high-level signal; the device can also be used to perform signal synchronization processing on the device when the detected bus synchronization signal is a low-level signal; wherein, the signal synchronization includes power frequency synchronization and carrier synchronization.

[0051] Exemplarily, during the operation of the device, the device synchronization signal can be sent to the bus in real time. When the device synchronization signals sent by each device received by the bus are all low-level signals, a low-level bus synchronization signal can be generated.

[0052] It should be noted that in this example, the correspondence between the device synchronization signal and the bus synchronization signal is not limited, and the signal level state of the bus synchronization signal used to trigger signal synchronization processing is also not limited. For example: when each device connected to the bus sends a device synchronization signal with a high level, a bus synchronization signal with a low level can also be generated, and the bus synchronization signal with a low level is used to trigger each device to perform signal synchronization processing. Another example: when each device connected to the bus sends a device synchronization signal with a low level, a bus synchronization signal with a high level can also be generated, and the bus synchronization signal with a high level is used to trigger each device to perform signal synchronization processing.

[0053] Exemplarily, for each device, it can send a device synchronization signal at a preset signal position according to its own power frequency signal and carrier signal, and start detecting the bus synchronization signal after sending the device synchronization signal; for example: the device can send a device synchronization signal to the bus when the power frequency signal passes through zero and the carrier signal passes through zero; then, after the power frequency passes through zero and the carrier passes through zero, start detecting the bus synchronization signal.

[0054] Exemplarily, the device can detect the bus synchronization signal at a preset position of the carrier signal; for example, it can detect the bus synchronization signal at the 1 / 4 carrier position of each carrier cycle; that is to say, after the device sends the device synchronization signal, at the 1 / 4 carrier position of the first carrier cycle, detect the bus synchronization signal. If the bus synchronization signal is not detected at this time, at the 1 / 4 carrier position of the second carrier cycle, continue to detect the bus synchronization signal. If the bus synchronization signal is still not detected at this time, at the 1 / 4 carrier position of the third carrier cycle, continue to detect the bus synchronization signal; and so on until the bus synchronization signal is detected.

[0055] Exemplarily, when the device detects that the bus synchronization signal is a low-level signal, it indicates that all devices connected to the bus at this time have sent device synchronization signals with a low level. At this time, based on this bus synchronization signal, signal synchronization processing can be performed on the power frequency and carrier of the device itself, so that the power frequency signal and carrier signal of the device are consistent with those of other devices connected to the bus.

[0056] Exemplarily, when the device is the last device among all devices to send the device synchronization signal in the preset signal state, this device can be used as a reference device; for the reference device, it can not adjust the power frequency signal and carrier signal. That is to say, the power frequency signals of other devices need to be aligned with the power frequency signal of this reference device, and the carrier signals of other devices also need to be aligned with the carrier signal of this reference device.

[0057] Exemplarily, when the device is not the reference device, the power frequency signal and the carrier signal of the device can be adjusted based on the bus synchronization signal so that the power frequency signal of the device is aligned with the power frequency signal of the reference device and the carrier signal of the device is aligned with the carrier signal of the reference device.

[0058] Exemplarily, when the device is not the reference device, it can be shown that the signal of the device is ahead of the reference device. At this time, it is necessary to slow down the signal speed of the device. For example, the power frequency phase angle of the power frequency signal of the device can be gradually approximated to the power frequency phase angle of the reference device by reducing the power frequency phase angle of the power frequency signal of the device to achieve power frequency synchronization; and the carrier synchronization can be achieved by increasing the carrier period of the device, that is, increasing the carrier count of the device to gradually approximate the carrier count of the reference device.

[0059] The devices connected to the bus can send device synchronization signals to the bus and detect the bus synchronization signal of the bus after sending the device synchronization signals. Then, when the detected bus synchronization signal is at a low level, signal synchronization processing is performed on each device; among them, when the device synchronization signals of the device and other devices are all low-level signals, the bus synchronization signal is at a low level; when there is at least one device synchronization signal of the device and other devices that is at a high level, the bus synchronization signal is at a high level; signal synchronization includes power frequency synchronization and carrier synchronization. That is to say, in the embodiments of the present application, by connecting each device to the same synchronization bus, and each device sends a device synchronization signal to the bus respectively, and when the device synchronization signals sent by each device are all low-level signals, the bus is triggered to generate a bus synchronization signal; thus, each device can synchronously correct the power frequency phase angle and carrier period of its own device when the bus synchronization signal is at a low level; compared with the traditional master-slave synchronization scheme, in the present application, there is no need to distinguish between the master device and the slave device connected to the same bus, but all devices send device synchronization signals to the bus to trigger the bus synchronization signal, which can avoid the problem of loss or inaccuracy of the synchronization signal caused by the failure of the master device, improve the accuracy and stability of signal synchronization, improve the signal synchronization effect, and further improve the circulating current suppression effect. In addition, by using the method in the present application, only one synchronization bus needs to be set to achieve the synchronization of the power frequency and carrier between the devices connected in parallel. Compared with the traditional method of separately setting the power frequency synchronization bus and the carrier synchronization bus, it can save costs and improve the comprehensive performance of the parallel system.

[0060] In an exemplary embodiment, for each device connected to the bus, the device can also generate a device synchronization signal according to its own power frequency signal and carrier signal and send the device synchronization signal to the bus.

[0061] Exemplarily, the industrial frequency phase angle of the industrial frequency signal of the device can be detected, and the carrier count of the carrier signal of the device can be detected; for example: the carrier count of the carrier signal can be obtained by detecting the count of the carrier counter. Exemplarily, when detecting the industrial frequency phase angle of the device, the corresponding industrial frequency phase angle can also be determined by the detected carrier count; for example: the industrial frequency phase angle corresponding to one carrier signal period can be determined according to the period of the industrial frequency signal and the period of the carrier signal, and even the industrial frequency phase angle corresponding to one carrier count can be determined; based on this, the corresponding industrial frequency phase angle can be determined according to the currently detected carrier count.

[0062] Exemplarily, when the industrial frequency phase angle of the industrial frequency signal is a preset angle and the carrier count of the carrier signal is a preset value, a device synchronization signal can be sent to the bus; wherein, the device synchronization signal can include a device synchronization signal with a preset signal state, or can also include a device synchronization signal with other signal states except the preset signal state. It should be noted that in the case where the device synchronization signal includes device synchronization signals with multiple different signal states, at least one of the industrial frequency phase angle and the carrier count corresponding to the device synchronization signals with different signal states is different.

[0063] Exemplarily, when the industrial frequency phase angle of the industrial frequency signal is 0° and the carrier count of the carrier signal is 0, the device can generate a first device synchronization signal and send the first device synchronization signal to the bus; when the industrial frequency phase angle of the industrial frequency signal is 180° and the carrier count of the carrier signal is 0, the device can generate a second device synchronization signal and send the second device synchronization signal to the bus.

[0064] Exemplarily, the first device synchronization signal can be a device synchronization signal in a low-level signal state, and the second device synchronization signal can be a device synchronization signal in a high-level signal state; when all the device synchronization signals sent by the devices to the bus are in a low-level signal state, the bus can generate a low-level bus synchronization signal.

[0065] In this embodiment, each device connected to the bus can detect the industrial frequency signal and the carrier signal of its own device, generate a device synchronization signal according to the industrial frequency signal and the carrier signal, and send the device synchronization signal to the bus; that is, when its own signal is in a specific position, send the device synchronization signal to the bus; in this way, it can be determined that all devices connected to the bus can send the device synchronization signal to the bus when their own signals are in the same specific position, so that the bus can generate a bus synchronization signal based on the signal state of the device synchronization signal of each device, thereby triggering each device to perform signal synchronization; adopting this method can achieve signal synchronization for each device connected to the bus without distinguishing between master and slave devices, solve various drawbacks of the master-slave synchronization scheme, improve the accuracy and stability of signal synchronization, and further improve the signal synchronization effect.

[0066] In an exemplary embodiment, for each device connected to the bus, the device may determine the device type when the detected bus synchronization signal is a low-level signal; and perform signal synchronization processing on the device when the device type is not the reference device.

[0067] Among them, the device type may include a reference device and a non-reference device. The reference device may indicate that the generation time of the low level of the device synchronization signal of this device is later than that of the device synchronization signals of other devices; that is, among all devices, the time to send the device synchronization signal in the preset signal state is the latest.

[0068] Exemplarily, the device can be determined as a reference device or a non-reference device according to the duration between the device sending the device synchronization signal in the preset signal state and detecting the bus synchronization signal, or the power frequency phase angle corresponding to this duration; for example: when this duration is less than or equal to the preset duration threshold, or the power frequency phase angle corresponding to this duration is less than or equal to the preset phase angle threshold, it can be determined that this device is a reference device; otherwise, it can be determined that this device is a non-reference device.

[0069] Exemplarily, for the moment corresponding to the detected bus synchronization signal, it can be the moment when the bus synchronization signal is detected at a preset position, such as the 1 / 4 carrier cycle position, or the actual generation moment of the bus synchronization signal; for example: in the device, a detection circuit for detecting the headquarter synchronization signal can be set up, and through this detection circuit, the actual generation moment of the bus synchronization signal can be recorded; when the bus synchronization signal is detected at the 1 / 4 carrier cycle position, the actual generation moment of the bus synchronization signal detected by this detection circuit can be obtained, and the device type of the device can be determined based on the actual generation moment of the bus synchronization signal.

[0070] Exemplarily, when the device type is a reference device, the device may not need to adjust the power frequency signal and the carrier signal, that is, it serves as a reference in signal synchronization.

[0071] Exemplarily, when the device type is not a reference device, the power frequency signal and the carrier signal of this device can be adjusted, so that the power frequency signal and the carrier signal of this device are consistent with those of the reference device, and signal synchronization between this device and the reference device is achieved.

[0072] Exemplarily, when synchronizing the signals of the device based on the bus synchronization signal, signal synchronization can be performed based on the power frequency phase angle corresponding to the bus synchronization signal and a preset power frequency phase angle range; that is, when the power frequency phase angle corresponding to the bus synchronization signal is within different preset power frequency phase angle ranges, different signal synchronization strategies can be adopted to adjust the power frequency signal and the carrier signal of the device.

[0073] Exemplarily, when the power frequency phase angle of the device is within the preset first power frequency phase angle range, the power frequency phase angle can be reduced by a preset first phase step, and the carrier period of the device can be increased by a preset period step; wherein, the first phase step is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device. The first power frequency phase angle range can be used to represent that the power frequency phase angle is greater than 0 and less than or equal to the first power frequency phase angle threshold. For example, the first power frequency phase angle range can be (0, 5]°. That is, when the bus synchronization signal is detected, the device only leads the reference device by a small part; at this time, by reducing the power frequency phase angle θ of the device by the phase difference Δθ between the device and the reference device, that is, θ′ = θ - Δθ, the power frequency phase angle of the device can be made to be consistent with the power frequency phase angle of the reference device. In addition, for the carrier period T of the device, the period step can be slightly increased, such as T’ = T + 1, so that the carrier signal of the device slows down slightly to approach the carrier signal of the reference device.

[0074] Exemplarily, when the power frequency phase angle of the device is within the preset second power frequency phase angle range, the power frequency phase angle can be increased by a preset second phase step, and the carrier period of the device can be reduced by a preset period step; wherein, the second phase step is the difference between the preset power frequency phase angle period and the preset phase difference; the preset phase difference is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device. The second power frequency phase angle range can be used to represent that the power frequency phase angle is greater than or equal to the second power frequency phase angle threshold and less than the power frequency phase angle period. For example, the second power frequency phase angle range can be [355, 360)°. That is, when the bus synchronization signal is detected, the device only lags behind the reference device by a small part; at this time, by increasing the power frequency phase angle of the device by the second phase step, that is, θ′ = θ + (360 - Δθ), the power frequency phase angle of the device can be made to be consistent with the power frequency phase angle of the reference device. In addition, for the carrier period T of the device, the period step can be slightly reduced, such as T’ = T - 1, so that the carrier signal of the device speeds up slightly to approach the carrier signal of the reference device.

[0075] Exemplarily, when the industrial frequency phase angle of the device is within a preset third industrial frequency phase angle range, the industrial frequency phase angle can be reduced by a preset third phase step while keeping the carrier period of the device unchanged. The third industrial frequency phase angle range can represent that the industrial frequency phase angle is greater than the first industrial frequency phase angle threshold and less than or equal to the third industrial frequency phase angle threshold, and the third industrial frequency phase angle threshold is less than the second industrial frequency phase angle threshold. For example, the third industrial frequency phase angle range can be (5, 180]°. That is, when the bus synchronization signal is detected, the device leads the reference device by a relatively large margin. At this time, through industrial frequency tracking, that is, reducing the industrial frequency phase angle by the third phase step, the device can gradually approach the reference device. The third phase step can be set according to the frequency of the industrial frequency signal to ensure that the change in the industrial frequency during the industrial frequency tracking process is neither too large nor too small. For example, the third phase step can be less than a preset phase step threshold, such as the preset phase step threshold can be 5°, 10°, etc.

[0076] In addition, during the industrial frequency tracking process, the synchronization adjustment of the carrier signal can be temporarily suspended. When the phase difference between the industrial frequency phase angle after tracking and the reference device is within the first industrial frequency phase angle range, the synchronization strategy corresponding to the first industrial frequency phase angle range can be used for industrial frequency signal synchronization and carrier signal synchronization.

[0077] Exemplarily, when the industrial frequency phase angle of the device is within a preset fourth industrial frequency phase angle range, the industrial frequency phase angle can be increased by a preset fourth phase step while keeping the carrier period of the device unchanged. The fourth industrial frequency phase angle range can represent that the industrial frequency phase angle is greater than the third industrial frequency phase angle threshold and less than the second industrial frequency phase angle threshold. For example, the fourth industrial frequency phase angle range can be (180, 355)°. That is, when the bus synchronization signal is detected, the device lags behind the reference device by a relatively large margin. At this time, through industrial frequency tracking, that is, increasing the industrial frequency phase angle by the fourth phase step, the device can gradually approach the reference device. The fourth phase step can be set according to the frequency of the industrial frequency signal to ensure that the change in the industrial frequency during the industrial frequency tracking process is neither too large nor too small. The fourth phase step can be the same as or different from the third phase step. For example, the fourth phase step can also be less than a preset phase step threshold, such as the preset phase step threshold can be 5°, 10°, etc. It should be noted that the preset phase step threshold corresponding to the fourth phase step can be the same as or different from the preset phase step threshold corresponding to the above third phase step. This is not specifically limited in this embodiment.

[0078] In addition, during the industrial frequency tracking process, the synchronization adjustment of the carrier signal can be temporarily suspended. When the phase difference between the industrial frequency phase angle after tracking and the reference device is within the second industrial frequency phase angle range, the synchronization strategy corresponding to the second industrial frequency phase angle range can be used for industrial frequency signal synchronization and carrier signal synchronization.

[0079] In this embodiment, for the devices connected to the bus, when the bus synchronization signal is at a low level, the device type of the device can be determined, and if the device type is not the reference device, signal synchronization processing can be performed on the device; where the reference device is used to represent that the generation time of the device synchronization signal of the device is the latest. That is to say, for multiple devices connected to the bus, during operation, each device may be the reference device with the latest generation of the device synchronization signal in the preset signal state, and when the device is the reference device, the signal of this reference device remains unchanged, and the signals of other devices are adjusted to achieve signal synchronization among devices; by adopting this method, it is possible to achieve signal synchronization for each device connected to the bus without distinguishing between master and slave devices, solve various drawbacks of the master-slave synchronization scheme, improve the accuracy and stability of signal synchronization, and thus improve the signal synchronization effect.

[0080] In an exemplary embodiment, for a device connected to the bus, the device can determine the delay duration between the device synchronization signal of the device and the bus synchronization signal, and if the delay duration is within the preset delay duration range, determine that the device type of the device is the reference device.

[0081] In this example, the detection moment of the bus synchronization signal can be the actual generation moment of the bus synchronization signal, that is, the moment when the head office synchronization signal is actually detected by the detection circuit in the device.

[0082] Exemplarily, when the moment of sending the device synchronization signal of the device and the actual generation moment of the bus synchronization signal are determined, the delay duration between the device synchronization signal of the device and the bus synchronization signal can be determined according to the moment of sending the device synchronization signal and the actual generation moment of the bus synchronization signal.

[0083] Among them, the preset delay duration can be the delay duration of the hardware circuit, that is, for the reference device, the hardware circuit delay between sending the device synchronization signal to the bus and actually detecting the bus synchronization signal.

[0084] Based on this, when the delay duration between the device synchronization signal and the bus synchronization signal of the device is determined, the delay duration can be compared with the preset delay duration. If the delay duration is within the preset delay duration range, it can be indicated that the device is the device that sends the device synchronization signal latest, that is, it can be used as the reference device; otherwise, it can be indicated that the device is not the device that sends the device synchronization signal latest, that is, it is not the reference device. Among them, the preset delay duration range can be a range determined based on the preset delay duration. For example: a certain delay error is added and / or subtracted based on the preset delay duration to obtain the preset delay duration range, etc. For example, when the preset delay duration is 5 milliseconds, the preset delay duration range can be 5 ± 1 millisecond, that is, [4, 6] milliseconds.

[0085] In this embodiment, when determining the device type, the delay duration between the device synchronization signal and the bus synchronization signal of the device can be determined, and when the delay duration is within the preset delay duration range, the device type of the device can be determined as the reference device. By using the method in this example, the accuracy of device type judgment can be improved, thereby improving the accuracy of signal synchronization between devices and the signal synchronization effect.

[0086] In an exemplary embodiment, taking the device as an inverter as an example, for multiple parallel-connected inverters connected to the synchronization bus, the specific implementation process of each inverter during signal synchronization can be as Figure 2 shown, which may include: by detecting the power frequency signal and the carrier signal of the inverter, and when the power frequency phase angle is 180° and the carrier count is 0, the device synchronization signal is set to high level, and when the power frequency phase angle is 0° and the carrier count is 0, the device synchronization signal is pulled to low level, refer to Figure 3 shown; then, at each 1 / 4 carrier period (the carrier period is 2Ts) position (such as Figure 4 at the t0 moment in), detect the falling edge of the bus synchronization signal of the synchronization bus, that is, determine whether the bus synchronization signal is a low-level signal; if the falling edge of the bus synchronization signal is detected, determine whether the inverter is the reference inverter. If so, the inverter does not need to adjust the power frequency signal and the carrier signal; if not, adjust the power frequency signal and the carrier signal of the inverter according to the power frequency phase angle corresponding to when the bus synchronization signal is detected and different preset power frequency phase angle ranges.

[0087] Refer to Figure 4As shown, when the inverter 1 and the inverter 2 are relatively close to each other, assuming that the inverter 2 reaches the power frequency phase angle of 0° and the carrier count of 0 first, and preferentially triggers the device synchronization signal with a low level, and the inverter 1 reaches the power frequency phase angle of 0° and the carrier count of 0 later, and triggers the device synchronization signal with a low level. Due to the hardware delay t1, therefore, relative to the inverter 1 (i.e., the reference device), after the delay t1, the falling edge of the bus synchronization signal can be detected; for the inverter 2, the actual duration for detecting the falling edge of the bus synchronization signal is t; at this time, the phase difference Δθ between the inverter 2 and the inverter 1, that is, the phase difference Δθ between the device synchronization signal of the inverter 2 and the device synchronization signal of the reference inverter 1 is the power frequency phase angle corresponding to the time difference △t, where △t = t - t1. T L is the carrier period.

[0088] In an actual application scenario, the actual generation duration of the falling edge of the bus synchronization signal can be obtained through the detection circuit in the inverter, that is, t1 is detected through the detection circuit in the inverter 1, and t is detected through the detection circuit in the inverter 2. Since the carrier period is known, the phase difference Δθ between the device synchronization signal of the inverter 2 and the device synchronization signal of the reference inverter 1 can be calculated.

[0089] For the case where the inverter 1 and the inverter 2 are relatively close to each other, for the inverter 2, at the moment t0, the power frequency phase angle at the moment t0 can be reduced by Δθ to make the power frequency phase angle of the inverter 2 consistent with the power frequency phase angle of the inverter 1, that is, to achieve the power frequency synchronization between the inverter 2 and the inverter 1; in addition, increase the carrier period of the inverter 2 by 1, so that the carrier signal of the inverter 2 gradually approaches the carrier signal of the inverter 1, and achieve the carrier synchronization between the inverter 2 and the inverter 1.

[0090] It should be noted that when the inverter 2 and the inverter 1 are very close to each other, the inverter 2 may detect the falling edge of the bus synchronization signal within the first carrier period, as Figure 4 shown; and when the inverter 2 and the inverter 1 are relatively close or far from each other, the inverter 2 can also detect the falling edge of the bus synchronization signal within the second, third, fourth, etc. other carrier periods; referring to Figure 5 shown, which shows the situation where the inverter 2 detects the falling edge of the bus synchronization signal within its second carrier period.

[0091] Exemplarily, when the falling edge of the bus synchronization signal is detected, when the power frequency phase angle θ of the inverter is in the range of (0, 5]°, the power frequency phase angle θ of the inverter is reduced by the phase difference Δθ between the inverter and the reference inverter, i.e., θ′ = θ - Δθ, and the carrier period of the inverter is increased by a preset period step, i.e., T’ = T + 1; when the power frequency phase angle θ is in the range of [355, 360)°, the power frequency phase angle θ of the inverter is increased by a second phase step, i.e., θ′ = θ + (360 - Δθ), and the carrier period of the inverter is reduced by a preset period step, i.e., T’ = T - 1; when the power frequency phase angle θ is in the range of (5, 180]°, the power frequency phase angle θ of the inverter is reduced by a third phase step, i.e., θ′ = θ - θ L , the carrier period of the inverter remains unchanged; when the power frequency phase angle θ is in the range of (180, 355)°, the power frequency phase angle θ of the inverter is increased by a fourth phase step, i.e., θ′ = θ + θ L , and the carrier period of the inverter remains unchanged.

[0092] Exemplarily, in order to accurately capture the delay between the falling edge of the device synchronization signal of the device and the falling edge of the bus synchronization signal, for a device using the c2000 series Digital Signal Process (DSP), the eCap module and the ePWM module can be used for clock synchronization to achieve this. In addition, for the delay of the hardware circuit, it can be obtained in advance by combining the device manual with calculations and actual measurements. Furthermore, when setting the detection position of the bus synchronization signal, such as 1 / 4 carrier period, it is necessary to ensure that the detection moment is greater than the delay of the hardware circuit, so as to ensure that the reference device can detect the bus synchronization signal after sending the device synchronization signal.

[0093] In an exemplary embodiment, a signal synchronization system is provided. The system includes a plurality of devices connected in parallel, and each device is commonly connected to the same bus.

[0094] Among them, each device is respectively used to send a device synchronization signal to the bus; then, the bus is used to generate a bus synchronization signal according to the device synchronization signals sent by each device, so that each device can detect the bus synchronization signal; among them, when the device synchronization signals of each device are all low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device whose device synchronization signal is a high-level signal among each device, the bus synchronization signal is a high-level signal; furthermore, each device is respectively further used to detect the bus synchronization signal of the bus after sending the device synchronization signal, and in the case where the detected bus synchronization signal is a low-level signal, perform signal synchronization processing on its own device; among them, signal synchronization includes power frequency synchronization and carrier synchronization.

[0095] Exemplarily, the device synchronization signals of each device can be generated based on the power frequency signals and carrier signals of their respective devices. The specific implementation processes and methods can refer to the respective embodiments corresponding to the above devices, and will not be repeated here.

[0096] In addition, in one implementation, the above-mentioned multiple devices connected in parallel can all be inverters, as Figure 6 shown, or they can all be rectifiers; taking the inverter as an example, in this signal synchronization system, multiple inverters connected in parallel are commonly connected to the same synchronization bus. Each inverter outputs, through its respective synchronization signal output interface, the device synchronization signal generated based on the power frequency signal and carrier signal of its own device to the bus; and detects, through its respective synchronization signal input interface, the bus synchronization signal output by the bus, and synchronizes the power frequency phase angle and carrier count of its own device according to the bus synchronization signal.

[0097] Exemplarily, when the device synchronization signals of each inverter are all low-level signals, the bus synchronization signal is a low-level signal; when there is at least one inverter among the inverters whose device synchronization signal is a high-level signal, the bus synchronization signal is a high-level signal; based on this, when the bus synchronization signal is a low-level signal, each inverter can perform signal synchronization processing, so that the power frequency phase angles and carrier counts among the inverters are synchronized, thereby achieving the effect of suppressing circulating current.

[0098] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as the scope described in this specification.

[0099] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A device, characterized in that, The device is commonly connected to the same bus as other devices. The device is used to send a device synchronization signal to the bus and detect the bus synchronization signal of the bus after sending the device synchronization signal; wherein, when the device synchronization signals of the device and the other devices are both low-level signals, the bus synchronization signal is a low-level signal; when there is at least one device with a high-level device synchronization signal among the device and the other devices, the bus synchronization signal is a high-level signal. The device is further used to perform signal synchronization processing when the detected bus synchronization signal is a low-level signal; wherein, the signal synchronization includes power frequency synchronization and carrier synchronization.

2. The device according to claim 1, characterized in that, The device synchronization signal is generated by the device according to the power frequency signal and carrier signal of the device.

3. The device according to claim 2, characterized in that, The device is further used to generate a first device synchronization signal if the power frequency phase angle of the power frequency signal corresponding to the device is 0° and the carrier count of the carrier signal is 0; generate a second device synchronization signal if the power frequency phase angle of the power frequency signal corresponding to the device is 180° and the carrier count of the carrier signal is 0; wherein, the first device synchronization signal is a low-level signal and the second device synchronization signal is a high-level signal.

4. The device according to claim 1, wherein the device is further used to determine the device type of the device when the bus synchronization signal is a low-level signal; perform signal synchronization processing when the device type is not the reference device; wherein, the reference device represents that the generation time of the low level of the device synchronization signal of the device is later than the generation time of the low level of the device synchronization signal of the other devices.

5. The device according to claim 4, characterized in that, The device is further used to if the power frequency phase angle of the device is within a preset first power frequency phase angle range, reduce the power frequency phase angle by a preset first phase step and increase the carrier period of the device by a preset period step; wherein, the first phase step is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device; or, if the power frequency phase angle of the device is within a preset second power frequency phase angle range, increase the power frequency phase angle by a preset second phase step and reduce the carrier period of the device by a preset period step; wherein, the second phase step is the difference between a preset power frequency phase angle period and a preset phase difference; the preset phase difference is the phase difference between the device synchronization signal of the device and the device synchronization signal of the reference device; or, if the power frequency phase angle of the device is within a preset third power frequency phase angle range, reduce the power frequency phase angle by a preset third phase step and keep the carrier period of the device unchanged; wherein, the third phase step is less than a preset phase step threshold; or, if the power frequency phase angle of the device is within a preset fourth power frequency phase angle range, increase the power frequency phase angle by a preset fourth phase step and keep the carrier period of the device unchanged; wherein, the fourth phase step is less than the preset phase step threshold.

6. The device according to claim 4, wherein: the device is further configured to determine a delay duration between the device synchronization signal of the device and the bus synchronization signal; if the delay duration is within a preset delay duration range, determine that the device type of the device is the reference device.

7. The device according to claim 1, characterized in that, The device and the other devices are all inverters or rectifiers, and the devices are connected in parallel with each other.

8. A signal synchronization system, characterized in that, The system includes a plurality of devices connected in parallel, and each of the devices is commonly connected to the same bus; each of the devices is respectively configured to send a device synchronization signal to the bus; the bus is configured to generate a bus synchronization signal according to the device synchronization signals sent by each of the devices, so that each of the devices detects the bus synchronization signal; wherein, when the device synchronization signals of each of the devices are all low-level signals, the bus synchronization signal is a low-level signal; when at least one of the device synchronization signals of each of the devices is a high-level signal, the bus synchronization signal is a high-level signal; each of the devices is further respectively configured to detect the bus synchronization signal of the bus after the device synchronization signal is sent, and perform signal synchronization processing respectively when the detected bus synchronization signal is a low-level signal; wherein, the signal synchronization includes power frequency synchronization and carrier synchronization.

9. The signal synchronization system according to claim 8, characterized in that, The device synchronization signal is generated according to the power frequency signal and the carrier signal of the corresponding device.

10. The signal synchronization system according to claim 8, characterized in that, The plurality of devices connected in parallel are all inverters or rectifiers.

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