A linear gain adjustment circuit for CMOS image sensor chip

Abstract

The present application provides a linear gain adjustment circuit for a CMOS image sensor chip, comprising a current source array, a signal output terminal, a gain resistor array, and a trimming resistor array. The signal output terminal is connected to the current source array circuit; the gain resistor array is connected to the current source array circuit, the gain resistor array and the signal output terminal are connected in parallel, and the trimming resistor array is connected to the current source array circuit, the trimming resistor array and the gain resistor array are connected in parallel. The gain resistor array is configured to perform amplitude gain on the voltage at the signal output terminal based on its total resistance value and a variable total current, so that the signal output terminal outputs a voltage signal having a ramp-varying property. The trimming resistor array is configured to simulate the linear resistance variation of the gain resistor array and perform nonlinear offset adjustment on the total resistance value based on the linear resistance variation, thereby offsetting the nonlinear effect of the gain resistor array during actual gain processing and improving gain accuracy.

Description

Technical Field

[0001] The present application relates to the field of CMOS image sensor chip design, and in particular to a linear gain adjustment circuit for a CMOS image sensor chip. Background Art

[0002] Single-slope column ADCs (SS-ADCs) are widely used in high-speed CMOS image sensors. The SS-ADC structure is suitable for column ADC integration, offers low power consumption, and facilitates the implementation of correlated double sampling (CDS), balancing chip performance and area cost. The basic principle of an SS-ADC is to connect a reference ramp voltage and the pixel photosensitive voltage of a CMOS image sensor to the two inputs of a comparator. Controlled by a high-speed clock, the ramp changes monotonically, gradually approaching the pixel photosensitive voltage until the comparator flips and outputs a 1-bit decision result. This decision result is used to control the counter count: the counter begins counting when the comparison starts (when the reference ramp begins its monotonic change) and stops counting when the comparator flips. The count value stored in the counter at this time represents the quantized result of the corresponding pixel photosensitive voltage.

[0003] In fact, gain adjustment circuits are necessary in the practical application of CMOS image sensors: in low-light environments, the pixel photosensitive voltage difference is small. Using a gain adjustment circuit that outputs a large-slope ramp voltage will cause the comparator to make a judgment very quickly. On the one hand, this will lead to too small a count result of each column ADC. On the other hand, it will cause little or no difference in the count values between different areas. Ultimately, the image brightness is low, the contrast is low, and details are missing. When switching to a gain adjustment circuit that outputs a small-slope ramp voltage, the ramp changes slowly, the comparator's judgment result is delayed, the counter can record more data, the image brightness is improved, and subtle differences between different columns can also be reflected in the count value.

[0004] In the prior art, to improve the gain accuracy of the gain adjustment circuit, it is necessary to increase the number of control bits. For any gain adjustment array, a larger area and multiple resistor units are required, which increases the mismatch between the resistor units and aggravates the array gradient difference. In the actual gain process, each resistor unit will have a slight difference, resulting in inconsistent changes in the slope slope of the overall output, and the DNL and INL are not zero, which in turn introduces nonlinearity into the slope gain of the gain adjustment circuit and reduces the gain accuracy. Summary of the Invention

[0005] The main purpose of the embodiments of the present application is to provide a linear gain adjustment circuit for a CMOS image sensor chip, which can offset the nonlinear effect between resistor units during the actual gain process, thereby improving the gain accuracy of the gain adjustment circuit.

[0006] To achieve the above objectives, a first aspect of an embodiment of the present application provides a linear gain adjustment circuit for a CMOS image sensor chip, comprising:

[0007] A current source array, comprising a plurality of bit-by-bit controllable current source units, each of which is connected in parallel, and configured to output a variable total current;

[0008] A signal output terminal connected to a current source array circuit;

[0009] A gain resistor array, the gain resistor array is connected to the current source array circuit, the gain resistor array and the signal output terminal are connected in parallel, the gain resistor array includes a plurality of resistor units, and the resistor units are connected in parallel;

[0010] A trimming resistor array is connected to the current source array circuit, and the trimming resistor array and the gain resistor array are connected in parallel;

[0011] The gain resistor array is used to perform amplitude gain on the voltage at the signal output end according to the total resistance value and variable total current collected by each resistor unit in the on state, so that the signal output end outputs a voltage signal with a ramp-changing property;

[0012] The trimming resistor array is used to simulate the linear variation of the resistance of the gain resistor array and perform nonlinear offset adjustment on the total resistance value according to the linear variation of the resistance, so that the voltage gain of the gain resistor array to the signal output end is stable in the linear region.

[0013] Furthermore, in some embodiments, the linear gain adjustment circuit further includes:

[0014] A gain resistor decoding controller connected to a gain resistor array circuit;

[0015] A trimming resistor decoding controller connected to a trimming resistor array circuit;

[0016] The gain resistor decoding controller is used to receive the resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in a conductive state;

[0017] The resistor decoding controller is used to receive the resistor array control signal and dynamically simulate the linear change of the resistance value of the gain resistor array according to the resistor array control signal.

[0018] Furthermore, in some embodiments, the linear gain adjustment circuit further includes:

[0019] A gain signal input terminal, the gain signal input terminal is connected to a gain resistor decoding controller circuit, the gain signal input terminal is connected to an adjustment resistor decoding controller circuit, and the gain resistor decoding controller and the adjustment resistor decoding controller are connected in parallel;

[0020] A current source signal input terminal connected to a current source array circuit;

[0021] The gain signal input terminal is used to transmit the resistor array control signal to the gain resistor decoding controller and the trim resistor decoding controller respectively;

[0022] The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each current source unit bit by bit according to the current source array control signal to output a variable total current.

[0023] Furthermore, in some embodiments, the resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal, and a clock control signal;

[0024] The current source array control signal includes a current source set / reset control signal, a current source gating enable signal and a clock control signal.

[0025] Furthermore, in some embodiments, a first input terminal of the resistance unit is connected to the current source array circuit, a second input terminal of the resistance unit is connected to the gain resistance decoding controller circuit, and an output terminal of the resistance unit is grounded;

[0026] The resistance unit has a built-in resistor and a MOS switch. The first pole of the MOS switch is connected to one end of the resistor circuit, the other end of the resistor is used as the first input end of the resistance unit, the second pole of the MOS switch is used as the output end of the resistance unit, and the third pole of the MOS switch is used as the second input end of the resistance unit. The third pole of the MOS switch is the gate.

[0027] Furthermore, in some embodiments, the linear gain adjustment circuit also includes a current source global bias generator, which is connected to the current source array circuit. The current source global bias generator is used to transmit a global bias signal to the current source array so that the current source array controls each current source unit to output the same current according to the global bias signal.

[0028] The embodiments of the first aspect of the present application have the following beneficial effects: the present application realizes the generation of a ramp voltage signal with high linearity and high stability at the signal output end through the collaborative design of the gain resistor array and the trimming resistor array. Among them, the parallel structure of the gain resistor array is used to dynamically adjust the total resistance value, and the flexible control of the amplitude gain is realized by combining the variable total current of the current source array; at the same time, the trimming resistor array actively compensates for the nonlinear offset by simulating the linear change of the resistance value of the gain resistor in real time, effectively suppressing the gain nonlinearity problem caused by the discreteness of the resistor unit, temperature drift or process deviation; and the dual-array parallel architecture not only retains the programmable characteristics of the resistor network, but also significantly improves the overall linearity of the system through the closed-loop adjustment mechanism, which is particularly suitable for fields with strict requirements on the linearity of the ramp signal, such as high-precision digital-to-analog conversion and power management chips. This structure reduces the calibration complexity while improving the signal quality, and improves the gain accuracy of the gain adjustment circuit.

[0029] To achieve the above-mentioned objectives, a second aspect of an embodiment of the present application provides a linear gain adjustment circuit for a CMOS image sensor chip, comprising:

[0030] A current source array, comprising a plurality of bit-by-bit controllable current source units, each of which is connected in parallel, and configured to output a variable total current;

[0031] A signal output terminal connected to a current source array circuit;

[0032] A gain resistor array, the gain resistor array is connected to the current source array circuit, the gain resistor array and the signal output terminal are connected in parallel, the gain resistor array includes a plurality of resistor units, and the resistor units are connected in parallel;

[0033] A gain resistor decoding controller connected to a gain resistor array circuit;

[0034] A DAC converter is connected to a gain resistor decoding controller circuit;

[0035] The gain resistor array is used to perform amplitude gain on the voltage at the signal output end according to the total resistance value and variable total current collected by each resistor unit in the on state, so that the signal output end outputs a voltage signal with a ramp-changing property;

[0036] The gain resistor decoding controller is used to receive the resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in a conductive state;

[0037] The DAC converter is used to adjust the high-level voltage value output by the gain resistor decoding controller according to the resistor array control signal, so as to adjust the number of resistor units that are turned on when the resistance value exhibits a nonlinear offset, so that the voltage gain of the gain resistor array to the signal output end is stabilized in the linear region.

[0038] Furthermore, in some embodiments, the linear gain adjustment circuit further includes:

[0039] The gain signal input terminal is connected to the gain resistor decoding controller and the DAC converter circuit respectively;

[0040] A current source signal input terminal connected to a current source array circuit;

[0041] The gain signal input terminal is used to transmit the resistor array control signal to the gain resistor decoding controller and the DAC converter respectively;

[0042] The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each current source unit bit by bit according to the current source array control signal to output a variable total current;

[0043] Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal and a clock control signal; the current source array control signal includes a current source set / reset control signal, a current source gating enable signal and a clock control signal.

[0044] Furthermore, in some embodiments, the linear gain adjustment circuit also includes a current source global bias generator, which is connected to the current source array circuit. The current source global bias generator is used to transmit a global bias signal to the current source array so that the current source array controls each current source unit to output the same current according to the global bias signal.

[0045] Furthermore, in some embodiments, a first input terminal of the resistance unit is connected to the current source array circuit, a second input terminal of the resistance unit is connected to the gain resistance decoding controller circuit, and an output terminal of the resistance unit is grounded;

[0046] The resistance unit has a built-in resistor and a MOS switch. The first pole of the MOS switch is connected in series with one end of the resistor. The other end of the resistor is used as the first input end of the resistance unit. The second pole of the MOS switch is used as the output end of the resistance unit. The third pole of the MOS switch is used as the second input end of the resistance unit. The third pole of the MOS switch is the gate.

[0047] The second aspect of the present application has the following advantageous effects: The present application achieves high-precision nonlinear compensation and dynamic linearization adjustment in a linear gain adjustment circuit through multi-stage coordinated control of a gain resistor array, a decoding controller, and a DAC converter. The DAC converter actively adjusts the high-level voltage output by the decoding controller based on a gain control signal, adaptively compensating for the nonlinear offset of the resistor unit by changing the conduction threshold of the resistor unit, significantly improving the overall linearity of the gain resistor array. The gain resistor decoding controller then achieves full conduction control of the resistor unit through constant voltage drive. Combined with the voltage fine-tuning mechanism of the DAC converter, the on-resistance distribution can be dynamically optimized without changing the physical layout, enhancing the system's robustness to process deviations and environmental interference. Furthermore, the present application integrates traditional analog adjustment functions with digital control logic, simplifies the calibration process through the digital interface of the DAC converter, reduces the complexity of the external compensation circuit, and improves the resolution and stability of the ramp signal. This allows the linear gain adjustment circuit to achieve the advantages of high linearity output, low power consumption, and process compatibility, providing an efficient solution for generating precise ramp signals for CMOS image sensor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is an overall structural diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided by some embodiments of the present application;

[0049] Figure 2 is an overall structural diagram of a resistor unit provided in some other embodiments of the present application;

[0050] Figure 3 This is an overall structural diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided in some other embodiments of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0052] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0053] It should also be noted that, in the description of this application, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0055] In the description of this application, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0056] Single-slope column ADCs (SS-ADCs) are widely used in high-speed CMOS image sensors. The SS-ADC structure is suitable for column ADC integration, offers low power consumption, and facilitates the implementation of correlated double sampling (CDS), balancing chip performance and area cost. The basic principle of an SS-ADC is to connect a reference ramp voltage and the pixel photosensitive voltage of a CMOS image sensor to the two inputs of a comparator. Controlled by a high-speed clock, the ramp changes monotonically, gradually approaching the pixel photosensitive voltage until the comparator flips and outputs a 1-bit decision result. This decision result is used to control the counter count: the counter begins counting when the comparison starts (when the reference ramp begins its monotonic change) and stops counting when the comparator flips. The count value stored in the counter at this time represents the quantized result of the corresponding pixel photosensitive voltage.

[0057] Pixel information from the column SS-ADC is read out row by row, with columns read in parallel. When a row is selected, all columns share a global reference ramp signal to compare and count pixel signals. The speed at which the reference ramp signal monotonically changes, or the ramp slope, determines the comparator flip-flop time. Using different reference ramps for the same pixel's photosensitive voltage will yield different counts. The slope variation is defined as gain adjustment: a larger slope corresponds to lower gain, while a smaller slope corresponds to higher gain. Gain adjustment circuits are essential in CMOS image sensor applications. In low-light environments, where the pixel photosensitive voltage difference is small, using a gain adjustment circuit that outputs a large ramp voltage results in a rapid comparator decision. This results in understated counts for each column ADC and minimal or no difference between counts in different regions, ultimately resulting in low image brightness, low contrast, and a loss of detail. Using a gain adjustment circuit that outputs a smaller ramp voltage allows the comparator to make a decision later due to the slower ramp change, allowing the counter to record more data, brightening the image and reflecting subtle differences between columns in the count values. This is why a large slope corresponds to a low gain, while a small slope corresponds to a high gain. A small slope increases the counter count value and improves the image brightness, which is equivalent to increasing the readout circuit's ability to amplify the photosensitive signal, that is, increasing the gain.

[0058] Because the photosensitive environment is variable, gain needs to be flexible and adjustable, and preferably linearly adjustable. For multi-frame synthesis (such as HDR), denoising, or color restoration algorithms, linear gain ensures comparability between frames, thereby improving image quality. It also facilitates white balance, exposure control, gamma correction, and other functions in the image signal processing chain, facilitating the creation of lookup tables (LUTs) in the ISP or the use of linear models for dynamic range control and gain compensation. Linear gain adjustment also more accurately implements the "analog gain + digital gain" combination strategy, thereby improving dynamic range without sacrificing image linearity.

[0059] In the prior art, in order to improve the gain accuracy of the gain adjustment circuit, it is necessary to increase the number of control bits. For any gain adjustment array, a larger area and multiple resistor units are required, which increases the mismatch between the resistor units and aggravates the array gradient difference: gain adjustment is achieved by controlling the number of resistor units actually connected to the ramp generation circuit in the gain adjustment array. Ideally, the resistor units are completely consistent, and the changes caused by connecting to the circuit are also completely consistent, so the change in the ramp slope is completely consistent. The change in the ramp slope within the gain adjustment range is statistically calculated, and its INL and DNL are theoretically 0, then the slope gain adjustment is considered linear; however, in the actual gain process, each resistor unit will have slight differences, resulting in inconsistent changes in the ramp slope of the overall output, and DNL and INL are not 0, which in turn introduces nonlinearity into the ramp gain of the gain adjustment circuit and reduces the gain accuracy.

[0060] Based on this, a linear gain adjustment circuit for CMOS image sensor chip is proposed, which can offset the nonlinear influence between resistor units in the actual gain process, thereby improving the gain accuracy of the gain adjustment circuit.

[0061] The embodiments of the present application provide a linear gain adjustment circuit for a CMOS image sensor chip, which is specifically described through the following embodiments.

[0062] First, refer to Figure 1 As shown, Figure 1 1 is an overall structural diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided by some embodiments of the present application. The linear gain adjustment circuit for a CMOS image sensor chip includes a current source array 110, a signal output terminal 120, a gain resistor array 130, and a trimming resistor array 140. The signal output terminal 120 is circuit-connected to the current source array 110; the gain resistor array 130 is circuit-connected to the current source array 110, and the gain resistor array 130 and the signal output terminal 120 are connected in parallel. The trimming resistor array 140 is circuit-connected to the current source array 110, and the trimming resistor array 140 and the gain resistor array 130 are connected in parallel.

[0063] The current source array 110 includes a plurality of bit-controllable current source units, each of which is connected in parallel. The current source array 110 is used to output a variable total current. The gain resistor array 130 includes a plurality of resistor units, each of which is connected in parallel.

[0064] The gain resistor array 130 is used to perform amplitude gain on the voltage of the signal output terminal 120 according to the total resistance value and variable total current collected by each resistor unit in the on state, so that the signal output terminal 120 outputs a voltage signal with a ramp-changing property.

[0065] Furthermore, the trimming resistor array 140 is used to simulate the resistance linear variation of the gain resistor array 130 and perform nonlinear offset adjustment on the total resistance value according to the resistance linear variation, so that the voltage gain of the gain resistor array 130 to the signal output terminal 120 is stably in the linear region.

[0066] It should be noted that each current source unit has the same output current, and each current source unit can be switched on and off sequentially, or the current source unit can be switched on and off row by row. Since the current source units in the on state are connected in parallel, the output currents of the current source units are aggregated into a variable total current I out , and then output to the gain resistor array 130 and the signal output terminal 120.

[0067] It should also be noted that each resistance unit has the same resistance value, and each resistance unit can be switched on and off individually, that is, any number of resistance units can be selected to be connected in parallel, thereby obtaining a total resistance value of each resistance unit when in the on state.

[0068] By switching each current source unit one by one, the total current I out will gradually change, and then the variable total current I out The voltage signal Vramp with a ramp variation property is multiplied by the total resistance value of the gain resistor array 130 collected according to the resistance units in the on state.

[0069] During a single ramp change, the total resistance value of the gain resistor array 130 is set to a fixed value before the ramp starts to change, and the total resistance value should be changed only after the ramp change is completed. out (That is, at this time I out The voltage signal Vramp is obtained by multiplying the current output by any current source unit in the current source array 110 by the total resistance value of the gain resistor array 130, and the resulting voltage is the step size of the ramp change at the current gain resistor, also known as the LSB of the ramp change. Figure 1 The voltage Vramp1 and voltage Vramp2 in FIG are two LSBs and different swing ramps. out In this case, changing the total resistance value of the gain resistor array 130 can change the slope LSB. The LSB multiplied by the total number of current source units is the slope swing. That is, the linear change performance of the total resistance value of the gain resistor array 130 determines the linearity of the slope LSB and swing changes.

[0070] Further, from Figure 1 It can be seen that the first input end of each resistor unit is connected to the current source array 110 circuit, the second input end of the resistor unit is connected to the gain resistor decoding controller 150 circuit, and the output end of the resistor unit is grounded.

[0071] Among them, reference Figure 2 As shown, Figure 2 This is a diagram of the overall structure of a resistor unit provided in some other embodiments of the present application. The resistor unit includes a resistor r and a MOS switch. The first terminal of the MOS switch is circuit-connected to one end of the resistor r. The other end of the resistor r serves as the first input terminal of the resistor unit. The second terminal of the MOS switch serves as the output terminal of the resistor unit. The third terminal of the MOS switch serves as the second input terminal of the resistor unit. The third terminal of the MOS switch serves as the gate. In one embodiment, when the MOS switch is an NMOS transistor, the first terminal of the MOS switch serves as the drain, and the second terminal of the MOS switch serves as the source. In another embodiment, when the MOS switch is an NMOS transistor, the first terminal of the MOS switch serves as the source, and the first terminal of the MOS switch serves as the drain.

[0072] In one embodiment, R1 to R16 are connected in parallel in the gain resistor array 130, and then R1 to R4 are selected to be connected in parallel and turned on. Ideally, the total resistance value of the gain resistor array 130 should be 1 / 4 of the maximum resistance value (i.e., R1 to R16 are turned on at the same time). However, due to the influence of resistor adaptation, line parasitics, gradient effects, etc., the resistance values within R1 to R4 vary slightly, resulting in the total resistance value of the gain resistor array 130 being higher than the theoretical value, making the step size of the gain change smaller, that is, the gain change of the gain resistor array 130 is nonlinear. Because the trimming resistor array 140 is connected in parallel with the gain resistor array 130, the trimming resistor array 140 can simulate the internal resistance values of R1-R4 in the gain resistor array 130. The resistance value of the trimming resistor array 140 is then adjusted to nonlinearly compensate for the resistance values of R1-R4 in the gain resistor array 130. This allows the total resistance value of the gain resistor array 130 to approach the theoretical value, resulting in the output voltage with a ramp property reaching the theoretical voltage value, and the signal output terminal 120 outputting a voltage signal with the theoretical ramp LSB change.

[0073] Furthermore, the linear gain adjustment circuit also includes a gain resistor decoding controller 150, which is connected to the gain resistor array 130 circuit; wherein the gain resistor decoding controller 150 is used to receive the resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal to put the resistor unit in a conductive state.

[0074] It should be noted that the resistor array control signal can control the switch of each resistor unit after being decoded by the gain resistor decoding controller 150. The high level output by the gain resistor decoding controller 150 is the power supply voltage of the current source array 110, and the low level output is the ground voltage. When the high level output by the gain resistor decoding controller 150 is connected to the circuit of the gain resistor decoding controller 150, the high level can be input to the third pole of the MOS switch of the resistor unit. At this time, the third pole of the MOS switch receives the high level, and the first and second poles of the MOS switch are turned on, so that the resistor r of the resistor unit is in an operating state.

[0075] In addition, the linear gain adjustment circuit also includes a trimming resistor decoding controller 160, which is connected to the trimming resistor array 140 circuit; the trimming resistor decoding controller 160 is used to receive the resistor array control signal and dynamically simulate the linear change of the resistance value of the gain resistor array 130 according to the resistor array control signal.

[0076] Furthermore, the linear gain adjustment circuit also includes a gain signal input terminal 170, which is connected to the gain resistor decoding controller 150 circuit. The gain signal input terminal 170 is connected to the adjustment resistor decoding controller 160 circuit. The gain resistor decoding controller 150 and the adjustment resistor decoding controller 160 are connected in parallel. The gain signal input terminal 170 is used to transmit the resistor array control signal to the gain resistor decoding controller 150 and the adjustment resistor decoding controller 160 respectively.

[0077] In addition, the linear gain adjustment circuit also includes a current source signal input terminal 180, which is connected to the current source array 110 circuit; the current source signal input terminal 180 is used to input a current source array 110 control signal to the current source array 110, so that the current source array 110 controls the opening and closing of each current source unit bit by bit according to the current source array 110 control signal to output a variable total current.

[0078] Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal and a clock control signal; the resistor set / reset control signal is used to realize the row-by-row gating of the resistor unit, and the resistor gating enable signal is used to specify the interval in which a certain resistor unit can be switched on and off one by one.

[0079] In addition, the control signal of the current source array 110 includes a current source set / reset control signal, a current source gating enable signal and a clock control signal. The current source set / reset control signal is used to realize the row-by-row gating of the current source unit. The current source gating enable signal is used to specify the interval in which a certain current source unit can be switched one by one. The clock control signal is used to determine at what equal time intervals the current source units or resistance units are switched one by one.

[0080] Furthermore, the linear gain adjustment circuit also includes a current source global bias generator 190, which is connected to the current source array 110 circuit. The current source global bias generator 190 is used to transmit a global bias signal to the current source array 110 so that the current source array 110 controls each current source unit to output the same current according to the global bias signal.

[0081] Secondly, refer to Figure 3 As shown, Figure 3 This is an overall structural diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided in some other embodiments of the present application. The linear gain adjustment circuit includes a current source array 210, a signal output terminal 220, a gain resistor array 230, a gain resistor decoding controller 240, and a DAC converter 250. The signal output terminal 220 is circuit-connected to the current source array 210, the gain resistor array is circuit-connected to the current source array 210, the gain resistor array 230 and the signal output terminal 220 are connected in parallel, the gain resistor decoding controller 240 is circuit-connected to the gain resistor array 230, and the DAC converter 250 is circuit-connected to the gain resistor decoding controller 240.

[0082] Among them, the current source array 210 includes multiple current source units that can be controlled bit by bit, and each current source unit is connected in parallel. The current source array 210 is used to output a variable total current; the gain resistor array 230 includes multiple resistor units, and each resistor unit is connected in parallel.

[0083] Furthermore, the gain resistor array 230 is used to perform amplitude gain on the voltage of the signal output terminal 220 according to the total resistance value and variable total current collected by each resistor unit in the on state, so that the signal output terminal 220 outputs a voltage signal with a ramp-varying property.

[0084] Furthermore, the gain resistor decoding controller 240 is configured to receive a resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that each resistor unit is in a conducting state.

[0085] At the same time, the DAC converter 250 is used to adjust the high-level voltage value output by the gain resistor decoding controller 240 according to the resistor array control signal to adjust the number of resistor units that are turned on when the resistance value exhibits a nonlinear offset, so that the voltage gain of the gain resistor array 230 to the signal output terminal 220 is stabilized in the linear region.

[0086] It should be noted that the first input end of the resistance unit is connected to the current source array 210 circuit, the second input end of the resistance unit is connected to the gain resistance decoding controller 240 circuit, and the output end of the resistance unit is grounded;

[0087] Among them, from Figure 2 As can be seen, the resistance unit includes a resistor and a MOS switch. The first electrode of the MOS switch is connected in series with one end of the resistor. The other end of the resistor serves as the first input of the resistance unit. The second electrode of the MOS switch serves as the output of the resistance unit. The third electrode of the MOS switch serves as the second input of the resistance unit. The third electrode of the MOS switch serves as the gate. In one embodiment, when the MOS switch is an NMOS transistor, the first electrode of the MOS switch serves as the drain, and the second electrode of the MOS switch serves as the source. In another embodiment, when the MOS switch is an NMOS transistor, the first electrode of the MOS switch serves as the source, and the first electrode of the MOS switch serves as the drain.

[0088] In one embodiment, R1 to R16 are connected in parallel in the gain resistor array 230, and then R1 to R4 are selected to be connected in parallel and turned on. Ideally, the total resistance value of the gain resistor array 230 should be 1 / 4 of the maximum resistance value (i.e., R1 to R16 are turned on at the same time). However, due to the influence of resistor adaptation, line parasitics, gradient effects, etc., the resistance values within R1 to R4 are slightly different, resulting in the total resistance value of the gain resistor array 230 being higher than the theoretical value, making the step size of the gain change smaller, that is, the gain change of the gain resistor array 230 is nonlinear. In this application, due to the DAC converter 250 and the gain If the resistor decoding controller 240 is connected to the resistor decoding controller 240, the DAC converter 250 can be used to adjust the high-level voltage value output by the gain resistor decoding controller 240, so that the voltage value of the third electrode of the MOS switch input to the resistor unit changes, thereby indirectly controlling the conduction state between the first and second electrodes of the MOS switch, so as to re-control the switching of R1 to R4, and further indirectly adjusting the total resistance value of the gain resistor array 230 to be close to the theoretical value, so that the output voltage with a ramp property reaches the theoretical voltage value, and the signal output terminal 220 outputs a voltage signal of the theoretical ramp LSB change amount.

[0089] In one embodiment, the internal resistance values of R1-R4 are too high, resulting in an excessively high total resistance value of the gain resistor array 230. However, the DAC converter 250 can be used to lower the voltage corresponding to the high level input to R1, thereby causing the first and second terminals of the MOS switch to switch from an on state to an off state, i.e., R1 is in a non-operating state. In this case, the total resistance value of the gain resistor array 230 is obtained by summing the internal resistance values of R2-R4, thereby reducing the total resistance value of the gain resistor array 230 and bringing the total resistance value of the gain resistor array 230 closer to the theoretical value.

[0090] Furthermore, the linear gain adjustment circuit also includes a gain signal input terminal 260, which is connected to the gain resistor decoding controller 240 and the DAC converter 250 circuit respectively. The gain signal input terminal 260 is used to transmit the resistor array control signal to the gain resistor decoding controller 240 and the DAC converter 250 respectively.

[0091] In addition, the linear gain adjustment circuit also includes a current source signal input terminal 270, which is connected to the current source array 210 circuit; the current source signal input terminal 270 is used to input the current source array 210 control signal to the current source array 210, so that the current source array 210 controls the opening and closing of each current source unit bit by bit according to the current source array 210 control signal to output a variable total current.

[0092] Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal and a clock control signal; the current source array 210 control signal includes a current source set / reset control signal, a current source gating enable signal and a clock control signal.

[0093] Furthermore, the linear gain adjustment circuit also includes a current source global bias generator 280, which is connected to the current source array 210 circuit. The current source global bias generator 280 is used to transmit a global bias signal to the current source array 210 so that the current source array 210 controls each current source unit to output the same current according to the global bias signal.

[0094] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0095] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0096] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0097] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0098] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0099] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the above units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0101] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0103] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application.

[0104] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A linear gain adjustment circuit for a CMOS image sensor chip, characterized in that: include: A current source array, comprising a plurality of bit-controllable current source units, each of which is connected in parallel, and configured to output a variable total current; a signal output terminal connected to the current source array circuit; A gain resistor array, the gain resistor array being connected to the current source array circuit, the gain resistor array and the signal output terminal being connected in parallel, the gain resistor array comprising a plurality of resistor units, each of the resistor units being connected in parallel; A trimming resistor array, wherein the trimming resistor array is connected to the current source array circuit, and the trimming resistor array and the gain resistor array are connected in parallel; The gain resistor array is used to perform amplitude gain on the voltage of the signal output end according to the total resistance value collected by each of the resistor units in the on state and the variable total current, so that the signal output end outputs a voltage signal with a ramp-changing property; The trimming resistor array is used to simulate the linear variation of the resistance of the gain resistor array, and to perform nonlinear offset adjustment on the total resistance value according to the linear variation of the resistance, so that the voltage gain of the gain resistor array to the signal output end is stably in a linear region.

2. The linear gain adjustment circuit according to claim 1, wherein: Also includes: A gain resistor decoding controller connected to the gain resistor array circuit; A trimming resistor decoding controller connected to the trimming resistor array circuit; The gain resistor decoding controller is configured to receive a resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in a conducting state; The trimming resistor decoding controller is used to receive the resistor array control signal and dynamically simulate the linear change of the resistance value of the gain resistor array according to the resistor array control signal.

3. The linear gain adjustment circuit according to claim 2, wherein: Also includes: a gain signal input terminal, the gain signal input terminal being connected to the gain resistor decoding controller circuit, the gain signal input terminal being connected to the adjustment resistor decoding controller circuit, the gain resistor decoding controller and the adjustment resistor decoding controller being connected in parallel; a current source signal input terminal connected to the current source array circuit; The gain signal input terminal is used to transmit the resistor array control signal to the gain resistor decoding controller and the trimming resistor decoding controller respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each current source unit bit by bit according to the current source array control signal to output the variable total current.

4. The linear gain adjustment circuit according to claim 3, characterized in that: The resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal and a clock control signal; The current source array control signal includes a current source set / reset control signal, a current source gating enable signal and the clock control signal.

5. The linear gain adjustment circuit according to claim 2, wherein: The first input end of the resistance unit is connected to the current source array circuit, the second input end of the resistance unit is connected to the gain resistance decoding controller circuit, and the output end of the resistance unit is grounded; The resistance unit has a built-in resistor and a MOS switch, the first pole of the MOS switch is circuit-connected to one end of the resistor, the other end of the resistor is used as the first input end of the resistance unit, the second pole of the MOS switch is used as the output end of the resistance unit, the third pole of the MOS switch is used as the second input end of the resistance unit, and the third pole of the MOS switch is the gate.

6. The linear gain adjustment circuit according to claim 1, wherein: Also includes: A current source global bias generator is connected to the current source array circuit and is used to transmit a global bias signal to the current source array so that the current source array controls each current source unit to output the same current according to the global bias signal.

7. A linear gain adjustment circuit for a CMOS image sensor chip, characterized in that: include: A current source array, comprising a plurality of bit-controllable current source units, each of which is connected in parallel, and configured to output a variable total current; a signal output terminal connected to the current source array circuit; A gain resistor array, the gain resistor array being connected to the current source array circuit, the gain resistor array and the signal output terminal being connected in parallel, the gain resistor array comprising a plurality of resistor units, each of the resistor units being connected in parallel; A gain resistor decoding controller connected to the gain resistor array circuit; A DAC converter connected to the gain resistor decoding controller circuit; The gain resistor array is used to perform amplitude gain on the voltage of the signal output end according to the total resistance value collected by each of the resistor units in the on state and the variable total current, so that the signal output end outputs a voltage signal with a ramp-changing property; The gain resistor decoding controller is used to receive a resistor array control signal and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in a conducting state; The DAC converter is used to adjust the high-level voltage value output by the gain resistor decoding controller according to the resistor array control signal, so as to adjust the number of conduction of the resistor unit when the resistance value exhibits a nonlinear offset, so as to stabilize the voltage gain of the gain resistor array to the signal output end in a linear region.

8. The linear gain adjustment circuit according to claim 7, wherein: Also includes: a gain signal input terminal, the gain signal input terminal being connected to the gain resistor decoding controller and the DAC converter circuit respectively; a current source signal input terminal connected to the current source array circuit; The gain signal input terminal is used to transmit the resistor array control signal to the gain resistor decoding controller and the DAC converter respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each current source unit bit by bit according to the current source array control signal to output the variable total current; Wherein, the resistor array control signal includes a resistor set / reset control signal, a resistor gating enable signal and a clock control signal; The current source array control signal includes a current source set / reset control signal, a current source gating enable signal and the clock control signal.

9. The linear gain adjustment circuit according to claim 7, characterized in that: Also includes: A current source global bias generator is connected to the current source array circuit and is used to transmit a global bias signal to the current source array so that the current source array controls each current source unit to output the same current according to the global bias signal.

10. The linear gain adjustment circuit according to claim 7, characterized in that: The first input end of the resistance unit is connected to the current source array circuit, the second input end of the resistance unit is connected to the gain resistance decoding controller circuit, and the output end of the resistance unit is grounded; The resistance unit has a built-in resistor and a MOS switch, the first pole of the MOS switch is connected in series with one end of the resistor, the other end of the resistor is used as the first input end of the resistance unit, the second pole of the MOS switch is used as the output end of the resistance unit, the third pole of the MOS switch is used as the second input end of the resistance unit, and the third pole of the MOS switch is the gate.

Images