Multi-die semiconductor package

Abstract

The invention relates to a multi-die semiconductor package. The semiconductor package includes: a carrier having a die pad and a plurality of leads; a first discrete power device die mounted on the die pad and having a first load terminal pad disposed on a major surface facing away from the die pad; a first packaged load terminal formed by one or more of the leads; and a first metal clip electrically connecting the first load terminal pad of the first discrete power device die with the first packaged load terminal, where the first metal clip includes a local contraction, the local contraction is configured to locally reduce thermal conductivity of the first metal clip in a segment region of the first metal clip between the first discrete power device die and the first packaged load terminal.

Description

Field of the Technology

[0001] The present disclosure relates to the field of semiconductor packaging and, in particular, to multi-die semiconductor packaging. Background Art

[0002] Many applications, such as automotive and industrial applications, use power devices to perform high-voltage switching and high-current conduction. A power device refers to a semiconductor device capable of blocking a voltage of at least 100V (volts) (more typically, about 600V or greater) and / or a semiconductor device capable of conducting a current of at least 1A (ampere) (more typically, about 10A or greater). A semiconductor package with modern power devices designed to minimize power loss can provide an energy-saving solution to reduce or prevent anthropogenic emissions of greenhouse gases (GHGs). For example, discrete power switching devices can be used in hybrid or pure electric vehicles to switch large amounts of current and / or voltage. More generally, modern power devices can be incorporated into any electrical setup to improve efficiency and reduce environmental impact. There is a strong need to improve the performance, cost, and efficiency of power device packaging and, thus, improve the efficiency of power delivery systems. Summary of the Invention

[0003] Those skilled in the art will realize additional features and advantages upon reading the following detailed description and viewing the drawings.

[0004] A semiconductor package is disclosed. According to an embodiment, the semiconductor package includes: a carrier including die pads and a plurality of leads; first and second switching device dies, each switching device die including a gate terminal pad and first and second load terminal pads disposed on a major surface; and first, second, and third package load terminals and a package gate terminal, each of which is formed by one or more of the leads, wherein the first and second switching device dies are each configured as discrete III-V semiconductor devices, wherein the first and second switching device dies are each mounted on the die pads with the major surface of each switching device die facing away from the die pads, and wherein the first and second switching device dies are electrically connected in parallel such that: a first electrical interconnect electrically connects the first load terminal pads from the first and second switching device dies to the first package load terminal; a second electrical interconnect electrically connects the second load terminal pads from the first and second switching device dies to the second package load terminal; and a third electrical interconnect electrically connects the gate terminal pads from the first and second switching device dies to the package gate terminal.

[0005] According to another embodiment, the semiconductor package includes: a carrier including die pads and a plurality of leads; and a first discrete power device die mounted on the die pad and including a first load terminal pad disposed on a major surface facing away from the die pad; a first package load terminal formed by one or more of the leads; and a first metal clip electrically connecting the first load terminal pad of the first discrete power device die to the first package load terminal, wherein the first metal clip includes a local constriction configured to locally reduce the thermal conductivity of the first metal clip in a section of the first metal clip between the first discrete power device die and the first package load terminal.

[0006] An electrical interconnect component is disclosed. According to an embodiment, the electrical interconnect component includes: a metal clip extending between a first end and a second end; a local constriction disposed between the first end and the second end, wherein the metal clip is configured to interface with a semiconductor die at the first end and with a carrier at the second end, and wherein the local constriction is configured to locally reduce the thermal conductivity of the metal clip in a section of the metal clip between the first end and the second end. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding like parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the drawings and detailed in the following description.

[0008] Figure 1 Schematically illustrated is a semiconductor package assembly according to an embodiment having a plurality of switching device dies connected in parallel with each other.

[0009] Figures 2-14 Illustrated are embodiments of a semiconductor package assembly having a plurality of switching device dies connected in parallel with each other.

[0010] Figure 15 Illustrated is a cross-sectional view of a semiconductor package according to an embodiment having a plurality of switching device dies connected in parallel with each other.

[0011] Figures 16-20 Illustrated are embodiments of a metal interconnect clip having a local constriction according to an embodiment. DETAILED DESCRIPTION

[0012] Embodiments of semiconductor packages that describe herein beneficial electrical interconnect configurations having die connected in parallel and for connecting the die to package leads are described. The semiconductor package includes two or more discrete switching device dies connected in parallel to create a switching device having a high current capacity. The multi-die configuration connected in parallel provides significant advantages such as improved yield and lower defect rates, improved heat dissipation, and lower likelihood of die cracking compared to a single-die configuration having equivalent conduction capacity. However, the multi-die configuration has some disadvantages such as interconnect congestion and potentially asymmetric switching behavior. Embodiments disclosed herein beneficially mitigate these problems. For example, embodiments disclosed herein match the impedance and / or resistance of the package interconnects, thereby facilitating synchronous switching behavior. Additionally, embodiments disclosed herein include die configurations and / or interconnect features and arrangements that mitigate interconnect congestion.

[0013] Embodiments of the semiconductor package may include a metal clip having beneficial heat flow confinement features. The device dies connected in parallel conduct high currents during operation and operate at high voltages and thus generate significant heat during operation. According to an embodiment, at least one metal clip from the semiconductor package that houses the load current of the device includes a local constriction that is configured to locally reduce the thermal conductivity of the metal clip. This provides a beneficial trade-off between electrical conductivity and thermal conductivity. That is, the metal clip has a beneficial low resistance compared to other interconnect element types (e.g., bond wires, tapes, etc.). At the same time, the local constriction provides a partial heat transfer barrier that prevents efficient transfer of the die surface temperature to the leads, thereby avoiding various problems such as damage to the connection between the leads and external devices.

[0014] Refer to Figure 1, according to an embodiment, a semiconductor package assembly 100 is shown. The semiconductor package assembly 100 includes a carrier that includes a die pad 104 and a plurality of leads 106 that extend away from the die pad 104. According to an embodiment, the carrier is provided from a metal lead frame. Such a lead frame can be formed of one or more conductive metals (such as, for example, Cu, Ni, and / or Ag). Additionally, for example, the lead frame can be characterized by or plated with Cu, Ni, Ag, Au, Pd, Pt, NiV, NiP, NiNiP, NiP / Pd, Ni / Au, NiP / Pd / Au, or NiP / Pd / AuAg. The lead frame can be provided from a planar sheet metal of uniform thickness and processed by metal processing techniques (such as, for example, stamping, cutting, etching, etc.). According to an embodiment, at least the die pad 104 portion of the carrier is provided from an insulating electronic device substrate. In such a case, the carrier can include an electrically insulating substrate region formed of, for example, ceramic, FR-4, etc., and a structured metal layer is placed on the electrically insulating substrate region. Examples of the insulating electronic device substrate include a PCB (printed circuit board) or a power electronic device carrier, such as a DCB (direct copper bond) substrate, an IMS (insulated metal) substrate, an AMB (active metal brazing) substrate, or a substrate having a 3D printed insulating layer and a metal layer formed thereon.

[0015] The lead 106 forms an externally accessible terminal of the completed semiconductor package. The depicted semiconductor package assembly 100 is configured with four external terminals, namely, one or more first package load terminals 108, a second package load terminal 110, a package gate terminal 112, and one or more package sense terminals 114. The first and second package load terminals 108, 110 accommodate the rated voltage and current of the device. The package gate terminal 112 is used to control the switching operation of the device. The package sense terminals 114 are used to measure the voltage present at the load terminals of the die. Each of the package terminals can be formed by one or more of the leads 106. As shown in the figure, both the first package load terminal 108 and the second package load terminal 110 are formed by a plurality of leads 106. The carrier includes one or more first landing pads 116, configured to receive electrical interconnect components (e.g., clips, tapes, bond wires, etc.) and form a merged connection between the leads 106 forming the one or more first package load terminals 108. Correspondingly, the carrier includes a second landing pad 118, configured to receive electrical interconnect components (e.g., clips, tapes, bond wires, etc.) and form a merged connection between the leads 106 forming the second package load terminal 110. The number of leads 106 for each of the package terminals can vary relative to what is shown and can depend on various factors, including operating voltage and current, package footprint, creepage and clearance requirements, etc. Separately or in combination, the lead configuration and the corresponding package style can vary relative to what is shown. For example, the package assembly can be configured for various different package styles, including leaded packages, leadless packages, SMD (surface mount device), through-hole packages, etc.

[0016] The semiconductor package assembly 100 includes a plurality of discrete switching device dies 120 mounted on die pads 104. In the depicted embodiment, the semiconductor package assembly 100 includes two discrete switching device dies 120 mounted on die pads 104. More generally, in accordance with the techniques disclosed herein, the semiconductor package assembly 100 may include any number of discrete switching device dies 120 mounted on the same die pads 104 and connected in parallel with each other, e.g., two, three, four, five, six, etc. The discrete switching device dies 120 may be formed according to various semiconductor material technologies, such as technologies for group-IV semiconductors, group-IV-IV compound semiconductor materials, group-III-V compound semiconductor materials, or group-II-VI compound semiconductor materials. Examples of semiconductor devices formed according to group-IV semiconductor technologies include devices formed according to silicon (Si), silicon carbide (SiC), and germanium (Ge). Examples of semiconductor devices formed according to group-III-V compound semiconductor material technologies include, for example, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs).

[0017] The discrete switching device die 120 includes a gate terminal pad 122 and first and second load terminal pads 124, 126. In a conventionally known manner, the discrete switching device die 120 is configured to control the conductive connection between the first and second load terminal pads 124, 126 via the gate terminal pad 122. According to an embodiment, the discrete switching device die 120 is configured as a discrete HEMT (high electron mobility transistor) die. In this case, the first load terminal pad 124 may correspond to the source terminal, and the second load terminal pad 126 may correspond to the drain terminal, and vice versa. According to another embodiment, the discrete switching device die 120 is configured as a bidirectional switch. In this case, the discrete switching device die 120 may include a second (different) gate terminal pad, and the semiconductor package assembly 100 may similarly include a second (different) package gate terminal ( Figure 1 not shown in the figure), the second (different) package gate terminal being connected to the second (different) gate terminal pad, wherein the devices are configured for bidirectional conduction through selective biasing of each gate terminal pad. In a particular embodiment, the discrete switching device die 120 is configured as a discrete GaN device die, wherein the active channel of the device is formed by a heterojunction between layers of GaN and its alloys, such as, AlGaN. For example, these GaN device dies may be configured as discrete HEMT dies for bidirectional switch dies.

[0018] The gate terminal pad 122 and the first and second load terminal pads 124, 126 are all formed on the major surface of the discrete switching device die 120. Accordingly, the discrete switching device die 120 is configured as a lateral device that conducts in a direction parallel to the major surface of the device. Optionally, the discrete switching device die 120 may include a substrate connection terminal ( Figure 1 not shown in). The substrate connection terminal may be used to hold the substrate of the die at a fixed potential, such as the source potential. The substrate connection terminal may be provided on the major surface of the die or on the back surface of the die. If the substrate connection terminal is provided on the back surface of the die, the substrate connection terminal may be electrically connected to the die pad 104 by a conductive adhesive (e.g., sinter, solder, etc.).

[0019] The semiconductor package assembly 100 is configured such that each discrete switching device die 120 in the discrete switching device die 120 is electrically connected in parallel. That is, from the perspective of the externally accessible terminals, the semiconductor package is configured to function as a single switching device. The parallel configuration of the semiconductor package is achieved through package-level electrical interconnections between the discrete switching device die 120 and the leads 106. These electrical interconnections are schematically depicted in Figure 1 . Generally, using any type of package interconnect element (e.g., metal interconnect clips, tapes, bond wires, etc.), each electrical interconnection can be achieved. Additionally, these electrical interconnections may include one or more conductive runners 105. The conductive runner 105 may be formed by an elongated metal strip or track extending along the die attachment surface of the die pad 104. The conductive runner 105 may be provided by a separate metal structure (e.g., a structure formed of copper, aluminum, and their alloys) mounted on the die pad 104. If electrical isolation from the die pad 104 is required, the separate metal structure may be attached using an electrically insulating adhesive (e.g., insulating tape, epoxy resin, etc.). The electrically insulating adhesive can be provided by a multi-piece material epoxy resin that separates the metal structure from the die pad 104, or by a continuous strip of material (e.g., insulating tape) disposed between the metal structure and the die pad 104. If electrical connection to the die pad 104 is required, the separate metal structure may be attached using a conductive adhesive (e.g., solder, sinter, conductive glue, etc.). In the case where the die pad 104 is part of or formed by an insulating electronic device substrate (e.g., PCB, DCB, IMS, AMB, etc.), the conductive runner 105 may also be formed by a metal track formed on the surface of the insulating electronic device substrate, and electrical isolation may be provided by the underlying electrically insulating substrate region.

[0020] The semiconductor package includes the following electrical interconnections. The first electrical interconnection 128 electrically connects the first load terminal pads 124 of each discrete switching device die 120 from the discrete switching device die 120 to the first package load terminal 108. The second electrical interconnection 130 electrically connects the second load terminal pads 126 of each discrete switching device die 120 from the discrete switching device die 120 to the second package load terminal 110. The third electrical interconnection 132 electrically connects the gate terminal pads 122 of each discrete switching device die 120 from the discrete switching device die 120 to the package gate terminal 112. The fourth electrical interconnection 134 electrically connects the first load terminal pads 124 of each discrete switching device die 120 from the discrete switching device die 120 to the package sense terminal 114.

[0021] According to an embodiment, the third electrical interconnection 132 is configured such that the resistance of the first gate connection that electrically connects the gate terminal pad 122 of the first discrete switching device die 120 from the discrete switching device die 120 to the package gate terminal 112 is substantially matched to the resistance of the second gate connection that electrically connects the gate terminal pad 122 of the second discrete switching device die 120 from the discrete switching device die 120 to the package gate terminal 112. That is, the gate connections of each discrete switching device die 120 from the discrete switching device die 120 are resistively matched to each other. This resistance matching promotes synchronous switching behavior between the two discrete switching device dies 120. The third electrical interconnection 132 can be further configured such that the inductance, capacitance, or overall impedance of the first and second gate connections are substantially matched to each other, thereby further promoting synchronous switching behavior.

[0022] Through the configuration and arrangement of the interconnect elements and the conductive traces 105 (if any) used to form the third electrical interconnect 132, resistance matching and / or impedance matching of the first and second gate connections can be achieved. For example, in embodiments where each of the first and second gate connections is formed by an electrical interconnect element, the total length of the electrical interconnect elements forming the first gate connection can be substantially matched to the total length of the electrical interconnect elements forming the second gate connection. More particularly, the first gate connection can include a first bond wire directly connecting the gate terminal pad 122 of the first discrete switching device die 120 from the discrete switching device die 120 to the package gate terminal 112 and a second bond wire directly connecting the gate terminal pad 122 of the second discrete switching device die 120 from the discrete switching device die 120 to the package gate terminal 112, and the first and second bond wires can be substantially equal in length, thereby creating a resistance-matched electrical connection. In cases where one or both of the first and second gate connections include multiple bond wires, the total length of the bond wires for each connection (i.e., the sum of the lengths of each bond wire) can be substantially matched. In cases where the third electrical interconnect 132 includes a conductive trace 105 and the first and second gate connections include bond wires that contact the conductive trace 105 at different locations, the lengths of the bond wires can be close to or the same as each other. In some cases, there may be a slight difference between the total lengths of the bond wires connecting between the die and the conductive trace 105 to account for different contact points of the bond wires.

[0023] Similarly, any one of the first, second, and fourth electrical interconnections 128, 130, 134 may also be configured such that the resistance and / or impedance of the corresponding connections are matched between two or more of the discrete switching device dies 120 in the discrete switching device die 120. In an embodiment, the first electrical connection may include: a first metal clip electrically connecting a first load terminal pad 124 from a first discrete switching device die 120 in the discrete switching device die 120 to a first package load terminal 108; and a second metal clip electrically connecting a first load terminal pad 124 from a second discrete switching device die 120 in the discrete switching device die 120 to the first package load terminal 108, wherein the first and second metal clips are substantially the same in length and may be identical to each other. Correspondingly, the second electrical connection may include: a third metal clip electrically connecting a second load terminal pad from a first discrete switching device die 120 in the discrete switching device die 120 to a second package load terminal 110; and a fourth metal clip electrically connecting a second load terminal pad from a second discrete switching device die 120 in the discrete switching device die 120 to the second package load terminal 110, wherein the third and fourth metal clips are substantially the same in length and may be identical to each other. The fourth electrical interconnection 134 may be implemented using the same electrical interconnection elements as the third electrical interconnection 132 and may be impedance and / or resistance matched in a similar manner as the third electrical interconnection 132.

[0024] In Figure 1 the semiconductor package assembly 100 to the left of, the third and fourth electrical interconnections 132, 134 each include conductive traces 105. By providing the conductive traces 105 on the die pads 104, the third and fourth electrical interconnections 132, 134 may be routed under at least one of the electrical interconnection elements used to form the first electrical interconnection 132. This allows for improved space efficiency and facilitates impedance and / or resistance matching of the third and fourth electrical interconnections 132, 134, for example, by selection of the electrical interconnection length between the die and the conductive traces 105. The third electrical interconnection 132 may include: a first electrical interconnection element electrically connecting a gate terminal pad 122 from a first discrete switching device die 120 in the discrete switching device die 120 to one of the conductive traces; a second electrical interconnection element electrically connecting a gate terminal pad 122 from a second discrete switching device die 120 in the discrete switching device die 120 to one of the conductive traces. The length and / or resistance of the first and second electrical interconnection elements may be adjusted to create impedance-matched connections.

[0025] In Figure 1In the semiconductor package assembly 100 in the middle, the discrete switching device dies 120 mounted adjacent to each other have different pad geometries. That is, the geometric arrangement of the gate terminal pads 122 and the first and second load terminal pads 124, 126 of the first discrete switching device die 120 among the discrete switching device dies 120 on the left semiconductor package assembly 100 is different from the geometric arrangement of the gate terminal pads 122 and the first and second load terminal pads 124, 126 of the second discrete switching device die 120 among the discrete switching device dies 120 on the right semiconductor package assembly 100. In this case, with respect to the pad geometry of the second discrete switching device die 120 among the discrete switching device dies 120, the pad geometry of the first discrete switching device die 120 among the discrete switching device dies 120 forms a mirror image. That is, with respect to the symmetry axis extending vertically through the center of each die, the two pad geometries are inverted. In addition, each discrete switching device die has an asymmetric pad geometry, where the gate terminal pad 122 is placed on one side of the corresponding device die. This allows an arrangement whereby the gate terminal pads 122 of the first discrete switching device die 120 among the discrete switching device dies 120 and the gate terminal pads 122 of the second discrete switching device die 120 among the discrete switching device dies 120 are placed adjacent to the sides of the first and second discrete switching device dies 120 facing each other. Thus, these gate terminal pads 122 can be easily accessed from the central region of the semiconductor package assembly 100 between the interconnect elements for forming the first electrical interconnection 132. The lead configuration of the carrier is thus adapted such that the leads 106 forming the package gate terminals 112 and the leads 106 forming the package sense terminals 114 are arranged between two sets of leads 106, each set of leads 106 forming a first package load terminal 108.

[0026] In Figure 1 the middle of the semiconductor package assembly 100, a third electrical interconnection 132 can be implemented without using the conductive tracks 105. A first gate connection can be achieved by directly connecting the gate terminal pads 122 of the first discrete switching device die 120 among the discrete switching device dies 120 to the first electrical interconnecting elements of the package gate terminals 112 and directly connecting the gate terminal pads 122 of the second discrete switching device die 120 among the discrete switching device dies 120 to the second electrical interconnecting elements of the package gate terminals 112. A fourth electrical interconnection 134 can likewise be implemented without using the conductive tracks 105.

[0027] In Figure 1In the semiconductor package component 100 on the right side, the discrete switching device dies 120 mounted adjacent to each other have the same pad geometry. Additionally, these discrete switching device dies 120 can be the same device. In this case, the pad geometry from the discrete switching device dies 120 is configured with two gate terminal pads 122 placed on opposite sides of the die. That is, the discrete switching device dies 120 are configured such that the gate can be accessed from either side of the die. In this way, the semiconductor package component 100 can be configured such that the gate terminal pads 122 from the first discrete switching device die 120 in the discrete switching device dies 120 and the gate terminal pads 122 from the second discrete switching device die 120 in the discrete switching device dies 120 are arranged adjacent to the sides of the first and second discrete switching device dies 120 facing each other. Thus, the semiconductor package component 100 can have an interconnect arrangement similar to that of Figure 1 the semiconductor package in the middle, where all of the interconnect elements forming the third and fourth electrical interconnections 132, 134 are placed in the central region of the semiconductor package. By making the discrete switching device dies 120 have the same pad geometry, the processing cost can be relatively low because exactly the same devices can be used. On the other hand, since a small amount of pad size of the second gate terminal pad 122 is sacrificed, for the reduced load terminal resistance, Figure 1 the semiconductor package component 100 in the middle may be preferred.

[0028] In addition to Figure 1In addition to the two-die arrangement specifically shown in the figure, the semiconductor package assembly 100 may also include a package configuration having more than two switching device dies, where each switching device die is connected in parallel with each other between the package device terminals. In a specific example of this case, the semiconductor package assembly 100 may include four discrete switching device dies 120 in the discrete switching device dies 120, that is, the first, second, third, and fourth discrete switching device dies 120 in the discrete switching device dies 120, where the first, second, third, and fourth discrete switching device dies 120 are all electrically connected in parallel. Thus, the first electrical interconnect 128 electrically connects the first load terminal pads 124 from the first, second, third, and fourth discrete switching device dies 120 to the first package load terminal 108, the second electrical interconnect 130 electrically connects the second load terminal pads from the first, second, third, and fourth discrete switching device dies 120 to the second package load terminal 110, the third electrical interconnect 132 electrically connects the gate terminal pads from the first, second, third, and fourth discrete switching device dies 120 to the package gate terminal 112, and the fourth electrical interconnect electrically connects the first load terminal pads 124 from the first, second, third, and fourth discrete switching device dies 120 to the package sense terminal 114. In this example, according to any of the above techniques / configurations, each of the first, second, third, and fourth electrical interconnects 128, 130, 132, and 134 can be implemented.

[0029] After the die is installed and the electrical interconnects are formed and the encapsulation process can be formed to cover the die pads 104, the discrete switching device die 120 and the electrical interconnect components can be encapsulated using an electrically insulating encapsulant body 205, for example, as Figure 15 shown. At the same time, the outer ends of the leads 106 remain exposed from the electrically insulating encapsulant body 205, forming externally accessible package terminals. The encapsulation process may include, for example, forming an electrically insulating molded compound by injection molding, transfer molding, compression molding, etc. A slicing process may be performed to form a complete semiconductor package.

[0030] Referring to Figure 2, according to an embodiment, a semiconductor package assembly 100 is depicted. The semiconductor package assembly 100 includes a pair of discrete switching device dies 120 mounted side by side with each other. Each of the discrete switching device dies 120 has an asymmetric pad geometry, where the gate terminal pads 122 are placed on one side of the corresponding die. The discrete switching device dies 120 can be identical to each other. The discrete switching device dies 120 are electrically connected in parallel with each other through first, second, third, and fourth electrical interconnections 128, 130, 132, 134. In this case, the first and second electrical interconnections 128, 130 are implemented through metal clips. In particular, the first electrical interconnection 128 includes: a first metal clip electrically connecting the first load terminal pad 124 from the first discrete switching device die 120 to the first package load terminal 108; and a second metal clip electrically connecting the first load terminal pad 124 from the second discrete switching device die 120 to the first package load terminal 108. At the same time, the second electrical interconnection 130 includes: a third metal clip electrically connecting the second load terminal pad 126 from the first discrete switching device die 120 to the second package load terminal 110; and a fourth metal clip electrically connecting the second load terminal pad 126 from the second discrete switching device die 120 to the second package load terminal 110. The third and fourth electrical interconnections 132, 134 of the semiconductor package assembly 100 include: conductive traces 105 bonded to the die pads 104 through an electrically insulating adhesive (e.g., epoxy resin). These conductive traces 105 all extend under the first metal clip from the first electrical interconnection 128 and are separated from the first metal clip.

[0031] Referring to Figure 3 , according to another embodiment, a semiconductor package assembly 100 is depicted. Different from Figure 2 the embodiment of Figure 3 , the semiconductor package assembly 100 includes a direct connection 138 between the die pad 104 and the first landing pad 116. This direct connection places the die pad 104 at the same electrical potential as the first package load terminal 108. In this case, the discrete switching device die 120 can include a substrate connection terminal placed on the back surface of the die, and the substrate connection terminal is electrically connected to the die pad 104 through an electrically conductive adhesive (e.g., sintered material, solder, etc.).

[0032] Referring to Figure 4 , according to another embodiment, a semiconductor package assembly 100 is depicted. Different from Figure 3 the embodiment of Figure 3The semiconductor package assembly 100 is configured such that the discrete switching device dies 120 mounted adjacent to each other have an asymmetric pad geometry, whereby the gate terminal pads 122 are placed on one side of the respective device die. Additionally, the pad geometry of the first discrete switching device die 120 (e.g., on the left side of the drawing) among the discrete switching device dies 120 forms a mirror image with respect to the pad geometry of the second discrete switching device die 120 (e.g., on the right side of the drawing) in the discrete switching device dies 120. As a result, the gate terminal pads 122 of the two discrete switching device dies 120 are arranged closely together in the central region of the semiconductor package assembly 100. In this embodiment, the third electrical interconnection 132 includes: a first gate connection formed by a bonding wire directly connecting between the bonding pad from the first discrete switching device die 120 among the discrete switching device dies 120 and the package gate terminal 112; and a second gate connection formed by a bonding wire directly connecting between the bonding pad from the second discrete switching device die 120 among the discrete switching device dies 120 and the package gate terminal 112. These two bonding wires can be configured to be substantially equal in length, thereby substantially matching the resistance of the first and second gate connections.

[0033] Referring to Figure 5 , according to another embodiment, the semiconductor package assembly 100 is depicted. Different from Figure 4 the embodiment of Figure 5 the semiconductor package assembly 100 is configured such that the discrete switching device dies 120 mounted adjacent to each other have the same pad geometry. The two discrete switching device dies 120 can be identical to each other. In this case, the pad geometry from the discrete switching device die 120 is configured with two gate terminal pads 122 placed on opposite sides of the die. As a result, the first gate connection is formed by a first bonding wire directly connecting the first gate terminal pad 122 from the first discrete switching device die 120 to the package gate terminal 112, and the second gate connection is formed by a second bonding wire directly connecting the second gate terminal pad 122 from the first discrete switching device die 120 to the package gate terminal 112, and the first and second gate connections can be arranged in the central region of the semiconductor package assembly 100 between the first and second metal clips in a manner similar to the above.

[0034] Referring to Figure 6 , according to another embodiment, the semiconductor package assembly 100 is depicted. Similar to Figure 5 the embodiment of Figure 6The semiconductor package assembly 100 is configured such that the discrete switching device dies 120 mounted adjacent to each other have the same pad geometry, and each discrete switching device die 120 is configured with two gate terminal pads 122 disposed on opposite sides of the die. In this case, the semiconductor package assembly 100 includes a total of four discrete switching device dies 120 among the discrete switching device dies 120, where two pairs of device dies are mounted side by side with each other in a manner similar to the above. The semiconductor package assembly 100 is configured such that all four discrete switching device dies 120 among the discrete switching device dies 120 are connected in parallel with each other. By tying together all the gate connection loops in the gate connections, a third electrical interconnection 132 is formed. In particular, the gate terminal pads 122 located outside the first and third discrete switching device dies 120 (e.g., on the right side of the drawing) among the discrete switching device dies 120 are connected together by bonding wires, and the gate terminal pads 122 located outside the second and fourth discrete switching device dies 120 (e.g., on the left side of the drawing) among the discrete switching device dies 120 are connected together by bonding wires. At the same time, the gate terminal pads 122 located inside each of the first, second, third, and fourth discrete switching device dies 120 among the discrete switching device dies 120 are directly connected to the center lead 106 forming the package gate terminal 112. This forms a symmetric loop that balances the gate signals among the various semiconductor dies, thereby promoting uniform switching behavior.

[0035] In Figure 6In an embodiment, the first and second electrical interconnections 128, 130 are provided by overlapping metal clips. More specifically, the first electrical interconnection 128 includes: a first metal clip that connects together the first load terminal pads 124 from the first and third discrete switching device dies 120 to the die pad 104; and a second metal clip that connects together the first load terminal pads 124 from the second and fourth discrete switching device dies 120 to the die pad 104. As can be seen, in a manner similar to the above, the die pad 104 is directly connected to the first landing pad 116 via a direct connection 138. In this way, the die pad 104 can be used to connect the first package load terminals 108 to each of the first load terminal pads 124. The second electrical interconnection 130 includes: a third metal clip that connects together the second load terminal pads 126 from the first and third discrete switching device dies 120; and a fourth metal clip that electrically connects together the second load terminal pads 126 from the second and fourth discrete switching device dies 120. The metal clips used to form these two electrical interconnections are stacked on top of each other in the vertical direction. In particular, the third metal clip extends above and is separated from the first metal clip, and the fourth metal clip extends above and is separated from the second metal clip.

[0036] Referring to Figure 7 , in accordance with another embodiment, a semiconductor package assembly 100 is depicted. Different from Figure 6 the embodiment of Figure 7 the semiconductor package assembly 100 is configured such that both the third and fourth electrical interconnections 132, 134 include conductive traces 105 mounted on the die pad 104 within the central region of the semiconductor package assembly 100. More specifically, the third electrical interconnection 132 includes a single conductive trace 105 that is disposed within the central region and extends completely to reach the landing pad associated with the package gate terminal 112. By bonding wires, the gate terminal pads 122 from each of the first, second, third, and fourth discrete switching device dies 120 are directly connected to this single conductive trace 105. At the same time, the fourth electrical interconnection 134 is provided by a pair of conductive traces 105 disposed on either side of the central conductive trace 105. Each of these conductive traces 105 can be attached to the die pad 104 by an electrically insulating adhesive and to the corresponding landing pad by a conductive adhesive. By allowing for equal or near-equal length interconnecting elements between all four dies, the provision of the conductive traces 105 can facilitate more uniform resistance and / or impedance matching for the third and fourth electrical interconnections 132, 134.

[0037] Referring to Figure 8, according to another embodiment, a semiconductor package assembly 100 is depicted. Figure 8 The semiconductor package assembly 100 of Figure 8 has a lead frame configuration and corresponding package style different from the previously depicted semiconductor package assembly 100. In this case, the die pads 104 are not large enough to accommodate the discrete switching device dies 120 mounted completely side by side with each other. Thus, as shown in the figure, the semiconductor package assembly 100 includes a pair of discrete switching device dies 120 arranged in a partially overlapping arrangement. In this embodiment, each of the first, second, third, and fourth electrical interconnections 128, 130, 132, 134 is at least partially formed by bonding wires. The lead 106 forming the package gate terminal 112 is placed on one side of a set of leads 106 forming the first package load terminal 108. The third electrical interconnection 132 includes: a bonding wire directly connecting the gate terminal pad 122 of the first discrete switching device die 120 from the discrete switching device dies 120 to the package gate terminal 112; and a second bonding wire directly connecting the gate terminal pad 122 of the second discrete switching device die 120 from the discrete switching device dies 120 to the package gate terminal 112. Due to the placement of the dies, these first and second bonding wires can be substantially equal in length. At the same time, using a combination of bonding wires and conductive traces 105, the first electrical interconnection 128 is realized. This allows the same number of bonding wires to be provided for each die within a limited area. The conductive trace 105 forming the first electrical interconnection 128 can be attached to both the die pad 104 and the first landing pad 116 by conductive epoxy resin.

[0038] Referring to Figure 9 , according to another embodiment, a semiconductor package assembly 100 is depicted. Different from Figure 8 the embodiment of Figure 9 the semiconductor package assembly 100 of Figure 9 is configured such that the discrete switching device dies 120 are mounted side by side with each other and have different pad geometries. In particular, in a manner similar to the embodiment of Figure 4 Figure 4 , the pad geometries of the discrete switching device dies 120 form a mirror image with respect to each other. In addition, Figure 9 the semiconductor package assembly 100 of Figure 9 is configured such that in a manner similar to Figure 4In a manner similar to the embodiment of, each of the first and second electrical interconnections 128, 130 is provided by a metal clip. In this case, both the third electrical interconnection 132 and the fourth electrical interconnection 134 each include one of the conductive traces 105 mounted on the die pad 104 and electrically insulated from the die pad 104. These conductive traces 105 are routed under the first metal clip and separated from the first metal clip. The bond wires between each of the discrete switching device dies 120 in the discrete switching device die 120 and the conductive trace 105 from the third electrical interconnection 132 can be of substantially the same length, thereby facilitating resistance and / or impedance matching.

[0039] Referring to Figure 10 , according to another embodiment, a semiconductor package assembly 100 is depicted. Different from Figure 9 the embodiment of Figure 10 the semiconductor package assembly 100 is configured such that the first and second electrical interconnections 128, 130 are provided by continuous metal clips connected to each semiconductor die. In particular, the first electrical interconnection 128 is provided by a first U-shaped clip connected between each of the first and second discrete switching device dies 120 in the first and second discrete switching device dies 120 and the first landing pad 116, and the second electrical connection 130 is provided by a second U-shaped clip connected between each of the first and second discrete switching device dies 120 in the first and second discrete switching device dies 120 and the second landing pad 118.

[0040] Referring to Figure 11, According to another embodiment, semiconductor package assembly 100 is depicted. In this case, semiconductor package assembly 100 includes three discrete switching device dies 120 mounted side by side on die pad 104. In this example, each of the discrete switching device dies 120 is configured as a bidirectional switching device. Different from the previously depicted device dies, each discrete switching device die 120 includes a second gate terminal pad 123. Additionally, each discrete device die includes a substrate connection terminal 125 placed on a major surface of the discrete device die that faces away from die pad 104. Semiconductor package assembly 100 is configured such that, in a manner similar to the above-described manner, each of the three discrete switching device dies 120 is connected in parallel with each other through package-level interconnections. In this case, semiconductor package assembly 100 includes: a second package gate terminal 113 electrically connected to the second gate terminal pad 123 of each of the discrete switching device dies 120 through a fifth electrical interconnection 135. Additionally, semiconductor package assembly 100 includes: a second package sense terminal 115 electrically connected to a second load terminal pad 126 from each of the discrete switching device dies 120 through a sixth electrical interconnection 137.

[0041] In Figure 11 the embodiment of, semiconductor package assembly 100 includes multi-channel conductive traces 105 placed above and below the row of discrete switching device dies 120. The multi-channel conductive traces 105 form two separate electrical paths. The multi-channel conductive traces 105 can be provided by pairs of metal strips mounted using the same electrically insulating adhesive and separated from each other. Alternatively, the multi-channel conductive traces 105 can be provided by a discrete structure having separate conductive metal spans and an insulating region (e.g., plastic, epoxy resin, glass, etc.) between the two spans. Alternatively, the multi-channel conductive traces 105 can be provided by tracks formed in an upper metallization of a carrier. The third and fourth electrical interconnections 132, 134 of semiconductor package assembly 100 include the multi-channel conductive traces 105 placed under the semiconductor die, and the fifth and sixth electrical interconnections 135, 137 of semiconductor package assembly 100 include the multi-channel conductive traces 105 placed under the semiconductor die.

[0042] Semiconductor package assembly 100 additionally includes a substrate connection between the substrate connection terminal 125 of each device die and die pad 104. The substrate connection includes one of the conductive traces 105, where each die is connected to this conductive trace 105 through a bonding wire (as shown in the figure) or other type of electrical interconnection element. The conductive trace 105 forming part of the substrate connection can be attached through conductive epoxy resin, solder material, selective plating, etc.

[0043] Referring to Figure 12 , according to another embodiment, semiconductor package assembly 100 is depicted. In this case, semiconductor package assembly 100 includes two discrete switching device dies 120 mounted side by side on die pad 104, wherein each of the discrete switching device dies 120 is configured as a bidirectional switching device. In this case, for example, in a manner similar to the above, the discrete switching device dies 120 mounted adjacent to each other have mirror-image pad geometries.

[0044] Referring to Figure 13 , according to another embodiment, semiconductor package assembly 100 is depicted. Figure 13 The semiconductor package assembly 100 of Figure 12 is substantially the same as the semiconductor package assembly 100 of Figure 12 with the following exceptions. The discrete switching device dies 120 each include substrate connection terminals 125. In this case, the substrate connection is formed by bonding wires extending directly from the substrate connection terminals 125 to the lead frame. Additionally, the discrete switching device dies 120 each include redundant pads for each of the first and second gate terminal pads 122, 123. In addition to being connected to the package gate terminal 112 and the second package gate terminal 113 of the package, the adjacent gates of the two device dies are directly connected to each other using the redundant pads, thereby improving the synchronous switching behavior.

[0045] Referring to Figure 14 , according to another embodiment, semiconductor package assembly 100 is depicted. Figure 14 The semiconductor package assembly 100 of Figure 13 is substantially the same as the semiconductor package assembly 100 of Figure 13 with the following exceptions: The first and second electrical interconnections 128, 130 are provided by continuous metal clips connected to each semiconductor die. In particular, the first electrical interconnection 128 is provided by a first U-shaped clip connected between each of the first and second discrete switching device dies 120 and the first landing pad 116, and the second electrical interconnection 130 is provided by a second U-shaped clip connected between each of the first and second discrete switching device dies 120 and the second landing pad 117.

[0046] Referring to Figure 15, according to an embodiment, a cross-sectional view of a semiconductor package 200 is shown. The semiconductor package 200 includes a carrier that includes a die pad 104 and a plurality of leads 106 that extend away from the die pad 104. At least one discrete switching device die 120 is mounted on the die pad 104. The semiconductor package 200 includes: a first package load terminal 108 formed by one or more of the leads 106; and a second package load terminal 110 formed by one or more of the leads 106. Through a first metal clip 202, a first load terminal pad 124 of the discrete switching device die 120 is electrically connected to the lead 106 that forms the first package load terminal 108. Through a second metal clip 202, a second load terminal pad 126 of the discrete switching device die 120 is electrically connected to the lead 106 that forms the second package load terminal 110. An electrically insulating encapsulant body 205 encapsulates the components mounted on the die pad 104 and the associated electrical interconnect components while exposing the outer ends of the leads 106. The encapsulant body 205 may be formed of a molding compound such as epoxy resin, thermosetting plastic, etc.

[0047] According to an embodiment, the semiconductor package 200 is provided from any of the semiconductor packages 100 in the above semiconductor package assembly 100, wherein the first and second electrical interconnections 128, 130 are provided by metal clips. Figure 15 The cross-sectional view may correspond to a cross-section intersecting any one of the dies connected in parallel. Additionally, embodiments of the semiconductor package 200 include configurations having more than two discrete switching device dies 120, for example, as Figure 5 and 6 shown in the semiconductor package assembly 100, wherein the metal clip that forms at least the second electrical interconnection 130 includes a local constriction 204 to be described below. More generally, the semiconductor package 200 may correspond to any semiconductor package having at least one discrete switching device die 120 and at least one metal clip 202 having a local constriction 204 to be described below.

[0048] During operation of the semiconductor package assembly 100, a large amount of heat is generated by the discrete switching device die 120. Some of this heat can be dissipated through the underside of the discrete switching device die 120, which is mounted on a thermally conductive die pad 104 that in turn can be mounted on an external heat sink. However, a large amount of heat can remain on the major surfaces of the discrete switching device die 120. This problem can be particularly acute for the lateral switching device configurations disclosed herein (specifically, for example, HEMTs and bidirectional switches formed according to III-V semiconductor technology). In an embodiment, the major surfaces of these devices can operate at temperatures in the range of approximately 100°C to 250°C (and more particularly, in the range of approximately 125°C to 150°C).

[0049] The metal clip 202 forms a highly thermally conductive structure that is capable of drawing heat away from the major surfaces of the discrete switching device die 120. In fact, the relatively large size and width of the metal clip 202 make these types of interconnect components an attractive option in power device applications because they are capable of accommodating large load currents. However, this also creates a highly thermally conductive path for much of the heat from the major surfaces of the discrete switching device die 120 to be transferred to the lead(s) 106 to which the metal clip 202 is connected. While some heat dissipation is beneficial, too much heat transfer can cause problems when the semiconductor package 200 is mounted because overheating of the leads 106 can damage or impair the lead connections (e.g., solder connections) between the semiconductor package and external devices (e.g., a PCB). In particular, in the case of a package configuration configured to operate at high current, this can result in unwanted overheating that can irreparably damage the lead connections.

[0050] According to an embodiment, at least one of the metal clips 202 includes: a local constriction 204 that is placed in the thermal conduction path between the discrete device die and the landing pad to which it is connected. The local constriction 204 is a geometric feature in the clip whereby the cross-sectional area of the clip is locally reduced and, as a result, the thermal conductivity of the metal clip 202 is lower compared to the adjacent section regions of the clip. The local constriction 204 can correspond to a section region of the metal clip 202 where the effective width of the metal clip 202 (i.e., the total width of the clip in the direction of thermal conduction / current flow) is reduced. Separately or in combination, the local constriction 204 can correspond to a section region of the metal clip 202 where the effective thickness of the metal clip 202 (i.e., the total thickness of the clip in the direction of thermal conduction / current flow) is reduced. The presence of the local constriction 204 allows for a beneficial trade-off between thermal conduction and electrical conduction, where the metal clip 202 is still able to accommodate large load currents but has sufficient thermal resistance to prevent overheating of the leads 106 from causing damage to the lead connections.

[0051] Refer toFigure 16 , according to an embodiment, a metal clip 202 with a local constriction 204 is shown. In this case, the local constriction 204 is formed by a pair of perforations in the metal clip 202. The clip includes: a first end 201 that can be attached to a terminal of a die; and a second end 203 that can be attached to a surface of a lead frame, such as a landing pad. The metal clip 202 is an elongated piece of metal, such as copper, aluminum, nickel, etc. and their alloys, that extends between the first end 201 and the second end 203. During operation of the device, heat flows from the first end 201 to the second end 203. In this example, the distance between the outer edge sides of the metal clip 202 remains constant along the entire length of the clip. The pair of perforations in the metal clip 202 reduces the effective width of the metal clip 202 and creates three local constrictions 204 in the local constriction 204. As a result, the metal clip 202 has a greater thermal resistance in the middle section area including the local constriction 204 compared to the adjacent portions of the metal clip 202.

[0052] Refer to Figure 17 , according to an embodiment, a metal clip 202 with a local constriction 204 is shown. In this case, the local constriction 204 is formed by a pair of grooves formed on the outer edge side of the metal clip 202. In this case, the pair of grooves are adjacent to each other and opposite. The pair of grooves reduces the effective width of the metal clip 202 and thus increases the thermal resistance in the middle section area including the local constriction 204. The grooves can have any geometric shape, such as rectangular, triangular, etc. Additionally, a local constriction 204 can be achieved by a single groove located on one outer side of the metal clip 202.

[0053] Refer to Figure 18 , according to an embodiment, a metal clip 202 with a local constriction 204 is shown. In this case, the metal clip 202 includes constrictions 204 placed at different length positions of the metal clip 202. In this embodiment, the metal clip 202 includes a pair of perforations that form multiple constrictions 204 at one length position and a groove that forms another constriction 204 at a different length position. Thus, the metal clip 202 has a greater thermal resistance in two different section areas along the heat flow direction.

[0054] Refer to Figure 19, according to an embodiment, a metal clip 202 with a local constriction 204 is shown. In this embodiment, in addition to the local constriction 204, the metal clip 202 further includes a local width increase 206. The local width increase 206 refers to a section of the metal clip 202 where the outer edge sides of the metal clip 202 extend outward. That is, the distance between the outer edge sides of the metal clip 202 is greater in the local width increase 206 compared to other parts of the metal clip 202. As a result, the metal clip 202 has a local increase in surface area. As shown in the drawings, the local width increase 206 can be provided before or after the (one or more) local constrictions 204 in the heat flow direction, and the local width increase 206 can be provided in combination with any type of geometry forming the constriction 204. The local width increase 206 can assist in the adhesion between the metal clip 202 and the surrounding encapsulant material. Separately or in combination, the local width increase 206 can enhance the heat dissipation between the metal clip 202 and the surrounding encapsulant material, thereby further restricting the heat transfer between the die and the package leads.

[0055] Referring to Figure 20 , various embodiments of a metal clip 202 having one or more constrictions 204 formed by one or more perforations are shown. As can be understood from the drawings, the geometry, size, and length position of the perforations and the corresponding constrictions 204 formed by the perforations can vary. The particular design chosen can depend on, for example, application requirements, process capabilities, etc. As shown in the figure, the metal clip 202 can include a plurality of perforations placed at different length positions, thereby creating a plurality of constrictions 204 at different length positions of the metal clip 202. Separately or in combination, the metal clip 202 can include a plurality of perforations arranged side by side at the same length position.

[0056] As used herein, the term "interconnect element" encompasses any conductive element capable of being connected between two conductive regions to effect electrical interconnection therebetween. Examples of interconnect elements include bond wires, tapes, and metal clips. The drawings show some connections provided by a plurality of interconnect elements connected in parallel and some connections provided by a single interconnect element. In any of the embodiments, each of these connections can be provided by a single interconnect element or by more than one interconnect element.

[0057] The terms "electrically connected", "directly electrically connected", etc. refer to an ohmic (i.e., non-rectifying) low-resistance connection between two elements. Such a connection can be achieved through physical contact between the elements involved, or through a conductive medium (such as solder, sinter, adhesive, etc.) disposed between the elements involved.

[0058] As used herein, the term "substantially" means: meeting the specified requirements to the extent possible given manufacturing process variability. For a description of substantially matching resistors and / or capacitors, substantially matching includes configurations that may deviate from each other by + / - 5%.

[0059] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting either. Similar terms always refer to similar elements throughout the description.

[0060] As used herein, the terms "having", "containing", "including", "comprising", etc. are open-ended terms that indicate the presence of the stated element or feature, but do not preclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0061] Although the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the present disclosure.

[0062] Example 1. A semiconductor package, comprising: a carrier including die pads and a plurality of leads; first and second switching device dies, each switching device die including a gate terminal pad and first and second load terminal pads disposed on a major surface; and first package load terminals, second package load terminals, and a package gate terminal, each of which is formed by one or more of the leads, wherein the first and second switching device dies are each configured as discrete III-V semiconductor devices, wherein the first and second switching device dies are each mounted on the die pads with the major surface of each switching device die facing away from the die pads, wherein the first and second switching device dies are electrically connected in parallel, whereby: a first electrical interconnect electrically connects the first load terminal pads from the first and second switching device dies to the first package load terminals; a second electrical interconnect electrically connects the second load terminal pads from the first and second switching device dies to the second package load terminals; and a third electrical interconnect electrically connects the gate terminal pads from the first and second switching device dies to the package gate terminal.

[0063] Example 2. The semiconductor package as described in Example 1, wherein the third electrical interconnection is configured such that: the resistance of electrically connecting the gate terminal pad of the first switching device die to the first gate connection of the package gate terminal is substantially matched with the resistance of electrically connecting the gate terminal pad of the second switching device die to the second gate connection of the package gate terminal; or the inductance of electrically connecting the gate terminal pad of the first switching device die to the first gate connection of the package gate terminal is substantially matched with the inductance of electrically connecting the gate terminal pad of the second switching device die to the second gate connection of the package gate terminal.

[0064] Example 3. The semiconductor package as described in Example 2, wherein the third electrical interconnection includes a conductive trace placed on the die pad, wherein the first gate connection includes a first bonding wire directly connecting the gate terminal pad from the first switching device die to the conductive trace, and wherein the second gate connection includes a second bonding wire directly connecting the gate terminal pad from the second switching device die to the conductive trace.

[0065] Example 4. The semiconductor package as described in Example 3, wherein the first electrical interconnection includes a first metal clip electrically connecting the first load terminal pad from the first switching device die to the first package load terminal, and wherein the conductive trace from the third electrical interconnection extends under the first metal clip and is electrically isolated from the first metal clip.

[0066] Example 5. The semiconductor package as described in Example 2, wherein the first gate connection is formed by a first interconnecting element directly connecting the gate terminal pad from the first switching device die to the package gate terminal, wherein the second gate connection is formed by a second interconnecting element directly connecting the gate terminal pad from the second switching device die to the package gate terminal, and wherein the length of the first interconnecting element is substantially matched with the length of the second interconnecting element.

[0067] Example 6. The semiconductor package as described in Example 5, wherein the gate terminal pad from the first switching device die and the gate terminal pad from the second switching device die are arranged adjacent to the sides of the first and second switching device dies facing each other.

[0068] Example 7. The semiconductor package as described in Example 6, wherein each of the first and second switching device dies has an asymmetric pad geometry.

[0069] Example 8. The semiconductor package as described in Example 6, wherein each of the first and second switching device dies has the same pad geometry, and wherein each of the first and second switching device dies includes two gate terminal pads among the gate terminal pads disposed adjacent to both sides of the corresponding switching device die.

[0070] Example 9. The semiconductor package as described in Example 5, wherein the first electrical interconnect includes a first metal clip electrically connecting the first load terminal pad from the first switching device die to the first package load terminal, a second metal clip electrically connecting the first load terminal pad from the second switching device die to the first package load terminal, and wherein the first and second interconnect elements are placed in the central region of the semiconductor package between the first and second metal clips.

[0071] Example 10. The semiconductor package as described in Example 2, wherein the carrier further includes a first landing pad disposed between the die pad and the lead forming the first package load terminal, wherein the first package load terminal is formed by a plurality of leads merged with the first landing pad, and wherein the carrier includes a direct connection between the die pad and the first landing pad.

[0072] Example 11. The semiconductor package as described in Example 1, further comprising: third and fourth switching device dies, each switching device die including gate terminal pads and first and second load terminal pads disposed on a major surface, wherein the first and second switching device dies are each configured as discrete III-V semiconductor devices, wherein the first, second, third, and fourth switching device dies are all electrically connected in parallel, whereby: the first electrical interconnect electrically connects the first load terminal pads from the first, second, third, and fourth switching device dies to the first package load terminal; the second electrical interconnect electrically connects the second load terminal pads from the first, second, third, and fourth switching device dies to the second package load terminal; and the third electrical interconnect electrically connects the gate terminal pads from the first, second, third, and fourth switching device dies to the package gate terminal.

[0073] Example 12. The semiconductor package as described in Example 11, wherein the third electrical interconnect is configured such that the resistance of each gate connection electrically connecting the gate terminal pads from each of the first, second, third, and fourth switching device dies to the package gate terminal is substantially matched to each other.

[0074] Example 13. A semiconductor package as described in Example 12, and wherein the first electrical interconnection includes a first metal clip and a second metal clip, the first metal clip connecting the first load terminal pads from the first and third switching device dies together to the die pad, the second metal clip connecting the first load terminal pads from the second and fourth switching device dies together to the die pad, and wherein the second electrical interconnection includes a third metal clip and a fourth metal clip, the third metal clip connecting the second load terminal pads from the first and third switching device dies together and extending over the first metal clip, the fourth metal clip electrically connecting the second load terminal pads from the second and fourth switching device dies together and extending over the second metal clip.

[0075] Example 14. A semiconductor package as described in Example 13, wherein the third electrical interconnection is formed by a set of electrical interconnection elements disposed within a central region of the semiconductor package between each of the first, second, third, and fourth metal clips.

[0076] Example 15. A semiconductor package as described in Example 1, wherein the first electrical interconnection includes a continuous metal clip directly connecting the first load terminal pads from both of the first switching device dies to the first package load terminal, and wherein the second electrical interconnection includes a continuous metal clip directly connecting the second load terminal pads from both of the first switching device dies to the second package load terminal.

[0077] Example 16. A semiconductor package as described in Example 1, wherein both the first and second switching device dies are configured as high electron mobility transistor dies.

[0078] Example 17. A semiconductor package as described in Example 1, wherein both the first and second switching device dies are configured as bidirectional switches, wherein both the first and second switching device dies include second gate terminal pads, and wherein the semiconductor package includes a second package gate terminal formed by one or more of the leads and a fourth electrical interconnection electrically connecting the second gate terminal pads from the first and second switching device dies to the second package gate terminal.

[0079] Example 18. The semiconductor package as described in Example 17, wherein the first electrical interconnection includes: a first set of bonding wires directly connecting the first load terminal pads from the first switching device die to the first package load terminal; a conductive trace directly connected to the first package load terminal; and a second set of bonding wires directly connecting the first load terminal pads from the second switching device die to the conductive trace.

[0080] Example 19. The semiconductor package as described in Example 17, wherein both the first and second switching device dies include second gate terminal pads, and wherein the semiconductor package further includes a second package gate terminal formed by one or more of the leads and a fifth electrical interconnection electrically connecting the second gate terminal pads from the first and second switching device dies to the second package gate terminal, and wherein each of the third and fifth electrical connections includes a multi-channel conductive trace.

[0081] Example 20. The semiconductor package as described in Example 19, wherein both the first and second switching device dies include substrate connection terminal pads, and wherein the substrate connection terminal pads from each of the first and second switching device dies are electrically connected to the die pads.

[0082] Example 21. The semiconductor package as described in Example 20, wherein the semiconductor package further includes a conductive trace mounted on the die pads and electrically connected to the die pads, and wherein, through electrical interconnection elements, the substrate connection terminal pads from each of the first and second switching device dies are electrically connected to the conductive trace.

[0083] Example 22. The semiconductor package as described in Example 1, wherein the semiconductor package further includes a package sense terminal formed by one or more of the leads, and wherein the semiconductor package further includes a fourth electrical interconnection electrically connecting the second load terminal pads from the first and second switching device dies to the package sense terminal.

[0084] Example 23. The semiconductor package as described in Example 22, wherein the fourth electrical interconnect is configured such that: the resistance of the electrical connection between the second terminal pad of the first switching device die and the first sense connection of the package sense terminal is substantially matched with the resistance of the electrical connection between the second terminal pad of the second switching device die and the second sense connection of the package sense terminal; or the inductance of the electrical connection between the second terminal pad of the first switching device die and the first sense connection of the package sense terminal is substantially matched with the inductance of the electrical connection between the second terminal pad of the second switching device die and the second sense connection of the package sense terminal.

[0085] Example 24. The semiconductor package as described in Example 1, wherein the first electrical interconnect includes a first metal clip that electrically connects the first load terminal pad from the first switching device die to the first package load terminal, and wherein the first metal clip includes a local constriction configured to locally reduce the thermal conductivity of the first metal clip in a section of the first metal clip between the first switching device die and the first package load terminal.

[0086] Example 25. The semiconductor package as described in Example 24, wherein the local constriction is formed by at least one of the following structures: a perforation spaced apart from the outer edge side of the first metal clip; and a groove formed in one of the outer edge sides of the first metal clip.

[0087] Example 26. The semiconductor package as described in Example 24, wherein the first electrical interconnect includes a second metal clip that electrically connects the first load terminal pad from the second switching device die to the first package load terminal, and wherein the second metal clip includes a local constriction configured to locally reduce the thermal conductivity of the second metal clip in a section of the second metal clip between the second switching device die and the first package load terminal.

[0088] It should be understood that, unless specifically stated otherwise, the features of the various embodiments described herein may be combined with each other.

[0089] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: A carrier, comprising die pads and a plurality of leads; First and second switching device dies, each switching device die comprising a gate terminal pad and first and second load terminal pads disposed on a major surface; And A first package load terminal, a second package load terminal, and a package gate terminal, each of which is formed by one or more of the leads, Wherein the first and second switching device dies are each configured as discrete III-V semiconductor devices, Wherein the first and second switching device dies are each mounted on the die pads, with the major surfaces from each switching device die facing away from the die pads, Wherein the first and second switching device dies are electrically connected in parallel, whereby: A first electrical interconnection electrically connects the first load terminal pads from the first and second switching device dies to the first package load terminal; A second electrical interconnection electrically connects the second load terminal pads from the first and second switching device dies to the second package load terminal; And A third electrical interconnection electrically connects the gate terminal pads from the first and second switching device dies to the package gate terminal.

2. The semiconductor package of claim 1, wherein the third electrical interconnection is configured such that: The resistance of a first gate connection electrically connecting the gate terminal pad of the first switching device die to the package gate terminal is substantially matched to the resistance of a second gate connection electrically connecting the gate terminal pad of the second switching device die to the package gate terminal; or The inductance of a first gate connection electrically connecting the gate terminal pad of the first switching device die to the package gate terminal is substantially matched to the inductance of a second gate connection electrically connecting the gate terminal pad of the second switching device die to the package gate terminal.

3. The semiconductor package of claim 2, wherein the third electrical interconnection comprises a conductive trace disposed on the die pads, wherein the first gate connection comprises a first bonding wire directly connecting the gate terminal pad from the first switching device die to the conductive trace, and wherein the second gate connection comprises a second bonding wire directly connecting the gate terminal pad from the second switching device die to the conductive trace.

4. The semiconductor package of claim 3, wherein the first electrical interconnection comprises a first metal clip electrically connecting the first load terminal pad from the first switching device die to the first package load terminal, and wherein the conductive trace from the third electrical interconnection extends under the first metal clip and is electrically isolated from the first metal clip.

5. The semiconductor package according to claim 2, wherein the first gate connection is formed by a first interconnecting element directly connecting the gate terminal pad from the first switching device die to the package gate terminal, wherein the second gate connection is formed by a second interconnecting element directly connecting the gate terminal pad from the second switching device die to the package gate terminal, and wherein the length of the first interconnecting element substantially matches the length of the second interconnecting element.

6. The semiconductor package according to claim 5, wherein the gate terminal pad from the first switching device die and the gate terminal pad from the second switching device die are disposed adjacent to the sides of the first and second switching device dies facing each other.

7. The semiconductor package according to claim 6, wherein each of the first and second switching device dies has an asymmetric pad geometry.

8. The semiconductor package according to claim 6, wherein each of the first and second switching device dies has the same pad geometry, and wherein each of the first and second switching device dies includes two gate terminal pads disposed adjacent to both sides of the corresponding switching device die.

9. The semiconductor package according to claim 5, wherein the first electrical interconnect includes a first metal clip electrically connecting the first load terminal pad from the first switching device die to the first package load terminal, a second metal clip electrically connecting the first load terminal pad from the second switching device die to the first package load terminal, and wherein the first and second interconnecting elements are placed in a central region of the semiconductor package between the first and second metal clips.

10. The semiconductor package according to claim 2, wherein the carrier further includes a first landing pad disposed between the die pad and the lead forming the first package load terminal, wherein the first package load terminal is formed by a plurality of leads merged with the first landing pad, and wherein the carrier includes a direct connection between the die pad and the first landing pad.

11. The semiconductor package according to claim 1, further comprising: third and fourth switching device dies, each switching device die including a gate terminal pad and first and second load terminal pads disposed on a major surface, wherein the first and second switching device dies are each configured as discrete III-V semiconductor devices, wherein the first, second, third, and fourth switching device dies are all electrically connected in parallel, whereby: the first electrical interconnect electrically connects the first load terminal pads from the first, second, third, and fourth switching device dies to the first package load terminal; the second electrical interconnect electrically connects the second load terminal pads from the first, second, third, and fourth switching device dies to the second package load terminal; and The third electrical interconnection electrically connects the gate terminal pads from the first, second, third, and fourth switching device dies to the package gate terminal.

12. The semiconductor package of claim 11, wherein the third electrical interconnection is configured such that the resistance of each gate connection electrically connecting the gate terminal pads from each of the first, second, third, and fourth switching device dies to the package gate terminal is substantially matched to each other.

13. The semiconductor package of claim 12, and wherein the first electrical interconnection includes a first metal clip and a second metal clip, the first metal clip connecting the first load terminal pads from the first and third switching device dies together to the die pad, the second metal clip connecting the first load terminal pads from the second and fourth switching device dies together to the die pad, and wherein the second electrical interconnection includes a third metal clip and a fourth metal clip, the third metal clip connecting the second load terminal pads from the first and third switching device dies together and extending over the first metal clip, the fourth metal clip electrically connecting the second load terminal pads from the second and fourth switching device dies together and extending over the second metal clip.

14. The semiconductor package of claim 13, wherein the third electrical interconnection is formed by a set of electrical interconnection elements disposed within a central region of the semiconductor package between each of the first, second, third, and fourth metal clips.

15. The semiconductor package of claim 1, wherein the first electrical interconnection includes a continuous metal clip directly connecting the first load terminal pads from both of the first switching device dies to the first package load terminal, and wherein the second electrical interconnection includes a continuous metal clip directly connecting the second load terminal pads from both of the first switching device dies to the second package load terminal.

16. The semiconductor package of claim 1, wherein both the first and second switching device dies are configured as high electron mobility transistor dies.

17. The semiconductor package of claim 1, wherein both the first and second switching device dies are configured as bidirectional switches, wherein both the first and second switching device dies include a second gate terminal pad, and wherein the semiconductor package includes a second package gate terminal formed by one or more of the leads and a fourth electrical interconnection electrically connecting the second gate terminal pads from the first and second switching device dies to the second package gate terminal.

18. The semiconductor package according to claim 17, wherein the first electrical interconnection includes: A first set of bond wires directly connecting the first load terminal pad from the first switching device die to the first package load terminal; A conductive trace directly connected to the first package load terminal; and a second set of bonding wires that directly connect the first load terminal pads from the second switching device die to the conductive traces.

19. The semiconductor package of claim 17, wherein both the first and second switching device dies include second gate terminal pads, and wherein the semiconductor package further includes a second package gate terminal formed by one or more of the leads and a fifth electrical interconnect that electrically connects the second gate terminal pads from the first and second switching device dies to the second package gate terminal, and wherein each of the third and fifth electrical connections includes a multi-channel conductive trace.

20. The semiconductor package of claim 19, wherein both the first and second switching device dies include substrate connection terminal pads, and wherein the substrate connection terminal pads from each of the first and second switching device dies are electrically connected to the die pads.

21. The semiconductor package of claim 20, wherein the semiconductor package further includes conductive traces mounted on the die pads and electrically connected to the die pads, and wherein the substrate connection terminal pads from each of the first and second switching device dies are electrically connected to the conductive traces by electrical interconnect components.

22. The semiconductor package of claim 1, wherein the semiconductor package further includes a package sense terminal formed by one or more of the leads, and wherein the semiconductor package further includes a fourth electrical interconnect that electrically connects the second load terminal pads from the first and second switching device dies to the package sense terminal.

23. The semiconductor package of claim 22, wherein the fourth electrical interconnect is configured such that: the resistance of a first sense connection that electrically connects the second terminal pad of the first switching device die to the package sense terminal substantially matches the resistance of a second sense connection that electrically connects the second terminal pad of the second switching device die to the package sense terminal; or the inductance of a first sense connection that electrically connects the second terminal pad of the first switching device die to the package sense terminal substantially matches the inductance of a second sense connection that electrically connects the second terminal pad of the second switching device die to the package sense terminal.

24. The semiconductor package of claim 1, wherein the first electrical interconnect includes a first metal clip that electrically connects the first load terminal pad from the first switching device die to the first package load terminal, and wherein the first metal clip includes a local constriction that is configured to locally reduce the thermal conductivity of the first metal clip in a section of the first metal clip between the first switching device die and the first package load terminal.

25. The semiconductor package according to claim 24, wherein the local constriction is formed by at least one of the following structures: Perforations, separated from the outer edge side of the first metal clip; and Grooves, formed in one of the outer edge sides of the first metal clip.

26. The semiconductor package according to claim 24, wherein the first electrical interconnection includes a second metal clip that electrically connects the first load terminal pad from the second switching device die to the first package load terminal, and wherein the second metal clip includes a local constriction configured to locally reduce the thermal conductivity of the second metal clip in a section of the second metal clip between the second switching device die and the first package load terminal.

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