Storage array, preparation method, memory and electronic equipment

Abstract

The invention discloses a memory array, a preparation method, a memory and an electronic device, the memory array comprises a ferroelectric capacitor array and a connection electrode, the ferroelectric capacitor array comprises a plurality of ferroelectric capacitors and dielectric layers arranged among the plurality of ferroelectric capacitors, each ferroelectric capacitor comprises a first electrode, a ferroelectric dielectric layer and a second electrode, the ferroelectric layer covers the bottom of the second electrode and extends to the top of the second electrode along part of the side wall of the second electrode, and the first electrode covers the ferroelectric layer. The connecting electrode is located between two adjacent ferroelectric capacitors, the two adjacent ferroelectric capacitors comprise a first ferroelectric capacitor and a second ferroelectric capacitor, a first end of the connecting electrode is connected to a first electrode of the first ferroelectric capacitor, and a second end of the connecting electrode is connected to a second electrode of the second ferroelectric capacitor; other connecting parts do not need to be arranged between the adjacent ferroelectric capacitors so as to be connected with other parts in the memory array, so that the space can be saved, and the arrangement density of the memory units can be improved.

Description

Technical Field

[0001] This application relates to the technical field of memories, and particularly to a memory array, a preparation method, a memory, and an electronic device. Background Art

[0002] A memory is a device used to store information in modern information technology, and can be divided into volatile memory and non-volatile memory. Among them, the volatile dynamic random access memory (DRAM) has the advantages of fast read / write speed and strong durability. However, the traditional DRAM has a small storage capacity and high power consumption. With the rapid development of the Internet of Things, big data, and artificial intelligence, the traditional DRAM can no longer meet the requirements. As a new type of memory, the ferroelectric random access memory (FRAM) has a smaller storage cell size than the traditional DRAM and can achieve faster access speed with lower power consumption, and has been more and more widely used at the present stage. To further improve the storage density of the memory array and increase the storage capacity of the memory, it is necessary to develop a new arrangement method of storage cells. Summary of the Invention

[0003] The memory array, preparation method, memory, and electronic device provided by this application can be used to improve the storage density of the memory array.

[0004] In a first aspect, an embodiment of the present application provides a storage array. The storage array includes a ferroelectric capacitor array and connection electrodes. The ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. Each ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. Among them, the ferroelectric dielectric layer covers the bottom of the second electrode and extends along a part of the sidewall of the second electrode to the top of the second electrode, and the first electrode covers the ferroelectric dielectric layer. Moreover, the plurality of ferroelectric capacitors includes a plurality of capacitor units arranged in a first direction, and each capacitor unit includes a plurality of ferroelectric capacitors arranged in a second direction. The connection electrodes are located between two adjacent ferroelectric capacitors in each capacitor unit. And, two adjacent ferroelectric capacitors include a first ferroelectric capacitor and a second ferroelectric capacitor. The first end of the connection electrode is connected to the first electrode of the first ferroelectric capacitor, and the second end of the connection electrode is connected to the second electrode of the second ferroelectric capacitor. With this arrangement, the first electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor can be electrically connected through the connection electrode, so that no other connection components need to be provided between two adjacent ferroelectric capacitors to connect to the transistors in the storage array, thereby saving space. In particular, in a storage array of the same size, more ferroelectric capacitors can be arranged, which is beneficial to increasing the arrangement density of storage units and further increasing the storage density of the storage array.

[0005] In some embodiments, the plurality of ferroelectric capacitors in the storage array includes a plurality of capacitor units arranged in a first direction. Each capacitor unit includes a plurality of first ferroelectric capacitors and a plurality of second ferroelectric capacitors arranged alternately in a second direction. In this way, the plurality of ferroelectric capacitors arranged in the second direction can be sequentially connected through the connection electrodes. The connection electrodes are embedded in the dielectric layer, and the dielectric layer exposes the first surface of the connection electrodes. The first surface is flush with the top of the second electrode, which can further save the longitudinal space of the storage array.

[0006] In some embodiments, the storage array further includes a transistor array. The transistor array includes a plurality of transistors. The plurality of transistors includes a plurality of first transistors. The plurality of first transistors and the plurality of ferroelectric capacitors are in one-to-one correspondence. And, the first transistor and the corresponding ferroelectric capacitor form a storage unit. Among them, the first electrodes of the ferroelectric capacitors are connected to the first poles of the corresponding first transistors, and the second electrodes of the ferroelectric capacitors are connected to the second poles of the corresponding first transistors. And, in the same capacitor unit, the ferroelectric capacitors are sequentially connected through the above connection method. Thus, the second pole of the first transistor corresponding to the first ferroelectric capacitor and the first pole of the first transistor corresponding to the second ferroelectric capacitor can share the same source-drain region, so that the first transistors corresponding to the ferroelectric capacitors in the same capacitor unit are connected in series to form a chain structure, which can save the space for setting the first pole and the second pole of the first transistor in the storage array, further facilitating the improvement of the arrangement density of storage units. And, the chain storage structure has advantages such as high speed, high density, and anti-crosstalk.

[0007] In some embodiments, the second electrode of the ferroelectric capacitor includes a first electrode portion and a second electrode portion. Among them, the first electrode portion and the second electrode portion are arranged in sequence in the direction from the top to the bottom of the second electrode. And, the ferroelectric dielectric layer wraps the sidewall of the second electrode portion and extends along the first part of the sidewall of the first electrode portion to the top of the second electrode, so that the ferroelectric dielectric layer can expose the second part of the sidewall of the first electrode portion. Thus, the first end of the connection electrode can be connected to at least a partial area of the sidewall of the first electrode at the first electrode portion, and the second end of the connection electrode can be connected to at least a partial area of the second part of the sidewall, so as to achieve the above-mentioned chain connection.

[0008] In some embodiments, in the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the second electrode is the same, that is, the second electrode is a columnar structure. Correspondingly, in the manufacturing process of the ferroelectric capacitor, only the first electrode material and the ferroelectric dielectric material need to be etched. For example, a wet etching process or a dry etching process can be used to etch the first electrode and the ferroelectric dielectric layer respectively.

[0009] Furthermore, the second end of the connection electrode is connected to a partial area of the second part of the sidewall, and the remaining area of the second part of the sidewall is covered by a dielectric layer, so that the dielectric layer can separate the connection electrode and the first electrode corresponding to the second electrode portion of the ferroelectric capacitor, so that the two are insulated from each other.

[0010] Or, in some embodiments, in the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the first electrode portion is smaller than the cross-sectional area of the second electrode portion. Correspondingly, in the manufacturing process of the ferroelectric capacitor, the second electrode, the ferroelectric dielectric layer and the first electrode need to be etched. For example, a dry etching process can be used to etch the second electrode material, the ferroelectric dielectric material and the first electrode material, and the above-mentioned ferroelectric capacitor structure can be formed by only one step of dry etching.

[0011] In some embodiments, the top of the second electrode portion has a first top area and a second top area. The first top area and the second top area are arranged along a second direction. The first electrode portion covers the first top area. The connection electrode is connected to a partial area of the second part of the sidewall, and the remaining area of the second part of the sidewall and the second top area are covered by a dielectric layer, so that the dielectric layer can separate the connection electrode and the first electrode corresponding to the second electrode portion of the ferroelectric capacitor, so that the two are insulated from each other.

[0012] Based on any of the above ferroelectric capacitor structures, the multiple capacitor units in the memory array can also have diverse arrangement patterns. Thus, the relative positional relationship of each capacitor unit can be adjusted according to different design requirements, improving the space utilization rate of the memory array. Exemplarily, at least some capacitor units can be arranged in a staggered manner, or multiple ferroelectric capacitors can be arranged in an array along a first direction and a second direction.

[0013] In some embodiments, in the same capacitor unit, the directions in which the first partial sidewalls of the ferroelectric capacitors point to the second partial sidewalls are the same, that is, each ferroelectric capacitor has the same structure.

[0014] In some embodiments, in each capacitor unit, the directions in which the first partial sidewalls of the ferroelectric capacitors point to the second partial sidewalls are the same, and the multiple ferroelectric capacitors in the memory array are arranged orthogonally, having a relatively high density.

[0015] In some embodiments, the multiple capacitor units include at least one first capacitor unit and at least one second capacitor unit. Among them, the direction in which the first partial sidewall of the ferroelectric capacitor in the first capacitor unit points to the second partial sidewall is a first orientation, and the direction in which the first partial sidewall of the ferroelectric capacitor in the second capacitor unit points to the second partial sidewall is a second orientation, and the first orientation and the second orientation are opposite. At least some capacitor units are arranged in a staggered manner, which can further improve the density of their arrangement. Exemplarily, one first capacitor unit and one second capacitor unit can be arranged alternately, or two first capacitor units and two second capacitor units can also be arranged alternately.

[0016] In some embodiments, the first capacitor unit and the second capacitor unit are arranged alternately along a first direction, and the multiple ferroelectric capacitors in the memory array are arranged in a honeycomb pattern, which can improve the density of their arrangement to a greater extent.

[0017] Second aspect, an embodiment of the present application further provides a method for manufacturing a storage array, the manufacturing method including: forming a ferroelectric capacitor array; forming trenches in a dielectric layer; filling connection electrodes in the trenches. Wherein, the ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors, the ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer and a second electrode, the ferroelectric dielectric layer covers the bottom of the second electrode and extends along a part of the side wall of the second electrode to the top of the second electrode, and the first electrode covers the ferroelectric dielectric layer. The trenches are located between two adjacent ferroelectric capacitors, the two adjacent ferroelectric capacitors include a first ferroelectric capacitor and a second ferroelectric capacitor, a first end of the trench is used to expose a partial area of the first electrode of the first ferroelectric capacitor, and a second end of the trench is used to expose a partial area of the second electrode of the second ferroelectric capacitor. The connection electrode can be embedded in the dielectric layer, a first end of the connection electrode is connected to the first electrode of the first ferroelectric capacitor, and a second end of the connection electrode is connected to the second electrode of the second ferroelectric capacitor. In this way, the plurality of ferroelectric capacitors in the storage array can be arranged compactly, and no other connection components need to be provided in the dielectric layer, and more ferroelectric capacitors can be arranged in a storage array of the same size, which is beneficial to improving the storage density of the storage array.

[0018] In some embodiments, forming the ferroelectric capacitor array may include but is not limited to the following process: forming a dielectric layer and initial ferroelectric capacitors; etching the first electrode material layer and the ferroelectric dielectric material layer to form a plurality of ferroelectric capacitors, or etching the first electrode material layer, the ferroelectric dielectric material layer and the second electrode material layer to form a plurality of ferroelectric capacitors.

[0019] Wherein, the initial ferroelectric capacitor includes a first electrode material layer, a ferroelectric dielectric material layer and a second electrode material layer, the ferroelectric dielectric material layer wraps the second electrode material layer, and the first electrode material layer wraps the ferroelectric dielectric material layer. Exemplarily, both the first electrode material layer and the second electrode material layer can adopt metal materials, such as TiN, W, TaN, etc., the ferroelectric dielectric material layer can adopt ferroelectric dielectric materials, such as HfZrO2, HfSiO, etc., and the ferroelectric dielectric material can also contain different doping elements, such as one or more of Ti, Y, Nb, La, etc.

[0020] When it is necessary to etch the first electrode material layer and the ferroelectric dielectric material layer, the first electrode material layer and the ferroelectric dielectric material layer can be etched respectively by a wet etching process. In each ferroelectric capacitor formed after completing this step, in the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the second electrode is the same.

[0021] When etching the first electrode material layer, ferroelectric dielectric material layer, and second electrode material layer is required, a dry etching process can be used to etch the first electrode material layer, ferroelectric dielectric material layer, and second electrode material layer synchronously. Among the ferroelectric capacitors formed by completing this step, the second electrode includes a first electrode portion and a second electrode portion. The first electrode portion and the second electrode portion are arranged in sequence along the direction from the top to the bottom of the second electrode. In the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the first electrode portion is smaller than the cross-sectional area of the second electrode portion.

[0022] In a third aspect, an embodiment of the present application further provides a memory array, which includes: a ferroelectric capacitor array and a plurality of contact posts. The ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along the sidewall of the second electrode to the top of the second electrode, and the first electrode covers the ferroelectric dielectric layer; the second electrodes of the ferroelectric capacitors are wrapped by the ferroelectric dielectric layer and the first electrode, and only the top surface is exposed. Therefore, contact posts are provided to connect the second electrodes of the ferroelectric capacitors to other components in the memory array. The plurality of ferroelectric capacitors include a plurality of capacitor units, and each capacitor unit includes two ferroelectric capacitors arranged along the second direction. The plurality of contact posts are disposed in the dielectric layer and correspond to the plurality of capacitor units one by one. The contact posts are connected to the second electrodes of the corresponding two ferroelectric capacitors; any two capacitor units arranged along the first direction form a capacitor group, and the contact posts connected to one capacitor unit in the capacitor group are disposed in the gap between the four ferroelectric capacitors of the capacitor group. In this way, contact posts can be provided without expanding the spacing between adjacent ferroelectric capacitors, and there is no need to set aside a separate space for the contact posts, so that more ferroelectric capacitors can be arranged in a memory array of the same size, which is beneficial to improving the storage density of the memory array.

[0023] In some embodiments, in the direction from the top of the contact post to the bottom of the contact post, the cross-sectional shape of the contact post is a quadrilateral, and the apex angles of the quadrilateral extend into the gaps between the ferroelectric capacitors adjacent to the contact post, so that the space between every two adjacent ferroelectric capacitors can be fully utilized, the size of the contact post can meet the design requirements and it is convenient to connect with the corresponding capacitor unit. At the same time, the spacing between the four ferroelectric capacitors in the capacitor group can be designed to be small enough, which is beneficial to improving the arrangement density of the ferroelectric capacitors in the memory array.

[0024] In some embodiments, for a contact post with a quadrilateral cross-section, the shape of each side of the quadrilateral can be arc-shaped, bending towards the center of the quadrilateral. Correspondingly, the cross-section of the ferroelectric capacitor can be circular, and the ferroelectric capacitor is cylindrical, which can minimize the distance between the ferroelectric capacitor and the contact post, so that the ferroelectric capacitor and the contact post are compactly arranged in the dielectric layer. Or, the minimum distance between each side of the quadrilateral and the adjacent ferroelectric capacitor is the same, which is convenient for fabrication while achieving compact arrangement.

[0025] In some embodiments, the memory array further includes a plurality of connection electrodes. The plurality of connection electrodes correspond to the capacitor units one by one. Two ends of the connection electrode are respectively connected to the tops of the second electrodes of the corresponding two ferroelectric capacitors. The top of the contact post corresponding to the capacitor unit is connected to the connection electrode. The connection electrode is disposed outside the dielectric layer, and there is no need to reserve space for the connection electrode in the dielectric layer, so as not to affect the arrangement density of the ferroelectric capacitor and the contact post.

[0026] In some embodiments, the contact area between the connection electrode and the second electrode is a first area, the area of the top surface of the second electrode is a second area, and the first area is less than or equal to half of the second area, which can ensure that the connection electrode can connect the corresponding second electrode and the contact post while not contacting other contact posts. If the first area is made equal to the second area, that is, the line width of the connection electrode is made as large as possible, it can have better electrical properties.

[0027] In some embodiments, the contact area between the connection electrode and the contact post is a third area, the area of the top surface of the contact post is a fourth area, and the third area is less than or equal to half of the fourth area, so that the connection electrode can avoid contacting other contact posts and causing abnormal circuit connection while connecting to the corresponding contact post.

[0028] In some embodiments, the plurality of capacitor units include a first capacitor unit and a second capacitor unit adjacent in a second direction. The first capacitor unit includes a first ferroelectric capacitor, and the second capacitor unit includes a second ferroelectric capacitor. The first ferroelectric capacitor and the second ferroelectric capacitor are adjacent. The first electrode of the first ferroelectric capacitor and the first electrode of the second ferroelectric capacitor are connected through a connection line, and the connection line is then connected to the corresponding transistor, which can form a chain structure. At this time, the contact post also needs to be connected to the transistor, and the components to which it is connected and the connection line can usually be disposed on the same layer and aligned. The contact area between the connection line and the bottom surface of the first electrode is a fifth area, the area of the bottom surface of the first electrode is a sixth area, and the fifth area is less than or equal to half of the sixth area, which can avoid abnormal circuit connection caused by the components connected to the contact post contacting other contact posts.

[0029] Fourthly, an embodiment of the present application further provides a method for manufacturing a storage array, including: forming a ferroelectric capacitor array and forming a plurality of contact posts. The ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along the sidewall of the second electrode to the top of the second electrode. The first electrode covers the ferroelectric dielectric layer. The plurality of ferroelectric capacitors include a plurality of capacitor units, and each capacitor unit includes two ferroelectric capacitors arranged along the second direction. Any two capacitor units arranged along the first direction form a capacitor group. The plurality of contact posts are disposed in the dielectric layer, and the plurality of contact posts correspond to the plurality of capacitor units one by one. The contact posts are connected to the second electrodes of the corresponding two ferroelectric capacitors. Among them, the contact posts connected to one capacitor unit in the capacitor group are disposed in the gap between the four ferroelectric capacitors of the capacitor group. In the embodiment of the present application, the space for accommodating the contact posts can be formed by a self-alignment technique, and the process difficulty is relatively low. The storage units in the storage array manufactured by this method have a relatively high density.

[0030] Fifthly, an embodiment of the present application further provides a memory, which includes a controller and a storage array. The number of storage arrays can be one or more, and the controller is used to access the storage array. Among them, the storage array is the storage array described in the first aspect or any possible implementation manner of the first aspect. Or, the storage array is the storage array described in the third aspect or any possible implementation manner of the third aspect.

[0031] Sixthly, the present application further provides an electronic device, which includes a circuit board and a memory, and the memory is disposed on the surface of the circuit board. Among them, the memory is the memory described in the fifth aspect or any possible implementation manner of the fifth aspect.

[0032] In addition, the technical effects of the corresponding solutions in the fifth aspect and the sixth aspect can be referred to the technical effects obtained from the corresponding solutions in the first aspect or the third aspect, and the repeated parts will not be described in detail. Description of the Drawings

[0033] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0034] Figure 2 It is an equivalent circuit diagram of a storage array provided by an embodiment of the present application;

[0035] Figure 3 It is a schematic three-dimensional structure diagram of a storage array provided by an embodiment of the present application;

[0036] Figure 4 is Figure 3 a cross-sectional view along the AA' direction;

[0037] Figure 5 A top view of the transistor array provided by the embodiment of the present application;

[0038] Figure 6 A top view of the storage array provided by the embodiment of the present application;

[0039] Figure 7 Another top view of the storage array provided by the embodiment of the present application;

[0040] Figure 8 Another top view of the storage array provided by the embodiment of the present application;

[0041] Figure 9 Another top view of the storage array provided by the embodiment of the present application;

[0042] Figure 10 A schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0043] Figure 11 Another schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0044] Figure 12 Another schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0045] Figure 13 Another schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0046] Figure 14 Another three-dimensional structural diagram of the storage array provided by the embodiment of the present application;

[0047] Figure 15 is Figure 14 A sectional view taken along the BB' direction in

[0048] Figure 16 Another schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0049] Figure 17 Another schematic structural diagram of the storage array provided by the embodiment of the present application during the preparation process;

[0050] Figure 18 Another three-dimensional structural diagram of the storage array provided by the embodiment of the present application;

[0051] Figure 19 Another sectional view of the storage array provided by the embodiment of the present application;

[0052] Figure 20 Another top view of the storage array provided by the embodiment of the present application;

[0053] Figure 21 Another schematic structural view of the storage array provided by the embodiment of the present application during the manufacturing process;

[0054] Figure 22 Another schematic structural view of the storage array provided by the embodiment of the present application during the manufacturing process;

[0055] Figure 23 Another schematic structural view of the storage array provided by the embodiment of the present application during the manufacturing process;

[0056] Figure 24 Another schematic structural view of the storage array provided by the embodiment of the present application during the manufacturing process.

[0057] Reference numerals:

[0058] Electronic device 1, memory 2, circuit board 3, storage array 4, controller 5, storage unit 6, first transistor T1, second transistor T2, capacitor C, transistor row H1, first transistor column H2, second transistor column H3, ferroelectric capacitor array 10, connection electrode 20, first surface 21, ferroelectric capacitor 11, dielectric layer 12, first electrode 111, ferroelectric dielectric layer 112, second electrode 113, first electrode portion 1131, second electrode portion 1132, first partial sidewall B1, second partial sidewall B2, first top region D1, second top region D2, capacitor unit Q, first direction Y, second direction X, third direction Z, transistor array 30, substrate 40, gate region G, source-drain region SD, conductive column 33, accommodating groove K, initial ferroelectric capacitor 100, first electrode material layer 101, ferroelectric dielectric material layer 102, second electrode material layer 103, protective layer P, trench 50, contact column 60, capacitor group L, first conductive column 331, second conductive column 332, connection line 70, first conductive layer E1, second conductive layer E2, first accommodating groove K1, second accommodating groove K2. Detailed implementation manners

[0059] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "a plurality of" can be understood as "at least two". In addition, it should be understood that in the description of the present application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0060] It should be noted that the same reference numerals in the accompanying drawings of the present application denote the same or similar structures, and thus repeated descriptions thereof will be omitted. The words expressing positions and directions described in the present application are all illustrated by taking the accompanying drawings as examples, but can also be changed as needed, and all the changes made are included in the protection scope of the present application. The accompanying drawings of the present application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0061] The storage array disclosed in the present application can be applicable to devices with storage capabilities. For example, it can be applicable to storage devices with only storage capabilities, such as memories, or to electronic devices with storage capabilities and other capabilities (such as read-write functions). The electronic device can be a portable electronic device, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), or a non-portable electronic device such as a vehicle-mounted device or a desktop computer. It can be understood that the specific implementation manners of the electronic device can be determined according to the actual application scenarios and are not limited herein.

[0062] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As Figure 1 shown, the electronic device 1 includes a memory 2 and a circuit board 3. The memory 2 is disposed on the circuit board 3. The circuit board 3 can be a printed circuit board (Printed Circuit Board, abbreviated as PCB) or a flexible printed circuit (Flexible Printed Circuit, abbreviated as FPC), etc. Other chips or independent devices can also be disposed on the circuit board 3, which are not limited herein.

[0063] The memory 2 includes a storage array 4 and a controller 5. Among them, the storage array 4 includes a plurality of storage units 6 arranged in a set manner. Each storage unit 6 can be used to store 1 bit (bit) or multiple bits of data. The controller 5 is used to access the storage array 4 to perform read and write operations on the data in the storage array 4. The memory 2 can also include one or more circuit structures such as a decoder, a driver, a buffer, or an input / output driver. The number of storage arrays 4 in the memory 2 can be one or more, which are not limited herein.

[0064] Figure 2 It is an equivalent circuit diagram of a storage array provided by an embodiment of the present application. As Figure 2 shown, the storage array includes a plurality of storage units 6. Each storage unit 6 is formed by connecting a first transistor T1 and a capacitor C in parallel, and also includes a plurality of second transistors T2, a plurality of word lines (word line, WL) WL0 to WL n and a plurality of bit lines (bit line, BL) BL0 to BL n, multiple plate lines (PL) PL0 to PL n and one block selector line (BS) BS0. Exemplarily, the capacitor C can be a ferroelectric capacitor.

[0065] Among them, a plurality of first transistors T1 arranged along the second direction X and one second transistor T2 form a transistor row H1. A plurality of transistor rows H1 are arranged along the first direction Y, and the plurality of transistor rows H1 correspond to multiple bit lines BL0 to BL n one-to-one, and the plurality of transistor rows H1 correspond to multiple plate lines PL0 to PL n one-to-one. In each transistor row H1, the first poles and second poles of the plurality of first transistors T1 and one second transistor T2 are connected in sequence. The first pole of the first transistor T1 at one end is connected to the corresponding plate line, and the second pole of the second transistor T2 at the other end is connected to the corresponding bit line. In the embodiments of the present application, the first pole of the transistor can be set as the source electrode, and the second pole can be set as the drain electrode. Alternatively, the first pole of the transistor can also be set as the drain electrode, and the second pole can be set as the source electrode, which is not limited herein.

[0066] A plurality of first transistors T1 arranged along the first direction Y form a first transistor column H2, and a plurality of second transistors T2 arranged along the first direction Y form a second transistor column H3. The plurality of first transistor columns H2 and one second transistor column H3 are arranged along the second direction X, and the plurality of first transistor columns H2 correspond to multiple word lines WL0 to WL n one-to-one. In the first transistor column H2, the gates of the plurality of first transistors T1 are connected through the corresponding word lines, so the word lines WL0 to WL n can be used to control the on and off of the first transistors T1 connected thereto; in the second transistor column H3, the gates of the plurality of second transistors T2 are connected to the block selector line BS0, so the block selector line BS0 can be used to select the bit lines BL0 to BL n , WL0 to WL n and BS0 can select the storage unit 6 to be read and written in the storage array by receiving the control level output by the controller. The first transistor T1 in the selected storage unit 6 is turned off, so that the corresponding plate line and bit line in the storage unit 6 can apply a voltage to the capacitor C in the storage unit 6, changing the polarization direction of the ferroelectric material to realize the read and write operations of data. The storage array provided by the embodiments of the present application adopts a chain structure and has the advantages of high speed, high density, and anti-crosstalk.

[0067] Figure 3 is a schematic three-dimensional structure diagram of a storage array provided by an embodiment of the present application; Figure 4 is Figure 3 a cross-sectional view along the AA' direction. As Figure 3As shown, the storage array includes a ferroelectric capacitor array 10 and a connection electrode 20. The ferroelectric capacitor array 10 includes a plurality of ferroelectric capacitors 11 and a dielectric layer 12 disposed between the plurality of ferroelectric capacitors 11. Among them, the plurality of ferroelectric capacitors 11 includes a plurality of capacitor units Q arranged along the first direction Y, and each capacitor unit Q includes a plurality of ferroelectric capacitors 11 arranged along the second direction X.

[0068] Specifically, referring to Figure 4 , the ferroelectric capacitor 11 includes a first electrode 111, a ferroelectric dielectric layer 112, and a second electrode 113. Among them, the ferroelectric dielectric layer 112 covers the bottom of the second electrode 113 and extends along a part of the side wall of the second electrode 113 to the top of the second electrode 113. The first electrode 111 covers the ferroelectric dielectric layer 112. In this way, the side wall of a part of the second electrode 113 of the ferroelectric capacitor 11 can be exposed, that is, the side wall of the second electrode 113 is not completely wrapped by the ferroelectric dielectric layer 112 and the first electrode 111. The plurality of ferroelectric capacitors 11 includes a first ferroelectric capacitor and a second ferroelectric capacitor. The first end of the connection electrode 20 is connected to the first electrode 111 of the first ferroelectric capacitor, and the second end of the connection electrode is connected to the second electrode 113 of the second ferroelectric capacitor.

[0069] Figure 4 The cross-sectional view of three ferroelectric capacitors among the plurality of ferroelectric capacitors arranged along the second direction X in the storage array and their corresponding connected transistors is shown. As Figure 4 shown, there is a connection electrode 20a between the ferroelectric capacitor C11 and the ferroelectric capacitor C12, and the first end of the connection electrode 20a is connected to the first electrode 111 of the ferroelectric capacitor C12, and the second end is connected to the second electrode 113 of the ferroelectric capacitor C11. At this time, the ferroelectric capacitor C12 serves as the first ferroelectric capacitor, and the ferroelectric capacitor C11 serves as the second ferroelectric capacitor. There is a connection electrode 20b between the ferroelectric capacitor C12 and the ferroelectric capacitor C13, and the first end of the connection electrode 20b is connected to the first electrode 111 of the ferroelectric capacitor C13, and the second end is connected to the second electrode 113 of the ferroelectric capacitor C12. At this time, the ferroelectric capacitor C13 serves as the first ferroelectric capacitor, and the ferroelectric capacitor C12 serves as the second ferroelectric capacitor, and so on.

[0070] In the embodiment of the present application, the storage array further includes a transistor array. Exemplarily, Figure 5 is a top view of the transistor array provided by the embodiment of the present application. Referring to Figure 4 And Figure 5, the transistor array 30 can be located between the ferroelectric capacitor array 10 and the substrate 40. The transistor array 30 includes a plurality of transistors, which can be arranged in an array along a first direction Y and a second direction X respectively. The plurality of transistors include a plurality of first transistors and a plurality of second transistors. Moreover, the circuit connection relationship between the plurality of first transistors and the plurality of second transistors, and the circuit connection relationship between the first transistor and the ferroelectric capacitor, can be referred to Figure 2 as shown in the equivalent circuit diagram. Exemplarily, the transistor array includes a plurality of word lines WL and a plurality of source / drain regions SD. Among them, each word line WL extends along the first direction Y, and the region where the word line WL is connected to the gate of the first transistor is used as the gate region G. Then, each gate region G extends along the first direction Y and is arranged along the second direction X. The position of the source / drain region SD is defined by the gate region G. The source / drain regions SD located on both sides of the gate region G can be used as the first pole and the second pole of the transistor.

[0071] Exemplarily, referring to Figure 2 、 Figure 3 and Figure 4 , a capacitor unit Q corresponds to a transistor row H1, and the plurality of ferroelectric capacitors in the capacitor unit Q correspond to the plurality of first transistors in the corresponding transistor row H1 one by one. For example, the second transistor T211 includes: a gate region G11, a source / drain region SD11, and a source / drain region SD12. Among them, the source / drain region SD11 is the first pole of the second transistor T211, and the source / drain region SD12 is the second pole of the second transistor T211. The first transistor T111 includes: a gate region G12, a source / drain region SD12, and a source / drain region SD13. Among them, the source / drain region SD12 is the first pole of the first transistor T111, and the source / drain region SD13 is the second pole of the first transistor T111. And the source / drain region SD12 is connected to the first electrode 111 of the ferroelectric capacitor C11 through a conductive pillar 33. Then, the first transistor T111 and the ferroelectric capacitor C11 form a storage unit. Moreover, the first transistor T112 includes: a gate region G13, a source / drain region SD13, and a source / drain region SD14. Among them, the source / drain region SD13 serves as the first pole of the first transistor T112, and the source / drain region SD14 serves as the second pole of the first transistor T112. And the source / drain region SD13 is connected to the first electrode 111 of the ferroelectric capacitor C12 through a conductive pillar 33. Then, the first transistor T112 and the ferroelectric capacitor C12 form a storage unit. The remaining structures are set in the same way and will not be elaborated here.

[0072] It can be seen that the second transistor T211 shares the source-drain region SD12 with the first transistor T111, and the first transistor T111 shares the source-drain region SD13 with the first transistor T112. By analogy, it can be known that in two adjacent ferroelectric capacitors 11, the second pole of the first transistor corresponding to the first ferroelectric capacitor and the first pole of the first transistor corresponding to the second ferroelectric capacitor share the same source-drain region. The first electrode 111 of the first ferroelectric capacitor is connected to the shared source-drain region through the conductive column 33. The second electrode 113 of the second ferroelectric capacitor is connected to the first electrode 111 of the first ferroelectric capacitor through the connection electrode. Thus, the second electrode 113 of the second ferroelectric capacitor can be electrically connected to the shared source-drain region. There is no need to additionally provide connection components between two adjacent ferroelectric capacitors to connect to the transistors, thereby saving space. More ferroelectric capacitors can be arranged in the memory array of the same size, which is beneficial to improving the arrangement density of the memory cells and further improving the storage density of the memory array.

[0073] Referring to Figure 3 and Figure 4 , a plurality of ferroelectric capacitors 11 arranged along the second direction X can be sequentially connected through the connection electrodes 20, and a chain structure as shown in Figure 2 can be realized. In some embodiments, the connection electrode 20 is embedded in the dielectric layer 12, and the dielectric layer 12 exposes the first surface 21 of the connection electrode 20. Among them, the first surface 21 of the connection electrode 20 is flush with the top of the central electrode 113. The connection electrode 20 is disposed inside the dielectric layer 12, which can further save the longitudinal space of the memory array.

[0074] Referring to Figure 4 , the second electrode 113 of the ferroelectric capacitor 11 includes a first electrode portion 1131 and a second electrode portion 1132. The first electrode portion 1131 and the second electrode portion 1132 are sequentially arranged along the direction from the top to the bottom of the second electrode 113. The direction from the top to the bottom of the second electrode 113 is the direction pointed by the arrow in the third direction Z shown in the figure. And, the ferroelectric dielectric layer 112 wraps the side wall of the second electrode portion 1132 and extends along the first part of the side wall B1 of the first electrode portion 1131 to the top of the second electrode 113. That is, both the ferroelectric dielectric layer 112 and the first electrode 111 have two parts with different heights, and the ferroelectric dielectric layer 112 can expose the second part of the side wall B2 of the first electrode portion 1131. The first end of the connection electrode 20 is connected to at least a part of the side wall of the first electrode 111 at the first electrode portion 1131, and the second end of the connection electrode 20 is connected to at least a part of the second part of the side wall B2, thereby connecting the side wall of the first electrode 111 of the first ferroelectric capacitor and the side wall of the second electrode 113 of the second ferroelectric capacitor. Exemplarily, the height of the first electrode portion 1131 and the height of the second electrode portion 1132 are the same or different.

[0075] Reference Figure 4 , in some embodiments, in the third direction Z pointing from the top to the bottom of the second electrode 113, the cross-sectional area of the second electrode 113 is the same, that is, the second electrode 113 is a columnar structure. Moreover, the second end of the connection electrode 20 is connected to a partial area of the second partial sidewall B2, and the remaining area of the second partial sidewall B2 is covered by the dielectric layer 12, so as to separate the connection electrode 20 and the first electrode 111 corresponding to the position of the second electrode portion 1132 by using the dielectric layer 12, so that the two are insulated from each other.

[0076] In specific implementation, the transistor in the embodiment of the present application can be a top-gate transistor, a bottom-gate transistor, or a buried transistor. Moreover, in some other embodiments, the transistor array 30 can also be disposed on the side of the ferroelectric capacitor array 10 away from the substrate 40. Therefore, the implementation manners of the transistor array and the ferroelectric capacitor array can be designed according to requirements, and the positions of other signal lines such as word lines, bit lines, and plate lines in the memory array can be set according to actual situations. The present application does not limit the specific structure and setting manner of the transistor and the setting manner of the signal lines. In the following embodiments, the transistor array 30 as shown in Figure 5 is taken as an example for illustration.

[0077] In the embodiment of the present application, when the multiple source-drain regions SD in the transistor array 30 are fabricated, they are usually arranged in an array and equidistantly arranged, so the corresponding conductive pillars 33 connected thereto are also arranged in an array and equidistantly arranged. The position of the ferroelectric capacitor 11 needs to be set according to the position of the conductive pillar 33. For example, the orthographic projection of the ferroelectric capacitor 11 on the substrate 40 can cover the orthographic projection of the corresponding conductive pillar 33 on the substrate 40. At this time, the relative position between the ferroelectric capacitor 11 and the corresponding conductive pillar 33 can be referred to Figure 4 , or the orthographic projection of the ferroelectric capacitor 11 on the substrate 40 can partially overlap the orthographic projection of the corresponding conductive pillar 33 on the substrate. The sizes of the conductive pillar 33 and the ferroelectric capacitor 11 can also be set according to requirements. For example, the area of the orthographic projection of the conductive pillar 33 on the substrate 40 can be smaller than the area of the orthographic projection of the ferroelectric capacitor 11 on the substrate 40.

[0078] Figure 6 is a top view of a memory array provided by the present application, Figure 7 is another top view of a memory array provided by the present application. As shown in Figure 6 and Figure 7As shown, a plurality of ferroelectric capacitors 11 can be arranged in an array along a first direction Y and a second direction X, and constitute a plurality of capacitor units arranged along the first direction Y. The orthographic projection of each ferroelectric capacitor 11 on the substrate 40 can cover the orthographic projection of the corresponding conductive column 33 on the substrate 40, that is, the ferroelectric capacitor 11 and the conductive column 33 are aligned. At this time, the plurality of ferroelectric capacitors 11 in the memory array have a high arrangement density, low process design difficulty and are easy to manufacture.

[0079] Figure 8 Another top view of the memory array provided by the present application; Figure 9 Another top view of the memory array provided by the present application. Refer to Figure 8 and Figure 9 , at least some of the capacitor units can be arranged in a staggered manner. The plurality of capacitor units can include a third capacitor unit and a fourth capacitor unit. In the third capacitor unit, the orthographic projection of each ferroelectric capacitor 11 on the substrate 40 covers the orthographic projection of the corresponding conductive column 33 on the substrate 40. In the fourth capacitor unit, the orthographic projection of the ferroelectric capacitor 11 on the substrate 40 and the orthographic projection of the conductive column 33 on the substrate 40 partially overlap. That is to say,

[0080] Figure 8 , the capacitor unit Q1 and the capacitor unit Q3 are used as the third capacitor unit, and the capacitor unit Q2 and the capacitor unit Q4 are used as the fourth capacitor unit;

[0081] Figure 9 , the capacitor unit Q1, the capacitor unit Q2, the capacitor unit Q3 and the capacitor unit Q4 are all used as the fourth capacitor unit.

[0082] In some of the capacitor units, each ferroelectric capacitor 11 is arranged in a staggered manner with the conductive column 33, so that some of the capacitor units can be arranged in a staggered manner with other capacitor units. In this way, the wider parts of the adjacent ferroelectric capacitors 11 in the second direction Y can be staggered, making more full use of the space in the first direction Y, reducing the distance between adjacent capacitor units, and more capacitor units can be arranged in the memory array of the same size, which is beneficial to improving the storage density of the memory array.

[0083] In a specific implementation, the number of the third capacitor units and the fourth capacitor units in the ferroelectric capacitor array can be the same or different. The third capacitor units and the fourth capacitor units can be arranged alternately, or, a plurality of third capacitor units can be arranged adjacent to each other, and a plurality of fourth capacitor units can be arranged adjacent to each other, which is not limited herein.

[0084] In the embodiments of the present application, in at least some of the ferroelectric capacitors, the direction of the first sidewall B1 pointing to the second sidewall B2 can be the same. For example, in the same capacitor unit, the direction of the first sidewall B1 pointing to the second sidewall B2 can be the same.

[0085] For example, with reference to Figure 6 and Figure 8 , the directions in which the first partial sidewalls B1 of each ferroelectric capacitor 11 in the ferroelectric capacitor array point to the second partial sidewalls B2 can all be the same. Or, with reference to Figure 7 and Figure 9 , a plurality of capacitor units can include a first capacitor unit and a second capacitor unit. Among them, the directions in which the first partial sidewalls B1 of the ferroelectric capacitors 11 in the first capacitor unit point to the second partial sidewalls B2 are the same, and the direction in which the first partial sidewall B1 of the ferroelectric capacitor 11 in the first capacitor unit points to the second partial sidewall B2 is a first orientation. The directions in which the first partial sidewalls B1 of the ferroelectric capacitors in the second capacitor unit point to the second partial sidewalls B2 are the same, and the direction in which the first partial sidewall B1 of the ferroelectric capacitor in the second capacitor unit points to the second partial sidewall B2 is a second orientation. The first orientation and the second orientation are opposite. For example, the first orientation can be to the left, and the second orientation can be to the right. Figure 7 In Figure 8 , the capacitor units Q1 and Q3 are used as the first capacitor unit, and the capacitor units Q2 and Q4 are used as the second capacitor unit; Figure 9 In

[0086] When specifically implemented, the numbers of the first capacitor unit and the second capacitor unit in the ferroelectric capacitor array can be the same or different. The first capacitor unit and the second capacitor unit can be arranged alternately, or a plurality of first capacitor units can be arranged adjacent to each other, and a plurality of second capacitor units can be arranged adjacent to each other, which is not limited herein.

[0087] Based on the same concept, the embodiments of the present application further provide a method for manufacturing a storage array. By using this manufacturing method, a storage array as shown in Figure 3 and Figure 4 can be manufactured. The structure of the storage array can refer to the above description and will not be elaborated herein. The following combines Figures 10 to 13 to specifically illustrate the preparation method of the storage array in the embodiments of the present application.

[0088] The method for manufacturing the storage array in the embodiments of the present application can include the following steps:

[0089] Step 1.1: Form a transistor array and conductive pillars on a substrate. Exemplarily, with reference to Figure 10 (a) and Figure 10 (a’), Figure 10(a) is a top - view structural schematic diagram of the storage array in the preparation process of an embodiment of the present application. Figure 10 (a’) is Figure 10 (a) is a cross - sectional view along the AA’ direction. First, the gate regions G of each transistor can be formed on the substrate 40, and then the source - drain regions SD can be formed by doping in the substrate 40 according to the positions of the gate regions G. After that, the conductive pillars 33 are formed on the source - drain regions SD through an etching - filling - planarization or damascene process.

[0090] Step 1.2: Form a dielectric layer. Exemplarily, referring to Figure 10 (b) and Figure 10 (b’), Figure 10 (b) is another top - view structural schematic diagram of the storage array in the preparation process of an embodiment of the present application. Figure 10 (b’) is Figure 10 (b) is a cross - sectional view along the AA’ direction. A dielectric material with a certain thickness is deposited on the structure formed in Step 1.1 to form the dielectric layer 12. Exemplarily, the dielectric material includes but is not limited to SiO2, SiN, etc. After that, a plurality of accommodation grooves K are formed in the dielectric layer 12, and the conductive pillars 33 are exposed through the accommodation grooves K.

[0091] Step 1.3: Form initial ferroelectric capacitors. Exemplarily, referring to Figure 11 (c) and Figure 11 (c’), Figure 11 (c) is another top - view structural schematic diagram of the storage array in the preparation process of an embodiment of the present application. Figure 11 (c’) is Figure 11 (c) is a cross - sectional view along the AA’ direction. The atomic layer deposition (ALD) technology, a thin - film deposition technology, can be used to sequentially deposit a first electrode material, a ferroelectric dielectric material, and a second electrode material in the accommodation grooves K to form a plurality of initial ferroelectric capacitors 100. The initial ferroelectric capacitor 100 includes a first electrode material layer 101, a ferroelectric dielectric material layer 102, and a second electrode material layer 103. The ferroelectric dielectric material layer 102 wraps the second electrode material layer 103, the first electrode material layer 101 wraps the ferroelectric dielectric material layer 102, and there is a certain distance between the top surface of the second electrode material layer 103 and the top surface of the dielectric layer 12. Exemplarily, the first electrode material can be a metal material such as TiN, W, TaN, etc., the ferroelectric dielectric material can be HfZrO2, HfSiO, etc., and the ferroelectric dielectric material can also contain different doping elements such as one or more of Ti, Y, Nb, La, etc., and the second electrode material can be a metal material such as TiN, W, TaN, etc.

[0092] Step 1.4: Form a protective layer. Exemplarily, referring toFigure 11 (d) and Figure 11 (d’), Figure 11 (d) is another top - view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 11 (d’) is Figure 11 A cross - sectional view of (d) along the AA’ direction. A dielectric material, such as SiO2 or SiN, can be deposited on the second electrode material layer to form a protective layer P, and then chemical mechanical polishing (CMP) is used for planarization to remove the ferroelectric dielectric material and the first electrode material on the surface of the dielectric layer 12.

[0093] Step 1.5: Etch the initial ferroelectric capacitor 100 to form the ferroelectric capacitor 11. Exemplarily, refer to Figure 12 (e1) and Figure 12 (e1’), Figure 12 (e1) is another top - view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 12 (e1’) is Figure 12 A cross - sectional view of (e1) along the AA’ direction. First, the dielectric material covering the sidewalls of each initial ferroelectric capacitor 100 can be removed by lithography mask and dry etching or dry - plus - wet etching, so as to expose the sidewalls of part of the first electrode material layer 101. Then, refer to Figure 12 (e2) and Figure 12 (e2’), Figure 12 (e2) is another top - view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 12 (e2’) is Figure 12 A cross - sectional view of (e2) along the AA’ direction. The sidewalls of the exposed first electrode material layer can be removed by one - time wet etching, and the sidewalls of part of the ferroelectric dielectric material layer are exposed. The protective layer P can protect the second electrode material layer from being etched during the wet etching of the first electrode material layer; the sidewalls of the exposed ferroelectric dielectric material layer are removed by re - wet etching. After completing Step 1.5, the ferroelectric capacitor 11 can be formed. The ferroelectric capacitor 11 includes a first electrode 111, a ferroelectric dielectric layer 112, and a second electrode 113. In the direction from the top to the bottom of the second electrode 113, the cross - sectional area of the second electrode 113 is the same.

[0094] Step 1.6: Refer to Figure 13 (f) and Figure 13 (f’), Figure 13 (f) is another top - view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 13 (f’) is Figure 13(f) Cross-sectional view along the AA’ direction. Fill the etched area in Step 1.5 with a dielectric material and planarize it by CMP so that the top surface of the dielectric layer 12 is flush with the top surface of the dielectric material deposited in Step 1.4.

[0095] Step 1.7: Form a plurality of trenches in the dielectric layer for accommodating connection electrodes. Exemplarily, referring to Figure 13 (g) and Figure 13 (g’), Figure 13 (g) is another top view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 13 (g’) is Figure 13 (g) Cross-sectional view along the AA’ direction. A plurality of trenches 50 can be formed in the dielectric layer 12 by a lithography process. Each trench 50 is located between two adjacent ferroelectric capacitors 11. The two adjacent ferroelectric capacitors 11 include a first ferroelectric capacitor and a second ferroelectric capacitor. The first end of the trench 50 is used to expose a partial area of the first electrode of the first ferroelectric capacitor, and the second end of the trench 50 is used to expose a partial area of the second electrode of the second ferroelectric capacitor.

[0096] Step 1.8: Form connection electrodes in the accommodation grooves. Exemplarily, referring to Figure 13 (h) and Figure 13 (h’), Figure 13 (h) is another top view structural schematic diagram of the storage array in the preparation process of the embodiment of the present application. Figure 13 (h’) is Figure 13 (h) Cross-sectional view along the AA’ direction. The connection electrodes 20 can be filled in the trenches 50 and planarized by CMP, so that the connection electrodes 20 are embedded in the dielectric layer 12. Its first end is connected to the first electrode 111 of the first ferroelectric capacitor, and its second end is connected to the second electrode 113 of the second ferroelectric capacitor. Exemplarily, the material of the connection electrodes 20 can be TiN, W, TaN, Co, Ni, Cu, etc.

[0097] In the method for manufacturing the storage array provided by the embodiment of the present application, only two steps of lithography are required when manufacturing the ferroelectric capacitor array 10, the lithography cost is low, and etching at the bottom of the accommodation groove is not required, so the process difficulty is small. Moreover, by first forming a plurality of trenches 50 in the dielectric layer 12 and then filling the connection electrodes 20 in the trenches 50, self-alignment can be achieved, so that the plurality of connection electrodes 20 are formed at one time, and the process is simple. The plurality of ferroelectric capacitors 11 in the storage array formed by the above method can be densely arranged, and no other connection components need to be provided in the dielectric layer 12. More ferroelectric capacitors 11 can be arranged in the storage array of the same size, which is beneficial to improving the storage density of the storage array.

[0098] Figure 14Schematic diagram of the three-dimensional structure of another storage array provided by the embodiment of the present application; Figure 15 is Figure 14 The cross-sectional view in the BB' direction. Refer to Figure 14 and Figure 15 , the difference between the storage array in the embodiment of the present application and the storage arrays shown in Figure 3 and Figure 4 is that: in the third direction Z pointing from the top of the second electrode 113 to the bottom of the second electrode 113, the cross-sectional area of the first electrode portion 1131 of the ferroelectric capacitor 11 is smaller than the cross-sectional area of the second electrode portion 1132. Further, the top of the second electrode portion 1132 has a first top region D1 and a second top region D2, the first top region D1 and the second top region D2 are arranged along the second direction X, and the first electrode portion 1131 covers the first top region D1, that is, the second electrode 113 has two parts with different cross-sectional areas. The connection electrode 20 is connected to a partial region of the side wall B2 of the second part, and the remaining region of the side wall B2 of the second part and the second top region D2 are covered by the dielectric layer 12, so that the dielectric layer 12 can separate the connection electrode 20 and the first electrode 111 corresponding to the second electrode portion 1132 of the ferroelectric capacitor 11, so that the two are insulated from each other. Exemplarily, the height of the first electrode portion 1131 and the height of the second electrode portion 1132 are the same or different.

[0099] Correspondingly, the manufacturing method of the storage array may not only include steps 1.1 to 1.4 in the above embodiment, but also include steps 2.5 to 2.8. The following combines Figure 16 with Figure 17 , and describes steps 2.5 to 2.8 as follows:

[0100] Step 2.5: Refer to Figure 16 (e) and Figure 16 (e’), Figure 16 (e) is another top view structure diagram of the storage array in the embodiment of the present application during the preparation process, Figure 16 (e’) is Figure 16 The cross-sectional view of (e) in the BB' direction. By using a photolithography mask and dry etching to remove part of the first electrode material layer, ferroelectric dielectric material layer and second electrode material layer, the ferroelectric capacitor 11 can be formed. In the direction pointing from the top of the second electrode 113 to the bottom of the second electrode 113, the second electrode 113 has two parts with different cross-sectional areas. When adopting the above method, the protective layer P may not be provided, that is, step 1.4 is omitted.

[0101] Step 2.6: Refer to Figure 16 (f) and Figure 16 (f’), Figure 16(f) is another top - view structural schematic diagram of the storage array in the preparation process of this application example. Figure 16 (f’) is Figure 16 The cross - sectional view of (f) along the BB’ direction. Fill the etched part with a dielectric material in step 2.5 and planarize it by CMP, so that the top surface of the dielectric layer 12 is flush with the top surface of the dielectric material deposited in step 1.4.

[0102] Step 2.7: Refer to Figure 17 (g) and Figure 17 (g’), Figure 17 (g) is another top - view structural schematic diagram of the storage array in the preparation process of this application example. Figure 17 (g’) is Figure 17 (g) The cross - sectional view along the BB’ direction. A plurality of trenches 50 can be formed in the dielectric layer 12 by a photolithography process.

[0103] Step 2.8: Refer to Figure 17 (h) and Figure 17 (h’), Figure 17 (h) is another top - view structural schematic diagram of the storage array in the preparation process of this application example. Figure 17 (h’) is Figure 17 (h) The cross - sectional view along the BB’ direction. The connection electrodes 20 can be filled in the trenches 50 and planarized by CMP.

[0104] Figure 18 It is a three - dimensional structural schematic diagram of another storage array provided by this application example; Figure 19 It is a cross - sectional view of another storage array provided by this application example. As Figure 18 and Figure 19 shown, this application also provides another storage array, and this storage array includes: a transistor array and a ferroelectric capacitor array.

[0105] Among them, the transistor array can be located between the ferroelectric capacitor array 10 and the substrate 40. The circuit connection relationship between the transistor array and the ferroelectric capacitor array 10 can refer to the equivalent circuit diagram as Figure 2 shown. The structure of the transistor array is the same as Figure 5The shown transistor array structures are similar. The transistor array includes a plurality of gate regions G and a plurality of source / drain regions SD. Among them, each gate region G extends along the first direction Y, and the plurality of gate regions G are arranged along the second direction X. The positions of the source / drain regions SD are defined by the gate regions G. The source / drain regions SD located on both sides of the gate region G can serve as the first and second poles of the transistor. However, in the embodiment of the present application, corresponding to the same number of ferroelectric capacitors 11, the number of source / drain regions SD in the transistor array is more than that in the transistor array of the previous embodiment.

[0106] The ferroelectric capacitor array includes a plurality of ferroelectric capacitors 11 and a dielectric layer 12 disposed between the plurality of ferroelectric capacitors 11. The ferroelectric capacitor 11 includes a first electrode 111, a ferroelectric dielectric layer 112, and a second electrode 113. The ferroelectric dielectric layer 112 covers the bottom of the second electrode 113 and extends along the side wall of the second electrode 113 to the top of the second electrode 113. The first electrode 111 covers the ferroelectric dielectric layer 112. The second electrode 113 of each ferroelectric capacitor 11 is wrapped by the ferroelectric dielectric layer 112 and the first electrode 111, and only the top surface is exposed. Therefore, contact posts 60 are also provided in the dielectric layer 12 to connect the second electrode 113 of the ferroelectric capacitor 11 to the corresponding transistor.

[0107] Figure 20 This is a top view of another storage array provided by the embodiment of the present application. Referring to Figure 18 and Figure 20 , the plurality of ferroelectric capacitors 11 include a plurality of capacitor units Q, and each capacitor unit Q includes two ferroelectric capacitors 11 arranged along the second direction X. The plurality of contact posts 60 correspond to the plurality of capacitor units Q one by one, and the contact posts 60 are connected to the second electrodes 113 of the corresponding two ferroelectric capacitors 11. Any two capacitor units Q arranged along the first direction Y form a capacitor group L. The contact posts 60 connected to one capacitor unit Q in the capacitor group L are disposed in the gap between the four ferroelectric capacitors 11 of the capacitor group L. In this way, the contact posts 60 can be provided without expanding the spacing between adjacent ferroelectric capacitors 11, and there is no need to reserve a separate space for the contact posts 60. Thus, more ferroelectric capacitors 11 can be arranged in the storage array of the same size, which is beneficial to improving the storage density of the storage array. Exemplarily, the size of the ferroelectric capacitor 11 can be 4F 2 .

[0108] Referring to Figure 19 and Figure 20, in the direction from the top of the contact post 60 to the bottom of the contact post 60, the cross-sectional shape of the contact post 60 can be quadrilateral, and the top angles of the quadrilateral extend into the gaps between the ferroelectric capacitors 11 adjacent to the contact post 60, so that the space between every two adjacent ferroelectric capacitors 11 can be fully utilized, the size of the contact post 60 can meet the design requirements and it is convenient to connect with the corresponding capacitor unit Q. At the same time, the spacing between the four ferroelectric capacitors 11 in the capacitor group L can be designed to be small enough, which is beneficial to improving the arrangement density of the ferroelectric capacitors 11 in the memory array.

[0109] Referring to Figure 18 and Figure 20 , in a possible implementation manner, the cross-section of the ferroelectric capacitor 11 can be circular, and the ferroelectric capacitor 11 is cylindrical. In this way, the gaps between the four ferroelectric capacitors 11 in the capacitor group L are large, while the gaps between every two adjacent ferroelectric capacitors 11 are small. Correspondingly, for the above-mentioned contact post 60 with a quadrilateral cross-section, the shape of each side of the quadrilateral can be arc-shaped, and the arc bends towards the center of the quadrilateral, so as to minimize the spacing between the ferroelectric capacitor 11 and the adjacent contact post 60 as much as possible, so that the ferroelectric capacitor 11 and the contact post 60 are closely arranged in the dielectric layer 12. The minimum distance between each side of the quadrilateral and the adjacent ferroelectric capacitor 11 can be the same, which is convenient for manufacturing while achieving close arrangement.

[0110] Figure 19 Exemplarily shows three capacitor units Q arranged along the second direction X and their connection relationship with the corresponding transistors. Referring to Figure 18 , Figure 19 and Figure 20 , the second transistor T221 includes: a gate region G21, a source-drain region SD21 and a source-drain region SD22, where the source-drain region SD21 is the first pole of the second transistor T221, and the source-drain region SD22 is the second pole of the second transistor T221.

[0111] The first transistor T121 includes: a gate region G22, a source-drain region SD22 and a source-drain region SD23, where the source-drain region SD22 is the first pole of the first transistor T121, the source-drain region SD23 is the second pole of the first transistor T121, and the source-drain region SD22 is connected to the first electrode 111 of the ferroelectric capacitor C21. The source-drain region SD23 can be connected to the contact post 60 through the first conductive post 331. The first transistor T121 and the ferroelectric capacitor C21 form a memory cell.

[0112] The first transistor T122 includes: a gate region G23, a source / drain region SD23, and a source / drain region SD24. Among them, the source / drain region SD23 is the first pole of the first transistor T122, the source / drain region SD24 is the second pole of the first transistor T122, and the source / drain region SD24 is connected to the first electrodes 111 of the ferroelectric capacitors C22 and C23 through the second conductive pillar 332 and the connection line 70. The first transistor T122 and the ferroelectric capacitor C22 form a memory cell.

[0113] The first transistor T123 includes: a gate region G24, a source / drain region SD24, and a source / drain region SD25. Among them, the source / drain region SD24 is the first pole of the first transistor T123, the source / drain region SD25 is the second pole of the first transistor T123, and the source / drain region SD25 can be connected to the contact pillar 60 through the first conductive pillar 331. The first transistor T123 and the ferroelectric capacitor C23 form a memory cell.

[0114] The first transistor T124 includes: a gate region G25, a source / drain region SD25, and a source / drain region SD26. Among them, the source / drain region SD25 is the first pole of the first transistor T124, the source / drain region SD26 is the second pole of the first transistor T124, and the source / drain region SD26 is connected to the first electrodes 111 of the ferroelectric capacitors C24 and C25 through the second conductive pillar 332 and the connection line 70. The first transistor T124 and the ferroelectric capacitor C24 form a memory cell.

[0115] The first transistor T125 includes: a gate region G26, a source / drain region SD26, and a source / drain region SD27. Among them, the source / drain region SD26 is the first pole of the first transistor T125, the source / drain region SD27 is the second pole of the first transistor T125, and the source / drain region SD27 can be connected to the conductive pillar 60 through the first conductive pillar 331. The first transistor T125 and the ferroelectric capacitor C25 form a memory cell. The remaining structures are set in the same way and will not be elaborated here.

[0116] It can be seen that the second pole of the second transistor T221 and the first pole of the first transistor T121 share the source-drain region SD22; the second pole of the first transistor T121 and the first pole of the first transistor T122 share the source-drain region SD23; the second pole of the first transistor T122 and the first pole of the first transistor T123 share the same source-drain region S24; the second pole of the first transistor T123 and the first pole of the first transistor T124 share the source-drain region SD25; the second pole of the first transistor T124 and the first pole of the first transistor T125 share the source-drain region SD26, and so on. It can be known that in a row of transistors arranged along the second direction X, every two adjacent transistors can share a source-drain region, which can improve the space utilization rate on the substrate 40 to a certain extent.

[0117] Moreover, in the embodiments of the present application, multiple capacitor units include a first capacitor unit and a second capacitor unit adjacent to each other along the second direction X. The first capacitor unit includes a first ferroelectric capacitor, and the second capacitor unit includes a second ferroelectric capacitor. The first ferroelectric capacitor is adjacent to the second ferroelectric capacitor. Refer to Figure 19 , capacitor unit Q21 and capacitor unit Q23 can be used as the first capacitor unit, and capacitor unit Q22 can be used as the second capacitor unit. At this time, ferroelectric capacitors C22 and C25 are the first ferroelectric capacitors, and ferroelectric capacitors C23 and C24 are the second ferroelectric capacitors. According to the above connection relationship, it can be known that in the embodiments of the present application, the first electrode 111 of the first ferroelectric capacitor is connected to the first electrode 111 of the second ferroelectric capacitor through the connection line 70, and the connection line 70 is then connected to the source-drain region SD of the corresponding first transistor.

[0118] Refer to Figures 18 to 20 , the memory array may further include multiple connection electrodes 20, and the multiple connection electrodes 20 correspond to the capacitor units Q one by one. Both ends of the connection electrode 20 are respectively connected to the tops of the second electrodes 113 of the corresponding two ferroelectric capacitors 11. The top of the contact post 60 corresponding to the capacitor unit Q is connected to the connection electrode 20. Thus, the second electrodes 113 of the two ferroelectric capacitors 11 in the capacitor unit Q can be connected to the corresponding transistor through the contact post 60 and the first conductive post 331. In the embodiments of the present application, the connection electrode 20 is disposed outside the dielectric layer 12, and there is no need to reserve space for disposing the connection electrode 20 in the dielectric layer 12, so as not to affect the arrangement density of the ferroelectric capacitors 11 and the contact posts 60. In specific implementation, the connection electrode 20 can be a strip-shaped electrode as shown in Figures 18 to 20 for easy fabrication, or it can be of other shapes, such as a broken line shape, etc., which is not limited herein.

[0119] In the embodiment of the present application, the contact area between the connecting electrode 20 and the second electrode 113 is the first area, the area of the top surface of the second electrode 113 is the second area, and the first area is less than or equal to half of the second area. It can ensure that the connecting electrode 20 can connect the corresponding second electrode 113 and the contact column 60 to each other without contacting other contact columns 60. If the first area is made equal to the second area, that is, the line width of the connecting electrode 20 is made as large as possible, it can have better electrical properties.

[0120] The contact area between the connecting electrode 20 and the contact column 60 is the third area, the area of the top surface of the contact column 60 is the fourth area, and the third area is less than or equal to half of the fourth area. In this way, when the connecting electrode 20 is connected to the corresponding contact column 60, it can avoid abnormal circuit connection caused by contacting other contact columns 60.

[0121] In the actual manufacturing process, multiple source-drain regions in the transistor array are usually arranged in an array and evenly distributed. Correspondingly, the first conductive column 331 and the connecting wire 70 are also aligned in the second direction X. The contact area between the connecting wire 70 and the bottom surface of the first electrode 111 is the fifth area, the area of the bottom surface of the first electrode 111 is the sixth area, and the fifth area is less than or equal to half of the sixth area. Similarly, it is to avoid abnormal circuit connection caused by the components connected to the contact column 60 contacting other contact columns 60.

[0122] Based on the same concept, the present application also provides another manufacturing method for a memory array. Using this manufacturing method, a memory array as shown in Figures 18 to 20 can be manufactured. The preparation method of the memory array in the embodiment of the present application will be specifically described below with reference to Figures 21 to 24

[0123] Step 3.1: Form a transistor array, a first conductive layer, and a second conductive layer on a substrate. Exemplarily, refer to Figure 21 (a) and Figure 21 (a’). Figure 21 (a) is a three-dimensional structural schematic diagram of the memory array in the embodiment of the present application during the preparation process. Figure 21 (a’) is Figure 21 ​The top view of (a). First, the gate regions G of each transistor can be formed on the substrate 40, and then the source-drain regions SD can be formed by doping semiconductor materials in the substrate 40 according to the positions of the gate regions G. Then, the first conductive layer E1 and the second conductive layer E2 can be formed by an etching-fill-planarization or damascene process. Among them, the first conductive layer E1 and the second conductive layer E2 include a plurality of first conductive posts 331 for connecting contact posts, the second conductive layer E2 includes a plurality of connection lines 70 for connecting the first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor, and the first conductive layer E1 includes a plurality of second conductive posts 332 for connecting the connection lines 70 and the transistors.

[0124] Step 3.2: Form a dielectric layer and a plurality of first accommodation grooves for accommodating ferroelectric capacitors. Exemplarily, referring to Figure 21 (b) and Figure 21 (b’), Figure 21 (b) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 21 (b’) is Figure 21 the top view of (b). On the structure formed in step 3.1, a dielectric material with a certain thickness is grown to form a dielectric layer 12. The dielectric material can be SiO2 or SiN, etc., and a plurality of first accommodation grooves K1 are formed to expose the connection lines 70.

[0125] Step 3.3: Referring to Figure 22 (c) and Figure 22 (c’), Figure 22 (c) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 22 (c’) is Figure 22 the top view of (c). The first electrode material layer 101 can be formed by depositing the first electrode material using a thin film deposition technique such as ALD. Exemplarily, the first electrode material can be a metal material such as TiN, W, TaN, etc., and a little of the top first electrode material is removed by a dry etching process to avoid contact between the two when forming the second electrode in the subsequent process.

[0126] Step 3.4: Form ferroelectric capacitors. Exemplarily, referring to Figure 22 (d) and Figure 22 (d’), Figure 22 (d) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 22 (d’) is Figure 22 (d) the top view of, Figure 22 (d”) is Figure 22(d’) Cross-sectional view along the CC’ direction. The ferroelectric dielectric material and the second electrode material can be sequentially deposited by thin film deposition techniques such as ALD, and planarization can be performed using CMP to form a plurality of ferroelectric capacitors 11. The ferroelectric capacitor 11 includes a first electrode 111, a ferroelectric dielectric layer 112, and a second electrode 113. The ferroelectric dielectric layer 112 covers the bottom of the second electrode 113 and extends along the sidewall of the second electrode 113 to the top of the second electrode 113, and the first electrode 111 covers the ferroelectric dielectric layer 112. Exemplarily, the ferroelectric dielectric material can be HfZrO2, HfSiO, etc., and the ferroelectric dielectric material can also contain different doping elements, such as one or more of Ti, Y, Nb, La, etc. The second electrode material can be a metal material such as TiN, W, TaN, etc.

[0127] Step 3.5: Refer to Figure 23 (e) and Figure 23 (e’), Figure 23 (e) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 23 (e’) is Figure 23 the top view of (e). Figure 23 (e”) is Figure 23 (e’) Cross-sectional view along the CC’ direction. The dielectric layer 12 between the first ferroelectric capacitor and the second ferroelectric capacitor can be removed by photolithography mask and dry etching, and the etched part S exposes the first conductive column 331.

[0128] Step 3.6: Form a plurality of second accommodation grooves for accommodating contact columns in the dielectric layer. Exemplarily, refer to Figure 23 (f) and Figure 23 (f’), Figure 23 (f) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 23 (f’) is Figure 23 (f) the top view of (f). The dielectric material can be deposited by thin film deposition techniques such as ALD, and the dielectric material can be SiO2 or SiN, etc. Since the dielectric material has isotropic properties, when the dielectric material grows to a certain thickness from the surface of the first electrode 111 of each ferroelectric capacitor 11, the dielectric materials can contact each other and form a space for accommodating the contact column 60, that is, a self-aligned second accommodation groove K2 can be formed. Then, the dielectric material at the bottom is etched by dry etching to expose the first conductive column 331, and chemical mechanical polishing is performed.

[0129] Step 3.7: Form contact columns in the second accommodation grooves. Exemplarily, refer to Figure 24 (g) and Figure 24 (g’), Figure 24(g) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 24 (g’) is Figure 24 (g)'s top view. The conductive material can be deposited by thin film deposition technology such as ALD to form the contact posts 60. The conductive material can be a metal material such as TiN, W, TaN, etc. The multiple ferroelectric capacitors 11 in the ferroelectric capacitor 11 array 10 include multiple capacitor units Q. Each capacitor unit Q includes two ferroelectric capacitors 11 arranged along the second direction X. Any two capacitor units Q arranged along the first direction Y form a capacitor group L. The multiple contact posts 60 correspond to the multiple capacitor units Q one by one, and the contact post 60 connected to one capacitor unit Q in the capacitor group L is arranged in the gap between the four ferroelectric capacitors 11 of the capacitor group L.

[0130] Step 3.8: Form the connection electrodes. Exemplarily, referring to Figure 24 (h) and Figure 24 (h’), Figure 24 (h) is another schematic three-dimensional structure diagram of the storage array in the preparation process of the embodiment of the present application. Figure 24 (h’) is Figure 24 (h)'s top view. The conductive material can be grown by thin film deposition technology such as physical vapor deposition (PVD), and multiple connection electrodes 20 can be formed through photolithography masking-etching or damascene process. Exemplarily, the conductive material can be a metal material such as TiN, W, TaN, Co, Ni, Cu, etc. The multiple connection electrodes 20 correspond to the capacitor units Q one by one. The two ends of the connection electrode 20 are respectively connected to the tops of the second electrodes 113 of the corresponding two ferroelectric capacitors 11, and the top of the contact post 60 corresponding to the capacitor unit Q is connected to the connection electrode 20.

[0131] In the embodiment of the present application, the space for accommodating the contact posts 60 can be formed by self-alignment technology. When forming the accommodation groove for the contact posts 60, it is not necessary to etch the dielectric layer 12, and the process difficulty is relatively low, which is beneficial to cost reduction. The ferroelectric capacitors 11 and the contact posts 60 in the storage array made by this method can be closely arranged, which is beneficial to improving the density of storage units.

[0132] It is worth mentioning that due to process conditions or other factors, in actual processes, there may be some deviations or errors, resulting in the "same" described above may not be completely accurate. For example, the "same" described above can be the same within the allowable error range. Of course, the "same" can also be understood as "substantially the same" or "completely the same". Therefore, as long as the "same" relationship described above generally meets the above conditions, it belongs to the protection scope of the present application.

[0133] In various embodiments of the present application, if there is no special indication and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be cross-referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships. The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. A storage array, characterized in that, Comprising: A ferroelectric capacitor array, including a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along a part of the side wall of the second electrode to the top of the second electrode, and the first electrode covers the ferroelectric dielectric layer; the plurality of ferroelectric capacitors include a plurality of capacitor units arranged in a first direction, and each of the capacitor units includes a plurality of ferroelectric capacitors arranged in a second direction. A connection electrode, located between two adjacent ferroelectric capacitors in each of the capacitor units. The two adjacent ferroelectric capacitors include a first ferroelectric capacitor and a second ferroelectric capacitor. A first end of the connection electrode is connected to the first electrode of the first ferroelectric capacitor, and a second end of the connection electrode is connected to the second electrode of the second ferroelectric capacitor.

2. The storage array according to claim 1, wherein The connection electrode is embedded in the dielectric layer, and the dielectric layer exposes a first surface of the connection electrode, and the first surface is flush with the top of the second electrode.

3. The storage array according to claim 1 or 2, characterized in that, The second electrode includes a first electrode portion and a second electrode portion. The first electrode portion and the second electrode portion are arranged in sequence along the direction from the top to the bottom of the second electrode. The ferroelectric dielectric layer wraps the side wall of the second electrode portion and extends along a first part of the side wall of the first electrode portion to the top of the second electrode, and the ferroelectric dielectric layer exposes a second part of the side wall of the first electrode portion. The first end of the connection electrode is connected to at least a part of the side wall region of the first electrode at the first electrode portion, and the second end of the connection electrode is connected to at least a part of the side wall region of the second part.

4. The storage array according to claim 3, wherein In the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the second electrode is the same.

5. The storage array according to claim 4, wherein The second end of the connection electrode is connected to a part of the side wall region of the second part, and the remaining region of the second part of the side wall is covered by the dielectric layer.

6. The storage array according to claim 3, wherein In the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the first electrode portion is smaller than the cross-sectional area of the second electrode portion.

7. The storage array according to claim 6, wherein The top of the second electrode portion has a first top region and a second top region. The first top region and the second top region are arranged in the second direction, and the first electrode portion covers the first top region. The connection electrode is connected to a part of the side wall region of the second part, and the remaining region of the second part of the side wall and the second top region are covered by the dielectric layer.

8. The storage array according to any one of claims 3-7, characterized in that, At least part of the capacitor units are arranged in a staggered manner, or the plurality of ferroelectric capacitors are arranged in an array in the first direction and the second direction.

9. The storage array according to claim 8, wherein, In the same capacitor unit, the directions in which the first part of the side walls of the ferroelectric capacitors point to the second part of the side walls are the same.

10. The storage array according to claim 9, wherein, In each capacitor unit, the directions in which the first part of the side walls of the ferroelectric capacitors point to the second part of the side walls are the same.

11. The storage array according to claim 9, wherein The multiple capacitor units include at least one first capacitor unit and at least one second capacitor unit. In the first capacitor unit, the direction in which the first partial sidewall of the ferroelectric capacitor points to the second partial sidewall is a first orientation. In the second capacitor unit, the direction in which the first partial sidewall of the ferroelectric capacitor points to the second partial sidewall is a second orientation, and the first orientation and the second orientation are opposite to each other.

12. The storage array according to claim 11, wherein, The first capacitor unit and the second capacitor unit are alternately arranged along the first direction.

13. A manufacturing method of a storage array, characterized in that, Comprising: Forming a ferroelectric capacitor array; The ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along a partial sidewall of the second electrode to the top of the second electrode, and the first electrode covers the ferroelectric dielectric layer; Forming a trench in the dielectric layer; The trench is located between two adjacent ferroelectric capacitors. The two adjacent ferroelectric capacitors include a first ferroelectric capacitor and a second ferroelectric capacitor. A first end of the trench is used to expose a partial area of the first electrode of the first ferroelectric capacitor, and a second end of the trench is used to expose a partial area of the second electrode of the second ferroelectric capacitor; Filling a connection electrode in the trench; a first end of the connection electrode is connected to the first electrode of the first ferroelectric capacitor, and a second end of the connection electrode is connected to the second electrode of the second ferroelectric capacitor.

14. The manufacturing method according to claim 13, characterized in that, The forming of the ferroelectric capacitor array includes: Forming a dielectric layer and an initial ferroelectric capacitor; the initial ferroelectric capacitor includes a first electrode material layer, a ferroelectric dielectric material layer, and a second electrode material layer. The ferroelectric dielectric material layer wraps the second electrode material layer, and the first electrode material layer wraps the ferroelectric dielectric material layer; Etching the first electrode material layer and the ferroelectric dielectric material layer to form a plurality of ferroelectric capacitors; in each of the ferroelectric capacitors, in the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the second electrode is the same; Alternatively, etching the first electrode material layer, the ferroelectric dielectric material layer, and the second electrode material layer to form a plurality of ferroelectric capacitors; the second electrode includes a first electrode portion and a second electrode portion, and the first electrode portion and the second electrode portion are arranged in sequence in the direction from the top of the second electrode to the bottom of the second electrode. In each of the ferroelectric capacitors, in the direction from the top of the second electrode to the bottom of the second electrode, the cross-sectional area of the first electrode portion is smaller than the cross-sectional area of the second electrode portion.

15. A storage array, characterized in that, Comprising: A ferroelectric capacitor array, including a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors; The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along the sidewall of the second electrode to the top of the second electrode. The first electrode covers the ferroelectric dielectric layer. The plurality of ferroelectric capacitors includes a plurality of capacitor units. Each capacitor unit includes two ferroelectric capacitors arranged in a second direction. Any two capacitor units arranged in a first direction form a capacitor group. A plurality of contact posts are disposed in the dielectric layer. The plurality of contact posts correspond to the plurality of capacitor units one by one. The contact posts are connected to the second electrodes of the corresponding two ferroelectric capacitors. Among them, the contact posts connected to one capacitor unit in the capacitor group are disposed in the gap between the four ferroelectric capacitors of the capacitor group.

16. The storage array according to claim 15, wherein In the direction from the top of the contact post to the bottom of the contact post, the cross-sectional shape of the contact post is a quadrilateral, and the apex angles of the quadrilateral extend into the gaps of the ferroelectric capacitors adjacent to the contact post.

17. The storage array according to claim 16, wherein The shape of each side of the quadrilateral is an arc, and the arc bends toward the center of the quadrilateral; or the minimum distance between each side of the quadrilateral and the adjacent ferroelectric capacitor is the same.

18. The storage array according to any one of claims 15-17, wherein It further includes a plurality of connection electrodes. The plurality of connection electrodes correspond to the capacitor units one by one. The two ends of the connection electrode are respectively connected to the tops of the second electrodes of the corresponding two ferroelectric capacitors. The top of the contact post corresponding to the capacitor unit is connected to the connection electrode.

19. The storage array according to claim 18, wherein, The contact area between the connection electrode and the second electrode is a first area, and the area of the top surface of the second electrode is a second area. The first area is less than or equal to half of the second area.

20. The storage array according to claim 18, wherein, The contact area between the connection electrode and the contact post is a third area, and the area of the top surface of the contact post is a fourth area. The third area is less than or equal to half of the fourth area.

21. The storage array according to claim 18, wherein, The plurality of capacitor units includes a first capacitor unit and a second capacitor unit adjacent in the second direction. The first capacitor unit includes a first ferroelectric capacitor, and the second capacitor unit includes a second ferroelectric capacitor. The first ferroelectric capacitor is adjacent to the second ferroelectric capacitor. The first electrode of the first ferroelectric capacitor is connected to the first electrode of the second ferroelectric capacitor through the connection line. The contact area between the connection line and the bottom surface of the first electrode is a fifth area, and the area of the bottom surface of the first electrode is a sixth area. The fifth area is less than or equal to half of the sixth area.

22. A method for manufacturing a storage array, characterized in that, Including: Forming a ferroelectric capacitor array; The ferroelectric capacitor array includes a plurality of ferroelectric capacitors and a dielectric layer disposed between the plurality of ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a ferroelectric dielectric layer, and a second electrode. The ferroelectric dielectric layer covers the bottom of the second electrode and extends along the sidewall of the second electrode to the top of the second electrode. The first electrode covers the ferroelectric dielectric layer. The plurality of ferroelectric capacitors includes a plurality of capacitor units. Each capacitor unit includes two ferroelectric capacitors arranged along the second direction. Any two capacitor units arranged along the first direction form a capacitor group. Form a plurality of contact posts. The plurality of contact posts are disposed in the dielectric layer. The plurality of contact posts correspond to the plurality of capacitor units one by one. The contact posts are connected to the second electrodes of the corresponding two ferroelectric capacitors. Among them, the contact posts connected to one capacitor unit in the capacitor group are disposed in the gap between the four ferroelectric capacitors of the capacitor group.

23. A memory, characterized in that, It includes a controller and a storage array as described in any one of claims 1-12 or claims 15-21. The controller is used to access the storage array.

24. An electronic device, characterized in that, It includes: A circuit board and a memory as described in claim 23. The memory is disposed on the circuit board.

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