Trench capacitor forming method

Abstract

The invention discloses a method for forming a trench capacitor. The method comprises the following steps of: forming a trench on a semiconductor substrate; a heavily doped lower electrode region of the first conductivity type is formed in the surface region of the semiconductor substrate at the inside surface of the trench using a plasma doping process. And forming a capacitor dielectric layer on the inner side surface of the groove. And filling an upper electrode conductive material layer in the groove. According to the invention, the doping effect of the lower electrode region can be improved, so that the resistance of the lower electrode plate can be reduced, the capacitance value can be improved, and very good doping of the bottom region of the groove can be ensured when the depth-to-width ratio of the groove is increased, so that the groove capacitor with high depth-to-width ratio can be realized, and the capacitance density can be increased.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for forming a trench capacitor. Background Art

[0002] With the accelerating development of artificial intelligence (AI) and high-performance computing (HPC), etc., the demand for a high number and high density of transistors is increasing rapidly, and the requirement for high-density decoupling capacitors in integrated circuits is also increasing.

[0003] Currently, due to the compatibility of MIM capacitors and MOS capacitors with CMOS, they are widely used as on-chip level decoupling capacitors in integrated circuits. However, it is difficult for MIM and MOS capacitors to achieve high density, while trench capacitors (DTCs) can overcome this difficulty and save a large amount of area for the chip.

[0004] As Figure 1 shown, it is a single-layer DTC. The doped polysilicon layer 105 (Poly) serves as the upper electrode plate, the SiO2 layer 104a and the Si3N4 layer 104b serve as the capacitor dielectric layer 104, and the N-type well 103 (NW) serves as the lower electrode plate. The lower electrode plate requires that the surface areas of the semiconductor substrate such as the silicon substrate 101 at the bottom and sidewalls of the trench 102 form N-type doped regions, namely N-type wells 103.

[0005] The top of the N-type well 103 outside the trench 102 will be connected to the contact hole 107a passing through the interlayer film 106, and the contact hole 107a will be connected to the top metal wire 110a; the tops of the polysilicon layers 105 will be connected to the same metal wire 110b through the contact holes 107b. In this way, the trench capacitor units in each trench are connected in parallel to form a trench capacitor with a larger area. The materials of the metal wires 110a and 110b are copper, which are formed in the interlayer film 109 by the damascene process. An nitrogen-doped silicon carbide (NDC) layer 108 is also formed at the bottom of the interlayer film 109. The NDC layer 108 can block the diffusion of copper and can also serve as a stop layer when etching the interlayer film 109 in the damascene process.

[0006] As Figure 2 shown, since the aspect ratio of the trench 102 is about 25:1, the NW is realized by two-step beamline ion implant. The first-step beamline ion implant 502 (implant 1) is at a 0-degree angle implant, and the second-step beamline ion implant 503 (implant 2) is at a 2-degree angle of incidence.

[0007] The aspect ratio of the trench 102 in the existing method can reach a maximum of 25:1. When the aspect ratio of the trench 102 is greater than 25:1, due to the limitation of the implantation angle, the NW cannot be formed in the bottom region of the trench 102. As Figure 3A shown, it is an enlarged view of the device structure during the second implantation in the lower electrode region when using a trench with a large aspect ratio in the existing method for manufacturing trench capacitors; the region corresponding to the dashed box 504, i.e., the bottom region of the trench 102, cannot be implanted with impurities.

[0008] As Figure 3B shown, it is Figure 3A a schematic diagram of the implantation depth limit that can be achieved when the maximum angle is used for the second implantation in

[0009] ; when the ion implantation angle is 2°, the process limit of the ion beam current injection has been reached, but it still cannot be implanted into the bottom of the sidewall of the deep trench, that is, the bottom region of the AA dashed line cannot be implanted with impurities. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a method for forming a trench capacitor, which can improve the doping effect of the lower electrode region, thereby reducing the lower plate resistance and improving the capacitance value, and is particularly beneficial for ensuring good doping of the bottom region of the trench when the aspect ratio of the trench increases, so as to realize a trench capacitor with a high aspect ratio and increase the capacitance density.

[0011] To solve the above technical problem, the method for forming a trench capacitor provided by the present invention includes the steps of:

[0012] Form a trench in the semiconductor substrate.

[0013] Adopt a plasma doping process to form a first-conductivity-type heavily doped lower electrode region in the surface region of the semiconductor substrate at the inner surface of the trench.

[0014] Form a capacitor dielectric layer on the inner surface of the trench.

[0015] Fill the trench with an upper electrode conductive material layer; a trench capacitor unit includes the lower electrode region, the capacitor dielectric layer, and the upper electrode conductive material layer formed in one of the trenches.

[0016] A further improvement is that the material of the semiconductor substrate includes silicon.

[0017] A further improvement is that the aspect ratio of the trench is greater than 25:1.

[0018] A further improvement is that the aspect ratio of the trench is from 30:1 to 40:1.

[0019] A further improvement is that the first conductivity type is N-type or P-type.

[0020] A further improvement is that the doping dose of the lower electrode region is E16 cm -2 .

[0021] A further improvement is that the capacitive dielectric layer is an oxide layer, or a silicon nitride layer, or a stacked layer of an oxide layer and a silicon nitride layer.

[0022] A further improvement is that the upper electrode conductive material layer is a heavily doped polysilicon layer. The steps for forming the upper electrode conductive material layer include:

[0023] Depositing the polysilicon layer, which completely fills the trench and extends outside the trench.

[0024] Performing CMP to remove the polysilicon layer outside the trench.

[0025] A further improvement is that a plurality of the trenches are formed on the semiconductor substrate; the trench capacitor is formed by connecting in parallel the trench capacitor units formed in each of the trenches.

[0026] When forming the lower electrode region, the plasma doping process also simultaneously forms a lower electrode connection region doped heavily with the first conductivity type in the surface region of the semiconductor substrate outside the trench, and the lower electrode connection region is connected to the lower electrode regions in each of the trenches through the lower electrode connection region.

[0027] A further improvement is that after forming the upper electrode conductive material layer, the following steps are further included:

[0028] Forming a first interlayer dielectric.

[0029] Forming contact holes passing through the first interlayer dielectric. The contact holes include a first contact hole and a second contact hole. The bottom of the first contact hole is connected to the lower electrode connection region, and a second contact hole is formed at the top of each of the upper electrode conductive material layers.

[0030] Forming a front metal layer and patterning the front metal layer to form metal interconnects. The metal interconnects include a lower electrode interconnect connecting the first contact hole and an upper electrode interconnect connecting each of the second contact holes.

[0031] A further improvement is that before performing the plasma doping process after forming the trench, the following is further included:

[0032] A sacrificial oxide layer is formed on the inner surface of the trench and the surface of the semiconductor substrate outside the trench.

[0033] After the plasma doping process is completed and before the capacitor dielectric layer is formed, the sacrificial oxide layer is removed.

[0034] A further improvement is that the capacitor dielectric layer also extends to the surface of the semiconductor substrate outside the trench.

[0035] The CMP stops on the surface of the capacitor dielectric layer.

[0036] A further improvement is that the material of the contact hole includes tungsten.

[0037] A further improvement is that the material of the front metal layer includes copper.

[0038] A further improvement is that the doping type of the polysilicon layer is N-type or P-type.

[0039] In the prior art, the lower electrode region of the trench capacitor is realized by ion beam current injection, and at least injections with different injection angles are required. Among them, in order to dope the bottom region of the trench, the injection angle needs to be increased. However, the maximum injection angle of the ion implanter is limited. For example, the maximum injection angle can only reach 2 degrees. Therefore, when the aspect ratio of the trench is relatively large, the implanted impurities cannot reach the bottom region of the trench, so doping of the bottom region of the trench cannot be achieved. In the present invention, the lower electrode region is formed by a plasma doping process. In the plasma doping process, the collision of ions randomizes the incident angle of the ions. Therefore, the doping in the present invention eliminates the limitation on the incident angle of ion implantation, so that good doping of the bottom region of the trench can be achieved. Especially when the aspect ratio of the trench is greater than the limit that the existing ion implanter can reach, for example, greater than 25:1, the present invention can still achieve good doping of the bottom region of the trench. Therefore, the present invention is particularly beneficial to ensuring good doping of the bottom region of the trench when the aspect ratio of the trench increases. Therefore, the present invention is beneficial to increasing the aspect ratio of the trench. When the aspect ratio of the trench increases, the capacitance density will also increase. Therefore, the present invention can finally further increase the capacitance density.

[0040] In addition, the randomization of the incident angle of the ions in the plasma doping process of the present invention can increase the doping uniformity, achieve conformal doping of the trench, reduce the junction depth and increase the doping concentration. Therefore, the present invention can also improve the doping effect of the lower electrode region, such as increasing the doping concentration of the lower electrode region, reducing the junction depth and improving the doping uniformity, and finally reducing the lower plate resistance and improving the capacitance value.

[0041] In addition, compared with the prior art where at least two implantations with different implantation angles are required to form the lower electrode region by ion beam current implantation, the present invention can form the lower electrode region by using a single plasma doping process. Therefore, the present invention can also reduce costs and increase output. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0043] Figure 1 is a schematic structural diagram of a conventional trench capacitor;

[0044] Figure 2 is a schematic diagram of the device structure during the formation of the lower electrode region in the manufacturing method of a conventional trench capacitor;

[0045] Figure 3A is an enlarged view of the device structure during the second implantation of the lower electrode region when using a trench with a large aspect ratio in the manufacturing method of a conventional trench capacitor;

[0046] Figure 3B is Figure 3A a schematic diagram of the limit of the implantation depth that can be achieved when the maximum angle is used for the second implantation in

[0047] Figure 4 is a flowchart of the manufacturing method of the trench capacitor according to an embodiment of the present invention;

[0048] Figures 5A - 5F is a schematic diagram of the device structure in each step of the manufacturing method of the trench capacitor according to an embodiment of the present invention;

[0049] Figure 6 is a schematic diagram of the structure of the process chamber of the plasma doping process in the manufacturing method of the trench capacitor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] As Figure 4 shown, it is a flowchart of the manufacturing method of the trench capacitor according to an embodiment of the present invention; as Figures 5A through 5F shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the trench capacitor according to an embodiment of the present invention; the method for forming the trench capacitor according to an embodiment of the present invention includes the steps of:

[0051] Step S101, as Figure 5A shown, a trench 202 is formed on a semiconductor substrate 201.

[0052] In the embodiment of the present invention, the material of the semiconductor substrate 201 is silicon. In other embodiments, the material of the semiconductor substrate 201 can also be other semiconductor materials, such as Ge, SiGe, and SiC, etc.

[0053] In the embodiments of the present invention, the aspect ratio of the trench 202 can be applicable to various values. In some embodiments, the aspect ratio of the trench 202 is greater than 25:1. Preferably, the aspect ratio of the trench 202 is from 30:1 to 40:1. In the existing methods, when the aspect ratio of the trench 202 is greater than 25:1, doping cannot be performed in the bottom region of the trench 202. The embodiments of the present invention solve the problems of the prior art, so the trench 202 with an aspect ratio greater than 25:1 can be adopted.

[0054] In the embodiments of the present invention, a plurality of the trenches 202 are formed on the semiconductor substrate 201.

[0055] In the embodiments of the present invention, after forming the trench 202 and before subsequent plasma doping process, it further includes:

[0056] A sacrificial oxide layer 301 is formed on the inner surface of the trench 202 and the surface of the semiconductor substrate 201 outside the trench 202.

[0057] Step S102, as Figure 5B shown, a first-conductivity-type heavily doped lower electrode region 203 is formed in the surface region of the semiconductor substrate 201 at the inner surface of the trench 202 by using a plasma doping process. In the embodiments of the present invention, the first conductivity type is N-type. In other embodiments, it can also be: the first conductivity type is P-type.

[0058] In some embodiments, the doping dose of the lower electrode region 203 is E16cm -2 .

[0059] In the embodiments of the present invention, the sacrificial oxide layer 301 is removed after completing the plasma doping process and before forming the capacitive dielectric layer 204.

[0060] Figure 5B In, the plasma doping process is shown by the arrow line corresponding to the label 302. It can be seen that the ion incident directions will be evenly distributed in various directions. This is because the ion collisions in the plasma doping process will randomize the incident angles of the ions, thus eliminating the defect that when the incident angle is fixed at a small value, the ions cannot penetrate into the bottom region of the trench 202. Therefore, the aspect ratio of the trench 202 in the embodiments of the present invention can be increased, that is, the depth can be increased when the width is fixed, or the width can be reduced when the depth is fixed.

[0061] In an embodiment of the present invention, when forming the lower electrode region 203, the plasma doping process also forms a heavily doped lower electrode connection region of the first conductivity type in the surface region of the semiconductor substrate 201 outside the trench 202 at the same time. The lower electrode connection region is connected to the lower electrode regions 203 in each of the trenches 202 through the lower electrode connection region. Figure 5B In this case, the lower electrode connection region and the lower electrode region 203 are of an integral structure, that is, both are composed of the same doped region, only the position regions are different.

[0062] As Figure 6 shown, it is a schematic structural diagram of a process chamber of a plasma doping process in a method for manufacturing a trench capacitor according to an embodiment of the present invention; the process chamber 401 is a closed structure, and is evacuated by a vacuum line 406 and a vacuum pump. A wafer 403 is placed on a wafer support device 402, and the wafer support device 402 also serves as a bottom electrode and is connected to a bias voltage.

[0063] The doping gas is introduced from the top cover of the cavity through a gas pipe 404, and the radio frequency power supply 405 is also connected to the top electrode formed by the top cover of the cavity. Under the action of the energy provided by the radio frequency power supply 405, the gas in the cavity 401 will be ionized to generate plasma 407.

[0064] Step S103, as Figure 5C shown, a capacitive dielectric layer 204 is formed on the inner surface of the trench 202.

[0065] In an embodiment of the present invention, the capacitive dielectric layer 204 is a stacked layer of an oxide layer 204a and a silicon nitride layer 204b. In other embodiments, it can also be: the capacitive dielectric layer 204 is a single oxide layer or a single silicon nitride layer, or a stacked layer of two or more oxide layers and silicon nitride layers, or composed of other dielectric layers.

[0066] In an embodiment of the present invention, the capacitive dielectric layer 204 also extends to the surface of the semiconductor substrate 201 outside the trench 202.

[0067] Step S104, as Figure 5D shown, an upper electrode conductive material layer 205 is filled in the trench 202; the trench capacitor unit includes the lower electrode region 203, the capacitive dielectric layer 204, and the upper electrode conductive material layer 205 formed in one of the trenches 202.

[0068] In an embodiment of the present invention, the upper electrode conductive material layer 205 is a heavily doped polysilicon layer. The sub-steps of forming the upper electrode conductive material layer 205 include:

[0069] As Figure 5CAs shown, the polysilicon layer, i.e., the upper electrode conductive material layer 205, is deposited. The polysilicon layer completely fills the trench 202 and extends outside the trench 202.

[0070] In some embodiments, the doping type of the polysilicon layer is N-type. In other embodiments, it can also be that the doping type of the polysilicon layer is P-type. The polysilicon layer is doped in-situ during the deposition growth process, or doped by ion implantation after the deposition growth is completed.

[0071] As Figure 5D shown, CMP is performed to remove the polysilicon layer outside the trench 202.

[0072] The CMP stops on the surface of the capacitor dielectric layer 204.

[0073] In the embodiment of the present invention, the trench capacitor is formed by paralleling the trench capacitor units formed in each trench 202.

[0074] After forming the upper electrode conductive material layer 205, the following steps are further included:

[0075] As Figure 5E shown, the first interlayer film 206 is formed.

[0076] As Figure 5E shown, contact holes passing through the first interlayer film 206 are formed. The contact holes include a first contact hole 207a and a second contact hole 207b. The bottom of the first contact hole 207a is connected to the lower electrode connection region, and a second contact hole 207b is formed on the top of each upper electrode conductive material layer 205.

[0077] In the embodiment of the present invention, the material of the contact holes includes tungsten.

[0078] As Figure 5F shown, a front metal layer is formed and patterned to form metal wirings. The metal wirings include a lower electrode wiring 210a connecting the first contact hole 207a and an upper electrode wiring 210b connecting each second contact hole 207b.

[0079] In the embodiment of the present invention, the material of the front metal layer includes copper. The front metal layer is formed by the damascene process. That is, a second interlayer film 209 is first formed; then, the second interlayer film 209 is patterned and etched to form a wiring groove; then, the front metal layer is filled in the wiring groove to form the metal wiring. Usually, the second interlayer film 209 uses a low dielectric constant material; a nitrogen-doped silicon carbide (NDC) layer 208 is also formed at the bottom of the second interlayer film 209.

[0080] In the prior art, the lower electrode region 203 of the trench capacitor is formed by ion beam current injection, and at least two injections with different injection angles are required. Among them, in order to dope the bottom region of the trench 202, the injection angle needs to be increased. However, the maximum injection angle of the ion implantation machine is limited. For example, the maximum injection angle can only reach 2 degrees. Therefore, when the aspect ratio of the trench 202 is relatively large, the implanted impurities cannot reach the bottom region of the trench 202, so doping the bottom region of the trench 202 cannot be achieved. In the embodiment of the present invention, the lower electrode region 203 is formed by a plasma doping process. In the plasma doping process, the collision of ions randomizes the incident angle of the ions. Therefore, the doping in the embodiment of the present invention eliminates the limitation on the incident angle of ion implantation, so that good doping of the bottom region of the trench 202 can be achieved. Especially when the aspect ratio of the trench 202 is greater than the limit that the existing ion implantation machine can reach, for example, greater than 25:1, the embodiment of the present invention can still achieve good doping of the bottom region of the trench 202. Therefore, the embodiment of the present invention is particularly beneficial to ensuring good doping of the bottom region of the trench 202 when the aspect ratio of the trench 202 increases. Therefore, the embodiment of the present invention is beneficial to increasing the aspect ratio of the trench 202. When the aspect ratio of the trench 202 increases, the capacitance density will also increase. Therefore, the embodiment of the present invention can finally further increase the capacitance density.

[0081] In addition, the randomization of the incident angle of the ions in the plasma doping process in the embodiment of the present invention can increase the doping uniformity, can achieve conformal doping of the trench 202, and can also reduce the junction depth and increase the doping concentration. Therefore, the embodiment of the present invention can also improve the doping effect of the lower electrode region 203. For example, it can increase the doping concentration of the lower electrode region 203, reduce the junction depth, and improve the doping uniformity, and finally can reduce the lower plate resistance and improve the capacitance value. This is because when the lower plate resistance decreases, the voltage drop brought by the lower plate also decreases. According to the capacitance formula C = Q / U, when the charge Q remains unchanged, after U decreases, the capacitance value C will increase.

[0082] In addition, compared with the prior art in which at least two injections with different injection angles are required to form the lower electrode region 203 by ion beam current injection, the embodiment of the present invention can form the lower electrode region 203 by one plasma doping process. Therefore, the embodiment of the present invention can also reduce costs and increase output.

[0083] The above has described the present invention in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a trench capacitor, characterized in that, Including the steps: Forming a trench in a semiconductor substrate; Forming a first conductivity type heavily doped lower electrode region in a surface region of the semiconductor substrate at an inner surface of the trench by using a plasma doping process; Forming a capacitive dielectric layer on the inner surface of the trench; Filling an upper electrode conductive material layer in the trench; The trench capacitor unit includes the lower electrode region, the capacitive dielectric layer, and the upper electrode conductive material layer formed in one of the trenches.

2. The method for forming a trench capacitor according to claim 1, wherein: The material of the semiconductor substrate includes silicon.

3. The method for forming a trench capacitor according to claim 1, wherein: The aspect ratio of the trench is greater than 25:

1.

4. The method for forming a trench capacitor according to claim 3, wherein: The aspect ratio of the trench is from 30:1 to 40:

1.

5. The method for forming a trench capacitor according to claim 1, wherein: The first conductivity type is N-type or P-type.

6. The method for forming a trench capacitor according to claim 1, wherein: The doping dose of the lower electrode region is E16 cm -2 .

7. The method for forming a trench capacitor according to claim 1, wherein: The capacitive dielectric layer is an oxide layer, or a silicon nitride layer, or a stacked layer of an oxide layer and a silicon nitride layer.

8. The method for forming a trench capacitor according to claim 1, wherein: The upper electrode conductive material layer is a heavily doped polysilicon layer. The steps of forming the upper electrode conductive material layer include: Depositing the polysilicon layer, and the polysilicon layer completely fills the trench and extends outside the trench; Performing CMP to remove the polysilicon layer outside the trench.

9. The method for forming a trench capacitor according to claim 1, wherein: A plurality of the trenches are formed on the semiconductor substrate; the trench capacitors are formed by connecting in parallel the trench capacitor units formed in each of the trenches; When forming the lower electrode region, the plasma doping process also simultaneously forms a first conductivity type heavily doped lower electrode connection region in a surface region of the semiconductor substrate outside the trench, and the lower electrode connection region is connected to the lower electrode regions in each of the trenches through the lower electrode connection region.

10. The method for forming a trench capacitor according to claim 9, wherein: After forming the upper electrode conductive material layer, the following steps are further included: Forming a first interlayer dielectric; Forming contact holes passing through the first interlayer dielectric. The contact holes include a first contact hole and a second contact hole. The bottom of the first contact hole is connected to the lower electrode connection region, and a second contact hole is formed on the top of each of the upper electrode conductive material layers; Forming a front metal layer and patterning the front metal layer to form metal interconnections. The metal interconnections include lower electrode interconnections connecting the first contact holes and upper electrode interconnections connecting the second contact holes.

11. The method for forming a trench capacitor according to claim 9, wherein: Before performing the plasma doping process after forming the trench, the following is further included: Forming a sacrificial oxide layer on an inner surface of the trench and on a surface of the semiconductor substrate outside the trench; Removing the sacrificial oxide layer after completing the plasma doping process and before forming the capacitive dielectric layer.

12. The method for forming a trench capacitor according to claim 8, wherein: The capacitive dielectric layer also extends to a surface of the semiconductor substrate outside the trench; The CMP stops on a surface of the capacitive dielectric layer.

13. The method for forming a trench capacitor according to claim 10, wherein: The material of the contact holes includes tungsten.

14. The method for forming a trench capacitor according to claim 10, wherein: The material of the front metal layer includes copper.

15. The method for forming a trench capacitor according to claim 8, wherein: The doping type of the polysilicon layer is N-type or P-type.

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