Cell structure of MOSFET device and preparation method thereof

Abstract

The present invention provides a cellular structure for a MOSFET device and a method for fabricating the same, comprising: a substrate comprising a first surface and a second surface opposite to each other; an epitaxial layer located on the first surface, a surface of the epitaxial layer remote from the substrate serving as a third surface, the epitaxial layer and the substrate having the same doping type; and a cellular region located in the portion of the epitaxial layer near the third surface. The cellular region includes a source structure and a gate structure, wherein the source and gate structures are non-linear in a first direction and alternately arranged in a second direction, the first and second directions being perpendicular to the thickness direction of the substrate. This improves the prior art technical problem of MOSFET devices requiring compromise optimization between on- and short-circuit characteristics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a cell structure of a MOSFET device and a method for preparing the cell structure of a MOSFET device. Background Art

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, has broad application prospects in high voltage, high power, high temperature and high frequency applications due to its advantages such as wide bandgap, high critical electric field strength, high thermal conductivity and high saturation drift velocity.

[0003] Compared to planar MOSFETs, silicon carbide trench-gate MOSFETs significantly reduce their on-state resistance due to their vertically arranged channels, small cell size, and high channel density, making them suitable for low-voltage and high-frequency applications. Traditional trench cell designs primarily use strip-shaped cells, where the total length of the strips within the cell region is the channel width. Once the cell dimensions are determined, the channel width is determined accordingly. For the same cell area, a smaller width increases the channel width, resulting in better on-state characteristics. However, the minimum width is often limited by process capabilities rather than design requirements. For example, the width of the contact hole is limited by the minimum line width of the lithography layer and the metal fill process. However, from a device performance perspective, the contact hole can be smaller. Therefore, process capabilities limit device performance improvements. From a device performance perspective, appropriately reducing the cell size can increase the channel width, improving on-state characteristics and optimizing short-circuit performance. However, when the cell size is too small, the distance between the P-well regions decreases, increasing the resistance of the JFET region and resulting in poor on-state characteristics. Summary of the Invention

[0004] The main purpose of the present invention is to provide a cellular structure of a MOSFET device and a method for preparing the cellular structure of a MOSFET device, so as to supplement the new design scheme in the prior art in which the conduction characteristics and short-circuit characteristics of the MOSFET device need to be compromised and optimized.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a cell structure of a MOSFET device is provided, comprising: a substrate, the substrate comprising a first surface and a second surface relative to each other; an epitaxial layer, located on the first surface, the surface of the epitaxial layer away from the substrate being a third surface, the epitaxial layer having the same doping type as the substrate; a cell region, located in a portion of the epitaxial layer close to the third surface, the cell region comprising a source structure and a gate structure, wherein in a first direction, the source structure and the gate structure are non-linear, and in a second direction, the source structure and the gate structure are alternately arranged, and the first direction and the second direction are respectively perpendicular to the thickness direction of the substrate.

[0006] Optionally, the epitaxial layer has a first groove and a second groove; the gate structure is located in the first groove, and the source structure is located in the second groove.

[0007] Optionally, the angle between the side wall of the first groove and the bottom surface of the first groove is 0°~180°, and the angle between the side wall of the second groove and the bottom surface of the second groove is 0°~180°.

[0008] Optionally, the number of levels of the first grooves is 0-3, and the number of levels of the second grooves is 0-4.

[0009] Optionally, in the second direction, distances between any two adjacent source structures and gate structures are equal or unequal.

[0010] Optionally, the orthographic projection of the gate structure on the second surface includes a first wide portion and a first narrow portion, and the orthographic projection of the source structure on the second surface includes a second wide portion and a second narrow portion, the first wide portion and the first narrow portion are alternately arranged in the first direction, the second wide portion and the second narrow portion are alternately arranged in the first direction, the first wide portion and the second narrow portion are alternately arranged in the second direction, and the second wide portion and the first narrow portion are alternately arranged in the second direction.

[0011] Optionally, the cell region further includes: a first doping region, located on a side of the gate structure close to the substrate, and a projection of the first doping region on the substrate overlaps with the first wide portion, and a doping type of the first doping region is different from a doping type of the substrate; a second doping region, located on a side of the source structure close to the substrate, and a projection of the second doping region on the substrate overlaps with the second wide portion, and a doping type of the first doping region is different from a doping type of the substrate.

[0012] Optionally, in the second direction, a third doping region, a fourth doping region and a fifth doping region are arranged in the epitaxial layer between the first groove and the second groove, the doping type of the third doping region is the same as the doping type of the substrate, the doping type of the fourth doping region and the doping type of the fifth doping region are different from the doping type of the substrate, and in the second direction, at least part of the third doping region is located between the source structure and the fifth doping region, and at least part of the fifth doping region is located between the fourth doping region and the second doping region.

[0013] Optionally, the cellular structure further includes: a sixth doping region, located on the side wall of the source structure, the doping type of the sixth doping region is the same as the doping type of the first doping region, and in the second direction, part of the sixth doping region is located between the third doping region and the source structure, part of the sixth doping region is located between the fourth doping region and the source structure, and part of the sixth doping region is located between the fifth doping region and the source structure.

[0014] Optionally, in the thickness direction of the substrate, at least part of the third doping region is located between part of the third surface and the fourth doping region, and at least part of the third doping region is located between part of the third surface and the fifth doping region.

[0015] Optionally, the cell structure of the MOSFET device further includes: a seventh doping region, located on a side of the fourth doping region away from the third surface and a side of the fifth doping region away from the third surface, wherein the doping type of the seventh doping region is the same as the doping type of the substrate, the doping concentration of the seventh doping region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the seventh doping region is less than the doping concentration of the third doping region.

[0016] Optionally, the source structure includes a stacked first metal layer and a second metal layer, the second metal layer is located on a side of the first metal layer away from the epitaxial layer, and the first metal layer forms an ohmic contact with the epitaxial layer.

[0017] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a method for preparing a cell structure of a MOSFET device is provided, comprising: providing a substrate; forming a preliminary epitaxial layer on a surface of one side of the substrate, wherein the surface of the preliminary epitaxial layer away from the substrate is a preliminary surface, and the doping type of the preliminary epitaxial layer is the same as the doping type of the substrate; removing part of the preliminary epitaxial layer, and the remaining preliminary epitaxial layer is an epitaxial layer, and the surface of the epitaxial layer away from the substrate is a third surface; forming a gate structure and a source structure in a part of the epitaxial layer close to the third surface.

[0018] The technical solution of the present invention provides a cellular structure for a MOSFET device, comprising: a substrate comprising first and second opposing surfaces; an epitaxial layer located on the first surface, a surface of the epitaxial layer distal to the substrate being a third surface, the epitaxial layer having the same doping type as the substrate; and a cellular region located in the portion of the epitaxial layer proximal to the third surface. The cellular region includes a source structure and a gate structure. The source and gate structures are nonlinear in a first direction and alternately arranged in a second direction, with the first and second directions being perpendicular to the thickness of the substrate. The nonlinear source and gate structures can increase the channel width while maintaining the same cellular region area, thereby improving the on-state characteristics of the MOSFET device. Furthermore, the use of a nonlinear source contact increases the source contact area, saving dimension in the cellular structure's width direction. Furthermore, due to the reduced current density and alternating current path, the highest hotspot is moved away from the substrate surface, which helps to reduce stress and strain between the surface layers during a short circuit, thereby improving the short-circuit characteristics. A new design strategy for optimizing the on-state and short-circuit characteristics of MOSFET devices is proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0020] Figure 1 A schematic structural diagram of a cell region provided according to an embodiment of the present invention is shown;

[0021] Figure 2 Shown Figure 1 A cross-sectional view along the AA` direction;

[0022] Figure 3 Shown Figure 1 A cross-sectional view along the BB` direction;

[0023] Figure 4 A schematic structural diagram of another cell region provided according to an embodiment of the present invention is shown;

[0024] Figure 5 Shown Figure 4 A cross-section along the CC` direction;

[0025] Figure 6 Shown Figure 4 A cross-section along the DD` direction;

[0026] Figure 7 Shown Figure 1 Another cross-sectional view along the AA` direction;

[0027] Figure 8 Shown Figure 1 Another cross-sectional view along the BB` direction;

[0028] Figure 9 Shown Figure 1 Another cross-sectional view along the AA' direction;

[0029] Figure 10 Shown Figure 1 Another cross-sectional view along the BB' direction;

[0030] Figure 11 Shown Figure 1 Another cross-sectional view along the AA' direction;

[0031] Figure 12 Shown Figure 1 Another cross-sectional view along the BB` direction;

[0032] Figure 13 A schematic structural diagram of another cell region provided according to an embodiment of the present invention is shown;

[0033] Figure 14 Shown Figure 13 A cross-section along the EE` direction;

[0034] Figure 15 Shown Figure 13 A cross-sectional view along the FF` direction;

[0035] Figure 16 A schematic flow chart of a method for preparing a cell structure of a MOSFET device provided in an embodiment of the present application is shown.

[0036] The above drawings include the following reference numerals:

[0037] 10. Substrate; 11. Epitaxial layer; 12. Cell region; 121. Source structure; 122. Gate structure; 1211. Second wide portion; 1212. Second narrow portion; 1221. First wide portion; 1222. First narrow portion; 123. First doped region; 124. Second doped region; 125. Third doped region; 126. Fourth doped region; 127. Fifth doped region; 128. Sixth doped region; 129. Seventh doped region; 1213. First metal layer; 1214. Second metal layer; 130. Gate oxide layer. DETAILED DESCRIPTION

[0038] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0041] As introduced in the background technology, the existing technology cannot take into account both the conduction characteristics and short-circuit characteristics of MOSFET devices at the same time. To solve the above problems, the embodiments of the present application provide a cell structure of a MOSFET device and a method for preparing the cell structure of a MOSFET device.

[0042] Figure 1 Schematic diagram of the cell structure of a MOSFET device according to an embodiment of the present application. Figures 1 to 15 Shown, including:

[0043] A substrate 10, wherein the substrate 10 includes a first surface and a second surface opposite to each other;

[0044] an epitaxial layer 11 located on the first surface, a surface of the epitaxial layer 11 away from the substrate 10 being a third surface, and the epitaxial layer 11 and the substrate 10 having the same doping type;

[0045] The cell region 12 is located in the portion of the epitaxial layer 11 close to the third surface. The cell region 12 includes a source structure 121 and a gate structure 122. In the first direction D1, the source structure 121 and the gate structure 122 are non-linear. In the second direction D2, the source structure 121 and the gate structure 122 are alternately arranged. The first direction D1 and the second direction D2 are respectively perpendicular to the thickness direction of the substrate 10.

[0046] Specifically, the material of the substrate 10 may be silicon carbide, for example, 4H-SiC. The doping concentration of the substrate 10 may be in the range of 5e 18 ~1e 21 cm -3 The thickness of the substrate 10 can be 50-500 μm. The epitaxial layer 11 can be a single layer structure or a double layer structure. For example, the epitaxial layer can include a buffer layer and a drift layer double layer structure. For example, the doping concentration of the buffer layer can be 5e 15 ~1e 19 cm -3 , the thickness can be 5~50μm; the doping concentration of the drift layer can be 1e 14 ~5e 17 cm -3 The thickness can be 5 to 150 μm. Furthermore, the substrate 10 and the epitaxial layer 11 have the same doping type. That is, if the substrate 10 is N-type, the epitaxial layer 11 is also N-type. The source structure 121 and the gate structure 122 can be either planar or trench structures.

[0047] This embodiment provides a cellular structure for a MOSFET device, comprising: a substrate comprising a first surface and a second surface facing each other; an epitaxial layer located on the first surface, a surface of the epitaxial layer distal to the substrate being a third surface, the epitaxial layer having the same doping type as the substrate; and a cellular region located in the portion of the epitaxial layer proximal to the third surface. The cellular region includes a source structure and a gate structure. The source and gate structures are nonlinear in a first direction and alternately arranged in a second direction, with the first and second directions being perpendicular to the thickness of the substrate. The nonlinearity of the source and gate structures increases the channel width for the same cellular region area, thereby improving the on-state characteristics of the MOSFET device. Furthermore, the use of a nonlinear source contact increases the source contact area, saving dimension in the width direction of the cellular structure. Furthermore, due to the reduced current density and alternating current path, the highest hotspot is moved away from the substrate surface, which helps to reduce stress and strain between the surface multilayer materials during a short circuit, thereby improving the short-circuit characteristics. A new design strategy for optimizing the on-state and short-circuit characteristics of MOSFET devices is proposed.

[0048] In other embodiments, Figure 2 and Figure 3 As shown, the epitaxial layer has a first groove and a second groove; the gate structure 122 is located in the first groove, and the source structure 121 is located in the second groove. Compared to a planar gate structure or a planar source structure, the trench structure formed by the first and second grooves can further improve the on-resistance and channel density of the MOSFET device.

[0049] Specifically, the source and gate structures can be formed by etching to form source trenches and depositing source metal or gate metal. The specific shapes of the source and gate structures are not limited and can be regular or irregular. The width of the source and gate structures can be 0.5-5 μm, and the depth can be 0.5-2 μm.

[0050] In some embodiments, the angle between the side wall of the first groove and the bottom surface of the first groove is 0°~180°, and the angle between the side wall of the second groove and the bottom surface of the second groove is 0°~180°. That is to say, the opening of the first groove can be larger than the bottom surface of the first groove, or smaller than the bottom surface of the first groove, and the same applies to the second groove. In the case where the opening of the first groove or the second groove is larger than the corresponding bottom surface, the gate oxide layer at the corner can be further protected, the concentration of stress can be reduced, and the reliability of the MOSFET device can be further improved. In the case where the opening of the first groove or the second groove is smaller than the corresponding bottom surface, the crystal plane at the bottom of the groove can have a higher atomic arrangement density, thereby forming a thicker gate oxide layer after thermal oxidation, which can further improve the breakdown voltage of the MOSFET device.

[0051] In some other embodiments, the number of levels of the first grooves is 0 to 3, and the number of levels of the second grooves is 0 to 4. The multi-level trench structure can further reduce the on-resistance of the device by increasing the channel density and optimizing the current path.

[0052] Specifically, the number of levels of the grooves is the number of steps of the grooves. When the gate structure is a planar structure, the number of levels of the first grooves is 0. Similarly, when the source structure is a planar structure, the number of levels of the second grooves is also 0. The number of levels of the first grooves can be the same as or different from the number of levels of the second grooves. Figure 2 and Figure 3 As shown, the gate structure 122 is located in the first groove, the source structure 121 is located in the second groove, the first groove has a level of 1, and the second groove has a level of 1. Another schematic diagram of the cell region structure is shown in FIG. Figure 4 As shown, along Figure 4 CC` in get Figure 5 The cross-sectional diagram shown is along Figure 4 DD` in gets Figure 6 The cross-sectional diagram is shown in FIG. Figure 5 As shown, the gate structure 122 is located in the first groove, the source structure 121 is located in the second groove, the number of levels of the first groove is 1, and the number of levels of the second groove is 2. Figure 6As shown, the gate structure 122 is located in the first groove, the source structure 121 is located in the second groove, the number of levels of the first groove is 1, and the number of levels of the second groove is 1. Figure 4 and Figure 5 As shown, through the above-mentioned method of step-doping the source structure 121, on the one hand, the sixth doping region 128 is only distributed in a limited range of the stepped trench and will not affect the doping concentration at the channel; on the other hand, the deeper the position in the source structure 121, the farther away from the gate structure 122 through the stepped configuration, which can further reduce the JFET resistance effect; on the other hand, the stepped source structure 121 is distributed at one level in the fifth doping region 127, and the resistivity of the fifth doping region 127 can be reduced by the injection of the sixth doping region 128, and the length of the ohmic contact region from the second doping region 124 to the third doping region 125 is lengthened with the design of the stepped source structure 121, and more holes are directly conducted away from the ohmic contact of the sixth doping region 128, while further avoiding the occurrence of BJT punch-through.

[0053] In some embodiments, in the second direction, the distances between any two adjacent source structures and gate structures are equal or unequal. The second direction is the direction in which the source structures and gate structures are alternately arranged.

[0054] It should be noted that Figure 1 and Figure 4 Only part of the source structure and part of the gate structure in the cell region are shown. In fact, the cell region also includes a plurality of other source structures 121 and gate structures 122 that are not shown. Figure 1 As shown, in the second direction D2 , the distances between two adjacent source structures 121 and gate structures 122 are equal.

[0055] like Figure 1 As shown, the orthographic projection of the gate structure 122 on the second surface includes a first wide portion 1221 and a first narrow portion 1222. The orthographic projection of the source structure 121 on the second surface includes a second wide portion 1211 and a second narrow portion 1212. The first wide portion 1221 and the first narrow portion 1222 are alternately arranged in the first direction D1, the second wide portion 1211 and the second narrow portion 1212 are alternately arranged in the first direction D1, the first wide portion 1221 and the second narrow portion 1212 are alternately arranged in the second direction D2, and the second wide portion 1211 and the first narrow portion 1222 are alternately arranged in the second direction D2. Furthermore, the source structure 121 and the gate structure 122 are simultaneously grooved, their positions corresponding to the positions of the source contact regions, and the relative position between the sidewalls of the source structure 121 and the channel remains unchanged. This arrangement simplifies the process and maintains the same relative position, further ensuring the uniformity of the avalanche hole current distribution.

[0056] In other embodiments, Figure 2 、 Figure 3 、 Figures 5 to 12 As shown, the cell region 12 further includes: a first doped region 123, located on a side of the gate structure 122 close to the substrate 10, with the projection of the first doped region 123 on the substrate 10 overlapping the first wide portion, and the doping type of the first doped region 123 being different from the doping type of the substrate 10; and a second doped region 124, located on a side of the source structure 121 close to the substrate 10, with the projection of the second doped region 124 on the substrate 10 overlapping the second wide portion, and the doping type of the first doped region 123 being different from the doping type of the substrate 10. The first doped region 123 can serve as a gate-cut region for the gate structure 122, and the second doped region 124 can serve as a source-cut region for the source structure 121. Providing source-cut regions in the source structure 121 and gate-cut regions in the gate structure 122 can provide enhanced blocking robustness, further reducing the short-circuit current of the MOSFET device and improving short-circuit characteristics.

[0057] Specifically, the source cut-off region can be set to a higher doping concentration. Below the source structure, a highly doped field stop layer is discontinuously configured. Due to its discontinuity, the resistance of the JFET region can be improved. In addition, the length from the source cut-off region to the ohmic contact region of the second doping structure is lengthened, and more holes are directly conducted away from the P++ ohmic contact. Both points avoid the occurrence of BJT punch-through. The doping concentration range of the source cut-off region can be 8e 16 -5e 19 cm -3 , the injection depth can be 0.5~3μm. The above-mentioned gate cut-off region can be set to a larger doping concentration. Below the gate structure, a highly doped field stop layer is discontinuously configured. Due to its discontinuity, the resistance of the JFET region can be improved. In addition, since the gate cut-off region and the source cut-off region are configured at equal intervals, the blocking characteristics can be guaranteed; at the same time, a part of the JFET pinch-off function is retained, which can limit the transient increase of the short-circuit current. The doping concentration range of the gate cut-off region can be 8e 16 -5e 19 cm -3 The implantation depth can be 0.5 to 3 μm. In practical applications, the first doped region can be located on a portion or the entire surface of the gate structure close to the substrate. Similarly, the second doped region can also be located on a portion or the entire surface of the source structure close to the substrate.

[0058] In practical applications, such as Figure 7 and Figure 8As shown, a first doped region 123 is provided on the side of the gate structure 122 close to the substrate 10, and a second doped region 124 is provided on the side of the source structure 121 close to the substrate 10. That is, cut-off regions are provided on both the side of the gate structure 122 and the side of the source structure 121 close to the substrate 10, with a gap between the two cut-off regions. This can partially increase the width of the JFET resistance region, improving the conduction characteristics, while partially retaining the small JFET resistance region width to ensure the short-circuit current peak clamping characteristics. In addition, the cut-off regions of the gate structure 122 and the source structure 121 are arranged alternately, with the high JFET resistance region located at the corner channel position (where the electric field is concentrated), which can reduce the current stress there, thereby further reducing the overall power stress concentration of the device, thereby further improving the reliability of the device.

[0059] In order to further improve the conduction characteristics of the MOSFET device, in some embodiments, another structural diagram of the cell region is as follows: Figure 13 As shown, along Figure 13 EE` in get Figure 14 The cross-sectional diagram shown is along Figure 13 FF` in get Figure 15 The cross-sectional diagram is shown in FIG. Figures 13 to 15 As shown, the source structure 121 has deep grooves only at positions corresponding to the second doping region 124, and contact grooves are only opened on the fifth doping region 127 at other positions; that is, the positive projection of the source structure 121 on the substrate 10 overlaps with the projection of the above-mentioned second doping region 124 on the above-mentioned substrate 10.

[0060] Specifically, if Figure 2 、 Figure 3 、 Figures 5 to 12 、 Figure 14 as well as Figure 15 As shown, the cell structure further includes a gate oxide layer 130 located on a side of the gate structure 122 close to the substrate 10 and on a sidewall of the gate structure 122. The gate oxide layer 130 is used to isolate the gate structure 122 from the substrate 10 and prevent impurities in the substrate 10 from diffusing into the gate structure 122.

[0061] In other embodiments, Figure 2 、 Figure 3 、 Figures 5 to 12 、 Figure 14 as well as Figure 15As shown, in the second direction D2, a third doping region 125, a fourth doping region 126, and a fifth doping region 127 are disposed in the epitaxial layer 11 between the first and second recesses. The doping type of the third doping region 125 is the same as the doping type of the substrate 10, while the doping types of the fourth doping region 126 and the fifth doping region 127 are different from the doping type of the substrate 10. In the second direction D2, at least a portion of the third doping region 125 is located between the source structure 121 and the fifth doping region 127, and at least a portion of the fifth doping region 127 is located between the fourth doping region 126 and the second doping region 124. The third doping region 125 can further reduce contact resistance and improve conduction characteristics.

[0062] Specifically, the doping concentration of the third doping region can be in the range of 1e 18 ~5e 21 cm -3 , the injection depth can be 0.1~3μm. Designing a contact area on the side of the third doping region can further increase the contact area of ​​the third doping region, which is beneficial to further reduce the contact resistance and improve the conduction characteristics. In addition, the downward shift of the source structure potential is also beneficial to improve the conduction and short-circuit characteristics of the MOSFET device. The third doping region contacts the first doping region in the first direction. The doping concentration of the fourth doping region can be in the range of 5e 15 ~2e 18 cm -3 The thickness can be 0.2~3μm. The fifth doping region can be of regular shape or irregular shape. The doping concentration of the fifth doping region can be in the range of 2e 17 ~8e 19 cm-3, and the injection depth can be 0~3μm.

[0063] In order to further improve the conduction characteristics of the MOSFET device, in other embodiments, a contact region may be designed on the side of the third doped region, such as Figure 9 and Figure 10 As shown, in the second direction, the third doped region 125 is in direct contact with the source structure 121, which can further increase the contact area of ​​the third doped region, thereby reducing the contact resistance and further improving the conduction characteristics. In addition, due to the downward shift of the potential of the source structure 121, the conduction and short-circuit characteristics can also be further improved.

[0064] In some further embodiments, Figure 11 and Figure 12As shown, in the second direction D2, the third doping region 125 directly contacts the fifth doping region 127, and the fifth doping region 127 extends to the side surface of the third doping region 125, which can reduce the ohmic contact resistivity and further improve the short-circuit characteristics.

[0065] like Figure 2 、 Figure 3 、 Figures 7 to 12 as well as Figure 14 As shown, the above-mentioned cellular structure also includes: a sixth doping region 128, which is located on the side wall of the above-mentioned source structure 121. The doping type of the above-mentioned sixth doping region 128 is the same as the doping type of the above-mentioned first doping region 123. In the second direction D2, part of the above-mentioned sixth doping region 128 is located between the above-mentioned third doping region 125 and the above-mentioned source structure 121, part of the above-mentioned sixth doping region 128 is located between the above-mentioned fourth doping region 126 and the above-mentioned source structure 121, and part of the above-mentioned sixth doping region 128 is located between the above-mentioned fifth doping region 127 and the above-mentioned source structure 121.

[0066] Specifically, the doping concentration of the sixth doping region is greater than the doping concentration of the fifth doping region. The doping concentration of the sixth doping region may be in the range of 4e 17 ~1e 20 cm -3 The implantation depth is 0.2~2μm. It should be noted that the location of the sixth doping region can be adjusted according to actual conditions. Figure 2 、 Figure 3 、 Figure 7 as well as Figure 8 As shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the source structure 121 away from the substrate 10, and in the second direction, the sixth doping region 128 is in contact with the third doping region 125 and the source structure 121 respectively. Figure 9 and Figure 10 As shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the fifth doping region 127 away from the substrate 10 , and in the second direction, the sixth doping region 128 is in contact with the fifth doping region 127 and the source structure 121 respectively. Figure 11 and Figure 12 As shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the source structure 121 away from the substrate 10 , and in the second direction, the sixth doping region 128 is in contact with the fifth doping region 127 and the source structure 121 respectively.

[0067] In some other embodiments, such as Figure 2 、 Figure 3 as well as Figures 5 to 12 、 Figure 14 as well as Figure 15As shown, in the thickness direction of the substrate 10, at least a portion of the third doping region 125 is located between a portion of the third surface and the fourth doping region 126, and at least a portion of the third doping region 125 is located between a portion of the third surface and the fifth doping region 127. In other words, the third doping region 125 is located on a side of the fourth doping region 126 away from the substrate 10 and on a side of the fifth doping region 127 away from the substrate 10.

[0068] In some specific embodiments, such as Figure 2 、 Figure 3 as well as Figures 7 to 12 、 Figure 14 as well as Figure 15 As shown, the cell structure of the MOSFET device further includes a seventh doping region 129 located on a side of the fourth doping region 126 away from the third surface and on a side of the fifth doping region 127 away from the third surface. The doping type of the seventh doping region 129 is the same as the doping type of the substrate 10, the doping concentration of the seventh doping region 129 is greater than the doping concentration of the epitaxial layer 11, and the doping concentration of the seventh doping region 129 is less than the doping concentration of the third doping region 125. The seventh doping region 129 can serve as a JFET region of the MOSFET device.

[0069] like Figure 2 、 Figure 3 、 Figures 6 to 12 as well as Figure 14 As shown, the source structure 121 includes a stacked first metal layer 1213 and a second metal layer 1214 . The second metal layer 1214 is located on a side of the first metal layer 1213 away from the epitaxial layer 11 . The first metal layer 1213 forms an ohmic contact with the epitaxial layer 11 .

[0070] The present application also provides a method for manufacturing a cell structure of a MOSFET device. Figure 16 FIG. 1 is a flow chart of a method for manufacturing a cell structure of a MOSFET device according to an embodiment of the present application. Figure 16 As shown, the method includes:

[0071] Step S701, providing a substrate, wherein the substrate includes a first surface and a second surface opposite to each other;

[0072] Step S702, forming a preliminary epitaxial layer on one side surface of the substrate, wherein the surface of the preliminary epitaxial layer away from the substrate is a preliminary surface, and the doping type of the preliminary epitaxial layer is the same as the doping type of the substrate;

[0073] Step S703, removing part of the prepared epitaxial layer, the remaining prepared epitaxial layer is the epitaxial layer, and the surface of the epitaxial layer away from the substrate is the third surface;

[0074] Step S704 , forming a gate structure and a source structure in a portion of the epitaxial layer close to the third surface.

[0075] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0076] The cell structure of the MOSFET device of the present application includes: a substrate, the substrate including a first surface and a second surface relative to each other; an epitaxial layer located on the first surface, the surface of the epitaxial layer away from the substrate being a third surface, the epitaxial layer having the same doping type as the substrate; and a cell region located in the portion of the epitaxial layer near the third surface. The cell region includes a source structure and a gate structure. In a first direction, the source structure and the gate structure are non-linear. In a second direction, the source structure and the gate structure are arranged alternately, with the first direction and the second direction being perpendicular to the thickness direction of the substrate. The non-linear source and gate structures can increase the channel width for the same cell region area, thereby improving the conduction characteristics of the MOSFET device. In addition, the use of a non-linear source contact method can increase the source contact area, saving the size of the cell structure in the width direction. At the same time, due to the reduction in current density and the change in current path, the highest hot spot is away from the substrate surface, which is beneficial to improve the stress and strain between the surface multilayer materials during short circuit, thereby improving the short-circuit characteristics. A new design idea for the compromise optimization of the conduction and short-circuit characteristics of the MOSFET device is proposed.

[0077] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A cell structure of a MOSFET device, characterized in that: include: a substrate comprising opposing first and second surfaces; an epitaxial layer located on the first surface, a surface of the epitaxial layer away from the substrate being a third surface, and the epitaxial layer and the substrate having the same doping type; A cell region is located in a portion of the epitaxial layer close to the third surface, the cell region including a source structure and a gate structure, wherein the source structure and the gate structure are non-linear in a first direction, and the source structure and the gate structure are alternately arranged in a second direction, and the first direction and the second direction are respectively perpendicular to the thickness direction of the substrate. The orthographic projection of the gate structure on the second surface includes a first wide portion and a first narrow portion, the orthographic projection of the source structure on the second surface includes a second wide portion and a second narrow portion, the first wide portion and the first narrow portion are alternately arranged in the first direction, the second wide portion and the second narrow portion are alternately arranged in the first direction, the first wide portion and the second narrow portion are alternately arranged in the second direction, and the second wide portion and the first narrow portion are alternately arranged in the second direction. The cellular region further includes: a first doping region, located on a side of the gate structure close to the substrate, wherein a projection of the first doping region on the substrate overlaps with the first wide portion, and a doping type of the first doping region is different from a doping type of the substrate; The second doping region is located on a side of the source structure close to the substrate, and a projection of the second doping region on the substrate overlaps with the second wide portion. The doping type of the first doping region is different from that of the substrate.

2. The cell structure of the MOSFET device according to claim 1, wherein: The epitaxial layer has a first groove and a second groove; the gate structure is located in the first groove, and the source structure is located in the second groove.

3. The cell structure of the MOSFET device according to claim 2, characterized in that: An included angle between the sidewall of the first groove and the bottom surface of the first groove is 0°~180°, and an included angle between the sidewall of the second groove and the bottom surface of the second groove is 0°~180°.

4. The cell structure of the MOSFET device according to claim 2, characterized in that: The number of the first grooves is 0-3, and the number of the second grooves is 0-4.

5. The cell structure of the MOSFET device according to claim 1, wherein: In the second direction, the distances between any two adjacent source structures and gate structures are equal or unequal.

6. The cell structure of the MOSFET device according to claim 1, characterized in that: In the second direction, a third doping region, a fourth doping region and a fifth doping region are arranged in the epitaxial layer between the first groove and the second groove, the doping type of the third doping region is the same as the doping type of the substrate, the doping type of the fourth doping region and the doping type of the fifth doping region are different from the doping type of the substrate, at least part of the third doping region is located between the source structure and the fifth doping region, and at least part of the fifth doping region is located between the fourth doping region and the second doping region.

7. The cell structure of the MOSFET device according to claim 6, characterized in that: The cellular structure further includes: a sixth doping region located on the side wall of the source structure, wherein the doping type of the sixth doping region is the same as the doping type of the first doping region; in the second direction, part of the sixth doping region is located between the third doping region and the source structure, part of the sixth doping region is located between the fourth doping region and the source structure, and part of the sixth doping region is located between the fifth doping region and the source structure.

8. The cell structure of the MOSFET device according to claim 6, characterized in that: In the thickness direction of the substrate, at least part of the third doping region is located between part of the third surface and the fourth doping region, and at least part of the third doping region is located between part of the third surface and the fifth doping region.

9. The cell structure of the MOSFET device according to claim 6, characterized in that: The cell structure of the MOSFET device further includes: A seventh doping region is located on a side of the fourth doping region away from the third surface and on a side of the fifth doping region away from the third surface, wherein the doping type of the seventh doping region is the same as the doping type of the substrate, the doping concentration of the seventh doping region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the seventh doping region is less than the doping concentration of the third doping region.

10. The cell structure of the MOSFET device according to claim 1, characterized in that: The source structure includes a first metal layer and a second metal layer stacked together. The second metal layer is located on a side of the first metal layer away from the epitaxial layer. The first metal layer forms an ohmic contact with the epitaxial layer.

11. A method for preparing a cell structure of a MOSFET device according to any one of claims 1 to 10, characterized in that: include: providing a substrate comprising a first surface and a second surface that are opposed to each other; forming a preliminary epitaxial layer on one side surface of the substrate, wherein a surface of the preliminary epitaxial layer away from the substrate is a preliminary surface, and a doping type of the preliminary epitaxial layer is the same as a doping type of the substrate; removing a portion of the prepared epitaxial layer, where the remaining prepared epitaxial layer is an epitaxial layer, and a surface of the epitaxial layer away from the substrate is a third surface; A gate structure and a source structure are formed in a portion of the epitaxial layer close to the third surface.

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