A self-aligned process and low-resistance structure of polysilicon gate for silicon carbide planar MOS devices

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a self-aligned polysilicon gate process and low-resistance structure for a silicon carbide planar MOS device. The device comprises a plurality of juxtaposed MOS cells, each comprising a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer. The P well layer in a single MOS cell is aligned with the gate in height and is located on the left and right sides of the gate. The N well layer and the P+ layer are both located above the gate and the P well layer, with the P+ layer located outside the N well layer. The present invention optimizes the conduction path by precisely aligning the P well layer with the gate and placing it on both sides of the gate, combined with a "T"-shaped source design. When a voltage is applied to the gate, vertical channels are formed on both sides of the P well layer, making the path for current flowing from the drain through the N drift layer to the source shorter and more evenly distributed.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a polysilicon gate self-alignment process and a low-resistance structure of a silicon carbide planar MOS device. Background Art

[0002] Silicon carbide (SiC) planar MOS devices offer significant advantages in high-voltage and high-temperature applications due to the material's high breakdown field strength and high thermal conductivity. However, due to SiC's low carrier mobility and traditional process defects, they still face reliability issues caused by excessively high on-resistance (Rdson) and gate-well misalignment. In existing technologies, polysilicon gate structures are prone to uneven channel conduction due to photolithography overlay errors, increasing conduction losses. Furthermore, the source contact design is insufficiently optimized for current spreading, further exacerbating contact resistance.

[0003] An existing patent discloses a low-dislocation-density, high-reliability, high- and low-voltage CMOS self-aligned dual-well process and device (publication number CN113380799A). The method steps include: 1) forming a low-defect-density, high-voltage N-type well and a low-voltage N-type well; 2) forming a self-aligned P-type well; 3) ensuring compatibility with both high and low voltages, and with thick and thin gate oxide structures; and 4) ensuring compatibility with multi-layer metal interconnect structures. This application addresses the high on-resistance and electric field concentration issues unique to silicon carbide MOS devices, which are not addressed in the existing patent. By precisely self-aligning the P-well and gate to form a vertical channel, shortening the current path, and employing a "T"-shaped source design to reduce contact resistance, the application also incorporates a high-resistance N-layer or isolation ring below the gate to optimize the electric field distribution. This synergistically improves the SiC device's current-carrying capacity, withstand voltage reliability, and thermal stability. This addresses the shortcomings of the prior art, which focuses solely on dislocation control in silicon-based CMOS wells and lacks solutions to the core bottlenecks of wide-bandgap semiconductor high-voltage devices. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a polysilicon gate self-alignment process and low-resistance structure for a silicon carbide planar MOS device, which solves the problem of significant electric field concentration below the gate under high-voltage conditions, which restricts the device's voltage resistance and long-term stability.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a polysilicon gate low-resistance structure of a silicon carbide planar MOS device is provided, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer, wherein the height of the P well layer in a single MOS cell is aligned with the gate, and the P well layer is located on the left and right sides of the gate; the N well layer and the P+ layer are both located above the gate and the P well layer, and the P+ layer is located outside the N well layer;

[0006] The cross-sectional profile of the source is in a "T" shape, wherein the source includes a transverse portion and a longitudinal portion, the longitudinal portion is in ohmic contact with the inner side of the N-well layer, and the transverse portion is in ohmic contact with both the N-well layer and the P+ layer.

[0007] Furthermore, a high-resistance N layer is formed inside the N substrate layer and near the N drift layer by ion implantation;

[0008] The high-resistance N layer is located directly below the gate, and the width of the high-resistance N layer is not less than the width of the gate.

[0009] Furthermore, a plurality of isolation rings are formed inside the N substrate layer and near the N drift layer by ion implantation.

[0010] Furthermore, the cross-sectional profile of a single isolation ring is semi-elliptical, and the total width of the plurality of isolation rings does not exceed the width of the gate.

[0011] Furthermore, a doped polysilicon layer is deposited inside the N substrate layer and directly below the gate.

[0012] Furthermore, the width of the doped polysilicon layer is not less than the width of the gate, and the doped polysilicon layer is in ohmic contact with the drain.

[0013] Furthermore, a low-doped N-layer is formed inside the N-drift layer in a single MOS cell by low-concentration ion implantation. The low-doped N-layer is located directly below the gate and divides the N-drift layer in the single MOS cell into two left and right parts.

[0014] A polysilicon gate self-alignment process for a silicon carbide planar MOS device comprises the following steps:

[0015] S1. Growing an N-drift layer outward on the surface of the N substrate layer by chemical vapor deposition;

[0016] S2. Depositing a composite hard mask layer on the surface of the N-drift layer, photolithography is used to define a gate region window, and using the hard mask as a barrier layer, performing an inclined aluminum ion implantation to form a P-well layer;

[0017] S3, photolithography the area just below the gate, and implant low-dose phosphorus ions to form a high-resistance N layer; or photolithography a semi-elliptical window at the edge of the gate, and implant boron ions through multiple energy gradients to form an isolation ring;

[0018] S4, etching the back side of the N substrate to the area directly below the gate, depositing a phosphorus-doped polysilicon layer, and metallizing the back side to form a drain;

[0019] S5. Implanting low-concentration nitrogen ions into the N-drift layer region to form a low-doped N-layer, dividing the N-drift layer into left-right symmetrical regions;

[0020] S6, using the edge of the P-well as an alignment reference, photolithographically define the gate pattern and deposit polysilicon to form the gate, then photolithographically define the N-well region and form an N-well layer by implanting nitrogen ions;

[0021] S7. Etch a deep trench in the semiconductor epitaxial layer to the inner side of the N-well layer, fill it with metal to make ohmic contact with the N-well layer, and extend the filled metal to cover the N-well layer and the outer P+ layer to form a source.

[0022] The present invention provides a self-aligned process for polysilicon gates of silicon carbide planar MOS devices and a low-resistance structure. Compared with the prior art, this method achieves the following effects:

[0023] 1. The present invention optimizes the conduction path by precisely aligning the height of the P-well layer with the gate and placing it on both sides of the gate, combined with a "T"-shaped source design. When voltage is applied to the gate, vertical channels are formed on both sides of the P-well layer, making the path of current flowing from the drain through the N-drift layer to the source shorter and more evenly distributed. In addition, the double contact between the source and the N-well / P+ layer further reduces the contact resistance, thereby significantly reducing the overall on-resistance of the device and improving the current carrying capacity.

[0024] 2. This invention forms a high-resistance N-layer directly beneath the gate by implanting a low dose of phosphorus ions, whose width covers the gate area, or achieves electric field gradient dispersion through a semi-elliptical isolation ring. The high-resistance N-layer modulates the electric field distribution, alleviating electric field concentration below the gate; the isolation ring suppresses the edge electric field peak. Both optimize the electric field distribution, ensuring stable blocking capability under high voltage, while significantly reducing leakage current and improving withstand voltage reliability.

[0025] 3. This invention utilizes a self-aligned process based on the P-well edge to photolithographically define the gate and N-well regions, reducing mask alignment errors. Combining a composite hard mask with tilted P-well implantation and gradient energy implantation using a semi-elliptical isolation ring ensures doping accuracy in critical areas. This design reduces process complexity, improves device parameter consistency, and avoids performance fluctuations caused by misalignment.

[0026] 4. This invention etches the backside of the N-substrate to below the gate and deposits a low-concentration phosphorus-doped polysilicon layer, forming a vertical low-resistance channel with an ohmic contact to the drain. By controlling the doping concentration to increase the resistivity of the polysilicon layer, the current is evenly distributed. This structure significantly reduces the drain series resistance, improving power conversion efficiency while avoiding an increase in cell size.

[0027] 5. This invention forms a low-doped N-layer by injecting low-concentration nitrogen ions into the N-drift layer directly below the gate, symmetrically dividing the drift layer into left and right sections. This layer acts as a current expansion region, weakening carrier mobility and optimizing lateral current distribution. By balancing the electric field and current density within the cell, local hotspot generation is reduced, conduction losses are lowered, and device thermal stability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of Example 1 of the present invention;

[0029] Figure 2 This is a schematic diagram of Example 2 of the present invention;

[0030] Figure 3 This is a schematic diagram of Example 3 of the present invention;

[0031] Figure 4 This is a schematic diagram of Example 4 of the present invention;

[0032] Figure 5 This is a schematic diagram of Example 5 of the present invention;

[0033] Figure 6 It is a schematic diagram of the principle of the present invention.

[0034] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N-well layer; 5. P+ layer; 6. P-well layer; 7. N-substrate layer; 8. N-drift layer; 9. High-resistance N-layer; 10. Isolation ring; 11. Doped polysilicon layer; 12. Low-doped N-layer. DETAILED DESCRIPTION

[0035] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 1 - 6, according to one aspect of the present invention, a process for self-aligning polysilicon gates of a silicon carbide planar MOS device is provided, comprising the following steps:

[0037] Step 1: Chemical vapor deposition (CVD) is used to grow an N-drift layer 8 onto the surface of the N-type substrate layer 7. This low-doped N-drift layer 8 is epitaxially grown on the N-type substrate layer 7, serving as the core region for the device's high-voltage blocking. This allows for precise control of the drift layer's thickness and doping concentration, ensuring a high breakdown voltage (≥1700V) while also providing a flat substrate for subsequent ion implantation.

[0038] Step 2: Deposit a composite hard mask layer on the surface of the N-drift layer 8, photolithographically define the gate region window, and use the hard mask as a barrier to perform tilted aluminum ion implantation to form the P-well layer 6. Deposit a composite hard mask layer on the surface of the N-drift layer 8, photolithographically define the gate region window, and then use the hard mask as a barrier to perform tilted aluminum ion implantation to form the P-well layer 6 symmetrically distributed on both sides of the gate. This tilted implantation achieves self-alignment of the P-well layer 6, avoiding the overlay errors of traditional photolithography. The height of the P-well layer 6 is aligned with the gate 3, optimizing the vertical channel formation path and reducing on-resistance.

[0039] Step 3: Photolithography is performed on the area directly below the gate 3, where a low-dose phosphorus ion implantation is performed to form a high-resistance N-layer 9. Alternatively, a semi-elliptical window is photolithographically formed at the gate edge, where boron ions are implanted multiple times using an energy gradient to form an isolation ring 10. The high-resistance N-layer 9 is formed using an extremely low-dose phosphorus ion implantation. High resistance is the primary design objective, and the phosphorus ion dose must be strictly controlled to the minimum effective level during implantation to maintain low carrier concentration and high resistance.

[0040] Step 4: Etch the backside of the N-substrate 7 to the area directly below the gate 3, deposit a phosphorus-doped polysilicon layer 11, and metallize the backside to form the drain 1. The doped polysilicon layer 11 is doped with a low concentration of phosphorus. This layer is located directly below the gate and forms an ohmic contact with the drain. Reducing the phosphorus doping concentration increases its resistivity, thereby increasing the resistance of the conduction path.

[0041] Step 5: Low-concentration nitrogen ions are implanted into the N-drift layer 8 to form a low-doped N-layer 12, dividing the N-drift layer 8 into bilaterally symmetrical regions. Low-concentration nitrogen ion implantation is required for the low-doped N-layer 12. This divides the N-drift layer into bilaterally symmetrical regions. Nitrogen ion implantation requires maintaining a low concentration (close to the intrinsic doping level) to reduce carrier mobility and increase resistance.

[0042] Step 6: Using the edge of the P-well layer 6 as the alignment reference, photolithography defines the gate 3 pattern and deposits polysilicon to form the gate 3. Then, photolithography defines the N-well region and forms the N-well layer 4 by injecting nitrogen ions. Directly using the edge of the P-well layer 6 as the alignment reference, photolithography the gate pattern, deposit polysilicon to form the gate 3. Then, photolithography injects nitrogen ions to form the N-well layer 6. This eliminates the alignment deviation between the gate and the P-well layer 6, improving process accuracy. The self-aligned design simplifies the process and improves device consistency and yield.

[0043] Step 7: A deep trench is etched into the semiconductor epitaxial layer to the inside of the N-well layer 4. Metal is then filled in to create an ohmic contact with the N-well layer 4. The metal fill extends to cover the N-well layer 4 and the outer P+ layer 5, forming the source 2. A deep trench is then etched into the inside of the N-well layer 4 and filled with metal to form a T-shaped source 2—the longitudinal portion contacts the inner side of the N-well layer 4, while the lateral portion covers the N-well layer 4 and the outer P+ layer 5. The T-shaped structure achieves dual ohmic contact between the N-well and P+ layers, significantly reducing source contact resistance. The deep trench design shortens the lateral current path, enhancing device reliability.

[0044] Example 1

[0045] like Figure 1 、 6 As shown, a polysilicon gate low-resistance structure of a silicon carbide planar MOS device includes a plurality of mutually parallel MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 7, an N drift layer 8, an N well layer 4, a P+ layer 5, and a P well layer 6. The characteristics are as follows: the height of the P well layer 6 in a single MOS cell is aligned with the gate 3, and the P well layer 6 is located on the left and right sides of the gate 3; the N well layer 4 and the P+ layer 5 are both located above the gate 3 and the P well layer 6, and the P+ layer 5 is located outside the N well layer 4; the cross-sectional profile of the source 2 is T-shaped, wherein the source 2 includes a transverse portion and a longitudinal portion. The longitudinal portion is in ohmic contact with the inner side of the N well layer 4, and the transverse portion is in ohmic contact with both the N well layer 4 and the P+ layer 5.

[0046] The working principle of this implementation is: when the drain 1 is connected to the drain voltage, the gate 3 is connected to the gate voltage, and the source 3 is grounded (0V), the gate electric field will exert an electric field force on the P-well layer 6 on the left and right sides, thereby forming a charge channel (such as Figure 6 The black rectangular part in the figure). At this time, a path is formed between the drain 1 and the source 2 (such as Figure 6 movement trajectory of the charges in the molecule).

[0047] By aligning the P-well layer 6 with the gate 3 and placing it on either side of the gate, combined with a T-shaped source 2 design (with its vertical portion contacting the inner side of the N-well layer 4 and its lateral portion covering both the N-well layer and the P+ layer 5), the device conduction path is optimized. When voltage is applied to the gate, a vertical channel forms on either side of the P-well layer, shortening the current path from the drain 1 through the N-drift layer 8 to the source 2 and ensuring a more even distribution. This significantly reduces on-resistance (Rdson) and improves current capability. The dual contact of the source with the N-well / P+ layer reduces contact resistance and enhances device reliability.

[0048] Example 2

[0049] like Figure 2As shown, a high-resistance N layer 9 is formed by ion implantation within the N substrate layer 7 and near the N drift layer 8. This high-resistance N layer 9 is located directly below the gate 3, and its width is no less than that of the gate 3. A low dose of phosphorus ions is implanted into the N substrate layer 7 directly below the gate 3 to form the high-resistance N layer 9, whose width covers the gate region. This layer modulates the electric field distribution, alleviating electric field concentration below the gate. This improves the device breakdown voltage (e.g., ≥1700V) while maintaining low leakage current. The width of the high-resistance layer matches the gate size, avoiding additional cell area.

[0050] Example 3

[0051] like Figure 3 As shown, several isolation rings 10 are formed within the N substrate layer 7 and near the N drift layer 8 through ion implantation. The cross-sectional profile of a single isolation ring 10 is semi-elliptical, and the total width of the multiple isolation rings 10 does not exceed the width of the gate 3. Boron ions are implanted in the N substrate layer 7 below the gate edge to form multiple isolation rings 10 with semi-elliptical cross-sections. The total width is controlled within the gate width. Gradient energy implantation optimizes the depth distribution of the rings to achieve a stepped dispersion of the electric field. This design significantly suppresses the edge electric field peak and improves withstand voltage stability. The semi-elliptical structure maximizes space utilization and avoids device size increase.

[0052] Example 4

[0053] like Figure 4 As shown, a doped polysilicon layer 11 is deposited within the N substrate layer 7, directly beneath the gate 3. The width of the doped polysilicon layer 11 is no less than that of the gate 3, and it forms an ohmic contact with the drain electrode. A phosphorus-doped polysilicon layer 11 is deposited on the backside of the N substrate 7 by etching directly beneath the gate electrode, forming an ohmic contact with the drain electrode, forming a low-resistance vertical current path. This design significantly reduces drain series resistance; the polysilicon layer width matches the gate, ensuring uniform current conduction and improving power conversion efficiency.

[0054] Example 5

[0055] like Figure 5 As shown, low-concentration ion implantation forms a low-doped N-layer 12 within the N-drift layer 8 of a single MOS cell. This low-doped N-layer 12 is located directly beneath the gate 3 and divides the N-drift layer 8 into two sections, left and right. Low-concentration nitrogen ions are implanted into the N-drift layer 8 directly beneath the gate to form the low-doped N-layer 12, symmetrically dividing the drift layer into two sections. This layer serves as a current expansion region, optimizing lateral current distribution. This design balances the electric field and current density within the cell, reducing conduction losses while maintaining high blocking voltage capability and improving device thermal stability.

[0056] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A polysilicon gate low-resistance structure of a silicon carbide planar MOS device, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (7), an N drift layer (8), an N well layer (4), a P+ layer (5) and a P well layer (6), and is characterized in that: The height of the P-well layer (6) in a single MOS cell is aligned with the gate (3), and the P-well layer (6) is located on the left and right sides of the gate (3); the N-well layer (4) and the P+ layer (5) are both located above the gate (3) and the P-well layer (6), and the P+ layer (5) is located outside the N-well layer (4); The cross-sectional profile of the source electrode (2) is in a "T" shape, wherein the source electrode (2) comprises a transverse portion and a longitudinal portion, the longitudinal portion is in ohmic contact with the inner side of the N-well layer (4), and the transverse portion is in ohmic contact with both the N-well layer (4) and the P+ layer (5); Several isolation rings (10) are formed inside the N substrate layer (7) and near the N drift layer (8) by ion implantation; The cross-sectional profile of a single isolation ring (10) is in a semi-elliptical shape, and the total width of a plurality of isolation rings (10) does not exceed the width of the gate (3).

2. The polysilicon gate low resistance structure of a silicon carbide planar MOS device according to claim 1, characterized in that: A high-resistance N layer (9) is formed inside the N substrate layer (7) and near the N drift layer (8) by ion implantation; The high-resistance N layer (9) is located directly below the gate (3), and the width of the high-resistance N layer (9) is not less than the width of the gate (3).

3. The polysilicon gate low resistance structure of a silicon carbide planar MOS device according to claim 1, characterized in that: A doped polysilicon layer (11) is deposited inside the N substrate layer (7) and directly below the gate (3).

4. The polysilicon gate low resistance structure of a silicon carbide planar MOS device according to claim 3, characterized in that: The width of the doped polysilicon layer (11) is not less than the width of the gate (3), and the doped polysilicon layer (11) is in ohmic contact with the drain (1).

5. The polysilicon gate low resistance structure of a silicon carbide planar MOS device according to claim 1, characterized in that: A low-doped N-layer (12) is formed inside the N-drift layer (8) in a single MOS cell by low-concentration ion implantation. The low-doped N-layer (12) is located directly below the gate (3), and the low-doped N-layer (12) divides the N-drift layer (8) in the single MOS cell into two left and right parts.

6. A polysilicon gate self-alignment process for a silicon carbide planar MOS device, characterized in that: The polysilicon gate low resistance structure of the silicon carbide planar MOS device according to any one of claims 1 to 5 is applied, and the polysilicon gate self-alignment process of the silicon carbide planar MOS device comprises the following steps: S1. Growing an N-drift layer (8) on the surface of the N substrate layer (7) by chemical vapor deposition; S2, depositing a composite hard mask layer on the surface of the N-drift layer (8), photolithographically defining a gate region window, using the hard mask as a barrier layer, and performing an inclined aluminum ion implantation to form a P-well layer (6); S3, photolithography the area directly below the gate (3), by implanting low-dose phosphorus ions to form a high-resistance N layer (9); or photolithography a semi-elliptical window at the edge of the gate, and implanting boron ions by multiple energy gradients to form an isolation ring (10); S4, etching the back side of the N substrate layer (7) to the area directly below the gate (3), depositing a phosphorus-doped polysilicon layer (11), and metallizing the back side to form a drain (1); S5, injecting low-concentration nitrogen ions into the N-drift layer (8) region to form a low-doped N-layer (12), dividing the N-drift layer (8) into left-right symmetrical regions; S6, using the edge of the P-well layer (6) as an alignment reference, photolithographically defining the gate (3) pattern and depositing polysilicon to form the gate (3), and then photolithographically defining the N-well region and forming the N-well layer (4) by injecting nitrogen ions; S7. A deep groove is etched in the semiconductor epitaxial layer to the inner side of the N-well layer (4), and a metal is filled to form an ohmic contact with the N-well layer (4). The filled metal extends and covers the N-well layer (4) and the outer P+ layer (5) to form a source (2).

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