Heterogeneous power device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a heterogeneous power device and a preparation method thereof, and the heterogeneous power device comprises a base structure which comprises a substrate layer, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top; and the P-type semiconductor layer is grown on the surface of the second epitaxial layer in a sputtering manner. By selectively etching the P-type semiconductor layer for multiple times, forming the strip-shaped field limiting ring blocks and connecting the field limiting ring blocks, an electric field is more uniform and smoother, the phenomenon of local electric field concentration is avoided, and the electric field intensity peak of the P-type semiconductor layer close to the side edge of the drain electrode or the source electrode is remarkably weakened, so that the voltage endurance capability of the device in an off state is effectively improved; besides, due to the design of the strip-shaped field limiting ring blocks, the coverage area of the P-type semiconductor layer is greatly reduced, the parasitic plate capacitance at a channel is further remarkably reduced, the switching speed of the device is favorably improved, and the reliability of the dynamic characteristic is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a heterojunction power device and a preparation method thereof. Background Art

[0002] In recent years, ultra-wide bandgap semiconductor materials with a bandgap wider than that of SiC and GaN have been regarded as an exciting and challenging new research field due to their superior optical and electrical properties. Among wide bandgap semiconductor materials, Ga2O3 has a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400, which is about 4 times that of GaN and 10 times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have greater research significance and broader market application prospects. Contrary to the ease of n-type doping, there is currently no precedent for successfully achieving p-type doping in Ga2O3, which limits the application of Ga2O3 in bipolar power devices compared to materials that can be bipolar-doped. There are three factors that make it almost impossible to achieve p-type Ga2O3 with hole conduction. First, it is difficult to find acceptor impurities with a small activation energy. Second, theoretical calculations show that the valence band maximum dispersion of Ga2O3 is small and the effective mass is very large, resulting in almost a local distribution of free holes with a small μ. Finally, it has been specifically predicted for Ga2O3 that due to local lattice distortion, the local self-trapping energy of free holes in the volume is very large, which leads to the formation of small polarons, undoubtedly prohibiting the effective conduction of holes.

[0003] In order to realize an enhancement-mode gallium oxide field effect transistor device (GaO FET), there is currently a scheme that uses a p-type NiO cap layer to form a p-NiO / n-GaO heterojunction with the GaO epitaxial channel layer

[0004] pn junction, thereby depleting the carriers on the surface of the GaO epitaxial layer to form a depletion region, so that when the gate voltage is 0, the device is turned off, forming a normally-off device. Although the above basic structure can realize an enhancement-mode GaO FET device in terms of forward conduction function, the blocking voltage withstand is degraded. The reason is that when the gate is turned off and the drain is applied with a high voltage, an electric field spike will appear at the drain side edge of the gate p-NiO cap layer. The electric field spike will increase the gate leakage here, and further lead to thermal breakdown and burnout failure of the device. At the same time, when the gate edge of the device is subjected to long-term high-voltage stress, the defect traps on the passivation layer Al2O3 will capture the hot electrons in the channel region, forming a "virtual gate" at the interface, causing current collapse effect.

[0005] To solve problems similar to the current collapse effect and improve the breakdown voltage of GaO power devices, the prior art proposed a conceptual structure of active passivation, that is, by extending the p-NiO layer to the gate-drain region, a part of the extended p-NiO is physically connected to the gate, and at the same time, the extended p-NiO close to the drain is etched and thinned. In this way, the extended p-NiO can be used as an active field plate structure to replace a part of the previous passivation layer. Since the extended p-NiO active passivation layer has the same potential as the gate, the thermionic emission effect will be weakened in the p-NiO region, thereby weakening the current collapse effect. At the same time, the depletion degree of the p-NiO active field plate at the same voltage is controlled by the thickness of the p-NiO active field plate, that is, the thickness of the p-NiO is controlled to modulate the channel carriers under it, so as to increase the depletion region width and the breakdown voltage.

[0006] However, although the above active passivation structure can improve the current collapse effect caused by thermionic emission, increase the forward conduction characteristics of GaO FET devices, and at the same time, under the condition of blocking breakdown voltage, it can suppress the electric field peak on the gate-drain side, thereby reducing leakage current and improving breakdown voltage. However, the introduction of the active passivation structure reduces the electric field peak at the edge of the drain side of the original p-NiO capping layer. At the same time, since the p-NiO layer extends closer to the drain, a new electric field peak will be re-formed in the p-NiO layer near the drain electrode side. This electric field peak is closer to the drain electrode side where the high voltage is applied, so the electric field peak at this place may be larger, the leakage current of the device at this place is larger, and the probability of breakdown is higher. In addition, the entire area of the p-NiO active layer can be regarded as the upper electrode plate of a parallel-plate capacitor. Since the parallel capacitance value increases with the increase of the area of the parallel electrode plates, the entire p-NiO layer will form a large parasitic parallel-plate capacitor in the active region of the device, which will lead to the degradation of the dynamic reliability of the device. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a heterogeneous power device and its manufacturing method.

[0008] In the first aspect, an embodiment of the present invention provides a heterogeneous power device, which includes:

[0009] A semi-insulating gallium oxide substrate structure, the substrate structure includes a substrate layer, a first epitaxial layer, and a second epitaxial layer arranged in sequence from bottom to top;

[0010] A P-type semiconductor layer, sputter-grown on the surface of the second epitaxial layer;

[0011] A P-type semiconductor guard ring, including a plurality of strip-shaped field guard ring blocks, and adjacent strip-shaped field guard ring blocks are connected by connecting field guard ring blocks; the outermost strip-shaped field guard ring block is electrically connected to the drain electrode or the source electrode through the connecting field guard ring block;

[0012] Among them, both the strip field limiting ring block and the connecting field limiting ring block are obtained by selectively etching a specified area of the P-type semiconductor layer.

[0013] Combined with the first aspect, the heterojunction power device further includes:

[0014] A passivation layer, deposited on the substrate structure and the P-type semiconductor layer, and the material of the passivation layer is one or a combination of aluminum oxide, silicon dioxide, and silicon nitride.

[0015] Combined with the first aspect, the width of the strip field limiting ring block gradually increases along the first direction.

[0016] Combined with the first aspect, the spacing between two adjacent strip field limiting ring blocks gradually increases along the first direction.

[0017] Combined with the first aspect, the material of the P-type semiconductor layer is gallium oxide, gallium nitride, silicon carbide, or other wide bandgap semiconductor materials.

[0018] In a second aspect, the present invention further provides a method for manufacturing a heterojunction power device, the method including:

[0019] Sputtering and growing a P-type semiconductor layer on the substrate structure; wherein, the substrate structure includes a substrate layer, a first epitaxial layer, and a second epitaxial layer sequentially arranged from bottom to top;

[0020] Performing multiple selective etching on the surface of the P-type semiconductor layer to form a plurality of strip field limiting ring blocks and connecting field limiting ring blocks, and connecting the plurality of strip field limiting ring blocks and the connecting field limiting ring blocks to form a P-type semiconductor limiting ring structure;

[0021] Depositing a passivation layer on the surfaces of the P-type semiconductor layer and the substrate structure, and performing local selective etching;

[0022] After depositing a metal stack using an electron beam evaporation process, using a lift-off process to prepare a source electrode, a drain electrode, and a gate electrode;

[0023] Electrically connecting the source electrode or the drain electrode to the outer connecting field limiting ring block.

[0024] Combined with the second aspect, the step of performing multiple selective etching on the surface of the P-type semiconductor layer to form a plurality of strip field limiting ring blocks and forming connecting field limiting ring blocks between the strip field limiting ring blocks includes:

[0025] Performing primary selective etching on the P-type semiconductor layer, and using the P-type semiconductor layer region retained by the etching as a gate cap layer and an active field limiting ring region;

[0026] Performing secondary selective etching on the P-type semiconductor layer, and etching and thinning the P-type semiconductor layer on the gate drain side to obtain a thinning region;

[0027] Perform a third selective etching on the thinning region to form a plurality of strip field limiting ring blocks and for connecting the field limiting ring blocks.

[0028] In combination with the second aspect, connect the field limiting ring block to the source electrode for electrical connection;

[0029] After the steps of performing a first selective etching on the P-type semiconductor layer and using the remaining P-type semiconductor layer region after etching as the gate cap layer and the active field limiting ring region, it further includes:

[0030] Perform a selective etching on the gate cap layer, which can divide the gate cap layer into an upper gate cap and a lower gate cap.

[0031] In combination with the second aspect, the step of performing a third selective etching on the thinning region includes:

[0032] Perform a third selective etching on the thinning region to electrically connect the field limiting ring block on the gate side to the source electrode.

[0033] In combination with the second aspect, the step of performing multiple selective etchings on the surface of the P-type semiconductor layer includes:

[0034] Use photoresist as a mask to expose and open holes in the designated etching region on the P-type semiconductor layer to obtain the corresponding open hole region;

[0035] Etch the open hole region.

[0036] The embodiments of the present invention bring the following beneficial effects: The heterogeneous power device and its manufacturing method provided by the present application, the heterogeneous power device includes: a substrate structure, the substrate structure includes a substrate layer, a first epitaxial layer, and a second epitaxial layer arranged in sequence from bottom to top; a P-type semiconductor layer, sputter-grown on the surface of the second epitaxial layer; a P-type semiconductor field limiting ring, including a plurality of strip field limiting ring blocks, and adjacent two strip field limiting ring blocks are connected by a connecting field limiting ring block; the outermost strip field limiting ring block is electrically connected to the drain or the source through the connecting field limiting ring block; wherein, the strip field limiting ring and the connecting field limiting ring block are both obtained by selectively etching the designated region of the P-type semiconductor layer.

[0037] Through multiple selective etching of the P-type semiconductor layer, the present technical solution forms strip field limiting ring blocks and connecting field limiting ring blocks, making the electric field more uniform and smooth, avoiding the phenomenon of local electric field concentration, significantly weakening the electric field intensity peaks at the edges of the P-type semiconductor layer near the drain electrode or the source electrode, and thus effectively improving the breakdown voltage capability of the device in the off state; in addition, the design of the strip field limiting ring blocks greatly reduces the coverage area of the P-type semiconductor layer, and further significantly reduces the parasitic planar capacitance at the channel, which helps to improve the switching speed of the device and enhances the reliability of the dynamic characteristics. In this way, not only the problem of electric field concentration caused by the traditional block-shaped P-type semiconductor layer is solved, but also the parasitic capacitance is effectively reduced, thereby improving the breakdown voltage capability and dynamic characteristics of the device at the same time.

[0038] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures particularly pointed out in the specification, claims, and drawings.

[0039] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, is described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 Schematic structural diagram of a heterojunction power device provided by an embodiment of the present invention;

[0042] Figure 2 Schematic front view of the structure of sputter-growing a P-type semiconductor layer on a substrate during the preparation of a heterojunction power device provided by an embodiment of the present invention;

[0043] Figure 3 For Figure 2 Schematic front view of the structure after the first selective etching of the P-type semiconductor layer in;

[0044] Figure 4 For Figure 3 Schematic front view of the structure after the second selective etching of the P-type semiconductor layer in;

[0045] Figure 5 For Figure 4The front view schematic diagram of the structure after the third selective etching of the P-type semiconductor layer in

[0046] Figure 6 For Figure 5 The front view schematic diagram of the structure obtained after depositing a passivation layer on the structure shown in

[0047] Figure 7 For Figure 6 The front view schematic diagram of the heterojunction power device obtained after electron beam evaporation of glass on the structure shown in

[0048] Figure 8 For Figure 1 The top view schematic diagram of the structure of the heterojunction power device provided in

[0049] Figure 9 The top view schematic diagram of the structure of another heterojunction power device provided by the embodiment of the present invention

[0050] Figure 10 The top view schematic diagram of the heterojunction power device provided by the embodiment of the present invention, in which the field limiting ring block is electrically connected to the source electrode

[0051] Figure 11 The flow schematic diagram of the preparation method of the heterojunction power device provided by the embodiment of the present invention

[0052] Reference numerals:

[0053] 1 - Substrate structure, 11 - Substrate layer, 12 - First epitaxial layer, 13 - Second epitaxial layer, 2 - P-type semiconductor layer, 3 - P-type semiconductor limiting ring, 31 - Strip-shaped field limiting ring block, 32 - Connecting field limiting ring block, 4 - Passivation layer. Detailed implementation manners

[0054] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] To facilitate the understanding of this embodiment, the technical terms designed in this application will be briefly introduced below.

[0056] The bandgap refers to the energy difference between the bottom of the conduction band and the top of the valence band in semiconductors or insulators in solid-state physics. This energy difference determines the minimum energy required for electrons to transition from the valence band to the conduction band. The bandgap is an important property of materials and directly affects their optical and electrical properties. A larger bandgap enables devices to be applied in many extremely harsh environments: in the context of geothermal energy production and oil and gas extraction, higher drilling speeds and lower failure rates can be achieved; at high temperatures, the operating temperatures of aluminum plants, steel plants, and coal-fired and gas-fired power plants controlled by electronic sensors can be higher, thereby improving the energy efficiency of these industrial processes. In power switch applications, the Baliga's figure-of-merit (BFOM) is an indicator used to represent the suitability of semiconductor materials in power electronics, and it is expressed as: BFOM = εμE 3 , where ε is the dielectric constant, μ is the mobility, and E is the breakdown electric field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap Eg. Therefore, a larger bandgap means that wide-bandgap semiconductors have lower power losses and higher conversion efficiencies in the application of power devices, thus achieving more excellent and ideal power electronics applications.

[0057] After introducing the technical terms involved in this application, next, a brief introduction to the application scenarios and design concepts of the embodiments of this application will be given.

[0058] Currently, other p-type semiconductor materials (such as p-type NiO / CuO, etc.) have been used to replace p-type gallium oxide. In particular, p-type NiO materials are combined with n-type GaO to form structures such as p-NiO / n-GaO heterojunctions (HJD) and p-NiO rings. Due to the advantageous material properties of gallium oxide, it has excellent properties such as a large bandgap and a high critical breakdown electric field. Therefore, using gallium oxide materials to manufacture power devices has excellent performance such as high blocking voltage, high operating temperature, and low leakage current. The gallium oxide heterojunction field-effect transistor (FET) combines the excellent material properties of gallium oxide and the high-voltage withstand electrical characteristics of FET devices, designs and manufactures gallium oxide heterojunction transistors that can carry high voltages or extra-high voltages, and enables them to be applied in fields such as extra-high voltage direct current transmission, smart grids, and pulsed power with high voltage and high current, showing great potential in the next generation of high-voltage and high-power applications.

[0059] Based on this, the embodiments of this application provide a heterojunction power device and a preparation method thereof.

[0060] Embodiment 1

[0061] This application provides a heterojunction power device, as shown in combination with Figure 1 , the heterojunction power device includes: a substrate structure 1, a p-type semiconductor layer 2, and a p-type semiconductor guard ring 3.

[0062] The base structure 1 includes a substrate layer 11, a first epitaxial layer 12, and a second epitaxial layer 13 arranged in sequence from bottom to top.

[0063] The P-type semiconductor layer 2 is sputter-grown on the surface of the second epitaxial layer 13.

[0064] The P-type semiconductor guard ring 3 includes a plurality of strip field limiting ring blocks 31 (FLR-Bar), and adjacent two strip field limiting ring blocks 31 (FLR-Bar) are connected by a connecting field limiting ring block 32 (Link-Bar); the outermost strip field limiting ring block 31 (FLR-Bar) is electrically connected to the drain electrode or the source electrode through the connecting field limiting ring block 32 (Link-Bar).

[0065] Among them, both the strip field limiting ring block 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) are obtained by selectively etching a specified area of the P-type semiconductor layer 2.

[0066] In this application, by selectively etching the P-type semiconductor layer 2 multiple times, the strip field limiting ring block 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) are formed, making the electric field more uniform and smooth, avoiding the phenomenon of local electric field concentration, significantly weakening the electric field intensity peak at the edge of the P-type semiconductor layer 2 near the drain electrode or the source electrode, thereby effectively improving the breakdown voltage capability of the device in the off state; in addition, the design of the strip field limiting ring block 31 is formed by selectively etching the P-type semiconductor layer 2, greatly reducing the coverage area of the P-type semiconductor layer 2, and then significantly reducing the parasitic planar capacitance at the channel, which helps to improve the switching speed of the device and enhances the reliability of the dynamic characteristics.

[0067] Among them, the number, width, the spacing between adjacent two strip field limiting ring blocks 31 (FLR-Bar) of the strip field limiting ring block 31 (FLR-Bar) (named FLR-Bar in this embodiment), and the number, setting position, and arrangement rule of the connecting field limiting ring block 32 (Link-Bar) (named Link-Bar in this embodiment) can all be adjusted according to requirements. The figure is only an example, and both the strip field limiting ring block 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) are obtained by selectively etching the P-type semiconductor layer 2. Therefore, the strip field limiting ring block 31 (FLR-Bar), the connecting field limiting ring block 32 (Link-Bar), and the P-type semiconductor layer 2 are substantially an integral structure.

[0068] When the buffer layer 11 is a semi-insulating gallium oxide layer, the first epitaxial layer 12 is a UID layer (unintentionally doped layer), the second epitaxial layer 13 is a channel layer, and the material of the P-type semiconductor layer 2 is P-type NiO. In particular, when the buffer layer 11 is a semi-insulating gallium nitride layer, the first epitaxial layer 12 is a GaN channel layer, the second epitaxial layer 13 is an AlGaN barrier layer, and the material of the P-type semiconductor layer 2 is P-type GaN. Among them, the AlGaN barrier layer is an alloy material composed of aluminum and gallium nitride, which grows on the GaN channel layer. Due to the bandgap difference between AlGaN and GaN, a quantum well will be formed at their interface. This quantum well can confine the movement of electrons, making them concentrate near the interface to form a two-dimensional electron gas (2DEG) with a high density. The 2DEG has extremely high mobility, enabling the device to operate efficiently under high-frequency and high-power conditions, thus achieving high electron mobility and low resistance characteristics.

[0069] During the preparation process, first, the first epitaxial layer 12 and the second epitaxial layer 13 are epitaxially grown on the surface of the buffer layer 11 to form the substrate structure 1, and then the P-type semiconductor layer 2 (as Figure 2 shown) is sputter-grown on the surface of the substrate structure 1. Subsequently, the sputter-grown P-type semiconductor layer 2 is subjected to a first selective etching, and the remaining P-type semiconductor layer 2 is used as the area of the gate cap layer and the active field limiting ring (as Figure 3 shown). Subsequently, the P-type semiconductor layer 2 is subjected to a second selective etching to thin the specified area (as Figure 4 shown). Subsequently, a third selective etching is performed on the thinned specified area as Figure 4 shown to obtain a structure in which the strip field limiting ring block 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) are interconnected (as Figure 5 shown).

[0070] It can be understood that the strip field limiting ring block 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) are obtained by selectively etching the P-type semiconductor layer 2. The space surrounded by two adjacent strip field limiting ring blocks 31 (FLR-Bar) and the connecting field limiting ring block 32 (Link-Bar) is obtained by completely etching away the P-type semiconductor layer 2 at that place. Since the P-type semiconductor layer 2 sputter-grown on the substrate structure 1 at that place is completely etched away, the substrate structure 1 located below can be seen at this space from a top view (as Figure 6 shown).

[0071] Combined with the first aspect, the heterogenous power device further includes: a passivation layer 4.

[0072] The passivation layer 4, which is deposited on the substrate structure 1 and the P-type semiconductor layer 2, is made of one or a combination of alumina, silicon dioxide, and silicon nitride.

[0073] After obtaining the structure shown in Figure 5 through multiple selective etching processes, the passivation layer 4 is deposited. Since the sputter-grown P-type semiconductor layer 2 has undergone multiple selective etching processes, the P-type semiconductor layer 2 in the gate-source side and some areas within the P-type semiconductor guard ring 3 has been etched away. Therefore, when the passivation layer 4 is deposited, this part of the area is deposited on the substrate structure 1; while the unetched P-type semiconductor layer 2 is deposited on the P-type semiconductor layer 2 when the passivation layer 4 is deposited (as shown in Figure 7 ).

[0074] Subsequently, local selective etching of the passivation layer 4 is carried out, and Ti / Au and Ni / Au evaporation are sequentially performed using an electron beam, and a lift-off process is used to fabricate the source electrode ( Figure 8 denoted as S in Figure 8 ), the drain electrode ( Figure 8 denoted as D in Figure 1 ), and the gate electrode ( Figure 8 denoted as G in Figure 1 ), such that the outermost strip-shaped field limit ring block 31 (FLR-Bar) is electrically connected to the drain electrode (D) or the source electrode (S) through the connecting field limit ring block 32 (Link-Bar) (as shown in Figure 1 ); when it needs to be electrically connected to the source electrode (S) to be consistent with the source potential, first, the area corresponding to the gate electrode (S) is etched and divided during the first selective etching process for thinning the P-type semiconductor layer 2, and then it is electrically connected to the source electrode when the P-type semiconductor guard ring 3 is formed during the third selective etching process.

[0075] Among them, the P-type semiconductor layer 2 can be P-type nickel oxide, P-type gallium nitride, etc. As shown in Figure 1 , the P-type semiconductor layer 2 can be P-type NiO, and the material of the passivation layer 4 is AL2O3.

[0076] As another implementable method, the P-type semiconductor layer 2 can be P-type GaN, and the material of the passivation layer 4 is SiN. At this time, the first epitaxial layer 12 is a GaN channel layer, and the second epitaxial layer 13 is an AlGaN barrier layer, forming a high electron mobility transistor (HEMT). Its principle has been described above and will not be elaborated here.

[0077] It can be understood that in the present application, the width of the strip field limiting ring block 31 (FLR-Bar) and the spacing between two adjacent strip field limiting ring blocks 31 (FLR-Bar) can be adjusted and prepared according to actual requirements, which are not limited herein. In addition, the number and setting positions of the connecting field limiting ring blocks 32 (Link-Bar) between two adjacent strip field limiting ring blocks 31 (FLR-Bar) can also be adjusted and prepared according to actual requirements. They can be arranged at intervals in the first direction (i.e., on the same horizontal line), or can be staggered in the second direction and arranged in a set shape (such as a wavy shape), which are not limited herein. Combining Figure 9 As shown, an example is provided where the connecting field limiting ring blocks 32 (Link-Bar) are arranged at intervals in the first direction (the horizontal direction shown in the figure) and at intervals in the second direction (the height direction perpendicular to the horizontal direction in the figure).

[0078] Combining with the first aspect, the width of the strip field limiting ring block 31 (FLR-Bar) gradually increases in the first direction.

[0079] Combining with the first aspect, the spacing between two adjacent strip field limiting ring blocks 31 (FLR-Bar) gradually increases in the first direction.

[0080] It can be understood that for the convenience of preparation, the width of the strip field limiting ring block 31 (FLR-Bar) and the spacing between two adjacent strip field limiting ring blocks 31 (FLR-Bar) can be increased regularly and continuously. The electric field distributions are coupled with each other, making the electric field distribution smoother and more uniform, and better achieving the purpose of reducing the surface electric field peak. In addition, through such a setting, it is also beneficial to the performance detection under different widths and spacings, without having to detect multiple devices simultaneously, saving the detection cost and improving the detection efficiency.

[0081] Combining with the first aspect, the material of the P-type semiconductor layer 2 is one of gallium oxide, gallium nitride, and silicon carbide.

[0082] The P-type semiconductor layer 2 can also be other wide-bandgap semiconductor materials. Wide-bandgap semiconductor materials refer to semiconductor materials with a bandgap width greater than or equal to 2.3 electron volts. Due to their unique physical properties, such as high breakdown electric field, high thermal conductivity, high saturated electron drift velocity, and radiation resistance, etc., these materials have broad application prospects in high-temperature, high-frequency, high-efficiency electronic devices and power devices, such as silicon carbide (SiC), gallium oxide (Ga O), etc.

[0083] In the second aspect, the present application also provides a preparation method for a heterojunction power device. Combining Figure 11 As shown, the method includes:

[0084] S110, sputter-grow a P-type semiconductor layer on a substrate structure; wherein, the substrate structure includes a substrate layer, a first epitaxial layer, and a second epitaxial layer which are sequentially arranged from bottom to top.

[0085] S120, perform multiple selective etching on the surface of the P-type semiconductor layer to form multiple strip field limiting ring blocks and connecting field limiting ring blocks, and the multiple strip field limiting ring blocks are connected to the connecting field limiting ring blocks to form a P-type semiconductor limiting ring structure.

[0086] S130, deposit a passivation layer on the surfaces of the P-type semiconductor layer and the substrate structure, and perform local selective etching.

[0087] S140, after depositing a metal stack using an electron beam evaporation process, prepare source electrodes, drain electrodes, and gate electrodes using a lift-off process.

[0088] S150, electrically connect a source electrode or a drain electrode to an outer connecting field limiting ring block.

[0089] In this embodiment, by performing multiple selective etching on the P-type semiconductor layer 2 grown by magnetron sputtering, a P-type semiconductor limiting ring 3 structure including multiple strip field limiting ring blocks 31 (FLR-Bar) and multiple connecting field limiting ring blocks 32 (Link-Bar) is formed. Subsequently, after depositing the passivation layer 4 and performing electron beam evaporation and metal stack, source electrodes, drain electrodes, and gate electrodes are prepared by performing a lift-off process, and a source electrode or a drain electrode is electrically connected to the connecting field limiting ring block 32 (Link-Bar) according to actual needs. Since the connecting field limiting ring block 32 (Link-Bar) and the strip field limiting ring block 31 (FLR-Bar) are connected to each other and form an integral structure, electrical conduction is transmitted to the strip field limiting ring block 31 (FLR-Bar), making the electric potential similar at the connection between the P-type semiconductor limiting ring 3 and the drain electrode or the gate electrode, making the electric field more uniform and smooth, avoiding the phenomenon of local electric field concentration, significantly weakening the electric field intensity peak at the contact between the P-type semiconductor limiting ring 3 and the drain electrode or the gate electrode, thereby effectively improving the breakdown voltage withstand ability of the device in the off state; in addition, the design of the strip field limiting ring block 31 (FLR-Bar) greatly reduces the coverage area of the P-type semiconductor layer 2, thereby significantly reducing the parasitic parallel-plate capacitance at the channel, contributing to improving the switching speed of the device, and enhancing the reliability of the dynamic characteristics.

[0090] Combined with the second aspect, step S120 includes:

[0091] S121, perform primary selective etching on the P-type semiconductor layer, and use the etched and reserved P-type semiconductor layer region as a gate cap layer and an active field limiting ring region.

[0092] S122, perform secondary selective etching on the P-type semiconductor layer, and etch and thin the P-type semiconductor layer on the drain side of the gate to obtain a thinned region.

[0093] S123, perform a third selective etching on the thinned region to form a plurality of strip field limiting ring blocks and for connecting the field limiting ring blocks.

[0094] In step S110, in combination with Figure 2 As shown, at room temperature, with a radio frequency power of 150 W, a volume ratio of inert gas (such as argon) to oxygen of 20:1, and a gas pressure of 0.5 - 0.8 Pa, a P-type semiconductor layer 2 (in this embodiment, the material for preparing the P-type semiconductor layer 2 is P-NiO) is magnetron sputtered and grown on the substrate structure 1.

[0095] Subsequently, in step S121, based on the preset source electrode position, gate electrode position, and drain electrode position, a primary selective etching is performed on the P-type semiconductor layer 2 to etch and combine the regions corresponding to the source electrode and the drain electrode Figure 3 As shown.

[0096] Subsequently, in step S122, a second selective etching is performed on the P-type semiconductor layer 2 to thin the P-type semiconductor layer 2 in the corresponding region between the gate electrode and the drain electrode, in combination with Figure 3 As shown.

[0097] After that, in step S123, a third selective etching is performed on the thinned P-type semiconductor layer 2 according to the preset P-type semiconductor field limiting ring 3 structure, so as to obtain a P-type semiconductor field limiting ring 3 structure with a specified structure.

[0098] After obtaining the P-type semiconductor field limiting ring 3 structure, a passivation layer 4 is deposited, electron beam evaporation and stripping are performed to electrically connect the source electrode (S) or the drain electrode (D) to the P-type semiconductor field limiting ring 3 structure, forming a heterogeneous power device with a distributed field limiting ring (FLR) cross-connected active field plate.

[0099] In combination with Figure 1 As shown, the connecting field limiting ring block 32 (Link-Bar) of the P-type semiconductor field limiting ring 3 structure is connected to the drain electrode (D). In combination with Figure 10 As shown, the connecting field limiting ring block 32 (Link-Bar) of the P-type semiconductor field limiting ring 3 structure is connected to the source electrode (S).

[0100] Combined with the second aspect, the connecting field limiting ring block 32 (Link-Bar) is electrically connected to the source electrode (S). After step S121, it further includes:

[0101] S124, perform a selective etching on the gate cap layer, and the gate cap layer can be divided into an upper gate cap and a lower gate cap.

[0102] It can be understood that after the initial selective etching of the P-type semiconductor layer 2 in step S121, the remaining area of the P-type semiconductor layer 2 after etching serves as the gate cap layer and the active field limiting ring area, and this area is closer to the drain electrode (D) and farther from the source electrode (S).

[0103] If it is necessary to maintain the potential close to the source electrode (S) at this time, the connection field limiting ring block 32 (Link-Bar) on the side close to the source electrode (S) should be electrically connected to the source electrode (S) at this time. At this time, the gate cap layer is etched and divided to leave a blank area for the connection field limiting ring block 32 (Link-Bar) to pass through until it is connected to the source electrode (S), as shown in Figure 10 shown.

[0104] Combined with the second aspect, step S123 includes:

[0105] S1231, perform a third selective etching on the thinning area to electrically connect the connection field limiting ring block on the gate side to the source electrode.

[0106] Afterwards, since the gate is separated in step S124, the incomplete depletion of electrons under the P-type semiconductor layer 2 (the p-NiO layer in combination with the above example) may cause the device to be a depletion-type device. Therefore, after depositing the passivation layer 4 in the subsequent process to cover the Link-Bar that passes through the gate electrode (G) and connects to the source electrode (S), a p-NiO layer is regrown above the area without the p-NiO layer by using the lift-off process (as shown in the above figure). In this way, all the carriers under the device gate electrode (G) can be depleted to form an enhancement-type device.

[0107] The steps of performing multiple selective etching on the surface of the P-type semiconductor layer 2 in step S120 include:

[0108] S1200, use photoresist as a mask to expose and open holes in the designated etching area on the P-type semiconductor layer 2 to obtain the corresponding open hole area.

[0109] S1201, etch the open hole area.

[0110] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0111] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0112] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0113] Finally, it should be noted that the above embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting them. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A heterogeneous power device, characterized in that, The heterogeneous power device includes: A substrate structure, which includes a substrate layer, a first epitaxial layer, and a second epitaxial layer arranged in sequence from bottom to top; A P-type semiconductor layer, sputter-grown on the surface of the second epitaxial layer; A P-type semiconductor guard ring, which includes a plurality of strip field guard ring blocks, and adjacent two of the strip field guard ring blocks are connected by a connecting field guard ring block; the outermost strip field guard ring block is electrically connected to a drain electrode or a source electrode through the connecting field guard ring block; Wherein, both the strip field guard ring block and the connecting field guard ring block are obtained by selectively etching a specified area of the P-type semiconductor layer.

2. The heterogeneous power device according to claim 1, wherein, The heterogeneous power device further includes: A passivation layer, deposited on the substrate structure and the P-type semiconductor layer, and the material of the passivation layer is one or a combination of alumina, silica, and silicon nitride.

3. The heterogeneous power device according to claim 1, characterized in that, The width of the strip field guard ring block gradually increases along a first direction.

4. The heterogeneous power device according to claim 1, characterized in that, The spacing between adjacent two of the strip field guard ring blocks gradually increases along the first direction.

5. The heterogeneous power device according to claim 1, characterized in that, The material of the P-type semiconductor layer is gallium oxide, gallium nitride, or silicon carbide.

6. A method for preparing a heterogeneous power device, characterized in that, The method includes: Sputter-growing a P-type semiconductor layer on a substrate structure; wherein, the substrate structure includes a substrate layer, a first epitaxial layer, and a second epitaxial layer arranged in sequence from bottom to top; Performing multiple selective etching on the surface of the P-type semiconductor layer to form a plurality of strip field guard ring blocks and connecting field guard ring blocks, and the plurality of strip field guard ring blocks and the connecting field guard ring blocks are connected to form a P-type semiconductor guard ring structure; Depositing a passivation layer on the surface of the P-type semiconductor layer and the substrate structure, and performing local selective etching; After depositing a metal stack using an electron beam evaporation process, using a lift-off process to prepare a source electrode, a drain electrode, and a gate electrode; Electrically connecting the source electrode or the drain electrode to the outermost connecting field guard ring block.

7. The method according to claim 6, characterized in that, The step of performing multiple selective etching on the surface of the P-type semiconductor layer to form a plurality of strip field guard ring blocks and form connecting field guard ring blocks between the strip field guard ring blocks includes: Performing primary selective etching on the P-type semiconductor layer, and taking the P-type semiconductor layer region retained by the etching as a gate cap layer and an active field guard ring region; Performing secondary selective etching on the P-type semiconductor layer, and etching and thinning the P-type semiconductor layer on the gate drain side to obtain a thinned region; Performing tertiary selective etching on the thinned region to form a plurality of strip field guard ring blocks and connecting field guard ring blocks.

8. The method according to claim 7, wherein The connecting field guard ring block is electrically connected to the source electrode; After the step of performing primary selective etching on the P-type semiconductor layer and taking the P-type semiconductor layer region retained by the etching as a gate cap layer and an active field guard ring region, further includes: Performing selective etching on the gate cap layer to divide the gate cap layer into an upper gate cap and a lower gate cap.

9. The method according to claim 7, wherein The step of performing tertiary selective etching on the thinned region includes: Performing tertiary selective etching on the thinned region to electrically connect the connecting field guard ring block on the gate side to the source electrode.

10. The method according to claim 6, wherein The step of performing multiple selective etching on the surface of the P-type semiconductor layer includes: Using photoresist as a mask, the designated etched area on the P-type semiconductor layer is exposed to form an opening, resulting in a corresponding opening area; Etch the opening area.

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