Method for improving threshold voltage uniformity of non-self-aligned CMOS (complementary metal oxide semiconductor) tube

Abstract

The invention discloses a method for improving threshold voltage uniformity of a non-self-aligned CMOS (complementary metal oxide semiconductor) tube, which comprises the following steps of: providing a substrate in which a well region is formed; performing a first ion implantation process to form two lightly doped drain regions arranged at an interval in the well region, and defining a region between the two lightly doped drain regions as an effective channel region; performing a second ion implantation process to form an auxiliary doped region on one side, close to the effective channel region, of each lightly doped drain region; forming a gate structure on the substrate, wherein the gate structure is located above the effective channel region; wherein in the second ion implantation process, the ion implantation dose is smaller than that of the first ion implantation process, and the ion implantation type is opposite to that of the first ion implantation process. According to the scheme, the threshold voltage uniformity of the CMOS device is improved.

Description

Technical Field

[0001] This application relates to the technical field of transistor manufacturing, and more particularly to a method for improving the threshold voltage uniformity of non-self-aligned CMOS transistors. Background Art

[0002] During the production of 55nm node embedded 5V CMOS devices, due to considerations of polysilicon thickness and device HCl (Hot Carrier Lifetime), only the LDD (Lightly Doped Drain) non-self-aligned process can be used.

[0003] As shown in the CMOS device structure in Figure 1 , the effective channel of the device is defined by the LDD region, that is, the critical dimension of the LDD directly affects the effective channel length of the actual device. For device competitiveness, the device size will be made as small as possible. When the device size is reduced to the limit, there will be obvious short-channel effects. A few nanometers of LDD critical dimension difference may lead to a threshold voltage difference of more than 20mV, which results in poor threshold voltage uniformity of CMOS devices in the 55nm node non-self-aligned CMOS process. Summary of the Invention

[0004] This application provides a method for improving the threshold voltage uniformity of non-self-aligned CMOS transistors, which can solve the problem of poor threshold voltage uniformity of CMOS devices in related technologies.

[0005] An embodiment of this application provides a method for improving the threshold voltage uniformity of non-self-aligned CMOS transistors, including: Providing a substrate in which a well region is formed; Performing a first ion implantation process to form two lightly doped drain regions with a spacing in the well region, and the region between the two lightly doped drain regions is defined as an effective channel region; Performing a second ion implantation process to form an auxiliary doping region on one side of each lightly doped drain region close to the effective channel region; Forming a gate structure on the substrate, and the gate structure is located above the effective channel region; Wherein, in the second ion implantation process, the ion implantation dose is less than that of the first ion implantation process, and the ion implantation type is opposite to that of the first ion implantation process.

[0006] In some embodiments, the ion doping type of the well region is opposite to that of the lightly doped drain region.

[0007] In some embodiments, in the second ion implantation process, the implantation angle is greater than that of the first ion implantation process.

[0008] In some embodiments, in the step of performing the first ion implantation process, the ion implantation dose is 3e13 - 7e13 / , and in the step of performing the second ion implantation process, the ion implantation dose is 1e12 - 5e12 / .

[0009] In some embodiments, in the step of performing the first ion implantation process, the implantation angle is 30 - 45°, and in the step of performing the second ion implantation process, the implantation angle is 45°.

[0010] The technical solution of the present application has at least the following advantages: 1. By forming an auxiliary doping region with an opposite ion doping type on one side of the lightly doped drain region close to the effective channel region, when the critical dimension of the lightly doped drain region is too large, that is, the width of the lightly doped drain region is too large and the effective channel region is too short, since the auxiliary doping region is closer to the carrier channel, the short-channel effect can be suppressed; when the critical dimension of the lightly doped drain region is too small, that is, the width of the lightly doped drain region is too small and the effective channel region is too long, the auxiliary doping region is far from the carrier channel and has little influence on the threshold voltage, thereby improving the threshold voltage uniformity of the CMOS device. Description of the Drawings

[0011] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 is a schematic diagram of the existing CMOS device structure in the background art of the present application; Figure 2 is a flowchart of a method for improving the threshold voltage uniformity of a non-self-aligned CMOS transistor provided by an exemplary embodiment of the present application; Figures 3 to 6 is a schematic diagram of a device for embodying the execution process of a method for improving the threshold voltage uniformity of a non-self-aligned CMOS transistor provided by an exemplary embodiment of the present application.

[0013] Explanation of the reference numerals: 1, well region; 2, gate structure; 3, lightly doped drain region; 4, auxiliary doping region. Detailed Embodiments

[0014] The technical solutions in the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0015] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0016] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0017] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0018] The present application provides a method for improving the threshold voltage uniformity of non-self-aligned CMOS transistors. Referring to Figure 2 , the method includes the following steps: S10: Provide a substrate in which a well region is formed.

[0019] Exemplarily, a substrate is provided. Referring to Figure 3 , a well region 1 is formed in the substrate.

[0020] S21: Perform a first ion implantation process to form two lightly doped drain regions with a spacing in the well region. The region between the two lightly doped drain regions is defined as the effective channel region.

[0021] Exemplarily, referring to Figure 4 , a first mask can be covered on the substrate, and then a first ion implantation process is performed on the well region 1, so as to form in the well region 1 as Figure 5Two spaced-apart lightly doped drain regions 3 are shown. The ion doping type of the lightly doped drain region 3 is opposite to that of the well region 1. For example, when the doping type of the well region 1 is N-type, the ion doping type of the formed lightly doped drain region 3 is P-type; when the doping type of the well region 1 is P-type, the ion doping type of the formed lightly doped drain region 3 is N-type. Among them, the region between the two lightly doped drain regions 3 is defined as the effective channel region.

[0022] S22: Perform a second ion implantation process to form an auxiliary doping region on one side of each lightly doped drain region close to the effective channel region.

[0023] It should be noted that the order of this step and step S21 is not fixed, that is, the first ion implantation process can be performed first, and then the second ion implantation process, or the second ion implantation process can be performed first, and then the first ion implantation process. In this step, referring to Figure 5 , the first mask is also used as a mask to perform a second ion implantation process on the well region 1. Among them, during the second ion implantation process, the ion implantation dose is less than that of the first ion implantation process, and the ion implantation type is opposite to that of the first ion implantation process. Within the range of the lightly doped drain region 3, the ions implanted in the second ion implantation process are directly covered by the ions implanted in the first ion implantation process. At the same time, when performing the second ion implantation process, the implantation angle is greater than that of the first ion implantation process, as shown in Figure 4 and Figure 5 , so that the lateral diffusion of the ions implanted in the second ion implantation process is faster, and thus an auxiliary doping region 4 as shown in Figure 6 is formed in the effective channel region. Among them, the ion doping type of the auxiliary doping region 4 is opposite to that of the lightly doped drain region 3. For example, when the ions implanted in the first ion implantation process are P-type ions, such as B, BF2, etc., then the ions implanted in the second ion implantation process are N-type ions, such as P, As, etc., and vice versa.

[0024] When the critical dimension of the lightly doped drain region 3 is large, that is, the width of the lightly doped drain region 3 is large and the effective channel region is short, since the auxiliary doping region 4 is closer to the carrier channel, the short-channel effect can be suppressed. When the critical dimension of the lightly doped drain region 3 is small, that is, the width of the lightly doped drain region 3 is small and the effective channel region is long, the auxiliary doping region 4 is far from the carrier channel and has little effect on the threshold voltage.

[0025] Further, in one embodiment, in the step of performing the first ion implantation process, the implanted ions are P, and the ion implantation dose is 3e13~7e13 / , in the step of performing the second ion implantation process, the implanted ions are B, and the ion implantation dose is 1e12~5e12 / Meanwhile, in this embodiment, in the step of performing the first ion implantation process, the implantation angle is 30 to 45°, and in the step of performing the second ion implantation process, the implantation angle is 45°, thereby forming an N-type lightly doped drain region 3 and a P-type auxiliary doped region 4.

[0026] S30: Form a gate structure on the substrate, and the gate structure is located above the effective channel region.

[0027] Exemplarily, referring to Figure 6 , a gate structure 2 is formed on the substrate, and the gate structure 2 is located above the effective channel region. Meanwhile, a part of the lightly doped drain region 3 is located below the gate structure 2.

[0028] The method for improving the threshold voltage uniformity of a non-self-aligned CMOS transistor provided by the embodiment of the present application forms an auxiliary doped region with an opposite ion doping type on one side of the lightly doped drain region close to the effective channel region. When the critical dimension of the lightly doped drain region is too large, that is, the width of the lightly doped drain region is too large and the effective channel region is too short, since the auxiliary doped region is closer to the carrier channel, the short-channel effect can be suppressed; when the critical dimension of the lightly doped drain region is too small, that is, the width of the lightly doped drain region is too small and the effective channel region is too long, the auxiliary doped region is far from the carrier channel and has little influence on the threshold voltage, thereby improving the threshold voltage uniformity of the CMOS device.

[0029] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A method for improving the threshold voltage uniformity of non-self-aligned CMOS transistors, characterized in that Including: Providing a substrate, in which a well region is formed; Performing a first ion implantation process to form two lightly doped drain regions with a spaced arrangement in the well region, and a region between the two lightly doped drain regions is defined as an effective channel region; Performing a second ion implantation process to form an auxiliary doping region on one side of each lightly doped drain region close to the effective channel region; Forming a gate structure on the substrate, and the gate structure is located above the effective channel region; Wherein, in the second ion implantation process, the ion implantation dose is less than that in the first ion implantation process, and the ion implantation type is opposite to that in the first ion implantation process.

2. The method according to claim 1, wherein The ion doping type of the well region is opposite to the ion doping type of the lightly doped drain region.

3. The method according to claim 1, characterized in that, In the second ion implantation process, the implantation angle is greater than that in the first ion implantation process.

4. The method according to claim 1, wherein In the step of performing the first ion implantation process, the ion implantation dose is 3e13~7e13 / , in the step of performing the second ion implantation process, the ion implantation dose is 1e12~5e12 / .

5. The method according to claim 3, wherein In the step of performing the first ion implantation process, the implantation angle is 30° to 45°, and in the step of performing the second ion implantation process, the implantation angle is 45°.

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