Side wall transistor forming method and semiconductor device

Abstract

The invention provides a side wall transistor forming method, which comprises the following steps of: etching a semiconductor substrate according to a preset hard mask layer to form a cantilever structure; when the side wall transistor is formed on the cantilever structure, first dielectric layers are formed on the two sides of the cantilever structure; etching and lowering the channel of the side wall transistor and the first dielectric layer around the source and drain regions to a preset depth, and exposing a part of the cantilever structure; and according to a preset transistor well injection photomask, carrying out ion injection with a preset doping concentration in the channel to enable the channel to float so as to reduce the coupling capacitance of the source electrode and the drain electrode. According to the invention, a high-speed sidewall transistor, a photodiode and other trench-compatible devices can be formed at the same time; the size of the side wall transistor can be freely adjusted to meet the design requirements of different circuits. Meanwhile, the method is low in process cost and has a relatively high process window.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for forming a sidewall transistor and a semiconductor device. Background Art

[0002] With the development of image sensors, the functions of images are becoming more and more abundant, and the performance requirements for image sensors, such as the power consumption and speed of digital circuits, are also getting higher and higher. There are mainly two directions for the conventional method of improving the speed of digital circuit transistors. One is to shorten the length of the transistors, but this requires a more difficult process node technology, which will also bring serious leakage problems and increase the static power consumption. The other is to increase the saturation mobility speed of carriers. This solution often requires the introduction of new materials and has a high process difficulty.

[0003] To solve this problem, in the prior art, there is a scheme of forming a sidewall transistor on a cantilever between photodiodes while forming the photodiodes of an image sensor by a self-alignment method. This scheme can form a sidewall transistor with high transconductance performance, but since its source and drain have a certain contact with the gate, the coupling capacitance is relatively large and the cut-off frequency is not high enough, resulting in a slow circuit speed. This kind of transistor can meet the requirements when used in analog circuits, but it will still slow down the circuit speed when used in digital circuits. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for forming a sidewall transistor, including: Etching a semiconductor substrate according to a preset hard mask layer to form a cantilever structure; When forming the sidewall transistor on the cantilever structure, forming a first dielectric layer on both sides of the cantilever structure; Etching to reduce the first dielectric layer around the channel of the sidewall transistor and the source and drain regions to a preset depth, and exposing part of the cantilever structure; Performing ion implantation with a preset doping concentration in the channel according to a preset transistor well implantation mask to float the channel, so as to reduce the coupling capacitance between the source and the drain.

[0005] Further, after performing the ion implantation with a preset doping concentration in the channel, it further includes: Removing the hard mask layer; Forming a gate oxide layer on the surface of the exposed part of the cantilever structure; Filling a polycrystalline semiconductor material according to a gate formation mask to form the gate of the sidewall transistor.

[0006] Further, after forming the gate of the sidewall transistor, it further includes: Ion implantation with a preset inclination angle is performed on the source and drain regions to compensate for the doping concentration and form the sidewall transistor.

[0007] Further, when forming the cantilever structure, when forming the first trench, it further includes: Forming a second dielectric layer in the first trench; Filling a polycrystalline semiconductor material in the second dielectric layer to form a pinned layer gate; Performing a re-etching on the pinned layer gate and filling a dielectric to cover the pinned layer gate to form the first dielectric layer.

[0008] Further, the etching of the semiconductor substrate includes: Etching the semiconductor substrate according to the hard mask layer to form a second trench; Forming a third dielectric layer on the surface of the second trench; Etching the bottom of the third dielectric layer and the semiconductor substrate to form a third trench; Performing a lateral etching on the third trench and using the third dielectric layer for protection to form the cantilever structure.

[0009] Further, the depth of the second trench does not exceed a preset depth to facilitate the floating of the channel.

[0010] Further, the sidewall transistor is disposed in the pixel unit region of the image sensor. Before forming the second dielectric layer, it further includes: forming an epitaxial layer on the surface of the first trench by an epitaxial process, and the epitaxial layer at least includes a part with a doping type opposite to that of the semiconductor substrate to form a lateral PN junction structure.

[0011] Further, the forming of the epitaxial layer on the surface of the first trench by the epitaxial process includes: Epitaxially growing an intrinsic semiconductor material on the surface of the first trench to form a first sub-epitaxial layer; Epitaxially growing a semiconductor material with a doping type opposite to that of the semiconductor substrate on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer.

[0012] The present invention also provides a semiconductor device, including a sidewall transistor device formed by using the sidewall transistor forming method as described above.

[0013] Through the above solution, the present invention provides a new method for forming a sidewall transistor and a semiconductor device. By designing the photomask pattern, a high-speed sidewall transistor, a photodiode, and other trench-compatible devices can be formed simultaneously in the present invention; the size of the sidewall transistor can be freely adjusted through the process and the layout size to meet the design requirements of different circuits. At the same time, the process involved in the present invention does not add extra photomasks, has a low process cost, and the photomask pattern involved is simple, with a relatively high process window. Description of the Drawings

[0014] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Figure 1 It is a schematic diagram of the photomask pattern during the process of forming a sidewall transistor in different embodiments of the present invention; Figures 2 to 9 It is a schematic structural diagram during the process of forming a sidewall transistor in different embodiments of the present invention. In the figures, throughout the different views, the same or similar reference numerals denote the same or similar devices (modules) or steps. Embodiment

[0015] The object of the present invention is to provide a method for forming a sidewall transistor.

[0016] As Figure 1 shown, in the present invention, a trench formation photomask A, a transistor formation photomask B, a gate etching photomask C, and a source and drain region D during doping ion implantation can be provided.

[0017] Specifically, the method for forming a sidewall transistor in the present invention includes the following steps: Step S100: According to a preset hard mask layer 200 (which can be formed according to the trench formation photomask A), etch the semiconductor substrate 100 to form a cantilever structure 110, as Figures 2 to 4 shown; Step S200: When forming the sidewall transistor (SWT) on the cantilever structure 110, form a first dielectric layer 111 on both sides of the cantilever structure 110. For example, an oxide can be used as the first dielectric layer 111; Step S300: Etch and reduce the first dielectric layer 111 around the channel of the sidewall transistor (SWT) and the source and drain regions to a preset depth, and expose part of the cantilever structure 110; Step S400: According to a preset transistor well implantation photomask (which can be adopted as Figure 1The transistor shown forms a photomask B), and ion implantation with a preset doping concentration is performed in the channel to float the channel, so as to reduce the coupling capacitance between the source and the drain.

[0018] In this solution, by sinking the dielectric layer around the source and the drain, when forming the transistor well ion implantation, anti-punchthrough ion implantation with a relatively high concentration is performed on the entire channel including the regions where the source and the drain are located; when performing the ion implantation of the source and the drain themselves, the well ion implantation doping of the source and the drain regions is compensated back. Since the concentration of the well implantation is generally 2 to 3 orders of magnitude lower than that of the ion implantation of the source and the drain, it will not affect the source and the drain. Since the lower part of the cantilever structure 110 is suspended, and the relatively thick oxide layer is adjacent to the lower part of the cantilever structure 110, the channel of this sidewall transistor (SWT) is basically floating, so the coupling capacitances with the source and the drain are very small, thereby the cut-off frequency can be increased and the speed can be further improved.

[0019] Further, while forming the cantilever structure 110 in step S100, a first trench 113 is formed. Preferably, the first trench 113 can be formed by etching. For example, the semiconductor substrate 100 can be etched to form island-like structures arranged in an array, and the island-like structures are separated by the first trench 113. By different process methods during etching, the cantilever structure 110 can be formed.

[0020] In an alternative embodiment, the cantilever structure 110 and the first trench 113 can be formed in step S100 through the following steps: Step S121: According to the hard mask layer 200, the semiconductor substrate 100 is etched to form a second trench 120, as Figure 2 shown. Optionally, the depth of the second trench 120 does not exceed a preset depth to facilitate floating the channel. The depth of the second trench 120 determines the height of the transistor. Preferably, it can be etched shallower to simplify the process difficulty; Step S122: As Figure 2 shown, a third dielectric layer 121 is formed on the surface of the second trench 120; Step S123: The bottom of the third dielectric layer 121 and the semiconductor substrate 100 are etched to form a third trench 130, as Figure 3 shown; Step S124: The third trench 130 is laterally etched, and the third dielectric layer 121 is used for protection to form the cantilever structure 110, as Figure 4 shown.

[0021] After forming the first trench 113, in step S200, the first dielectric layer 111 can be formed through the following steps: Step S111: Form a second dielectric layer 114 in the first trench 113, as Figure 5 shown; Step S112: Fill the second dielectric layer 114 with a polycrystalline semiconductor material to form a pinned layer gate 115, as Figure 5 shown; Step S113: Perform etch-back on the pinned layer gate 115 and fill the dielectric to cover the pinned layer gate 115, thereby forming the first dielectric layer 111, as Figure 6 shown.

[0022] After that, step S300 can be performed to etch the first dielectric layer 111 around the channel of the sidewall transistor (SWT) and the source and drain regions to a preset depth and expose part of the cantilever structure 110, as Figure 7 shown.

[0023] Further, after performing ion implantation with a preset doping concentration in the channel in step S400, it further includes: Step S510: Remove the hard mask layer 200; Step S520: Form a gate oxide layer 112 on the surface of the exposed part of the cantilever structure 110, as Figure 8 shown; Step S530: According to the gate formation photomask C (as Figure 1 shown), fill the polycrystalline semiconductor material to form the gate 300 of the sidewall transistor (SWT), as Figure 9 shown.

[0024] On this basis, after step S530, it further includes: Step S540: Perform ion implantation with a preset tilt angle on the source and drain regions D (as Figure 1 shown) to compensate the doping concentration and form the sidewall transistor (SWT).

[0025] In an alternative embodiment, the sidewall transistor (SWT) is disposed in the pixel unit region of the image sensor. Before forming the second dielectric layer 114 in the foregoing step S111, it further includes: Step S130: Form an epitaxial layer 140 (not shown in the figure) on the surface of the first trench 113 through an epitaxial process. The epitaxial layer 140 at least includes a part with a doping type opposite to that of the semiconductor substrate 100, thereby forming a lateral PN junction structure. For example, for an N-type doped semiconductor substrate 100, a P-type doped epitaxial layer 140 can be formed to form the photosensitive region of the image sensor.

[0026] In an alternative embodiment, in step S130, the epitaxial layer 140 can be formed in the following manner: Step S131: Epitaxially grow an intrinsic semiconductor material on the surface of the first trench 113 through an epitaxial process to form a first sub-epitaxial layer 141 (not shown in the figure); Step S132: Epitaxially grow a semiconductor material with a doping type opposite to that of the semiconductor substrate 100 on the surface of the first sub-epitaxial layer 141 to form a second sub-epitaxial layer 142 (not shown in the figure).

[0027] In the above manner, a lateral P-I-N junction structure is formed, and the intrinsic semiconductor layer can play a buffering role.

[0028] The present invention also provides a semiconductor device, including a sidewall transistor device formed by using the sidewall transistor forming method as described above.

[0029] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. In addition, obviously, the word "including" does not exclude other elements and steps, and the word "a" does not exclude a plurality. A plurality of elements stated in the apparatus claims can also be implemented by one element. Words such as first, second, etc. are used to indicate names and do not indicate any specific order.

Claims

1. A method for forming a sidewall transistor, characterized in that Including: Etch a semiconductor substrate according to a preset hard mask layer to form a cantilever structure; When forming the sidewall transistor on the cantilever structure, form a first dielectric layer on both sides of the cantilever structure; Etch and reduce the first dielectric layer around the channel of the sidewall transistor and the source and drain regions to a preset depth, and expose part of the cantilever structure; According to a preset transistor well implantation mask, perform ion implantation with a preset doping concentration in the channel to float the channel, so as to reduce the coupling capacitance between the source and the drain.

2. The method for forming a sidewall transistor according to claim 1, wherein After performing ion implantation with a preset doping concentration in the channel, it further includes: Remove the hard mask layer; Form a gate oxide layer on the surface of the exposed part of the cantilever structure; According to a gate formation mask, fill with a polycrystalline semiconductor material to form the gate of the sidewall transistor.

3. The method for forming a sidewall transistor according to claim 2, wherein After forming the gate of the sidewall transistor, it further includes: Perform ion implantation with a preset tilt angle on the source and drain regions to compensate the doping concentration and form the sidewall transistor.

4. The method for forming a sidewall transistor according to claim 1, wherein It also includes: When forming the cantilever structure, form a first trench; Form a second dielectric layer in the first trench; Fill the second dielectric layer with a polycrystalline semiconductor material to form a pinned layer gate; Perform re-etching on the pinned layer gate and fill the dielectric to cover the pinned layer gate to form the first dielectric layer.

5. The method for forming a sidewall transistor according to claim 4, wherein The etching of the semiconductor substrate includes: Etch the semiconductor substrate according to the hard mask layer to form a second trench; Form a third dielectric layer on the surface of the second trench; Etch the bottom of the third dielectric layer and the semiconductor substrate to form a third trench; Perform lateral etching on the third trench and use the third dielectric layer for protection to form the cantilever structure.

6. The method for forming a sidewall transistor according to claim 5, wherein The depth of the second trench does not exceed a preset depth to facilitate floating the channel.

7. The method for forming a sidewall transistor according to claim 4, wherein The sidewall transistor is disposed in the pixel unit region of an image sensor. Before forming the second dielectric layer, it further includes: forming an epitaxial layer on the surface of the first trench through an epitaxial process, and the epitaxial layer at least includes a part with a doping type opposite to that of the semiconductor substrate to form a lateral PN junction structure.

8. The method for forming a sidewall transistor according to claim 7, wherein, The forming of the epitaxial layer on the surface of the first trench through the epitaxial process includes: Epitaxially grow an intrinsic semiconductor material on the surface of the first trench through an epitaxial process to form a first sub-epitaxial layer; Epitaxially grow a semiconductor material with a doping type opposite to that of the semiconductor substrate on the surface of the first sub-epitaxial layer to form a second sub-epitaxial layer.

9. A semiconductor device, characterized in that, Including a sidewall transistor device formed by using the sidewall transistor forming method as described in claims 1 to 8.

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