Low temperature compatible hermetic package for superconducting quantum chips

Abstract

The invention discloses a packaging structure (100) for a superconducting quantum processing unit (110). The package structure comprises a ceramic support portion (101) for supporting a quantum processing unit (110), the support portion (101) comprising a plurality of electrical connections (104) for connecting the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic package structure (100). In addition, the invention discloses a packaged quantum processing unit and a method for packaging the quantum processing unit by using the packaging structure.

Description

Technical Field

[0001] The present invention generally relates to materials science. In particular, the present invention relates to ceramic-based materials suitable for various solutions in cryogenic environments and superconducting applications such as quantum information processing and quantum hardware. Background Art

[0002] The core of a superconducting QPU is a silicon or sapphire chip with a qubit structure made of superconducting metal on top. In a large QPU, the qubits will be arranged in a two-dimensional lattice. To route control signals to the middle of the lattice, wires need to be introduced from a direction perpendicular to the plane.

[0003] The wiring solution needs to meet several criteria simultaneously, including: high bandwidth (for some signals), controlled impedance, low crosstalk, low dissipation, low microwave loss, shielding of qubit circuits from lossy materials, tight pitch compatible with the QPU unit cell and the number of signals per unit cell, high reliability, and the ability to replace the QPU.

[0004] Ceramic technology is well-known as a packaging solution for semiconductor wafers, such as a solution using a silicon substrate and multilayer wiring with a planarized dielectric material. Summary of the Invention

[0005] This summary of the invention is provided to introduce a series of concepts that are further described below in the detailed description in a simplified form. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The object of the present invention is to provide a novel material comprising ceramic and metal components, which provides superconducting properties in a functional ceramic substrate. The material can be manufactured using known manufacturing methods, for example, by using a low-temperature co-fired ceramic (LTCC) green sheet or green body sheet or other substrates, depositing a mixture of a suitable metal and, for example, a polymer carrier as a layer thereon, and then pre-firing or drying; forming a functionalized layer on top of the pre-fired green body sheet as needed, including, for example, physical two-dimensional or three-dimensional structures such as perforations, cavities, lines, etc., and finally pressing and firing to achieve a functionalized multilayer structure, which can be used as a component for several different purposes, as described below. This type of material has many beneficial properties, including high stiffness, conductivity, a thermal expansion coefficient suitable for various applications, airtightness (due to the glassy composition after firing), and processability, to name just a few. It can also be conveniently used as a base layer or an intermediate layer for various purposes.

[0006] This solution meets all the engineering standards disclosed in the background art, while being relatively inexpensive and scalable to large substrate sizes (up to 6" or 15.24 cm) and a large number of wiring layers (up to 38 layers) using off-the-shelf processes. Note that compression springs require a large amount of force (typically 10 grams per contact), and a ceramic layer is required to avoid excessive bending of the chip stack, which would compromise the usability of the QPU and superconducting chips.

[0007] The problems solved by the present invention include:

[0008] - Vertical transfer of signals and signal fan-out from a dense pitch silicon TSV pad array to a conventional PCB

[0009] - Proposing a material with a CTE closer to silicon rather than a conventional PCB

[0010] - Higher signal-to-signal isolation than SiO2 / Si multilayer wiring

[0011] - The stiffness of the rigid ceramic stack may allow for a reusable package using compression spring contacts and easy sample replacement, enabling high-throughput good sample discovery.

[0012] The proposed technical solution and possible alternatives include a ceramic-based multi-layer (possibly 30 to 50 layers) interposer with indium-based solder contacts or spring contacts.

[0013] Thus, a first aspect of the present invention relates to a packaging structure for a superconducting quantum processing unit. The packaging structure includes a ceramic support portion for supporting the quantum processing unit, the support portion including a plurality of electrical connectors for connecting the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic packaging structure.

[0014] A second aspect of the present invention relates to a packaged quantum processing unit, the packaged quantum processing unit including a packaging structure and a quantum processing unit.

[0015] The packaging structure may further include one or more sidewalls enclosing the plurality of electrical connectors in at least two dimensions, and the space enclosed by the one or more sidewalls may be configured to accommodate the quantum processing unit. The one or more sidewalls may be formed of a ceramic material.

[0016] The packaging structure may further include a lid configured to enclose the plurality of electrical connectors such that the support portion, the one or more sidewalls, and the lid form a cavity configured to accommodate the quantum processing unit and enclosed in three dimensions. The lid may also be formed of a ceramic material. Alternatively, the lid may be formed of a metal material.

[0017] One or more of the support portion, the sidewalls, and the lid may be formed of a ceramic material that includes one or more superconducting material layers or superconducting material traces either within the ceramic material or on the surface of the ceramic material. Thus, the ceramic material includes a superconducting metal layer. The ceramic material may be a low-temperature co-fired ceramic or a high-temperature co-fired ceramic.

[0018] A ceramic material that includes one or more superconducting material layers or superconducting material traces may shield the cavity from external electric and magnetic fields.

[0019] The encapsulation structure may further include one or more of activated carbon, getters, and molecular sieves.

[0020] The plurality of electrical connectors of the support portion may extend in one direction by at least 50 mm.

[0021] At 1 K and 300 K, the thermal expansion coefficient of the ceramic support portion may be within ±50% of the thermal expansion coefficient of silicon.

[0022] The cavity may be airtight. The cavity may be under vacuum or filled with an inert gas.

[0023] The inert gas may be helium, which is configured to form a superfluid when the encapsulated quantum processing unit is cooled to low temperatures.

[0024] A third aspect of the present invention relates to a method of manufacturing an encapsulated quantum processing unit. The method includes: inserting a quantum processing unit into an encapsulation structure that includes a ceramic support portion for supporting the quantum processing unit; and connecting the quantum processing unit to a plurality of electrical connectors located on the support portion, the plurality of electrical connectors being configured to connect the quantum processing unit to a plurality of electrical contacts on the outer surface of the ceramic encapsulation structure.

[0025] The encapsulation structure may further include one or more sidewalls that enclose the plurality of electrical connectors in at least two dimensions, and the space enclosed by the one or more sidewalls is configured to accommodate the quantum processing unit.

[0026] The method may further include enclosing the quantum processing unit within the encapsulation structure by sealing the enclosed space with a lid.

[0027] The lid and the one or more sidewalls may form an airtight seal around the quantum processing unit. Enclosing the quantum processing unit may be performed in a vacuum or an inert gas environment (e.g., helium). Description of the Drawings

[0028] Figure 1 Depicts a conventional manufacturing method for a ceramic functional layer.

[0029] Figure 2Depicts a schematic QPU or chip stack with an interposer layer made of superconducting material.

[0030] Figure 3 Depicts a packaging structure for a superconducting quantum processing unit.

[0031] Figure 4 Depicts Figure 3 a cross-section of the packaging structure of

[0032] Figure 5 Depicts Figure 3 the underside of the packaging structure of

[0033] Figure 6 Depicts a method for packaging a superconducting quantum processing unit. Detailed Description

[0034] The present invention includes the general idea of using ceramic materials as components in chips (such as superconducting chips including at least one QPU), similar to conventional semiconductor chips on printed circuit boards. Since ceramic materials can be made superconducting as described above, they are particularly suitable for superconductors, for example, in quantum computers with quantum processing units (QPU). Herein, "superconducting ceramic" means a ceramic material with one or more superconducting material layers or superconducting material traces inside or on the surface of the ceramic material.

[0035] In essence, ceramic materials can be made superconducting by including suitable superconducting (metal) materials in their composition, for example, by introducing superconducting materials into the slurry coating the LTCC green body substrate material or sheet, and manufacturing a ceramic multi-layer structure via conventional manufacturing methods known in the art (see Figure 1 ). For example, introducing metal materials onto a green sheet with a suitable binder component (such as a polymer) in the slurry, and firing the resulting composition to provide a single superconducting ceramic material body. The superconducting material can be, for example, aluminum-based, or can contain niobium, molybdenum, or tungsten. In particular, the latter two may be suitable due to their high melting points. Such composed ceramic materials or even ceramic materials with suitable metal layers provide a low-loss wiring structure within the chip layer (such as the interposer layer in a chip stack) made of the material. The superconducting ceramic material is amorphous and has almost no resonance. As an alternative to LTCC, high-temperature co-fired ceramics (HTCC) can be used, as well as tungsten, molybdenum, niobium (e.g., niobium nitride), and / or titanium (e.g., titanium nitride)-based metal pastes or slurries.

[0036] The resulting superconducting ceramic material can be freely modified, for example, by machining it into the desired shape or structure, having cavities, wiring channels (vertical or horizontal), inlays, or any other suitable structure in, on, or through the material layer. In one embodiment, the niobium-based superconducting ceramic material is used for various superconducting applications. For example, it is fully compatible with any currently known flip-chip configuration, and many more configurations can be envisioned. Aluminum nitrate is also a possible superconducting component that can be used. A printed circuit board made of the superconducting ceramic material according to the present invention can be used as a base layer for a superconducting chip stack that includes a large number of qubits on a QPU layer, because a relatively large PCB can be fabricated due to the stiffness of the ceramic material. In this way, a QPU stack including >1000 qubits can be fabricated.

[0037] The ceramic material can be used as an interposer layer in a superconducting QPU stack (see Figure 2 ) to provide structural integrity to a stack including a dielectric insulating layer on top of the QPU and the printed circuit board (PCB). Control lines for transmitting signals and the required electrical components can be embedded in or pass through the ceramic interposer layer bonded to the QPU chip layer, for example, by indium bumps, as known in flip-chip type QPUs according to the prior art. According to the present invention, by using so-called vias, multiple electronic lines can pass through the ceramic interposer layer, similar to a common silicon chip layer, where silicon crystal vias are used for this purpose without compromising the structural integrity of the ceramic interposer layer. Thereafter, the stacks of different layers can be pressed together to form a stacked superconducting element or chip by pressing on the ceramic interposer layer rather than on the fragile QPU or flip-chip layer. In PCT, thermal connectors or equivalents can be used to route control lines outside the chip stack. Thus, the stacks can be aligned and pressed together to connect to the thermal connector pins without damaging the structurally fragile parts or layers of the stack. The ceramic interposer layer can also be used to transmit signals via lines embedded in the lateral direction of the interposer layer. Thus, in essence, the ceramic interposer layer can be a functional structure rather than a mechanical structure.

[0038] Alternatively or additionally, the chip stack is a wiring stack that has spring contact pins ("spring pins" or "pogo pins") at one interface in the stack and indium or cryogenic solder contacts at another interface in the stack, and the ceramic layer is used to route electrical signals between the two interfaces.

[0039] An interposer stack such as Figure 2As shown. The components from top to bottom are as follows. 1) QPU chip ("QPU" in the sketch). 2) First interposer ("I.P."), i.e., a silicon chip with through-silicon vias, with superconducting patterned metallization on both sides. 3) Ceramic wiring layer ("Ceramic"). 4) Second interposer ("I.P2") 5) Conventional printed circuit board ("PCB"). The electrical contacts at the QPU-I.P. and Ceramic-I.P. interfaces are implemented as indium or low-temperature solder balls or bumps. The electrical contacts between the ceramic layer and the PCB layer are implemented as compression springs embedded in IP2. The ceramic layer is pressed down by an annular clamp (using F-type clamp force) not shown.

[0040] Multiple variations are possible. The PCB layer can be replaced by a block with coaxial wires terminated therein (similar to the ArdentTR interface). The compression springs can be conventional solder joints.

[0041] Superconducting ceramic materials can also be used in ceramic-based high-density microwave connector applications, such as for guiding signals from a room-temperature environment to a cryostat or between different temperature zones of a cryostat.

[0042] Superconducting ceramic materials enable a significant reduction in the size of the connector. For example, in a connector that is equivalent in size to an Ardent connector, hundreds of lines can be implemented instead of the 24 lines of an Ardent connector. In Figure 4 an exemplary construction of such a connector according to the present invention is presented. The exemplary construction includes processing the above superconducting ceramic materials into appropriate shapes and sizes to allow use with different multi-wire connector solutions. In a specific embodiment, commercially available nano-scale or pico-scale coaxial cables are used to connect the signal lines to the connector. Such cables can be arranged in a 50×50 or 100×100 lateral structure, and the cables implement signal lines traveling to and from different temperature zones of the cryostat all the way to the QPU, and alternatively or additionally, provide signal lines traveling from the cryostat to the room-temperature environment. This will significantly reduce the space occupied by wiring and cable laying and also reduce the thermal load from the signal lines.

[0043] The above connector can be used as a cryogenic alternator between different temperature zones of a cryostat, enabling efficient signal transmission through the wires implemented using connectors based on superconducting ceramic materials.

[0044] Superconducting ceramic materials can also be used in feedthrough vacuum-sealed connectors or in ultra-high vacuum coaxial high-density microwave feedthroughs for feeding control signals into and out of a cryostat.

[0045] As Figure 5As depicted in FIGS. 1 to 7, superconducting ceramic materials can also be used in the controlled encapsulation of the vacuum environment of the QPU. For example, a suitable gas can be introduced into the cavity surrounding the QPU to prevent the oxidation and degradation of the QPU structure over time.

[0046] In Figure 3 this is presented in an exemplary manner. Figure 4 is Figure 3 a cross-section of the encapsulation shown. Figure 5 Shows Figure 5 and Figure 6 the underside of the encapsulation. Encapsulation 101 includes: a support portion (base layer) 101 that is machined to form a suitable cavity for the QPU 110 together with a lid (top layer) 103; and a channel 104 for control lines that is coated with or filled with metal to control the environment within the QPU cavity. The channel 104 is connected to electrical contacts 108 on the outer surface of the encapsulation (as Figure 5 shown), and forms an electrical connection (and optionally a thermal connection) between the outside and inside of the encapsulation 100.

[0047] The QPU cavity is further defined by one or more sidewalls 102 that enclose the electrical connection / channel 104 in at least two dimensions, that is, if the surface of the support portion 101 on which the QPU 110 is supported defines the X-Y plane, the sidewalls enclose the cavity at least in the X dimension and the Y dimension. The lid 103 closes the cavity in the Z direction. When the lid 103 is integrally formed with one or more sidewalls, it can be said that the cavity is also enclosed by the sidewalls in the Z dimension.

[0048] The space (i.e., the cavity) enclosed by the sidewalls 102 and the lid 103 is configured to accommodate the QPU 110. The sidewalls 102, the lid 103, and the support portion 101 can form an airtight seal around a cavity suitable for forming and supporting a vacuum. Herein, according to MIL-STD-750E test method 1071.9 or MIL-STD-883H test method 1014.13, an airtight seal can be defined as a seal having a leakage rate of at most 1×10 -8 cc / s.

[0049] The sidewalls 102 and / or the lid 103 can also be formed of the superconducting ceramic material described above with respect to Figure 1 In the case where the ceramic material is a superconducting ceramic material, the encapsulation 100 can provide an almost completely isolated electromagnetic environment within the cavity. Alternatively, the sidewalls 102 and / or the lid 103 can also be formed of a metallic material, which can form a Faraday shielding layer around the cavity to block high-frequency electromagnetic fields even if the metallic material does not have superconductivity.

[0050] The cavity can also be connected to an ion pump, a cryopump, or other vacuum pumps, which are used to form and / or maintain a vacuum within the cavity. Accordingly, appropriate channels 107 are provided in the support portion 101 (as Figure 4 depicted), or the sidewall 102, or the lid 103, for connecting the cavity to the vacuum pump. Alternatively or additionally, a vacuum can be formed within the cavity of the package 100 before sealing the cavity with the lid 103.

[0051] Alternatively, the cavity can be filled with an inert gas. Using an inert gas within the cavity can allow for greater heat dissipation from the QPU and a more uniform heat distribution within the cavity. In one example, the inert gas can be helium. The helium within the cavity forms a superfluid under the cryogenic conditions of QPU operation. As a superfluid, the helium within the cavity coats the QPU and the inner wall of the cavity, thereby allowing for excellent heat distribution and heat dissipation within the cavity.

[0052] The package 100 can include sorption elements 105, 106, such as one or more of the following: adsorbent elements (e.g., activated carbon, zeolite), absorbent elements (e.g., palladium or palladium composites), and molecular sieves for adsorbing harmful substances having a size smaller than a specific molecular size. In this context, a "harmful" substance is one whose presence within the package results in a reduction in QPU performance, e.g., due to a shortening of the qubit decoherence time. Additionally, control lines can be used to equalize the temperature within the package. Using one or more sorption elements 105, 106 within the package can also enable the vacuum within the cavity to be maintained for a longer period, even though small molecules inevitably penetrate into the cavity.

[0053] The package 100 can also be used as a tool for high-throughput testing of QPUs without the sidewall 102 or the lid 103. In particular, the physical properties of the ceramic support portion 101 enable a fixture (such as the Figure 2 F-type fixture shown) to be used to apply a large force on the support portion (labeled "ceramic") and press a temporary connector (such as a pogo pin arranged in a land grid array on "I.P.2") against the electrical connectors on the lower side of the support portion 101. This would not be possible for a conventional silicon substrate because the force required to compress a large number (e.g., hundreds) of these temporary connectors to form a reliable electrical connection would cause the silicon to break. Thus, using a ceramic material for the support portion 101 enables the QPU located on the support portion 101 to be quickly and easily inserted into and removed from the test environment.

[0054] The encapsulation 100 of the present invention is particularly effective in minimizing the degradation of the QPU and the sensitive components (such as Josephson junctions) that make it up. When the QPU is exposed to moisture, atmosphere, and repeated thermal cycles, the performance of its QPU (e.g., qubit coherence time) will decline. The encapsulation 100 protects the QPU from the main sources of pollution (i.e., hydrogen, oxygen, and moisture). In addition, many ceramic materials have a coefficient of thermal expansion (CTE) (i.e., from 0K to 300K) in the relevant temperature range that is close to that of silicon (a common substrate for superconducting quantum processing units). This is important for large enclosures and large QPUs, such as those where the connectors between the QPU and the encapsulation support portion 101 span at least 50 mm in at least one dimension, because the relative movement of the contacts on the QPU and the corresponding contacts on the support portion 101 under thermal cycling, i.e., the temperature change from room temperature to cryogenic temperature, increases with the increase in the size of the QPU. The large relative movement between the QPU and the support portion causes the electrical connectors between the QPU and the support portion to degrade and eventually break. In this context, a "closely matched" CTE means that the CTE of the ceramic material is ±50% of the CTE of silicon at 1K and 300K.

[0055] The present invention also includes a method of manufacturing an encapsulated quantum processing unit. Figure 6 The method 200 depicted in

[0056] At step 801, a quantum processing unit is inserted into an encapsulation structure that includes a ceramic support portion for supporting the quantum processing unit, such as as described above with respect to Figure 5 FIGS. 1 to 7.

[0057] At step 802, the quantum processing unit is connected to a plurality of electrical connectors located on the support portion, such as Figure 5 the electrical connectors 104 shown in FIGS. 1 to 7. The electrical connectors are configured to connect the quantum processing unit to a plurality of electrical contacts on the outer surface of the ceramic encapsulation structure, such as Figure 5 the electrical contacts 107 shown in

[0058] As described above with respect to Figure 5 FIGS. 1 to 7, the encapsulation structure may include one or more sidewalls that enclose the electrical connectors in at least two dimensions. The space enclosed by the one or more sidewalls is configured to accommodate the quantum processing unit.

[0059] In step 803, the quantum processing unit and the open encapsulation structure are placed in a controlled environment, such as an inert gas environment or a vacuum.

[0060] In step 804, the quantum processing unit is enclosed in the encapsulation structure by sealing the enclosed space using a lid. The lid and one or more sidewalls can form an airtight seal around the quantum processing unit. Performing this step in a controlled environment ensures that the cavity enclosed by the sidewalls and the lid is filled with an inert gas (such as helium) or under vacuum.

Claims

1. An encapsulation structure (100) for a superconducting quantum processing unit (110), the encapsulation structure comprising: A ceramic support portion (101) for supporting the quantum processing unit, the support portion including a plurality of electrical connectors (104) for connecting the quantum processing unit to a plurality of electrical contacts (108) on an outer surface of the ceramic encapsulation structure.

2. An encapsulated quantum processing unit, comprising the encapsulation structure (100) according to claim 1 and a quantum processing unit (110).

3. The encapsulation structure according to claim 1 or the encapsulated quantum processing unit according to claim 2, wherein the encapsulation structure (100) further includes one or more sidewalls (102) enclosing the plurality of electrical connectors in at least two dimensions, and a space enclosed by the one or more sidewalls is configured to accommodate the quantum processing unit (110).

4. The encapsulation structure or the encapsulated quantum processing unit according to claim 3, wherein the one or more sidewalls (102) are formed of a ceramic material.

5. The encapsulation structure or the encapsulated quantum processing unit according to claim 3 or 4, wherein the encapsulation structure further includes a lid (103), the lid being configured to enclose the plurality of electrical connectors such that the support portion (101), the one or more sidewalls (102) and the lid form a cavity configured to accommodate the quantum processing unit and enclosed in three dimensions.

6. The encapsulation structure or the encapsulated quantum processing unit according to claim 5, wherein the lid (103) is formed of a ceramic material and / or a metal material.

7. The encapsulation structure or the encapsulated quantum processing unit according to claims 4 and 6, wherein one or more of the support portion, the sidewalls and the lid are formed of a ceramic material, the ceramic material including one or more superconducting material layers or superconducting material traces inside or on a surface of the ceramic material.

8. The encapsulation structure or the encapsulated quantum processing unit according to claim 7, wherein the ceramic material includes a superconducting metal layer.

9. The encapsulation structure or the encapsulated quantum processing unit according to claim 8, wherein the ceramic material is a low temperature co-fired ceramic or a high temperature co-fired ceramic.

10. The encapsulation structure or the encapsulated quantum processing unit according to any one of claims 7 to 9, wherein the ceramic material shields the cavity from external electric and magnetic fields.

11. The encapsulation structure or the encapsulated quantum processing unit according to any of the preceding claims, wherein the encapsulation structure (100) further includes one or more of activated carbon, getter and molecular sieve.

12. The encapsulation structure or the encapsulated quantum processing unit according to any of the preceding claims, wherein the plurality of electrical connectors of the support portion extend at least 50 mm in one direction.

13. The encapsulation structure or the encapsulated quantum processing unit according to any of the preceding claims, wherein at 1K and 300K, the thermal expansion coefficient of the ceramic support portion is within ±50% of the thermal expansion coefficient of silicon.

14. The encapsulated quantum processing unit according to any one of the preceding claims, wherein the cavity is airtight.

15. The encapsulated quantum processing unit according to claim 14, wherein the cavity is under vacuum.

16. The encapsulated quantum processing unit according to claim 15, wherein the cavity is filled with an inert gas.

17. The encapsulated quantum processing unit according to claim 16, wherein the inert gas is helium, and wherein when the encapsulated quantum processing unit is cooled to cryogenic temperatures, the helium is configured to form a superfluid.

18. A method of manufacturing an encapsulated quantum processing unit, the method comprising: inserting a quantum processing unit into a packaging structure, the packaging structure including a ceramic support portion for supporting the quantum processing unit; connecting the quantum processing unit to a plurality of electrical connectors located on the support portion, the electrical connectors being configured to connect the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic packaging structure.

19. The method according to claim 18, wherein the packaging structure further includes one or more sidewalls enclosing the plurality of electrical connectors in at least two dimensions, wherein the space enclosed by the one or more sidewalls is configured to accommodate the quantum processing unit.

20. The method according to claim 19, wherein the method further includes enclosing the quantum processing unit within the packaging structure by sealing the enclosed space with a lid.

21. The method according to claim 20, wherein the lid and the one or more sidewalls form an airtight seal around the quantum processing unit.

22. The method according to claim 21, wherein enclosing the quantum processing unit is performed in a vacuum or an inert gas environment.

23. The method according to claim 22, wherein the inert gas is helium.

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