Field effect transistor time-dependent breakdown test method and system based on parallel bonding

Abstract

The invention discloses a field effect transistor time-dependent breakdown test method and system based on parallel bonding, and belongs to the technical field of power electronics, and the method comprises the steps: enabling a plurality of field effect transistors to be connected in parallel and bonded on a current collection circuit; voltage stress is applied between the grid electrode and the drain electrode of the field effect transistor, and thermal stress is applied to the tray of the current acquisition circuit; collecting the leakage current of each field effect transistor through a data collection module while applying the stress; when any leakage current is greater than a preset breakdown threshold value or the duration of applying the stress reaches a preset test time limit, stopping applying the electric stress and recording the total duration of applying the stress to the field effect transistor; and predicting the service life of the field effect transistor according to the total time length, so that by implementing the method and the device, the problems that in the prior art, expensive equipment is needed to carry out a time-dependent breakdown test, and a plurality of field effect transistor devices cannot be tested at the same time, so that the test efficiency is low can be solved.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, and specifically relates to a method and system for time-dependent breakdown testing of field effect transistors based on parallel bonding. Background Art

[0002] With the continuous development of power electronics technology, metal-oxide-semiconductor field effect transistors made of silicon carbide (SiC-MOSFET for short, hereinafter referred to as field effect transistors) have been increasingly widely used in high-voltage and high-frequency power applications. However, there are relatively high electric fields and low barrier heights at the interface of silicon carbide or silicon oxide. Therefore, field effect transistors made of silicon carbide are prone to dielectric breakdown under strong electric fields, resulting in the loss of electrical insulation ability and device damage such as material fragmentation. Time-dependent breakdown is a type of dielectric breakdown related to time and is a key factor affecting the stability of field effect transistors. Therefore, time-dependent breakdown tests are often performed on field effect transistors to evaluate their reliability under long-term extreme loads, thereby helping engineers design and optimize transistor performance and improve their service life.

[0003] Traditional time-dependent breakdown test methods usually use a probe station combined with a semiconductor parameter analyzer to detect the breakdown time when the transistor exhibits time-dependent breakdown. However, this method requires expensive equipment and cannot simultaneously test multiple MOS field effect transistor devices, resulting in high test costs and low efficiency, which limits its wide application in academic research and industrial production. Summary of the Invention

[0004] This application proposes a method and system for time-dependent breakdown testing of field effect transistors based on parallel bonding, which can solve the problems in the prior art that expensive equipment is required for time-dependent breakdown testing and multiple field effect transistor devices cannot be tested simultaneously, resulting in low test efficiency.

[0005] The first aspect of this application provides a method for time-dependent breakdown testing of field effect transistors based on parallel bonding, the method comprising:

[0006] Bonding a plurality of field effect transistors in parallel to a current acquisition circuit based on a current mirror;

[0007] Applying a constant voltage stress between the gate and drain of the field effect transistor, and simultaneously applying a constant thermal stress uniformly to the tray of the current acquisition circuit;

[0008] While applying the voltage stress and the thermal stress, collecting the drain current of each field effect transistor through a data acquisition module;

[0009] When any one of the drain currents is greater than a preset breakdown threshold, or the duration of applying the stress reaches a preset test time limit, stop applying the voltage stress and the thermal stress and record the total duration of applying the stress to the field effect transistor;

[0010] Based on the total duration, the magnitude of the voltage stress, and the magnitude of the thermal stress, the lifetime of the field effect transistor is predicted.

[0011] In the above solution, the bare chips of multiple field effect transistors are first bonded together in parallel and placed on a current acquisition circuit based on a current mirror. Since multiple field effect transistors are bonded in parallel, it is possible to simultaneously perform time-dependent breakdown tests on multiple field effect transistors, which can greatly improve the test efficiency and meet the quality inspection requirements in large-scale production. Then, a fixed magnitude of voltage stress is applied between the gate and drain of the field effect transistor, and a fixed magnitude of thermal stress is uniformly applied to the tray of the current acquisition circuit to complete the application of extreme load conditions. By applying a high voltage to drive damage to the oxide layer of the field effect transistor, and at the same time creating a high-temperature working condition of the field effect transistor by applying thermal stress to the tray, it provides environmental support for the occurrence of time-dependent breakdown of the field effect transistor. While applying the stress, the drain current of each field effect transistor is accurately collected. When the drain current is greater than the preset breakdown threshold, it can be considered that the field effect transistor has a time-dependent breakdown. At this time, the time when the time-dependent breakdown occurs is recorded as the breakdown time of the field effect transistor, which is the failure time when the field effect transistor fails. Finally, based on the recorded time data and the magnitude of the applied stress, the service life and reliability under extreme working conditions of the field effect transistor are predicted. Just by collecting the drain current through a relatively simple current acquisition circuit, the time when the field effect transistor has a time-dependent breakdown can be accurately judged, which can effectively reduce the test cost.

[0012] In a possible implementation method of the first aspect, several field effect transistors are bonded in parallel on a current acquisition circuit based on a current mirror, specifically:

[0013] The field effect transistors are bonded in parallel on the immersion gold pads of the current acquisition circuit, and the drain electrodes of the field effect transistors are fixed by conductive adhesive; wherein, the immersion gold pads are used to prevent the field effect transistors from being oxidized; the number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit;

[0014] The source and drain electrodes of the field effect transistors are short-circuited through the wires of the current acquisition circuit and connected to the power ground.

[0015] The above solution bonds multiple field effect transistors in parallel together to achieve simultaneous measurement of multiple field effect transistors, and places the field effect transistors on the immersion gold pads to prevent the field effect transistors from being oxidized, improving the conductivity and enabling more accurate collection of the drain current.

[0016] In a possible implementation method of the first aspect, a constant voltage stress is applied between the gate and drain of the field effect transistor, and a constant thermal stress is uniformly applied to the tray of the current acquisition circuit, specifically:

[0017] According to a preset electric field strength of a fixed magnitude, a constant gate voltage is applied between the gate and the drain of the field effect transistor from an initial moment;

[0018] From the initial moment, a constant thermal stress is uniformly applied to the entire tray of the current collection circuit through the heating plate, and the surface temperature of the tray is monitored in real time through the temperature sensor to ensure that the thermal stress is stable.

[0019] The above scheme applies a fixed voltage between the gate and drain of the field effect tube to accelerate the rate at which the oxide layer of the gate breaks down over time; at the same time, a constant thermal stress is uniformly applied to the entire tray of the current collection circuit so that each field effect tube is heated evenly and is in a consistent high temperature condition, thereby improving the accuracy of leakage current collection.

[0020] In a possible implementation method of the first aspect, the leakage current of each field effect transistor is collected by a data collection module, specifically:

[0021] The leakage current between the gate and the drain of the field effect tube is mirrored to the loop where the sampling resistor is located through the current mirror of the current acquisition circuit;

[0022] The voltage on the sampling resistor is monitored by a data acquisition module, and the leakage current is calculated according to the resistance value of the sampling resistor and the voltage.

[0023] The above scheme uses a current mirror to mirror the leakage current to the loop where the sampling resistor is located, then collects the voltage of the sampling resistor, calculates the current value flowing through the sampling resistor by Ohm's law, and obtains a preliminary predicted leakage current. Because some errors will be generated in the mirroring process, the current of the sampling resistor is corrected by a preset current mirror correction formula, and then the accurate leakage current value is calculated based on the resistance value of the loop where the sampling resistor is located.

[0024] In a possible implementation method of the first aspect, the leakage current is calculated according to the resistance value of the sampling resistor and the voltage, specifically:

[0025] Calculating the current of the sampling resistor according to the resistance value of the sampling resistor and the voltage;

[0026] Correcting the current of the sampling resistor by a preset current mirror correction formula to obtain a predicted value of the leakage current;

[0027] The real value of the leakage current is calculated according to the predicted value of the leakage current, the resistance value of the sampling resistor and the resistance value of the voltage-dividing resistor; wherein the voltage-dividing resistor is located on the loop where the sampling resistor is located.

[0028] In a possible implementation method of the first aspect, when any one of the leakage currents is greater than a preset breakdown threshold, or the duration of applying stress reaches a preset test time limit, stop applying voltage stress and thermal stress and record the total duration of applying stress to the field effect transistor. Specifically:

[0029] When the leakage current of the field effect transistor is greater than a preset breakdown threshold, it can be considered that the field effect transistor has experienced time-dependent breakdown. At this time, stop applying voltage stress and thermal stress to the field effect transistor and record the total duration of applying stress to the field effect transistor as the breakdown time; wherein, according to a preset leakage current-temperature model, the breakdown threshold is dynamically adjusted;

[0030] When the duration of applying stress to the field effect transistor reaches a preset test time limit, stop applying voltage stress and thermal stress to the field effect transistor and record the total duration of applying stress to the field effect transistor as the total test duration;

[0031] According to the breakdown time and the total test duration, obtain the total duration of applying stress to the field effect transistor.

[0032] In the above solution, when the leakage current is greater than the preset breakdown threshold, it indicates that the oxide layer of the gate has suffered non-negligible damage, resulting in a rapid increase in the magnitude of the leakage current in a short period of time. At this time, it can be considered that the field effect transistor has experienced time-dependent breakdown. By recording the time of time-dependent breakdown, it can be considered that the field effect transistor has been damaged and fails. By recording the breakdown time, the lifespan of the field effect transistor under extreme load conditions can be known, and thus the performance and reliability of the field effect transistor can be evaluated.

[0033] In a possible implementation method of the first aspect, according to a preset leakage current-temperature model, the breakdown threshold is dynamically adjusted. Specifically:

[0034] According to the test data, calculate the breakdown threshold at the current temperature of the field effect transistor through the leakage current-temperature model;

[0035] Wherein, the test data includes the duration of applying thermal stress to the field effect transistor, the initial temperature of the field effect transistor, the current temperature, the initial leakage current of the field effect transistor, and the current room temperature.

[0036] In the above solution, considering that the leakage currents when the field effect transistor experiences time-dependent breakdown at different test temperatures are different, the breakdown threshold that conforms to the current test situation is calculated through the leakage current-temperature model, which can more accurately judge whether the field effect transistor has experienced time-dependent breakdown.

[0037] In a possible implementation method of the first aspect, the leakage current-temperature model, the specific expression is:

[0038]

[0039] In the formula, I th (T) is the breakdown threshold at the current temperature of the field effect transistor, and I th,0 is the initial drain current of the field effect transistor, T is the current temperature of the field effect transistor, T0 is the initial temperature of the field effect transistor, and E a is the current room temperature, and k is the Boltzmann constant.

[0040] The second aspect of the present application provides a time-dependent breakdown test device for a field effect transistor based on parallel bonding. The device includes: a field effect transistor parallel module, a stress application module, a drain current acquisition module, a breakdown time recording module, and a device life prediction module;

[0041] Among them, the field effect transistor parallel module is used to bond several field effect transistors in parallel on a current acquisition circuit based on a current mirror;

[0042] The stress application module is used to apply a constant voltage stress between the gate and the drain of the field effect transistor, and at the same time apply a constant thermal stress uniformly to the tray of the current acquisition circuit;

[0043] The drain current acquisition module is used to collect the drain current of each field effect transistor through a data acquisition module while applying voltage stress and thermal stress;

[0044] The breakdown time recording module is used to stop applying voltage stress and thermal stress and record the total duration of applying stress to the field effect transistor when any of the drain currents is greater than a preset breakdown threshold, or the duration of applying stress reaches a preset test time limit;

[0045] The device life prediction module is used to predict the life of the field effect transistor according to the total duration and the state of the field effect transistor when the voltage stress and thermal stress are stopped from being applied.

[0046] The third aspect of the present application provides a time-dependent breakdown test system for a field effect transistor based on parallel bonding. The system includes: a time-dependent breakdown test device for a field effect transistor based on parallel bonding and a current acquisition circuit based on a current mirror;

[0047] Among them, the time-dependent breakdown test device for a field effect transistor based on parallel bonding is used to implement the time-dependent breakdown test method for a field effect transistor based on parallel bonding according to any one of the embodiments of the present application;

[0048] The current acquisition circuit based on a current mirror is used to place several field effect transistors and collect the drain current of the field effect transistors.

[0049] In a possible implementation method of the third aspect, the current acquisition circuit based on a current mirror further includes:

[0050] The current acquisition circuit based on a current mirror includes an immersion gold board, wires, conductive adhesive, and square pads;

[0051] The square pads are used to lead out the gate and source of the field effect transistor, and the conductive adhesive is used to fix the drain of the field effect transistor;

[0052] The field effect transistor is placed on the immersion gold board, and the wires short-circuit the source and drain of the field effect transistor and connect them to the power ground;

[0053] Among them, the total number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit based on the current mirror. Description of the Drawings

[0054] To more clearly illustrate the technical solutions of the present application, the drawings required for implementation will be briefly introduced below. Obviously, the drawings in the following description are only some implementations of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0055] Figure 1 It is a specific flowchart of a method for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application;

[0056] Figure 2 It is a schematic diagram of a current acquisition circuit for a method for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application;

[0057] Figure 3 It is a time-dependent breakdown test chart of a method for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application;

[0058] Figure 4 It is a schematic diagram of a current mirror for a method for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application;

[0059] Figure 5 It is a structural diagram of a device for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application;

[0060] Figure 6 It is a structural diagram of a system for testing the time-dependent breakdown of field effect transistors based on parallel bonding provided by an embodiment of the present application. Detailed Embodiments

[0061] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0062] It should be understood that the step numbers used in the text are only for convenient description and are not intended to limit the order of execution of the steps.

[0063] First Embodiment

[0064] Time-dependent breakdown is a time-related dielectric breakdown. That is, in the case of high voltage on the gate oxide layer of a field effect transistor, its leakage current will gradually increase and finally lead to breakdown, thereby causing the gate oxide layer to lose its insulation function and the field effect transistor to be damaged and unable to work properly. Therefore, time-dependent breakdown can be used to evaluate the reliability of field effect transistors under long-term operation, helping engineers optimize the design and production process of field effect transistor devices and reducing the failure risk of field effect transistors during use.

[0065] Currently, time-dependent breakdown detection of field effect transistors is mainly carried out through a probe station in combination with a semiconductor parameter analyzer. However, this method can only detect one field effect transistor at a time, which takes a long time. Moreover, the price of the semiconductor parameter analyzer is relatively high, resulting in an increase in measurement costs and unable to meet the quality inspection requirements in mass production. Therefore, the embodiments of the present application aim to study a time-dependent breakdown test method with low cost and high detection efficiency for accurately evaluating the service life of field effect transistors.

[0066] As Figure 1 shown, to solve the problems in the prior art that expensive equipment is required for time-dependent breakdown testing and the testing efficiency is low because multiple field effect transistor devices cannot be tested simultaneously, the first embodiment of the present application provides a schematic flow diagram of a time-dependent breakdown test method for field effect transistors based on parallel bonding. The time-dependent breakdown test method for field effect transistors based on parallel bonding in this embodiment includes steps S1 to S5, which are described in detail as follows:

[0067] Step S1, bond a plurality of field effect transistors in parallel to a current acquisition circuit based on a current mirror.

[0068] In the embodiments of the present application, the same type of field effect transistor based on silicon carbide is used. Compared with field effect transistors based on silicon with the same power level, its on-resistance and switching losses are significantly reduced, it is suitable for higher operating frequencies, and it has stability in high-temperature environments.

[0069] First, the embodiments of the present application provide a 32-channel current acquisition circuit based on a current mirror, specifically as Figure 2As shown in the figure. The current acquisition circuit includes an immersion gold board, wires, conductive glue, square pads, etc. Here, Gate refers to the gate, and Source refers to the source. Place the field effect transistor on the square pad with an immersion gold board above it. Then the square pad is used to lead out the gate and source of the field effect transistor. In addition, conductive glue is used to fix the drain of the field effect transistor, and the source and drain of the field effect transistor are short-circuited and connected to the power ground through the internal wires of the circuit.

[0070] Among them, the immersion gold pad can utilize the antioxidant property of the gold layer to block the copper-based oxidation of the field effect transistor, and improve the conductivity of the field effect transistor through high conductivity and low roughness, so as to detect the leakage current more accurately.

[0071] In order to detect multiple bare chips of field effect transistors at one time, in the embodiment of the present application, multiple bare chips of field effect transistors are bonded in parallel on the tray of the current acquisition circuit. Since the current acquisition circuit has 32 channels, up to 32 bare chips of field effect transistors can be detected at one time. Compared with the traditional time-dependent breakdown detection method, this greatly improves the detection efficiency and can be applied to large-scale detection.

[0072] As an improvement of the above solution, in the embodiment of the present application, the 32 channels of the current acquisition circuit can be independently acquired, and the field effect transistors are bonded by gold wires, and the pad pitch is greater than or equal to 150 microns to avoid crosstalk between the field effect transistors.

[0073] Optionally, since the total number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit based on the current mirror, in other embodiments, if the current acquisition circuit has 68 channels, then 68 bare chips of field effect transistors can be detected at one time. 68 channels is the balance point of electricity, heat and process, and it is the maximum number of field effect transistors that can be measured at one time currently. The embodiment of the present application selects 32 as a compromise choice considering the test efficiency and cost.

[0074] Step S2, apply a constant voltage stress between the gate and the drain of the field effect transistor, and at the same time apply a constant thermal stress uniformly to the tray of the current acquisition circuit.

[0075] The influence of voltage on time-dependent breakdown is mainly reflected in the damage of the gate oxide layer by the voltage stress. As the voltage applied to the oxide layer increases, the leakage current increases, resulting in an increase in hole and electron traps in the oxide layer, and finally forming a conductive channel, leading to breakdown.

[0076] The influence of temperature on time-dependent breakdown is mainly reflected in the impact of temperature changes on leakage current and breakdown time. Under low-temperature conditions, the resistivity of semiconductor materials increases and the carrier concentration decreases, resulting in an increase in breakdown voltage; while under high-temperature conditions, the resistivity decreases and the carrier concentration increases, leading to a decrease in breakdown voltage. In addition, temperature also affects the rate of leakage current, thereby affecting the breakdown time.

[0077] Therefore, in order to test the breakdown time of the field-effect transistor under preset load conditions, the embodiments of the present application simultaneously apply a voltage stress and a thermal stress of a constant magnitude to the field-effect transistor to drive the rapid increase of the leakage current and cause time-dependent breakdown of the field-effect transistor.

[0078] First, a fixed electric field strength is set, and then a constant gate voltage is directly applied between the gate and the drain of each bare chip of the field-effect transistor to drive time-dependent breakdown of the gate oxide layer of the field-effect transistor through high voltage. In other embodiments, a constant gate voltage is also applied between the gate and the source of the bare chip of the field-effect transistor.

[0079] Exemplarily, in the embodiments of the present application, the set range of the electric field strength is 8 - 10 MV / cm. In an experiment of the embodiments of the present application, an electric field of 9 MV / cm is applied between the gate and the drain of each bare chip of the field-effect transistor from the initial moment, and the corresponding gate voltage is 45V.

[0080] In addition, the electric field strength is fixed and stably output from the beginning of the test, rather than rising gradually.

[0081] While applying the voltage stress, a constant thermal stress is also uniformly applied to the entire tray of the current acquisition circuit through a silicone heating plate to provide a high-temperature working condition for the field-effect transistor.

[0082] Specifically, a thermal stress is uniformly applied to the entire push tray of the current acquisition circuit through a silicone heating plate to increase the substrate temperature. At the same time, the surface temperature of the tray is also monitored in real time through a temperature sensor to ensure that the thermal stress remains stable.

[0083] Exemplarily, the magnitudes of the thermal stress set in the embodiments of the present application include 31°C, 72°C, and 90°C. The applied thermal stress reaches the set value instantaneously and is constant during the application process, rather than rising in a gradient manner.

[0084] Figure 3 It shows the monitoring of the application of voltage stress and thermal stress through a microcontroller (MCU) to ensure that the applied electric field strength and temperature magnitude are constant. At the same time, the leakage current of the field-effect transistor is also collected through a multi-channel data acquisition module (DAQ).

[0085] Step S3, while applying voltage stress and thermal stress, collect the drain current of each of the field effect transistors through the data acquisition module.

[0086] Collect the drain current of each of the field effect transistors through the data acquisition module from the start of applying voltage stress and thermal stress. However, the data collected here is not obtained through direct collection, but through conversion by the current mirror of the current acquisition circuit.

[0087] Specifically, as Figure 4 shown, the drain current I between the gate and the drain g is mirrored to the loop where the sampling resistor R3 is located through the current mirror. After mirroring, the current I o flows through the sampling resistor. At this time, by detecting the voltage of the sampling resistor through the data acquisition module, the value of I o can be obtained through Ohm's law. And the current I o is exactly the basis for calculating the drain current. In the figure, R2 is a high-precision voltage-dividing resistor, which is used to combine the current after mirroring and the resistance value of the sampling resistor to calculate the true value of the drain current.

[0088] Among them, the expression of the current mirroring principle is as follows:

[0089]

[0090] In the formula, I g is the drain current, x is the common-emitter current gain, and I o is the current after mirroring, which is the current of the sampling resistor.

[0091] In addition, when the type selection of the field effect transistor satisfies that the common-emitter current gain is equal to 50, the mirroring error is only 0.04%. When the drain current is 1 μA under this mirroring error, the current I o after mirroring is 0.9996 μA. The error between the two is extremely small and can be regarded as an ideal mirroring, that is, I g ≈I o . Therefore, the common-emitter current gain adopted in the embodiment of the present application is 50.

[0092] Exemplarily, the embodiment of the present application selects a 10 kΩ high-precision voltage-dividing resistor and a 100 Ω sampling resistor to perform a current mirroring. The voltage of the sampling resistor collected is 50 mV. Through Ohm's law, the current magnitude flowing through the sampling resistor can be obtained as 500 μA. Then, the current flowing through the sampling resistor is verified through the above expression of the current mirroring principle to obtain the predicted value of the drain current, specifically:

[0093]

[0094] Finally, by combining the resistance value of the sampling resistor and the resistance value of the voltage-dividing resistor, the true value of the drain current can be calculated:

[0095]

[0096] Wherein, I g,real is the true value of the leakage current.

[0097] Optionally, the embodiment of the present application selects a Wilson current mirror to implement the mirror current, and the data acquisition module acquires data at a frequency of 1 Hz.

[0098] Step S4, when any one of the leakage currents is greater than a preset breakdown threshold, or the duration of applying stress reaches a preset test time limit, stop applying the voltage stress and the thermal stress, and record the total duration of applying stress to the field effect transistor.

[0099] Due to continuously applying a high voltage and creating a high-temperature working condition, the leakage current will continuously increase until time-dependent breakdown occurs. When it is detected that time-dependent breakdown occurs, the stress application can be stopped. In the embodiment of the present application, two conditions for terminating the stress application are set: when any one of the acquired leakage currents is greater than a preset breakdown threshold, or the duration of applying stress reaches a preset test time limit, stop applying the voltage stress and the thermal stress.

[0100] Wherein, the magnitude of the breakdown threshold is dynamically adjusted according to the temperature of the field effect transistor, and the test time limit is set artificially and is used as the maximum time for stopping the stress application when time-dependent breakdown does not occur in the field effect transistor. The setting of the test implementation needs to comprehensively consider the performance limitations of the test equipment, test conditions (such as electric field strength and temperature), and the specific requirements of the user. In industrial production, the test time limit is usually set to several hours to 10 hours to quickly evaluate the reliability of the device; while in academic research, to obtain more comprehensive data, the test time limit may be extended to dozens of hours or even longer. Stopping the stress application when the test time reaches the preset time limit is mainly to protect the equipment and the device, avoid unnecessary damage to them caused by long-term high voltage and high temperature, save resources, and ensure the reliability of the test results.

[0101] Since the leakage current is stable at 30 - 100 μA when time-dependent breakdown does not occur under normal electric fields, and the leakage current suddenly increases to more than 200 μA when time-dependent breakdown occurs, at this time, the data acquisition module will be triggered to collect the voltage of the sampling resistor.

[0102] In order to enable the data acquisition module to more timely respond to when to collect, the embodiment of the present application sets a warning threshold during the rising process of the leakage current to prompt that the current value of the leakage current has reached a certain height and issue a breakdown warning.

[0103] Exemplarily, the warning threshold is related to the breakdown threshold. In the embodiment of the present application, if the breakdown threshold is set to 500 μA, then the warning threshold is set to 100 μA. That is, when the voltage of the sampling resistor is greater than 10 mV, the current of the sampling resistor is greater than 100 μA, and a breakdown warning will be issued.

[0104] The dynamic adjustment of the breakdown threshold is mainly determined according to temperature adaptively. In the embodiment of the present application, a leakage current-temperature model is constructed to calculate the breakdown threshold of the field effect transistor at the current temperature. The specific expression is:

[0105]

[0106] In the formula, I th (T) is the breakdown threshold of the field effect transistor at the current temperature, I th,0 is the initial leakage current of the field effect transistor, T is the current temperature of the field effect transistor, T0 is the initial temperature of the field effect transistor, E a is the current room temperature, and k is the Boltzmann constant.

[0107] In the embodiment of the present application, the room temperature is 31 °C.

[0108] As an improvement to the above solution, the embodiment of the present application also monitors the volatility of the leakage current in real time. The specific calculation formula is as follows:

[0109]

[0110] In the formula, δ is the volatility of the leakage current, Δt is the time interval, and ΔI o is the change in the current of the sampling resistor within the time interval, and I o is the current of the sampling resistor.

[0111] When δ > 0.1%, for example, when the current of the sampling resistor suddenly changes from 500 μA to 550 μA within one second, a breakdown warning is triggered.

[0112] By monitoring the volatility of the leakage current in real time, it is possible to more accurately determine whether the field effect transistor has broken down, thereby improving the accuracy and reliability of the test. The calculation of the volatility can be used as a reference index for dynamically adjusting the breakdown threshold to reduce false judgments caused by environmental factors or device noise; in addition, the volatility data can also provide support for subsequent data analysis and model optimization, helping to further understand the breakdown mechanism of the field effect transistor, thereby optimizing the test parameters and improving the device design.

[0113] Step S5, predict the lifetime of the field effect transistor according to the total duration, the magnitude of the voltage stress, and the magnitude of the thermal stress.

[0114] In the embodiment of the present application, the collected current data is analyzed by mean filtering and Weibull distribution, and combined with the breakdown times under different voltage stresses and thermal stresses collected, to estimate the lifetime of the field effect transistor. The specific expression is:

[0115]

[0116] In the formula, t bd is the predicted lifetime of the field effect transistor, A o is a reference value, which is the lifetime of the field effect transistor under ideal conditions without the influence of external electric field and temperature; E ox is the electric field applied to the gate oxide layer of the field effect transistor, E a is the activation energy, γ is the electric field acceleration parameter, k is the Boltzmann constant, and T is the absolute temperature.

[0117] Implementing the embodiment of the present application has the following effects:

[0118] In the embodiment of the present application, the bare chips of multiple field effect transistors are first bonded together in parallel and placed on a current acquisition circuit based on a current mirror. Since multiple field effect transistors are bonded in parallel, it is possible to simultaneously perform time-dependent breakdown tests on multiple field effect transistors, which can greatly improve the test efficiency and meet the quality inspection requirements in large-scale production. Then, a fixed voltage stress is applied between the gate and drain of the field effect transistor, and at the same time, a fixed thermal stress is uniformly applied to the tray of the current acquisition circuit to complete the application of extreme load conditions. By applying a high voltage to drive the damage of the oxide layer of the field effect transistor, and at the same time applying a thermal stress to the tray to create a high-temperature working condition of the field effect transistor, it provides environmental support for the time-dependent breakdown of the field effect transistor. While applying the stress, the drain current of each field effect transistor is accurately collected. When the drain current is greater than the preset breakdown threshold, it can be considered that the field effect transistor has a time-dependent breakdown. At this time, the time of the time-dependent breakdown is recorded as the breakdown time of the field effect transistor, that is, the failure time when the field effect transistor fails. Finally, based on the recorded time data and the magnitude of the applied stress, the service life and reliability under extreme working conditions of the field effect transistor are predicted. Just by collecting the drain current through a relatively simple current acquisition circuit, the time of the time-dependent breakdown of the field effect transistor can be accurately judged, which can effectively reduce the test cost.

[0119] Second Embodiment

[0120] Furthermore, in order to implement the time-dependent breakdown test device of the field effect transistor based on parallel bonding corresponding to the above method embodiment to achieve the corresponding functions and technical effects, Figure 5 a structural diagram of the time-dependent breakdown test device of the field effect transistor based on parallel bonding is provided. For the sake of convenience of description, only the parts related to this embodiment are shown. The time-dependent breakdown test device of the field effect transistor based on parallel bonding provided by the embodiment of the present application includes:

[0121] A field effect transistor parallel module 201 is used to bond several field effect transistors in parallel on a current acquisition circuit based on a current mirror.

[0122] In the embodiment of the present application, a silicon carbide-based field effect transistor is used. Compared with a silicon-based field effect transistor of the same power level, its on-resistance and switching loss are greatly reduced, it is suitable for higher operating frequencies, and it has stability in a high-temperature environment.

[0123] First, the embodiment of the present application provides a 32-channel current acquisition circuit based on a current mirror, including an immersion gold board, wires, conductive glue, square pads, etc. Place the field effect transistor on the square pad with the immersion gold board above. Then the square pad is used to lead out the gate and source of the field effect transistor. In addition, conductive glue is used to fix the drain of the field effect transistor, and the source and drain of the field effect transistor are short-circuited and connected to the power ground through the internal wires of the circuit.

[0124] Among them, the immersion gold pad can utilize the antioxidant property of the gold layer to block the copper-based oxidation of the field effect transistor, and improve the conductivity of the field effect transistor through high conductivity and low roughness, and more accurately detect the leakage current.

[0125] In order to detect multiple bare chips of field effect transistors at one time, the embodiment of the present application bonds multiple bare chips of field effect transistors in parallel on the tray of the current acquisition circuit. Since the current acquisition circuit has 32 channels, up to 32 bare chips of field effect transistors can be detected at one time. Compared with the traditional time-dependent breakdown detection method, this greatly improves the detection efficiency and can be applied to large-scale detection.

[0126] Optionally, because the total number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit based on the current mirror, in other embodiments, if the current acquisition circuit has 68 channels, then 68 bare chips of field effect transistors can be detected at one time. 68 channels is the balance point of electricity, heat and technology, and it is the maximum number of field effect transistors that can be measured at one time currently. The embodiment of the present application selects 32 channels as a trade-off choice considering the test efficiency and cost.

[0127] A stress application module 202 is used to apply a constant voltage stress between the gate and the drain of the field effect transistor, and at the same time apply a constant thermal stress evenly to the tray of the current acquisition circuit.

[0128] In the embodiment of the present application, the influence of voltage on time-dependent breakdown is mainly reflected in the damage of the gate oxide layer by the voltage stress. As the voltage applied to the oxide layer increases, the leakage current increases, resulting in an increase in hole and electron traps in the oxide layer, and finally forming a conductive channel, leading to breakdown.

[0129] The influence of temperature on time-dependent breakdown is mainly reflected in the effects of temperature changes on leakage current and breakdown time. Under low-temperature conditions, the resistivity of semiconductor materials increases and the carrier concentration decreases, resulting in an increase in breakdown voltage; while under high-temperature conditions, the resistivity decreases and the carrier concentration increases, resulting in a decrease in breakdown voltage. In addition, temperature also affects the rate of leakage current, thereby affecting the breakdown time.

[0130] Therefore, in order to test the breakdown time of the field-effect transistor under preset load conditions, the embodiments of the present application simultaneously apply a voltage stress and a thermal stress of a constant magnitude to the field-effect transistor to drive the rapid increase of the leakage current to cause time-dependent breakdown of the field-effect transistor.

[0131] First, a fixed electric field strength is set, and then a constant gate voltage is directly applied between the gate and the drain of each bare chip of the field-effect transistor to drive time-dependent breakdown of the gate oxide layer of the field-effect transistor through high voltage. In other embodiments, a constant gate voltage is also applied between the gate and the source of the bare chip of the field-effect transistor.

[0132] Exemplarily, in the embodiments of the present application, the set range of the electric field strength is 8-10 MV / cm. In an experiment of the embodiments of the present application, an electric field of 9 MV / cm is applied between the gate and the drain of each bare chip of the field-effect transistor from the initial moment, and the corresponding gate voltage is 45 V.

[0133] In addition, the electric field strength is fixed and stably output from the beginning of the test, rather than increasing gradually.

[0134] While applying the voltage stress, a constant thermal stress is also uniformly applied to the entire tray of the current acquisition circuit through a silicone heating plate to provide a high-temperature working condition for the field-effect transistor.

[0135] Specifically, a thermal stress is uniformly applied to the entire push tray of the current acquisition circuit through a silicone heating plate to increase the substrate temperature. At the same time, the surface temperature of the tray is also monitored in real time through a temperature sensor to ensure that the thermal stress remains stable.

[0136] Exemplarily, the magnitudes of the thermal stress set in the embodiments of the present application include 31°C, 72°C, and 90°C. The applied thermal stress reaches the set value instantaneously and is constant during the application process, rather than increasing in a gradient manner.

[0137] The leakage current acquisition module 203 is used to collect the leakage current of each field-effect transistor through the data acquisition module while applying the voltage stress and the thermal stress.

[0138] The drain current of each of the field effect transistors is collected by the data acquisition module starting from the beginning of the application of voltage stress and thermal stress. However, the data collected here is not obtained by direct acquisition, but is converted through the current mirror of the current acquisition circuit.

[0139] Specifically, the drain current between the gate and the drain is mirrored to the loop where the sampling resistor is located through the current mirror. The current after mirroring flows through the sampling resistor. At this time, by detecting the voltage of the sampling resistor through the data acquisition module, the value of the current after mirroring can be obtained through Ohm's law, and the current after mirroring is the basis for calculating the drain current. In addition, a high-precision voltage-dividing resistor is also set up to calculate the true value of the drain current in combination with the current after mirroring and the resistance value of the sampling resistor.

[0140] Among them, the expression of the current mirror principle is as follows:

[0141]

[0142] In the formula, I g is the drain current, x is the common-emitter current gain, and I o is the current after mirroring, which is the current of the sampling resistor.

[0143] In addition, when the selection of the field effect transistor satisfies that the common-emitter current gain is equal to 50, the mirroring error is only 0.04%. When the drain current is 1 μA under this mirroring error, the current I o after mirroring is 0.9996 μA. The error between the two is extremely small and can be regarded as an ideal mirroring, that is, I g ≈I o . Therefore, the common-emitter current gain adopted in the embodiment of the present application is 50.

[0144] Exemplarily, the embodiment of the present application selects a 10 kΩ high-precision voltage-dividing resistor and a 100 Ω sampling resistor for current mirroring once. The voltage of the sampling resistor collected is 50 mV. The magnitude of the current flowing through the sampling resistor can be obtained through Ohm's law as 500 μA. Then, the current flowing through the sampling resistor is verified through the above expression of the current mirror principle to obtain the predicted value of the drain current, specifically:

[0145]

[0146] Finally, in combination with the resistance value of the sampling resistor and the resistance value of the voltage-dividing resistor, the true value of the drain current can be calculated:

[0147]

[0148] In the formula, I g,real is the true value of the drain current.

[0149] Optionally, in the embodiments of the present application, a Wilson current mirror is selected to implement the mirrored current, and the data acquisition module acquires data at a frequency of 1 Hz.

[0150] The breakdown time recording module 204 is configured to stop applying the voltage stress and the thermal stress and record the total duration of applying the stress to the field effect transistor when any one of the leakage currents is greater than a preset breakdown threshold or the duration of applying the stress reaches a preset test time limit.

[0151] Due to continuously applying a high voltage and creating a high-temperature working condition, the leakage current will continuously increase until time-dependent breakdown occurs. When it is detected that time-dependent breakdown occurs, the stress application can be stopped. In the embodiments of the present application, two conditions for terminating the stress application are set: when any one of the acquired leakage currents is greater than a preset breakdown threshold, or the duration of applying the stress reaches a preset test time limit, the voltage stress and the thermal stress are stopped from being applied.

[0152] Among them, the magnitude of the breakdown threshold is dynamically adjusted according to the temperature of the field effect transistor. The test time limit is set artificially and is used as the maximum time for stopping the stress application when time-dependent breakdown does not occur in the field effect transistor. The setting of the test implementation needs to comprehensively consider the performance limitations of the test equipment, the test conditions (such as electric field strength and temperature), and the specific requirements of the user. In industrial production, the test time limit is usually set to several hours to 10 hours to quickly evaluate the reliability of the device; while in academic research, in order to obtain more comprehensive data, the test time limit may be extended to dozens of hours or even longer. Stopping the stress application when the test time reaches the preset time limit is mainly to protect the equipment and the device, avoid unnecessary damage to them caused by long-term high voltage and high temperature, save resources, and ensure the reliability of the test results.

[0153] Since the leakage current is stable at 30 - 100 μA under normal electric fields when time-dependent breakdown does not occur, and the leakage current suddenly increases to more than 200 μA when time-dependent breakdown occurs, at this time, the data acquisition module will be triggered to acquire the voltage of the sampling resistor.

[0154] In order to enable the data acquisition module to more timely respond to when to acquire, in the embodiments of the present application, a warning threshold is set during the rising process of the leakage current to prompt that the current value of the leakage current has reached a certain level and issue a breakdown warning.

[0155] Exemplarily, the warning threshold is related to the magnitude of the breakdown threshold. In the embodiments of the present application, if the breakdown threshold is set to 500 μA, then the warning threshold is set to 100 μA, that is, when the voltage of the sampling resistor is greater than 10 mV, at this time, the current of the sampling resistor is greater than 100 μA, and a breakdown warning will be issued.

[0156] The dynamic adjustment of the breakdown threshold is mainly determined adaptively according to temperature. In the embodiments of the present application, a leakage current-temperature model is constructed to calculate the breakdown threshold of the field effect transistor at the current temperature. The specific expression is:

[0157]

[0158] In the formula, I th (T) is the breakdown threshold of the field effect transistor at the current temperature, I th,0 is the initial leakage current of the field effect transistor, T is the current temperature of the field effect transistor, T0 is the initial temperature of the field effect transistor, E a is the current room temperature, and k is the Boltzmann constant.

[0159] In the embodiments of the present application, the room temperature is 31°C.

[0160] The device life prediction module 205 is configured to predict the life of the field effect transistor according to the total duration, the magnitude of the voltage stress, and the magnitude of the thermal stress.

[0161] In the embodiments of the present application, the collected current data is analyzed by mean filtering and Weibull distribution, and combined with the breakdown times under different voltage stresses and thermal stresses collected, to estimate the life of the field effect transistor. The specific expression is:

[0162]

[0163] In the formula, t bd is the predicted life of the field effect transistor, A o is a reference value, which is the life of the field effect transistor under ideal conditions without the influence of external electric field and temperature; E ox is the electric field applied to the gate oxide layer of the field effect transistor, E a is the activation energy, γ is the electric field acceleration parameter, k is the Boltzmann constant, and T is the absolute temperature.

[0164] Implementing the embodiments of the present application has the following effects:

[0165] In the embodiment of the present application, the bare chips of multiple field effect transistors are first bonded together and connected in parallel, and then placed on a current acquisition circuit based on a current mirror. Since multiple field effect transistors are bonded in parallel, the time-dependent breakdown test can be simultaneously performed on multiple field effect transistors, greatly improving the test efficiency and meeting the quality inspection requirements in mass production. Then, a fixed voltage stress is applied between the gate and drain of the field effect transistor, and at the same time, a fixed thermal stress is evenly applied to the tray of the current acquisition circuit to complete the application of extreme load conditions. By applying a high voltage to drive the oxide layer of the field effect transistor to be damaged, and at the same time, by applying a thermal stress to the tray to create a high-temperature working condition of the field effect transistor, environmental support is provided for the occurrence of time-dependent breakdown of the field effect transistor. While applying the stress, the drain current of each field effect transistor is accurately collected. When the drain current is greater than the preset breakdown threshold, it can be considered that the field effect transistor has a time-dependent breakdown. At this time, the time of the time-dependent breakdown is recorded as the breakdown time of the field effect transistor, that is, the failure time when the field effect transistor fails. Finally, based on the recorded time data and the magnitude of the applied stress, the service life and reliability of the field effect transistor under extreme working conditions are predicted. By simply collecting the drain current through a current acquisition circuit, the time of the time-dependent breakdown of the field effect transistor can be accurately judged, effectively reducing the test cost.

[0166] The third embodiment

[0167] Further, in order to execute the time-dependent breakdown test method of the field effect transistor based on parallel bonding corresponding to the above method embodiment to achieve the corresponding functions and technical effects, Figure 6 A structural diagram of a time-dependent breakdown test system for a field effect transistor based on parallel bonding is provided. For the sake of convenience of description, only the parts related to this embodiment are shown. The time-dependent breakdown test system for a field effect transistor based on parallel bonding provided by the embodiment of the present application includes:

[0168] A time-dependent breakdown test device M1 for a field effect transistor based on parallel bonding, which is used for the above method embodiment.

[0169] A current acquisition circuit M2 based on a current mirror, which is used to place several field effect transistors and collect the drain current of the field effect transistors.

[0170] Wherein, the current acquisition circuit based on the current mirror includes an immersion gold board, a wire, a conductive adhesive and a square pad;

[0171] The square pad is used to lead out the gate and source of the field effect transistor, and the conductive adhesive is used to fix the drain of the field effect transistor;

[0172] The field effect transistor is placed on the immersion gold board, and the wire shorts the source and drain of the field effect transistor and connects them to the power ground;

[0173] Among them, the total number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit based on the current mirror.

[0174] Implementing the embodiments of the present application has the following effects:

[0175] In the embodiments of the present application, the bare chips of multiple field effect transistors are first bonded together in parallel and placed on a current acquisition circuit based on a current mirror. Since multiple field effect transistors are bonded in parallel, it is possible to simultaneously perform time-dependent breakdown tests on multiple field effect transistors, which can greatly improve the test efficiency and meet the quality inspection requirements in mass production. Then, a fixed voltage stress is applied between the gate and drain of the field effect transistor, and at the same time, a fixed thermal stress is uniformly applied to the tray of the current acquisition circuit to complete the application of extreme load conditions. By applying a high voltage to drive the oxide layer of the field effect transistor to be damaged, and at the same time applying a thermal stress to the tray to create a high-temperature working condition for the field effect transistor, it provides environmental support for the occurrence of time-dependent breakdown of the field effect transistor. While applying the stress, the drain current of each field effect transistor is accurately collected. When the drain current is greater than the preset breakdown threshold, it can be considered that the field effect transistor has experienced time-dependent breakdown. At this time, the time when the time-dependent breakdown occurs is recorded as the breakdown time of the field effect transistor, that is, the failure time when the field effect transistor fails. Finally, based on the recorded time data and the magnitude of the applied stress, the service life and reliability of the field effect transistor under extreme working conditions are predicted. Just by collecting the drain current through a relatively simple current acquisition circuit, the time when the field effect transistor experiences time-dependent breakdown can be accurately judged, which can effectively reduce the test cost.

[0176] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the protection scope of the present application. It is particularly pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A time-dependent breakdown test method for a field effect transistor based on parallel bonding, characterized in that, Including: Bonding several field effect transistors in parallel on a current acquisition circuit based on a current mirror; Applying a constant voltage stress between the gate and drain of the field effect transistor, and simultaneously applying a constant thermal stress uniformly to the tray of the current acquisition circuit; While applying the voltage stress and thermal stress, collecting the drain current of each field effect transistor through a data acquisition module; When any of the drain currents is greater than a preset breakdown threshold, or the duration of applying the stress reaches a preset test time limit, stop applying the voltage stress and thermal stress and record the total duration of applying the stress to the field effect transistor; Predict the lifespan of the field effect transistor according to the total duration, the magnitude of the voltage stress, and the magnitude of the thermal stress.

2. The time-dependent breakdown test method for a field-effect transistor based on parallel bonding according to claim 1, wherein The step of bonding several field effect transistors in parallel on a current acquisition circuit based on a current mirror is specifically: Bonding the field effect transistors in parallel on the immersion gold pads of the current acquisition circuit, and fixing the drain of the field effect transistor through conductive adhesive; wherein, the immersion gold pads are used to prevent the field effect transistor from being oxidized; the number of field effect transistors that can be bonded in parallel depends on the number of channels of the current acquisition circuit; Short-circuit the source and drain of the field effect transistor through the wire of the current acquisition circuit and connect it to the power ground.

3. The time-dependent breakdown test method for a field-effect transistor based on parallel bonding according to claim 1, characterized in that, The step of applying a constant voltage stress between the gate and drain of the field effect transistor, and simultaneously applying a constant thermal stress uniformly to the tray of the current acquisition circuit is specifically: According to a preset fixed magnitude of electric field strength, apply a constant gate voltage between the gate and drain of the field effect transistor starting from the initial moment; Starting from the initial moment, apply a constant thermal stress uniformly to the entire tray of the current acquisition circuit through a heating plate, and simultaneously monitor the surface temperature of the tray in real time through a temperature sensor to ensure the stability of the thermal stress.

4. The time-dependent breakdown test method for a field-effect transistor based on parallel bonding according to claim 1, characterized in that The step of collecting the drain current of each field effect transistor through a data acquisition module is specifically: Through the current mirror of the current acquisition circuit, mirror the drain current between the gate and drain of the field effect transistor to the loop where the sampling resistor is located; Monitor the voltage on the sampling resistor through the data acquisition module, and calculate the drain current according to the resistance value of the sampling resistor and the voltage.

5. The time-dependent breakdown test method for a field effect transistor based on parallel bonding according to claim 4, wherein The step of calculating the drain current according to the resistance value of the sampling resistor and the voltage is specifically: Calculate the current of the sampling resistor according to the resistance value of the sampling resistor and the voltage; Correct the current of the sampling resistor through a preset current mirror correction formula to obtain a predicted value of the drain current; Calculate the true value of the drain current according to the predicted value of the drain current, the resistance value of the sampling resistor, and the resistance value of the voltage dividing resistor; wherein, the voltage dividing resistor is located on the loop where the sampling resistor is located.

6. The time-dependent breakdown test method for a field-effect transistor based on parallel bonding according to claim 1, wherein The step of when any of the drain currents is greater than a preset breakdown threshold, or the duration of applying the stress reaches a preset test time limit, stop applying the voltage stress and thermal stress and record the total duration of applying the stress to the field effect transistor is specifically: When the drain current of the field effect transistor is greater than a preset breakdown threshold, it can be considered that the field effect transistor has experienced time-dependent breakdown. At this time, the voltage stress and thermal stress applied to the field effect transistor are stopped, and the total duration of applying stress to the field effect transistor is recorded as the breakdown time; among them, according to the preset drain current-temperature model, the breakdown threshold is dynamically adjusted; When the duration of applying stress to the field effect transistor reaches a preset test time limit, the voltage stress and thermal stress applied to the field effect transistor are stopped, and the total duration of applying stress to the field effect transistor is recorded as the total test duration; Based on the breakdown time and the total test duration, the total duration of applying stress to the field effect transistor is obtained.

7. The time-dependent breakdown test method for a field effect transistor based on parallel bonding according to claim 6, characterized in that The breakdown threshold is dynamically adjusted according to the preset drain current-temperature model, specifically: According to the test data, the breakdown threshold at the current temperature of the field effect transistor is calculated through the drain current-temperature model; Among them, the test data includes the duration of applying thermal stress to the field effect transistor, the initial temperature of the field effect transistor, the current temperature, the initial drain current of the field effect transistor, and the current room temperature.

8. The time-dependent breakdown test method for a field effect transistor based on parallel bonding according to claim 7, characterized in that, The drain current-temperature model, the specific expression is: Wherein, I th (T) is the breakdown threshold at the current temperature of the field effect transistor, I th,0 is the initial drain current of the field effect transistor, T is the current temperature of the field effect transistor, T0 is the initial temperature of the field effect transistor, E a is the current room temperature, and k is the Boltzmann constant.

9. A time-dependent breakdown test device for a field-effect transistor based on parallel bonding, characterized in that, including: A field effect transistor parallel module, a stress application module, a drain current acquisition module, a breakdown time recording module, and a device life prediction module; Among them, the field effect transistor parallel module is used to parallelly bond several field effect transistors on a current acquisition circuit based on a current mirror; The stress application module is used to apply a constant voltage stress between the gate and drain of the field effect transistor, and at the same time apply a constant thermal stress evenly to the tray of the current acquisition circuit; The drain current acquisition module is used to collect the drain current of each field effect transistor through the data acquisition module while applying voltage stress and thermal stress; The breakdown time recording module is used to stop applying voltage stress and thermal stress and record the total duration of applying stress to the field effect transistor when any of the drain currents is greater than a preset breakdown threshold, or the duration of applying stress reaches a preset test time limit; The device life prediction module is used to predict the life of the field effect transistor according to the total duration, the magnitude of the voltage stress, and the magnitude of the thermal stress.

10. A time-dependent breakdown test system for a field effect transistor based on parallel bonding, characterized in that, including: A time-dependent breakdown test device for field effect transistors based on parallel bonding and a current acquisition circuit based on a current mirror; Among them, the time-dependent breakdown test device for field effect transistors based on parallel bonding is used to execute the time-dependent breakdown test method for field effect transistors based on parallel bonding according to any one of claims 1 to 8; The current acquisition circuit based on a current mirror is used to place several field effect transistors and collect the drain current of the field effect transistors.

11. The time-dependent breakdown test system for field effect transistors based on parallel bonding according to claim 10, wherein The current acquisition circuit based on a current mirror further includes: The current acquisition circuit based on a current mirror includes an immersion gold board, wires, conductive glue, and square pads; The square pads are used to lead out the gate and source of the field effect transistor, and the conductive glue is used to fix the drain of the field effect transistor; The field effect transistor is placed on the immersion gold board, and the wires short-circuit the source and drain of the field effect transistor and connect them to the power ground; Among them, the total number of field effect transistors that can be parallelly bonded depends on the number of channels of the current acquisition circuit based on a current mirror.

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