A chip BI electrical performance aging test method and system

Abstract

The present invention relates to the field of chip aging testing technology, and discloses a chip BI electrical performance aging testing method and system. The method comprises obtaining test time, temperature, and voltage; inputting these characteristics into a preset model to obtain predicted electrical performance parameters; obtaining the current electrical performance parameters during the test and calculating the variation characteristics between the current electrical performance parameters and the predicted values; when the variation characteristics do not meet corresponding conditions, calculating first, second, and / or third quantitative indicators; and inputting these quantitative indicators into a chip life prediction model to obtain a life prediction result. This method can accurately reflect the performance variation state or actual lifespan of a chip in actual application.

Description

Technical Field

[0001] The present invention relates to the technical field of chip aging test, and in particular to an aging test method and system for chip BI electrical performance. Background Art

[0002] Currently, chip burn-in testing is an electrical stress test method that uses applied voltage and high temperature to accelerate device electrical failure. Because the electrical stimulus applied during the burn-in process reflects the chip's worst-case operating conditions, the burn-in process simulates the chip's entire lifespan. Depending on the burn-in time and operating environment, the reliability of the test data can affect the early lifespan or wear of the device. In other words, burn-in testing can be used as a reliable device inspection to detect early-stage failures.

[0003] Existing technology simulates the stress conditions of long-term use by running chips continuously for extended periods of time at elevated temperatures. This accelerates the development of potential defects within the chips, allowing for the rapid identification of chips that may fail over time. However, accelerating chip aging in a high-temperature environment, such a single extreme condition, cannot fully simulate the complex operating conditions of chips in actual use. For example, in the early stages of aging, a chip's leakage current may only increase slightly, but as aging progresses, the increase in leakage current will gradually increase, ultimately leading to chip failure.

[0004] In summary, the test results of the existing technology cannot accurately reflect the performance change state or actual lifespan of the chip in actual application. Summary of the Invention

[0005] The present invention provides a chip BI electrical performance aging test method and system to solve the problem that the test results of the prior art cannot accurately reflect the performance change state or actual life of the chip in actual application.

[0006] In a first aspect, in order to solve the above technical problems, the present invention provides a method for aging test of chip BI electrical performance, comprising:

[0007] Obtain the test time, test temperature and test voltage before the chip aging test;

[0008] Inputting the test time, the test temperature, and the test voltage into a preset time trend model, a temperature correlation model, and a voltage correlation model, respectively, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include a predicted leakage current, a predicted threshold voltage, and a predicted driving capability value;

[0009] Obtain current electrical performance parameters during the test;

[0010] Calculating change characteristics between the current electrical performance parameters and the predicted electrical performance parameters, the change characteristics including leakage current change rate, threshold voltage drift degree and driving capability change trend graph;

[0011] When it is determined that the leakage current change rate exceeds a preset change rate threshold, a first quantitative index of the leakage current abnormal change time period is calculated;

[0012] When it is determined that the threshold voltage drift degree presents a nonlinear change, a second quantitative index of material property degradation is obtained by fitting;

[0013] When it is determined that the driving capability variation trend graph shows an accelerating trend, a third quantitative index of abnormal electric field distribution is obtained by fitting;

[0014] The first quantitative index, the second quantitative index and / or the third quantitative index are input into a preset chip life prediction model to obtain a life prediction result.

[0015] In an optional embodiment, the calculating a variation characteristic between the current electrical performance parameter and the predicted electrical performance parameter includes:

[0016] Using a data preprocessing method to clean and normalize the current electrical performance parameters to obtain processed electrical performance parameters; the processed electrical performance parameters include a processed leakage current, a processed threshold voltage, and a processed driving capability value;

[0017] Calculating a leakage current difference between the processed leakage current and the predicted leakage current, and dividing the difference by the leakage current of the predicted electrical performance parameter to obtain a leakage current change rate;

[0018] calculating a threshold voltage difference between the processed threshold voltage and the predicted threshold voltage as a threshold voltage drift degree;

[0019] A driving capability change trend graph is plotted based on the processed driving capability value, the predicted driving capability value, and corresponding time points.

[0020] In an optional embodiment, when it is determined that the leakage current change rate exceeds a preset change rate threshold, a first quantitative indicator of the leakage current abnormal change time period is calculated, including:

[0021] Determining a time period during which the difference between the leakage current change rate and a preset change rate threshold is greater than zero as a time period of abnormal leakage current change, and dividing the time period into sub-time intervals;

[0022] Calculating the average value of the leakage current change rate in each of the sub-time intervals to obtain a set of average values ​​of the leakage current change rate;

[0023] The maximum value, minimum value and average value of the mean value of the leakage current change rate in the mean value set are determined, and the maximum value, minimum value and average value of the mean value of the leakage current change rate are weightedly fitted to obtain a first quantitative index.

[0024] In an optional embodiment, when it is determined that the threshold voltage drift degree presents a nonlinear change, fitting to obtain a second quantitative index of material property degradation includes:

[0025] Acquiring a plurality of threshold voltage drift degrees at different time points, and determining whether the offset change trend of the plurality of threshold voltage drift degrees conforms to a nonlinear characteristic;

[0026] If the offset variation trend conforms to a nonlinear characteristic, polynomial fitting is used to fit the multiple threshold voltage drift degrees to obtain a drift variation curve, and key drift parameters of material property degradation are extracted from the drift variation curve;

[0027] Constructing a rate quantification model of the drift rate according to the key drift parameters;

[0028] The maximum value, minimum value and average value of the drift rate are calculated by the rate quantification model, and the maximum value, minimum value and average value of the drift rate are weightedly fitted to obtain a second quantitative index.

[0029] In an optional embodiment, when it is determined that the driving capability variation trend graph presents an accelerating trend, a third quantitative index of abnormal electric field distribution is obtained by fitting, including:

[0030] When the driving capability variation trend graph shows acceleration, exponential fitting is used to obtain fitting results, and key electric field parameters of abnormal electric field distribution are extracted from the fitting results;

[0031] constructing an electric field quantification model of abnormal electric field distribution according to the key electric field parameters;

[0032] The maximum value, minimum value and average value of the voltage stress under different temperature conditions are calculated by using the electric field quantification model, and the maximum value, minimum value and average value of the voltage stress are weightedly fitted to obtain a third quantitative index.

[0033] In an optional embodiment, the training process of the preset chip life prediction model includes:

[0034] Acquire historical chip data, extract historical quantitative indicators, and build a support vector machine model; the historical chip data includes historical leakage current change rate mean, historical drift rate, and historical voltage stress;

[0035] Adjust the kernel function type and penalty coefficient of the support vector machine model until the accuracy of the support vector machine model reaches the preset accuracy threshold;

[0036] Inputting the historical chip data into the support vector machine model to obtain a chip life prediction value;

[0037] If the chip life prediction value exceeds the preset life range, the parameters of the support vector machine model are readjusted and iterated until the chip life prediction value does not exceed the preset life range.

[0038] In a second aspect, the present invention provides an aging test system for chip BI electrical performance, comprising:

[0039] A data acquisition module is used to obtain test time, test temperature and test voltage;

[0040] a prediction module, configured to perform electrical performance prediction based on the test time, test temperature, and test voltage, in combination with a preset time trend model, a temperature correlation model, and a voltage correlation model, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include a predicted leakage current, a predicted threshold voltage, and a predicted driving capability value;

[0041] Current parameter acquisition module, used to obtain current electrical performance parameters during the test;

[0042] a change characteristic calculation module, configured to calculate, based on the current electrical performance parameters and the predicted electrical performance parameters, the change characteristics between the two, the change characteristics including the leakage current change rate, the threshold voltage drift degree, and the driving capability change trend diagram;

[0043] A first determination module is configured to determine when the leakage current change rate exceeds a preset change rate threshold, and calculate a first quantitative indicator of a leakage current abnormal change time period;

[0044] A second determination module is configured to determine when the threshold voltage drift degree presents a nonlinear change, and to obtain a second quantitative index of material property degradation by fitting;

[0045] a third determination module, configured to determine that when the driving capability variation trend graph shows an accelerating trend, a third quantitative indicator of abnormal electric field distribution is obtained by fitting;

[0046] The life prediction module is used to input the first quantitative index, the second quantitative index and / or the third quantitative index into a pre-trained chip life prediction model to obtain a life prediction result.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] The present invention discloses a chip aging test method, comprising obtaining a test time, test temperature, and test voltage before the chip aging test, inputting the test time, test temperature, and test voltage into a preset time trend model, a temperature correlation model, and a voltage correlation model, respectively, to obtain predicted electrical performance parameters; obtaining the current electrical performance parameters during the test, calculating the variation characteristics between the current electrical performance parameters and the predicted electrical performance parameters, the variation characteristics including the leakage current change rate, the threshold voltage drift degree, and a driving capability change trend graph; when it is determined that the leakage current change rate exceeds a preset change rate threshold, calculating a first quantitative index of the leakage current abnormal change time period; when it is determined that the threshold voltage drift degree exhibits a nonlinear change, fitting a second quantitative index of material property degradation; and when it is determined that the driving capability change trend graph exhibits an accelerating trend, fitting a third quantitative index of electric field distribution abnormality. The first, second, and / or third quantitative indexes are input into a preset chip life prediction model to obtain a life prediction result.

[0049] This chip aging test method obtains key parameters such as test time, temperature, and voltage before testing and inputs these parameters into pre-set time trend models, temperature correlation models, and voltage correlation models to predict the chip's electrical performance parameters under various operating conditions, simulating the complex operating conditions encountered in actual use. During the test, the system monitors and records the changes in the current electrical performance parameters in real time and compares them with the predicted results to promptly identify any deviations from the expected trend. Once an abnormal change is detected, such as an increase in leakage current exceeding a set threshold or a nonlinear drift in the threshold voltage, the system automatically outputs a corresponding early degradation signal and calculates corresponding quantitative indicators, including a first quantitative indicator for the time period of abnormal leakage current change, a second quantitative indicator for material property degradation, and a third quantitative indicator for abnormal electric field distribution. This method accurately identifies early degradation signals of the chip and promptly identifies potential aging issues. Finally, these quantitative indicators are integrated and input into a pre-trained life prediction model to derive an estimate of the chip's remaining useful life. This method incorporates the influence of multiple aging factors to accurately assess the chip's useful life.

[0050] In summary, this method can simulate various complex working conditions of the chip in actual use, monitor the changes in the chip's electrical performance parameters during use, promptly discover potential aging problems, and accurately evaluate the chip's service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a flow chart of a chip BI electrical performance aging test method provided by the first embodiment of the present invention;

[0052] Figure 21 is a schematic structural diagram of a chip BI electrical performance aging test system provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0054] Reference Figure 1 The first embodiment of the present invention provides an aging test method for the electrical performance of a chip BI, comprising the following steps:

[0055] S1, obtaining the test time, test temperature and test voltage before the chip aging test;

[0056] S2, inputting the test time, the test temperature, and the test voltage into a preset time trend model, a temperature correlation model, and a voltage correlation model, respectively, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include a predicted leakage current, a predicted threshold voltage, and a predicted driving capability;

[0057] S3, obtaining the current electrical performance parameters during the test;

[0058] S4, calculating the change characteristics between the current electrical performance parameters and the predicted electrical performance parameters, wherein the change characteristics include a leakage current change rate, a threshold voltage drift degree, and a driving capability change trend diagram;

[0059] S5, when it is determined that the leakage current change rate exceeds a preset change rate threshold, calculating a first quantitative indicator of the leakage current abnormal change time period;

[0060] S6, when it is determined that the threshold voltage drift degree presents a nonlinear change, fitting to obtain a second quantitative index of material property degradation;

[0061] S7, when it is determined that the driving capability variation trend graph shows an accelerating trend, fitting to obtain a third quantitative indicator of abnormal electric field distribution;

[0062] S8, inputting the first quantitative index, the second quantitative index and / or the third quantitative index into a preset chip life prediction model to obtain a life prediction result.

[0063] In step S1 , it is necessary to obtain the test time, test temperature, and test voltage before the chip aging test.

[0064] It should be noted that the test time is a reference time point or time period set before the aging test is performed. The test temperature is the specific temperature condition of the chip's environment before the aging test begins. The test voltage is the voltage value applied to the chip before the aging test is started. The test time is obtained by recording the exact time point before the aging test using the system clock. The test temperature is obtained by measuring and recording the specific temperature of the chip's environment using a high-precision temperature sensor. The test voltage is obtained by accurately measuring and recording the voltage value applied to the chip before the aging test is started using a voltage measuring instrument. The obtained test time, test temperature, and test voltage are respectively input into the preset time trend model, temperature correlation model, and voltage correlation model. These models are used to generate predicted electrical performance parameters about the chip's future performance. The predicted electrical performance parameters include predicted leakage current, predicted threshold voltage, and predicted driving capability, thus laying the foundation for evaluating chip life and performance changes.

[0065] In step S2, the test time, the test temperature and the test voltage are respectively input into a preset time trend model, a temperature correlation model and a voltage correlation model to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include predicted leakage current, predicted threshold voltage and predicted driving capability.

[0066] It is worth noting that the pre-defined time trend model is constructed by pre-processing the time series data for three electrical performance parameters, namely, leakage current, threshold voltage, and drive capability, to remove outliers and noise. A linear regression algorithm is then used to fit the pre-processed data to the leakage current, threshold voltage, and drive capability data, resulting in a linear trend model of each parameter over time. If the goodness-of-fit of the linear regression model falls below a pre-defined threshold, a polynomial regression algorithm is used for quadratic fitting to obtain a more accurate nonlinear trend model. The pre-defined temperature correlation model relies on an understanding of the Arrhenius equation or its extended form, which describes the temperature-dependent trends of electrical performance parameters in semiconductor devices. Key electrical performance parameters, such as leakage current, threshold voltage, and drive capability, are measured across a range of temperatures. The raw data are pre-processed to remove outliers or normalize the data. Time series analysis is then used to analyze the data to construct a relationship between temperature and electrical performance. Based on the analysis results, a polynomial regression model is then fitted to the data. For Arrhenius-type behavior, a natural logarithm transformation is used to convert the nonlinear relationship into a linear one, enabling the least squares method to be used for fitting. The model accuracy is then evaluated using an independent test set to optimize prediction performance. A voltage-correlation model was constructed by performing device-level simulations with the help of TCAD tools such as Silvaco and Sentaurus. The changes in key electrical performance parameters were observed and recorded under different voltage conditions. High-voltage stress tests were performed to obtain actual device responses and compared with simulation results to ensure model accuracy and applicability. The relationship between voltage and electrical performance parameters was determined based on simulation and experimental results and described using a polynomial regression model. The effectiveness and practicality of the model were ensured through continuous verification and optimization.

[0067] In this embodiment, by combining linear regression and polynomial regression algorithms, the most suitable model type is automatically selected according to the goodness of fit of the data, so that the changing trend of electrical performance parameters over time can be captured more accurately. This adaptive method can effectively handle linear and nonlinear change patterns and improve the accuracy of prediction. The preset temperature correlation model is based on the Arrhenius equation or its extended form, which makes the model not only suitable for describing simple thermal activation processes, but also for dealing with complex temperature-dependent behaviors. The nonlinear relationship is converted into a linear relationship using the natural logarithm transformation, which facilitates the use of the least squares method for accurate fitting, and polynomial regression is used to further improve the model accuracy. This method enhances the applicability of the model under different temperature conditions and ensures that reliable prediction results can be provided within a wide range of operating temperature ranges. The voltage correlation model uses advanced TCAD simulation tools such as Silvaco and Sentaurus for device-level simulation, and is verified and optimized in combination with data from actual high-voltage stress tests, ensuring that the model has both a theoretical basis and has been tested in practice, accurately reflecting the influence of voltage on electrical performance parameters.

[0068] For example, the test duration is set to 1,000 hours, the test temperature is set to 130 degrees Celsius, and the test voltage is set to 3.3 volts. The test time is input into the time trend model, and analysis can predict the leakage current trend. Through previous model training, the time trend model has already grasped the temporal variation of chip leakage current. When the test duration is set to 1,000 hours, the time trend model predicts that the leakage current will gradually increase from an initial value of 0.2 mA to 0.8 mA, showing a nearly linear growth trend. This growth trend reflects the aging effects of the chip's internal structure over time. The temperature-dependent model is used to predict changes in threshold voltage. When the test temperature is 130 degrees Celsius, the temperature-dependent model predicts that the threshold voltage will decrease from an initial value of 0.7 V to 0.5 V. This decrease in threshold voltage indicates a change in the chip's conduction characteristics, which is directly related to the increase in temperature. High temperatures accelerate carrier migration within the chip, causing the threshold voltage to drift. The voltage-dependent model is used to predict changes in driving capability. When the test voltage is 3.3V, the voltage-dependent model predicts that the driving capability will decrease from the initial value of 5mA / V to 3mA / V.

[0069] In step S3, the current electrical performance parameters during the test are obtained.

[0070] It should be noted that electrical performance parameters include leakage current, threshold voltage and driving capability, which directly reflect the state of the chip under actual working conditions. Among them, leakage current refers to the tiny current flowing through the two ends of the transistor when it is in the off state, and the leakage current can be measured by a precision ammeter. The threshold voltage refers to the minimum gate voltage required to switch the transistor from the off state to the on state. The threshold voltage is determined by adjusting the input voltage and monitoring the output response. Driving capability refers to the maximum output current that the transistor can provide, and the driving capability can be evaluated using a load test circuit. The current electrical performance parameters obtained are compared and analyzed with the parameters predicted earlier based on the time trend model, temperature correlation model and voltage correlation model to calculate the change characteristics between the two, where the change characteristics include the leakage current change rate, the threshold voltage drift degree and the driving capability change trend.

[0071] In step S4, the variation characteristics between the current electrical performance parameters and the predicted electrical performance parameters are calculated, where the variation characteristics include the leakage current variation rate, the threshold voltage drift degree, and the driving capability variation trend diagram.

[0072] In one implementation, the calculating a variation characteristic between the current electrical performance parameter and the predicted electrical performance parameter includes:

[0073] Using a data preprocessing method to clean and normalize the current electrical performance parameters to obtain processed electrical performance parameters, wherein the processed electrical performance parameters include a processed leakage current, a processed threshold voltage, and a processed driving capability value;

[0074] Calculating a leakage current difference between the processed leakage current and the predicted leakage current, and dividing the difference by the leakage current of the predicted electrical performance parameter to obtain a leakage current change rate;

[0075] calculating a threshold voltage difference between the processed threshold voltage and the predicted threshold voltage as a threshold voltage drift degree;

[0076] A driving capability change trend graph is plotted based on the processed driving capability value, the predicted driving capability value, and corresponding time points.

[0077] It should be noted that before using the data preprocessing method to clean and normalize the current electrical performance parameters, the consistency and integrity of the data should be checked first to ensure that all relevant data points are valid and suitable for subsequent analysis. Data cleaning not only includes removing obvious errors or outliers, but may also involve operations such as filling missing values ​​and correcting data entry errors; normalization processing aims to convert data of different magnitudes to the same scale for easy comparison and analysis. This step is crucial to eliminating deviations caused by differences in measurement units. When drawing the driving capacity change trend graph, mark the time point on the horizontal axis and the driving current change of the driving capacity on the vertical axis. Then, different lines are used to represent the actual processed driving capacity value and the predicted driving capacity value.

[0078] It's worth noting that the predicted electrical performance parameters are based on time trend models, temperature correlation models, and voltage correlation models. These models are trained using extensive historical data, covering a wide range of scenarios under diverse conditions to ensure comprehensiveness. To ensure good generalization and prediction accuracy, the model is trained using a cross-validation approach. The dataset is divided into a training set and a validation set, and the model is continuously optimized through iteration until the error between the predicted results and the actual observed values ​​is minimized.

[0079] In step S5, when it is determined that the leakage current change rate exceeds the preset change rate threshold, a first quantitative index of the leakage current abnormal change time period is calculated.

[0080] It should be noted that when the leakage current change rate does not exceed the preset change rate threshold, we determine that the leakage current is changing normally and no additional processing is performed.

[0081] In one embodiment, when it is determined that the leakage current change rate exceeds a preset change rate threshold, calculating a first quantitative indicator of the leakage current abnormal change time period includes:

[0082] Determining a time period during which the difference between the leakage current change rate and a preset change rate threshold is greater than zero as a time period of abnormal leakage current change, and dividing the time period into sub-time intervals;

[0083] Calculating the average value of the leakage current change rate in each of the sub-time intervals to obtain a set of average values ​​of the leakage current change rate;

[0084] The maximum value, minimum value and average value of the mean value of the leakage current change rate in the mean value set are determined, and the maximum value, minimum value and average value of the mean value of the leakage current change rate are weightedly fitted to obtain a first quantitative index.

[0085] It should be noted that the leakage current change rate is compared with the preset change rate threshold, and the time period in which the difference between the two is greater than zero is identified as the time period of abnormal leakage current change, and the time period is divided to obtain multiple sub-time intervals; then, the mean leakage current change rate is calculated for each sub-time interval, thereby forming a set containing the mean leakage current change rate of each sub-time interval; next, the maximum value, minimum value and average value of the leakage current change rate are determined from the mean value set; finally, the maximum value, minimum value and average value are weightedly fitted according to the preset value weights to obtain the first quantitative index.

[0086] In step S6, when it is determined that the threshold voltage drift degree presents a nonlinear change, a second quantitative index of material property degradation is obtained by fitting.

[0087] In one embodiment, when it is determined that the threshold voltage drift degree presents a nonlinear change, fitting to obtain a second quantitative index of material property degradation includes:

[0088] Acquiring a plurality of threshold voltage drift degrees at different time points, and determining whether the offset change trend of the plurality of threshold voltage drift degrees conforms to a nonlinear characteristic;

[0089] If the offset variation trend conforms to a nonlinear characteristic, polynomial fitting is used to fit the multiple threshold voltage drift degrees to obtain a drift variation curve, and key drift parameters of material property degradation are extracted from the drift variation curve;

[0090] Constructing a rate quantification model of the drift rate according to the key drift parameters;

[0091] The maximum value, minimum value and average value of the drift rate are calculated by the rate quantification model, and the maximum value, minimum value and average value of the drift rate are weightedly fitted to obtain a second quantitative index.

[0092] It should be noted that the second quantitative indicator of material property degradation is obtained by weighted fitting the maximum, minimum, and average values ​​of the drift rate. The drift rate is a key drift parameter for material property degradation and refers to the change in threshold voltage per unit time. The rate quantification model for the drift rate is obtained by fitting a linear model. If the threshold voltage drift degree shows a linear change, no processing is performed.

[0093] For example, the threshold voltage data is initially at 2V. As aging increases, the threshold voltage drifts. First, determine whether the threshold voltage drift exhibits nonlinear characteristics. This can be done by plotting a scatter plot of the data. If the data points show a distinct curved distribution within the coordinate system, this indicates a nonlinear characteristic. After determining that nonlinear characteristics are present, a polynomial fitting method is used to analyze the threshold voltage drift. The appropriate polynomial order is selected during fitting. A high order may lead to overfitting, while a low order may not accurately describe the variation trend. For example, after 1,000 hours of stress testing, the threshold voltage of a batch of devices drifted from 2V to 3V, showing a trend of initially rising slowly followed by a rapid increase. A third-order polynomial fitting yields a relatively accurate fitting curve. From the fitting results, a key drift parameter, namely the drift rate, can be extracted. For example, under specific stress conditions, the device drift rate reaches its maximum after 500 hours. This time point can be used as the key drift parameter. Combining these parameters can determine the degradation pattern of material properties. For example, under high-temperature conditions, the threshold voltage drift rate exhibits an exponential relationship with temperature. Based on the extracted key drift parameters, a quantitative model for material property degradation is constructed. This model takes into account factors such as temperature and electric field strength. This model can calculate the maximum, minimum, and average values ​​of material property degradation under different operating conditions. For example, under rated operating conditions, the threshold voltage drift of a batch of devices has a maximum of 1.5 volts, a minimum of 0.5 volts, and an average of 1 volt. Based on these characteristic values, a weighted approach is used to fit and derive a second quantitative index.

[0094] In step S7, when it is determined that the driving capability variation trend diagram presents an accelerating trend, a third quantitative index of abnormal electric field distribution is obtained by fitting.

[0095] In one embodiment, when it is determined that the driving capability variation trend graph presents an accelerating trend, fitting to obtain a third indicator of abnormal electric field distribution includes:

[0096] When the driving capability variation trend graph shows acceleration, exponential fitting is used to obtain fitting results, and key electric field parameters of abnormal electric field distribution are extracted from the fitting results;

[0097] constructing an electric field quantification model of abnormal electric field distribution according to the key electric field parameters;

[0098] The maximum value, minimum value and average value of the voltage stress under different temperature conditions are calculated by using the electric field quantification model, and the maximum value, minimum value and average value of the voltage stress are weightedly fitted to obtain a third quantitative index.

[0099] It should be noted that driving capability is related to threshold voltage, carrier mobility, on-resistance, and drive current. Driving capability reflects the ability of a power device to control load current, and the driving capability trend can be determined by measuring the drive current. The third quantitative indicator of electric field distribution anomaly is obtained by weighted fitting the maximum, minimum, and average values ​​of the voltage stress, where voltage stress is a key electric field parameter for electric field distribution anomalies. If the driving capability trend graph does not show an accelerating trend, no processing is performed.

[0100] It is worth noting that when an acceleration trend is determined, the exponential fitting method is used to fit the driving capability change data to obtain the fitting results, and the key electric field parameters related to the abnormal electric field distribution are extracted from them. Next, based on these key electric field parameters, an electric field quantification model is constructed to describe the abnormal electric field distribution. This model aims to quantify the impact of voltage stress on the electric field distribution under different conditions and is constructed through a support vector machine model. Subsequently, the electric field quantification model is used to calculate the maximum, minimum and average values ​​of the voltage stress under different temperature conditions. Taking into account the differences in the importance of different voltage stresses, these statistics are weightedly fitted through appropriate weight allocation, and finally a third quantitative indicator that comprehensively reflects the degree of abnormal electric field distribution is obtained.

[0101] For example, taking a MOSFET device as an example, during a 500-hour stress test, the drive current slowly decreases to 90 mA in the first 200 hours, then rapidly drops to 60 mA in the last 300 hours. This trend is consistent with accelerated decay characteristics and requires in-depth analysis using exponential fitting methods. Exponential fitting can be used to extract key electric field parameters that indicate an abnormal electric field distribution. For example, in the gate region, uneven electric field distribution leads to carrier injection, accelerating the decay of driving capability. The fitting curve can be used to determine the time point and degree of the electric field anomaly. For example, the device experiences an inflection point at 300 hours, after which the electric field anomaly intensifies, causing a rapid decline in driving capability. Based on the extracted key electric field parameters, an electric field quantification model is constructed to identify the abnormal electric field distribution. An electric field quantification model must consider multiple influencing factors. In practical applications, temperature and voltage stress can affect the electric field distribution. For example, under high temperature and high pressure conditions, the electric field anomaly is more pronounced. By establishing an electric field quantification model, the degree of electric field anomaly can be predicted under different operating conditions. Specifically, at rated operating temperature, the maximum electric field strength of a batch of devices is 3,000 volts per centimeter, the minimum is 1,000 volts per centimeter, and the average is 2,000 volts per centimeter. Using the electric field quantification model, the maximum, minimum, and average values ​​of the electric field distribution anomaly are calculated. The maximum, minimum, and average values ​​of the voltage stress are then weighted and fitted to produce a third quantitative index.

[0102] In step S8, the first quantitative index, the second quantitative index and / or the third quantitative index are input into a preset chip life prediction model to obtain a life prediction result.

[0103] In one embodiment, the training process of the preset chip life prediction model includes:

[0104] Acquire historical chip data, extract historical quantitative indicators, and build a support vector machine model; the historical chip data includes historical leakage current change rate mean, historical drift rate, and historical voltage stress;

[0105] Adjust the kernel function type and penalty coefficient of the support vector machine model until the accuracy of the support vector machine model reaches the preset accuracy threshold;

[0106] Inputting the historical chip data into the support vector machine model to obtain a chip life prediction value;

[0107] If the chip life prediction value exceeds the preset life range, the parameters of the support vector machine model are readjusted and iterated until the chip life prediction value does not exceed the preset life range.

[0108] It should be noted that the historical chip data includes the historical mean leakage current rate of change, historical drift rate, and historical voltage stress. A support vector machine model is initially trained on this data. The initial model can use a radial basis function as the kernel function and a default penalty coefficient C is set. To verify the model's effectiveness, the dataset can be divided into a training set and a test set. The training set is used to train the model, and the test set is used to evaluate the model's accuracy. If the initial evaluation finds that the model's accuracy does not meet the preset standard, the kernel function type or the penalty coefficient C value is adjusted until a model configuration that provides sufficiently high prediction accuracy is found. Once the optimal model configuration is determined, it can be used to predict new chip lifetime values. If the predicted lifetime value based on the model falls outside the expected range, the model parameters are adjusted to ensure that all predictions are within a reasonable range. In addition, to more comprehensively understand the factors affecting chip aging, the impact of electric field distribution on chip performance should also be considered. By performing exponential fitting on the electric field distribution data, it is possible to identify areas with abnormalities and update previously defined key quantitative indicators. If any key parameter shows an abnormality exceeding the set safety threshold, the quantitative indicators need to be adjusted again and linear regression methods are used to refit these updated indicators to capture the accelerated degradation of material properties. As real-time data continues to flow in, the performance of newly produced chips is continuously monitored and input into the trained support vector machine model to obtain the latest chip life prediction results. If the prediction results show large fluctuations that exceed the pre-set fluctuation threshold, the model parameters are optimized to ensure stable and reliable prediction results.

[0109] The following describes the working process of the present invention using a relatively common scenario as an example.

[0110] A high-performance computing server chip was subjected to burn-in testing. Designed to process large amounts of data, this chip's reliability and longevity are crucial. To ensure this, all necessary initial parameters were collected before testing began: the test duration was set to 1000 hours, the standard duration for highly accelerated life testing (HTOL); the test temperature was set to 125 degrees Celsius, simulating operating conditions in an extreme environment; and the test voltage was set to 1.8 volts, the maximum operating voltage this chip model can withstand.

[0111] Based on these initial parameters, the chip's electrical performance parameters were predicted using pre-set time trend models, temperature correlation models, and voltage correlation models. It was expected that the leakage current would remain at approximately 1 microampere, the threshold voltage would be around 0.7 volts, and the drive capability would reach 20 milliamperes. However, as testing progressed, the actual measured data diverged from the predictions. The leakage current rose to 1.2 microamperes, representing a 20% increase, far exceeding the expected 5% rate of change threshold. Simultaneously, the threshold voltage dropped to 0.68 volts, indicating a nonlinear drift. As for the drive capability, it weakened slightly to 19 milliamperes. To account for the abnormal leakage current increase, the abnormal time interval was divided into subintervals, from the 800th to the 1400th hour of testing. The mean leakage current change rate within each subinterval was calculated to obtain a set of leakage current change rate means. The maximum, minimum, and average values ​​of the leakage current change rate mean within the set were determined, and a weighted fit was performed on the maximum, minimum, and average values ​​of the leakage current change rate mean to obtain the first quantitative index. For the nonlinear drift of the threshold voltage, a fitting analysis was performed to determine the offset rate of material property degradation. A rate quantification model for the drift rate was constructed. The maximum, minimum, and average values ​​of the drift rate were calculated using this rate quantification model. A weighted fit was performed on these values ​​to generate a second quantitative indicator. The driving capability trend was normal and no additional processing was performed.

[0112] Finally, these quantitative indicators are input into the pre-trained chip life prediction model, and it is concluded that the chip is expected to operate stably for five years under normal working conditions.

[0113] In summary, this method can simulate various complex working conditions of the chip in actual use, monitor the changes in the chip's electrical performance parameters during use, promptly discover potential aging problems, and accurately evaluate the chip's service life.

[0114] The present invention simulates various complex working conditions of the chip in actual use and monitors the changes in the electrical performance parameters of the chip during use, thereby achieving an accurate assessment of the performance change state and service life of the chip in actual application.

[0115] Reference Figure 2 The second embodiment of the present invention provides an aging test system for chip BI electrical performance, comprising:

[0116] A data acquisition module is used to obtain test time, test temperature and test voltage;

[0117] a prediction module, configured to input the test time, the test temperature, and the test voltage into a preset time trend model, a temperature correlation model, and a voltage correlation model, respectively, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include predicted leakage current, predicted threshold voltage, and predicted driving capability;

[0118] Current parameter acquisition module, used to obtain current electrical performance parameters during the test;

[0119] a change characteristic calculation module, configured to calculate, based on the current electrical performance parameters and the predicted electrical performance parameters, the change characteristics between the two, the change characteristics including the leakage current change rate, the threshold voltage drift degree, and the driving capability change trend diagram;

[0120] A first determination module is configured to determine when the leakage current change rate exceeds a preset change rate threshold, and calculate a first quantitative indicator of a leakage current abnormal change time period;

[0121] A second determination module is configured to determine when the threshold voltage drift degree presents a nonlinear change, and to obtain a second quantitative index of material property degradation by fitting;

[0122] a third determination module, configured to determine that when the driving capability variation trend graph shows an accelerating trend, a third quantitative indicator of abnormal electric field distribution is obtained by fitting;

[0123] The life prediction module is used to input the first quantitative index, the second quantitative index and / or the third quantitative index into a pre-trained chip life prediction model to obtain a life prediction result.

[0124] It should be noted that the chip BI electrical performance aging test system provided in an embodiment of the present invention is used to execute all the process steps of the chip BI electrical performance aging test method in the above embodiment. The working principles and beneficial effects of the two correspond one to one, so they will not be repeated here.

[0125] An embodiment of the present invention further provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a life prediction model. When the processor executes the computer program, the above-mentioned calculation and model building steps are implemented, such as Figure 1 Alternatively, the processor implements the functions of the modules / units in the above-mentioned device embodiments when executing the computer program.

[0126] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0127] The electronic device may be a computing device such as a desktop computer, notebook, PDA, or smart tablet. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will appreciate that the aforementioned components are merely examples of electronic devices and do not constitute a limitation of the electronic device. The electronic device may include more or fewer components than those described above, or a combination of certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, and the like.

[0128] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. The processor is the control center of the electronic device and connects various parts of the entire electronic device using various interfaces and lines.

[0129] The memory can be used to store the computer programs and / or modules. The processor implements the various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and accessing the data stored in the memory. The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the mobile phone (such as audio data, a phone book, etc.). Furthermore, the memory may include high-speed random access memory and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0130] If the module / unit integrated into the electronic device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0131] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0132] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A chip BI electrical performance aging test method, characterized in that: include: Obtain the test time, test temperature and test voltage before the chip aging test; Inputting the test time, the test temperature, and the test voltage into a preset time trend model, a temperature correlation model, and a voltage correlation model, respectively, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include a predicted leakage current, a predicted threshold voltage, and a predicted driving capability value; Obtain current electrical performance parameters during the test; Calculating change characteristics between the current electrical performance parameters and the predicted electrical performance parameters, the change characteristics including leakage current change rate, threshold voltage drift degree and driving capability change trend graph; When it is determined that the leakage current change rate exceeds a preset change rate threshold, a first quantitative index of the leakage current abnormal change time period is calculated; When it is determined that the threshold voltage drift degree presents a nonlinear change, a second quantitative index of material property degradation is obtained by fitting; When it is determined that the driving capability variation trend graph shows an accelerating trend, a third quantitative index of abnormal electric field distribution is obtained by fitting; The first quantitative index, the second quantitative index and / or the third quantitative index are input into a preset chip life prediction model to obtain a life prediction result.

2. The aging test method for chip BI electrical performance according to claim 1, characterized in that: The calculating a change characteristic between the current electrical performance parameter and the predicted electrical performance parameter includes: Using a data preprocessing method to clean and normalize the current electrical performance parameters to obtain processed electrical performance parameters, wherein the processed electrical performance parameters include a processed leakage current, a processed threshold voltage, and a processed driving capability value; Calculating a leakage current difference between the processed leakage current and the predicted leakage current, and dividing the difference by the leakage current of the predicted electrical performance parameter to obtain a leakage current change rate; calculating a threshold voltage difference between the processed threshold voltage and the predicted threshold voltage as a threshold voltage drift degree; A driving capability change trend graph is plotted based on the processed driving capability value, the predicted driving capability value, and corresponding time points.

3. The aging test method for chip BI electrical performance according to claim 1, characterized in that: When it is determined that the leakage current change rate exceeds a preset change rate threshold, the first quantitative indicator of the leakage current abnormal change time period is calculated, including: Determining a time period during which the difference between the leakage current change rate and a preset change rate threshold is greater than zero as a time period of abnormal leakage current change, and dividing the time period into sub-time intervals; Calculating the average value of the leakage current change rate in each of the sub-time intervals to obtain a set of average values ​​of the leakage current change rate; The maximum value, minimum value and average value of the mean value of the leakage current change rate in the mean value set are determined, and the maximum value, minimum value and average value of the mean value of the leakage current change rate are weightedly fitted to obtain a first quantitative index.

4. The aging test method for chip BI electrical performance according to claim 1, characterized in that: When it is determined that the threshold voltage drift degree presents a nonlinear change, a second quantitative index of material property degradation is obtained by fitting, including: Acquiring a plurality of threshold voltage drift degrees at different time points, and determining whether the offset change trend of the plurality of threshold voltage drift degrees conforms to a nonlinear characteristic; If the offset variation trend conforms to a nonlinear characteristic, polynomial fitting is used to fit the multiple threshold voltage drift degrees to obtain a drift variation curve, and key drift parameters of material property degradation are extracted from the drift variation curve; Constructing a rate quantification model of the drift rate according to the key drift parameters; The maximum value, minimum value and average value of the drift rate are calculated by the rate quantification model, and the maximum value, minimum value and average value of the drift rate are weightedly fitted to obtain a second quantitative index.

5. The aging test method for chip BI electrical performance according to claim 1, characterized in that: When it is determined that the driving capability variation trend graph shows an accelerating trend, a third quantitative index of abnormal electric field distribution is obtained by fitting, including: When the driving capability variation trend graph shows acceleration, exponential fitting is used to obtain fitting results, and key electric field parameters of abnormal electric field distribution are extracted from the fitting results; constructing an electric field quantification model of abnormal electric field distribution according to the key electric field parameters; The maximum value, minimum value and average value of the voltage stress under different temperature conditions are calculated by using the electric field quantification model, and the maximum value, minimum value and average value of the voltage stress are weightedly fitted to obtain a third quantitative index.

6. The aging test method for chip BI electrical performance according to claim 1, characterized in that: The training process of the preset chip life prediction model includes: Acquire historical chip data, extract historical quantitative indicators, and build a support vector machine model; the historical chip data includes historical leakage current change rate mean, historical drift rate, and historical voltage stress; Adjust the kernel function type and penalty coefficient of the support vector machine model until the accuracy of the support vector machine model reaches the preset accuracy threshold; Inputting the historical chip data into the support vector machine model to obtain a chip life prediction value; If the chip life prediction value exceeds the preset life range, the parameters of the support vector machine model are readjusted and iterated until the chip life prediction value does not exceed the preset life range.

7. The aging test method for chip BI electrical performance according to claim 1, characterized in that: After determining that the leakage current change rate exceeds a preset change rate threshold, the method further includes: Obtaining physical characteristic parameters of the gate oxide layer, and determining a breakdown degree of the gate oxide layer according to the physical characteristic parameters; When the breakdown degree is early breakdown, an early signal including gate oxide layer breakdown is output.

8. The aging test method for chip BI electrical performance according to claim 1, characterized in that: After determining that the threshold voltage drift degree exhibits a nonlinear change, the method further includes: Get the current temperature; When the drift change shows nonlinearity and the temperature exceeds a preset temperature threshold, the output includes an early signal of a high-temperature accelerated oxidation process.

9. The aging test method for chip BI electrical performance according to claim 1, characterized in that: After determining that the driving capability change trend graph shows an accelerating trend, the method further includes: Obtain current voltage data and extract quantitative indicators of high voltage stress conditions; Establishing a correlation model between the quantitative index of the high voltage stress condition and the abnormal electric field distribution; When the driving capability variation trend graph shows acceleration and the voltage data exceeds a preset voltage threshold, an early signal including an abnormal electric field distribution caused by a high voltage stress condition is output.

10. A chip BI electrical performance aging test system, characterized in that: include: A data acquisition module is used to obtain test time, test temperature and test voltage; a prediction module, configured to perform electrical performance prediction based on the test time, test temperature, and test voltage, in combination with a preset time trend model, a temperature correlation model, and a voltage correlation model, to obtain predicted electrical performance parameters, wherein the predicted electrical performance parameters include a predicted leakage current, a predicted threshold voltage, and a predicted driving capability value; Current parameter acquisition module, used to obtain current electrical performance parameters during the test; a change characteristic calculation module, configured to calculate, based on the current electrical performance parameters and the predicted electrical performance parameters, the change characteristics between the two, the change characteristics including the leakage current change rate, the threshold voltage drift degree, and the driving capability change trend diagram; A first determination module is configured to determine when the leakage current change rate exceeds a preset change rate threshold, and calculate a first quantitative indicator of a leakage current abnormal change time period; A second determination module is configured to determine when the threshold voltage drift degree presents a nonlinear change, and to obtain a second quantitative index of material property degradation by fitting; a third determination module, configured to determine that when the driving capability variation trend graph shows an accelerating trend, a third quantitative indicator of abnormal electric field distribution is obtained by fitting; The life prediction module is used to input the first quantitative index, the second quantitative index and / or the third quantitative index into a pre-trained chip life prediction model to obtain a life prediction result.

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