LDO quick response circuit with zero suppression function based on MNMC architecture

Abstract

The invention discloses an LDO quick response circuit with a zero suppression function based on an MNMC architecture. The LDO quick response circuit comprises a feedforward compensation circuit module, a first-stage amplification circuit module gm1, a second-stage amplification circuit module gm2 and a third-stage amplification circuit module gm3, wherein the first-stage amplification circuit module gm1, the second-stage amplification circuit module gm2 and the third-stage amplification circuit module gm3 are sequentially connected; the feed-forward compensation circuit module comprises a feed-forward capacitor Cmf0, and a feed-forward amplifier gmf0, a feed-forward resistor Rf0 and a feed-forward amplifier gmf1 which are connected in sequence; the input end of the feed-forward amplifier gmf0 is connected to the input end of the first-stage amplification circuit module gm1, the output end of the feed-forward amplifier gmf1 is connected between the second-stage amplification circuit module gm2 and the third-stage amplification circuit module gm3, and the two ends of the feed-forward capacitor Cmf0 are connected to the input end and the output end of the feed-forward amplifier gmf1 respectively. By introducing the feed-forward compensation circuit module, a low-frequency left half plane (LHP) zero point is constructed to counteract the limitation of a secondary dominant pole on the bandwidth, so that the system bandwidth is effectively expanded, meanwhile, the high-frequency alternating-current gain is also improved, the secondary dominant pole is pushed away to a higher frequency band, and the overall frequency response characteristic of the circuit is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit power supplies, and in particular to an LDO fast response circuit with zero point suppression function based on the MNMC architecture. Background Art

[0002] With the rapid development of integrated circuit technology, miniaturization, high performance, and low power consumption have become the core requirements of modern electronic system design. As a key component in the field of power management, the low dropout linear regulator (LDO) plays an important role in mixed-signal chips. While providing a stable output voltage in high-density integration and across the full load range, the LDO also needs to have excellent transient response characteristics to cope with the disturbances caused by load mutations at the nanosecond level.

[0003] The design of LDO circuits faces the complexity of stability compensation in multi-stage operational amplifier structures, especially the phase margin requirements of multi-pole systems. Existing compensation techniques such as nested Miller compensation and feed-forward path optimization, although improving the system stability to a certain extent, have problems such as complex circuits, high power consumption, or generating more zeros and poles, resulting in poor overall circuit stability, and are difficult to be widely applied. Summary of the Invention

[0004] In view of the above situation, it is necessary to provide an LDO circuit with zero point suppression function based on the MNMC architecture to solve the problems of complex circuits, high power consumption, or generating more zeros and poles in the existing LDO circuit design, resulting in poor overall circuit stability.

[0005] To achieve the above object, the technical solution of the present invention is as follows: An LDO fast response circuit with zero point suppression function based on the MNMC architecture, comprising: a feed-forward compensation circuit module and a first-stage amplifier circuit module gm1, a second-stage amplifier circuit module gm2, and a third-stage amplifier circuit module gm3 connected in sequence;

[0006] The feed-forward compensation circuit module includes a feed-forward capacitor Cmf0 and a feed-forward amplifier gmf0, a feed-forward resistor Rf0, and a feed-forward amplifier gmf1 connected in sequence;

[0007] The input end of the feed-forward amplifier gmf0 is connected to the input end of the first-stage amplifier circuit module gm1, the output end of the feed-forward amplifier gmf1 is connected between the second-stage amplifier circuit module gm2 and the third-stage amplifier circuit module gm3, and both ends of the feed-forward capacitor Cmf0 are respectively connected to the input end and the output end of the feed-forward amplifier gmf1.

[0008] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, a first frequency compensation capacitor Cm1 is further included. One end of the first frequency compensation capacitor Cm1 is connected to the input end of the second-stage amplifier circuit module gm2, and the other end is connected to the output end of the third-stage amplifier circuit module gm3.

[0009] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, a second frequency compensation circuit is further included. The second frequency compensation circuit includes a second frequency compensation capacitor Cm2 and an NMOS transistor M9. One end of the second frequency compensation capacitor Cm2 is connected to the input end of the third-stage amplifier circuit module gm3 through the NMOS transistor M9, and the NMOS transistor M9 is a common-gate transistor.

[0010] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, the feedforward amplifier gmf0 includes a PMOS transistor M1, the feedforward amplifier gmf1 includes an NMOS transistor M3, and the first-stage amplifier circuit module gm1 includes a PMOS transistor M2, an NMOS transistor M4, and a PMOS transistor M5;

[0011] The source of the PMOS transistor M1 is connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M3, and the source of the PMOS transistor M5 is externally connected to VDD;

[0012] The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M3 is connected to the source of the NMOS transistor M4 and grounded;

[0013] The drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2, and the source of the PMOS transistor M2 is connected between the source of the PMOS transistor M1 and the drain of the PMOS transistor M5.

[0014] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, the second-stage amplifier circuit module gm2 includes an NMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8;

[0015] The gate of the NMOS transistor M6 is connected to one end of the first frequency compensation capacitor Cm1, the drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, and the source of the NMOS transistor M6 is grounded;

[0016] The sources of the PMOS transistor M7 and the PMOS transistor M8 are connected and externally connected to VDD, the gates of the PMOS transistor M7 and the PMOS transistor M8 are connected, and the drain of the PMOS transistor M8 is connected to the input end of the third-stage amplifier circuit module gm3.

[0017] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, the third-stage amplifier circuit module gm3 includes an NMOS transistor M9, an NMOS transistor M10, and a PMOS transistor M11;

[0018] The drain of the NMOS transistor M9 is connected to the gate of the PMOS transistor M11, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M10, the source of the NMOS transistor M10 is grounded, the source of the PMOS transistor M11 is externally connected to VDD, and the drain of the PMOS transistor M11 is grounded.

[0019] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, it further includes a series-connected resistor R1 and resistor R2, and the drain of the PMOS transistor M11 is grounded through the resistor R1 and resistor R2.

[0020] In the LDO fast response circuit with zero-point suppression function based on the MNMC architecture of the present invention, it further includes a capacitor CL, and the capacitor CL is connected in parallel with the resistor R1 and resistor R2.

[0021] By the above technical solutions, the beneficial effects of the present invention are as follows: By introducing a feedforward compensation circuit module, a low-frequency left half-plane (LHP) zero point is constructed in the present invention. This zero point cancels out with the second pole of the system, thereby expanding the bandwidth of the system and avoiding the bandwidth limitation problem caused by the second pole in the traditional MNMC circuit. At the same time, the gain of high-frequency signals is improved through the feedforward compensation circuit module, pushing the second pole to a higher frequency band, further optimizing the frequency response of the system, improving the stability of the system at high frequencies, and accelerating the transient response speed of the circuit, enabling it to quickly return to stability when the load changes suddenly. The circuit of this solution is simple and low in cost, and is suitable for wide application and promotion. Description of the Drawings

[0022] Figure 1 is the main block diagram of the circuit of the embodiment of the present invention;

[0023] Figure 2 is the schematic diagram of the circuit of the embodiment of the present invention;

[0024] Figure 3 is the schematic diagram of the Ahuja frequency compensation technology of the embodiment of the present invention;

[0025] Figure 4 is the frequency characteristic simulation result diagram of the embodiment of the present invention with and without the feedforward compensation circuit module under light load (10uA);

[0026] Figure 5 is the frequency characteristic simulation result diagram of the embodiment of the present invention with and without the feedforward compensation circuit module under heavy load (2mA);

[0027] Figure 6 It is the frequency characteristic simulation result diagram of Miller compensation and Ahuja compensation in the case of light load (10uA) in the embodiments of the present invention;

[0028] Figure 7 It is the frequency characteristic simulation result diagram of Miller compensation and Ahuja compensation in the case of heavy load (2mA) in the embodiments of the present invention. Specific embodiments

[0029] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following further details a fast response circuit of an LDO with zero-point suppression function based on the MNMC architecture of the present invention in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] Please refer to Figure 1-7 , a fast response circuit of an LDO with zero-point suppression function based on the MNMC architecture, including: a feedforward compensation circuit module and a first-stage amplifier module gm1, a second-stage amplifier module gm2, and a third-stage amplifier module gm3 connected in sequence; the feedforward compensation circuit module includes a feedforward capacitor Cmf0 and a feedforward amplifier gmf0, a feedforward resistor Rf0, and a feedforward amplifier gmf1 connected in sequence; the input end of the feedforward amplifier gmf0 is connected to the input end of the first-stage amplifier module gm1, the output end of the feedforward amplifier gmf1 is connected between the second-stage amplifier module gm2 and the third-stage amplifier module gm3, and both ends of the feedforward capacitor Cmf0 are respectively connected to the input end and the output end of the feedforward amplifier gmf1.

[0031] In this solution, by introducing a feedforward compensation circuit module, a low-frequency left-half plane (LHP) zero point is constructed, and this zero point cancels out with the second pole of the system, thereby expanding the bandwidth of the system and avoiding the bandwidth limitation problem caused by the second pole in the traditional MNMC circuit. Specifically, under the condition of gm3 >> gm1, gm2, the formula for the second pole VP2 is:

[0032]

[0033] And the zero point generated by the feedforward compensation circuit module is:

[0034]

[0035] The pole-zero cancellation is achieved by setting z1 = VP2. At the same time, the gain of high-frequency signals is enhanced by the feed-forward compensation circuit module, pushing the secondary dominant pole to a higher frequency band, further optimizing the frequency response of the system, improving the stability of the system at high frequencies, and accelerating the transient response speed of the circuit, enabling it to quickly recover stability during load mutation.

[0036] Please refer to Figure 1-2 , in this embodiment, it further includes a first frequency compensation capacitor Cm1. One end of the first frequency compensation capacitor Cm1 is connected to the input end of the second-stage amplifier circuit module gm2, and the other end is connected to the output end of the third-stage amplifier circuit module gm3. In a multi-stage amplifier, each stage will introduce a pole. If these poles are too close, it will cause the phase margin of the system to decrease, thereby affecting stability. The first frequency compensation capacitor Cm1 is used for pole separation frequency compensation, separating the poles of the second-stage amplifier circuit module gm2 and the third-stage amplifier circuit module gm3, so that they are distributed in different frequency ranges, improving the phase margin of the system and enhancing stability.

[0037] Please refer to Figure 1-3 , in this embodiment, it further includes a second frequency compensation circuit. The second frequency compensation circuit includes a second frequency compensation capacitor Cm2 and an NMOS transistor M9. One end of the second frequency compensation capacitor Cm2 is connected to the input end of the third-stage amplifier circuit module gm3 through the NMOS transistor M9, and the NMOS transistor M9 is a common-gate transistor. The second frequency compensation capacitor Cm2 pushes the pole of the third-stage amplifier circuit module gm3 to a higher frequency band, optimizing the frequency response of the system. Further, one end of the second frequency compensation capacitor Cm2 is connected to the input end of the third-stage amplifier circuit module gm3 through the NMOS transistor M9, establishing an Ahuja compensation loop (as Figure 3 shown), which avoids the appearance of positive zeros in traditional Miller compensation by introducing an additional compensation path, improving the bandwidth and phase margin of the circuit at high frequencies and accelerating the LDO response speed.

[0038] Please refer to Figure 1-2, in this embodiment, the feedforward amplifier gmf0 includes a PMOS transistor M1, the feedforward amplifier gmf1 includes an NMOS transistor M3, and the first-stage amplifier circuit module gm1 includes a PMOS transistor M2, an NMOS transistor M4, and a PMOS transistor M5; the source of the PMOS transistor M1 is connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M3, and the source of the PMOS transistor M5 is externally connected to VDD; the gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M3 is connected to the source of the NMOS transistor M4 and grounded; the drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2, and the source of the PMOS transistor M2 is connected between the source of the PMOS transistor M1 and the drain of the PMOS transistor M5. The PMOS transistor M1, the PMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, and the PMOS transistor M5 form a classic five-transistor operational transconductance amplifier (OTA), which ensures stable operating points and excellent performance of the amplifier while achieving high gain and high input impedance. Among them, the PMOS transistor M1 and the PMOS transistor M2 form a fully differential input pair transistor, which can provide high input impedance and excellent common-mode rejection ability. The NMOS transistor M3 and the NMOS transistor M4 are current mirror loads, which provide a stable bias current for the input pair transistor, and the PMOS transistor M5 is a tail current source.

[0039] Please refer to Figure 1-2 , in this embodiment, the second-stage amplifier circuit module gm2 includes an NMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8; the gate of the NMOS transistor M6 is connected to one end of the first frequency compensation capacitor Cm1, and it is also connected between the drain of the PMOS transistor M4 and the drain of the PMOS transistor M2 in the first-stage amplifier circuit module gm1. The drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, and the source of the NMOS transistor M6 is grounded; the sources of the PMOS transistor M7 and the PMOS transistor M8 are connected and externally connected to VDD, the gates of the PMOS transistor M7 and the PMOS transistor M8 are connected, and the drain of the PMOS transistor M8 is connected to the input end of the third-stage amplifier circuit module gm3, specifically connected between the drain of the NMOS transistor M9 and the gate of the PMOS transistor M11. The main function of the second-stage amplifier circuit module gm2 is to isolate the previous stage, enhance the driving ability of the circuit, and improve the frequency response and stability of the multi-stage amplifier through the "Miller Effect";

[0040] Please refer to Figure 1-2, in this embodiment, the third-stage amplifier circuit module gm3 includes an NMOS transistor M9, an NMOS transistor M10, and a PMOS transistor M11; the drain of the NMOS transistor M9 is connected to the gate of the PMOS transistor M11, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M10, the source of the NMOS transistor M10 is grounded, the source of the PMOS transistor M11 is externally connected to VDD, and the drain of the PMOS transistor M11 is grounded. The third-stage amplifier circuit module gm3 is the output stage and adopts a common-source structure, which not only endows it with excellent output swing ability but also ensures the stability of the output voltage, thus adapting to various load requirements.

[0041] Please refer to Figure 2 , in this embodiment, it further includes a series-connected resistor R1 and resistor R2, and the drain of the PMOS transistor M11 is grounded through the resistor R1 and resistor R2. The resistor R1 and resistor R2 form a voltage-dividing network for adjusting the output voltage and implementing feedback control.

[0042] Please refer to Figure 2 In this embodiment, it further includes a capacitor CL, and the capacitor CL is connected in parallel with the resistor R1 and resistor R2. The capacitor CL can be used to smooth the output voltage and reduce the ripple and noise of the output voltage.

[0043] In summary, the present invention provides an LDO fast-response circuit with a zero-suppression function in an MNMC architecture. By introducing a feed-forward compensation circuit module, a low-frequency left-half plane (LHP) zero is constructed, and this zero cancels out with the second pole of the system, thereby expanding the bandwidth of the system and avoiding the bandwidth limitation problem caused by the second pole in traditional MNMC circuits. At the same time, the gain of high-frequency signals is improved through the feed-forward compensation circuit module, pushing the second pole to a higher frequency band, further optimizing the frequency response of the system, improving the stability of the system at high frequencies, and accelerating the transient response speed of the circuit, enabling it to quickly recover stability when the load changes suddenly. Further, the first frequency compensation capacitor Cm1 is used for pole separation frequency compensation to separate the poles of the second-stage amplifier circuit module gm2 and the third-stage amplifier circuit module gm3, so that they are distributed in different frequency ranges, improving the phase margin of the system and enhancing stability. One end of the second frequency compensation capacitor Cm2 is connected to the input end of the third-stage amplifier circuit module gm3 through the NMOS transistor M9, establishing an Ahuja compensation loop (as Figure 3 shown), which avoids the appearance of positive zeros in traditional Miller compensation by introducing an additional compensation path, improves the bandwidth and phase margin at high frequencies of the circuit, and accelerates the LDO response speed. The circuit of the present invention is simple and low-cost, and is suitable for wide application and promotion.

[0044] Details not described in the present invention are all well-known technologies to those skilled in the art.

[0045] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A fast response circuit of an LDO with zero - point suppression function based on the MNMC architecture, characterized in that, Including: A feedforward compensation circuit module and a first-stage amplifier circuit module gm1, a second-stage amplifier circuit module gm2, and a third-stage amplifier circuit module gm3 connected in sequence; The feedforward compensation circuit module includes a feedforward capacitor Cmf0 and a feedforward amplifier gmf0, a feedforward resistor Rf0, and a feedforward amplifier gmf1 connected in sequence; The input end of the feedforward amplifier gmf0 is connected to the input end of the first-stage amplifier circuit module gm1, the output end of the feedforward amplifier gmf1 is connected between the second-stage amplifier circuit module gm2 and the third-stage amplifier circuit module gm3, and both ends of the feedforward capacitor Cmf0 are respectively connected to the input end and the output end of the feedforward amplifier gmf1.

2. The LDO fast response circuit with zero-point suppression function based on the MNMC architecture according to claim 1, characterized in that, It further includes a first frequency compensation capacitor Cm1, one end of the first frequency compensation capacitor Cm1 is connected to the input end of the second-stage amplifier circuit module gm2, and the other end is connected to the output end of the third-stage amplifier circuit module gm3.

3. The LDO fast response circuit with zero point suppression function based on the MNMC architecture according to claim 1, wherein, It further includes a second frequency compensation circuit, the second frequency compensation circuit includes a second frequency compensation capacitor Cm2 and an NMOS transistor M9, one end of the second frequency compensation capacitor Cm2 is connected to the input end of the third-stage amplifier circuit module gm3 through the NMOS transistor M9, and the NMOS transistor M9 is a common-gate transistor.

4. A fast response circuit of an LDO with zero-point suppression function based on the MNMC architecture according to claim 1, characterized in that, The feedforward amplifier gmf0 includes a PMOS transistor M1, the feedforward amplifier gmf1 includes an NMOS transistor M3, and the first-stage amplifier circuit module gm1 includes a PMOS transistor M2, an NMOS transistor M4, and a PMOS transistor M5; The source of the PMOS transistor M1 is connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M3, and the source of the PMOS transistor M5 is externally connected to VDD; The gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M3 is connected to the source of the NMOS transistor M4 and grounded; The drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2, and the source of the PMOS transistor M2 is connected between the source of the PMOS transistor M1 and the drain of the PMOS transistor M5.

5. The LDO fast response circuit with zero point suppression function based on the MNMC architecture according to claim 2, characterized in that The second-stage amplifier circuit module gm2 includes an NMOS transistor M6, a PMOS transistor M7, and a PMOS transistor M8; The gate of the NMOS transistor M6 is connected to one end of the first frequency compensation capacitor Cm1, the drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, and the source of the NMOS transistor M6 is grounded; The sources of the PMOS transistor M7 and the PMOS transistor M8 are connected and externally connected to VDD, the gates of the PMOS transistor M7 and the PMOS transistor M8 are connected, and the drain of the PMOS transistor M8 is connected to the input end of the third-stage amplifier circuit module gm3.

6. A fast response circuit of an LDO with zero point suppression function based on the MNMC architecture according to claim 3, characterized in that, The third-stage amplifier circuit module gm3 includes the NMOS transistor M9, the NMOS transistor M10, and the PMOS transistor M11; The drain of the NMOS transistor M9 is connected to the gate of the PMOS transistor M11, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M10, the source of the NMOS transistor M10 is grounded, the source of the PMOS transistor M11 is externally connected to VDD, and the drain of the PMOS transistor M11 is grounded.

7. A fast response circuit of an LDO with zero-point suppression function based on the MNMC architecture according to claim 6, characterized in that It further includes a series-connected resistor R1 and resistor R2, and the drain of the PMOS transistor M11 is grounded through the resistor R1 and the resistor R2.

8. A fast response circuit of an LDO with zero-point suppression function based on the MNMC architecture according to claim 7, characterized in that, It further includes a capacitor CL, and the capacitor CL is connected in parallel with the resistor R1 and the resistor R2.

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