External card clock switching control method, device, controller and storage medium

Abstract

The present application discloses a clock switching control method, device, controller and storage medium for an external card, which relates to the field of computer hardware technology, including: during the operation of a storage device, by real-time collection of external card operation information and calculation of the link real-time rate, combined with dynamic detection of the clock source output status, high-precision matching of the clock frequency and the link requirements is achieved; if the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, a clock switching instruction is sent to a clock source output switching module to enable the clock source output switching module to switch to a target clock source, so as to ensure that the deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold, thereby reducing the waste of clock resources and reducing the overall energy consumption of the storage device.

Description

Technical Field

[0001] The present application relates to the field of computer hardware technology, and in particular to a clock switching control method, device, controller and storage medium for an external card. Background Art

[0002] In storage devices, the PCIe (Peripheral Component Interconnect Express) clock plays a crucial role. Because storage devices require the insertion of various PCIe add-in cards, higher requirements are placed on the adaptability of the PCIe clock.

[0003] In the related art, PCIe clocks are designed to be backward compatible with low-level PCIe clocks using high-level PCIe protocols. When storage devices use low-level PCIe add-in cards, high-level PCIe clocks are used. However, this adaptation method wastes clock resources. Summary of the Invention

[0004] The present application provides a clock switching control method, device, controller and storage medium for an external card, so as to at least solve the problem of clock resource waste in the related art.

[0005] The present application provides a clock switching control method for an external card, comprising: sending an operation information query instruction to the external card to obtain the operation information of the external card; determining the link real-time rate of the external card based on the operation information; sending a detection instruction to the clock source output switching module corresponding to the external card to detect the link clock rate output by the clock source output switching module to the external card, wherein the link clock rate is the link clock rate output by one clock source among multiple clock sources to the clock source output switching module; if the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, sending a clock switching instruction to the clock source output switching module to enable the clock source output switching module to switch the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

[0006] The present application also provides a clock switching control device for an external card, comprising:

[0007] The operation information acquisition module is used to send an operation information query instruction to the external card to obtain the operation information of the external card.

[0008] The link real-time rate acquisition module is used to determine the link real-time rate of the external card according to the operation information.

[0009] The link clock rate acquisition module is used to send a detection instruction to the clock source output switching module corresponding to the external card to detect the link clock rate output by the clock source output switching module to the external card, where the link clock rate is the clock rate output by one clock source among multiple clock sources to the clock source output switching module.

[0010] The clock switching module is used to send a clock switching instruction to the clock source output switching module if the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, so that the clock source output switching module switches the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

[0011] The present application also provides a baseboard management controller, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned external card clock switching control methods when executing the computer program.

[0012] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned external card clock switching control methods are implemented.

[0013] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned external card clock switching control methods when executed by a processor.

[0014] The external card clock switching control method, device, controller and storage medium of the present application, during the operation of the storage device, realizes high-precision matching of clock frequency and link requirements by real-time collection of external card operation information and calculation of link real-time rate, combined with dynamic detection of clock source output status. If the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, a clock switching instruction is sent to the clock source output switching module to enable the clock source output switching module to switch to the target clock source, so as to ensure that the deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold, thereby reducing the waste of clock resources and reducing the overall energy consumption of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A schematic diagram of a scenario of a clock switching control method for an external card provided in an embodiment of the present application;

[0017] Figure 2 A flow chart of a clock switching control method for an external card provided in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of the structure of the clock switching control device for an external card provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the structure of the baseboard management controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0022] In order to clearly understand the technical solution of the present application, the solution of the prior art is first introduced in detail. In storage devices, the PCIe clock plays a very important role. Since storage devices need to be inserted into different PCIe plug-in cards, this puts higher requirements on the adaptability of the PCIe clock. The PCIe clock includes the PCIe3.0 clock and the PCIe4.0 clock, of which the PCIe4.0 clock is backward compatible with the PCIe3.0 clock. In the related art, when the storage device uses a low-level protocol PCIe plug-in card, the high-level protocol PCIe clock is also used. However, this adaptation method causes a waste of clock resources.

[0023] In order to solve the above technical problems, the inventors have come up with the idea of ​​determining whether it is necessary to switch the clock source for the external card by obtaining the link real-time rate of the external card and the link clock rate output by the clock source during the operation of the storage device, and comparing whether the relative deviation between the link real-time rate and the link clock rate output by the clock source exceeds a first preset threshold. If the relative deviation between the link clock rate and the link real-time rate exceeds the first preset threshold, a clock switching instruction is sent to the clock source output switching module to enable the clock source output switching module to switch to the target clock source, so as to ensure that the deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold, thereby reducing the waste of clock resources and reducing the overall energy consumption of the storage device.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the external card clock switching control method depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1 , Figure 1 Schematic diagram of the scenario of the external card clock switching control method provided in the embodiment of the present application. Figure 1 As shown, the scenario includes: multiple clock sources 101 , a clock source output switching module 102 , a baseboard management controller 103 and an external card 104 .

[0026] The clock source 101 may be a PCIe 3.0 clock source, a PCIe 4.0 clock source, a PCIe 5.0 clock source, etc., and is used to provide the clock signal required by the external card 104 .

[0027] Specifically, the clock source 101 is connected to the clock source output switching module 102 , and the baseboard management controller 103 is connected to the external card 104 and the clock source output switching module 102 .

[0028] Specifically, the baseboard management controller 103 sends an operation information query instruction to the external card 104 to obtain the operation information of the external card. Based on the operation information, the baseboard management controller 103 can determine the link real-time rate of the external card 104. At the same time, the baseboard management controller 103 sends a detection instruction to the clock source output switching module 102 corresponding to the external card to detect the link clock rate output by the clock source output switching module 102 to the external card 104. If the relative deviation between the link clock rate and the link real-time rate exceeds the first preset threshold, a clock switching instruction is sent to the clock source output switching module 102. The clock source output switching module 102 switches the clock source 101 according to the clock switching instruction to output a link clock rate whose relative deviation from the link real-time rate is within the first preset threshold.

[0029] Figure 2 This is a flow chart of the external card clock switching control method provided by the embodiment of the present application. The execution subject of the embodiment of the present application can be Figure 1 The baseboard management controller shown may also be other devices with similar functions, and the present application embodiment does not make specific restrictions, such as Figure 2 As shown, the embodiment of the present application provides a clock switching control method for an external card, and the method is described in detail as follows:

[0030] S201: Sending an operation information query instruction to an external card to obtain operation information of the external card.

[0031] Specifically, the baseboard management controller first proactively sends an operational information query command to the external card to obtain the card's current operating status and related parameters. After receiving the command, the external card returns its own operational information to the baseboard controller. This operational information includes the external card's operating mode, data transmission status, link status, and more.

[0032] S202: Determine the real-time link rate of the external card according to the operation information.

[0033] Specifically, after acquiring the operation information of the external card, the baseboard management controller extracts data related to the real-time rate of the link from the information.

[0034] S203: Send a detection instruction to the clock source output switching module corresponding to the external card to detect the link clock rate output by the clock source output switching module to the external card, where the link clock rate is the clock rate output by one of the multiple clock sources to the clock source output switching module.

[0035] Specifically, the baseboard management controller sends a detection instruction to the clock source output switching module corresponding to the external card, requesting the clock source output switching module to detect and feedback the link clock rate currently output to the external card. The link clock rate is provided by one of multiple clock sources, and the clock source output switching module is responsible for receiving the clock signal from the clock source and outputting it to the external card.

[0036] S204: If the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, a clock switching instruction is sent to the clock source output switching module so that the clock source output switching module switches the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

[0037] Specifically, the baseboard management controller uses the following formula to calculate the relative deviation between the link clock rate and the link real-time rate:

[0038]

[0039] Where R dev Indicates the relative deviation between the link clock rate and the link real-time rate. v1 indicates the link clock rate, and v2 indicates the link real-time rate.

[0040] For example, if the relative deviation between the link clock rate and the link real-time rate is within 2%, it is determined that the link clock rate matches the link real-time rate, and there is no need to trigger clock switching. If the relative deviation between the link clock rate and the link real-time rate exceeds 2%, multiple clock sources are screened based on the link real-time rate to obtain a target clock source. The baseboard management controller encodes the configuration of the target clock source and the switching control parameters based on the preset coding format and transmission mechanism, generates a clock switching instruction, and sends the clock switching instruction to the clock source output switching module. After the clock output signal of the external card is switched to the link clock rate of the target clock source, the relative deviation between the link real-time rate and the link clock rate output by the target clock source is within a first preset threshold.

[0041] Specifically, before sending a clock switching instruction to the clock source output switching module, multiple clock sources are screened based on the link real-time rate to obtain a target clock source. The baseboard management controller encodes the configuration and switching control parameters of the target clock source based on a preset encoding format and transmission mechanism. The process of generating the clock switching instruction includes:

[0042] Sa1: Based on the link real-time rate, a candidate clock source that supports the link real-time rate is matched from multiple clock sources.

[0043] Specifically, a candidate clock source that supports the link real-time rate is matched from multiple clock sources, including:

[0044] Sb1: Gets the standard defined rate of each clock source from multiple clock sources.

[0045] Specifically, the baseboard management controller queries a pre-stored clock source configuration table of multiple clock sources based on the real-time rate of the link, and obtains a standard defined rate of each clock source.

[0046] Sb2: Calculates the matching degree between the link real-time rate and the standard defined rate of each clock source.

[0047] Specifically, the formula for calculating the degree of matching between the standard defined rate of each clock source and the link real-time rate is:

[0048]

[0049] Where M represents the degree of match between the standard-defined rate of each clock source and the real-time rate of the link, v3 represents the standard-defined rate of each clock source, and v4 represents the real-time rate of the link.

[0050] Sb3: If the matching degree of any clock source exceeds a third preset threshold and the standard-defined rate of the clock source is not lower than the link real-time rate, the clock source is determined as a candidate clock source.

[0051] Exemplarily, if M is less than 1, and the matching degree between the standard-defined rate and the link real-time rate is greater than 90%, then the clock source with the highest matching degree is selected from the clock sources to be determined as the candidate clock source.

[0052] Sa2: If there are multiple candidate clock sources, obtain the power consumption parameters of each candidate clock source.

[0053] Specifically, when a candidate clock source with the highest matching degree exists, the baseboard management controller obtains power consumption parameters of each clock source. These parameters can be read through the hardware register of the clock source or obtained from a preconfigured power consumption data table.

[0054] Sa3: Determine the candidate clock source with the smallest power consumption parameter as the target clock source.

[0055] Specifically, the baseboard management controller selects a candidate clock source with the lowest power consumption as the target clock source.

[0056] Specifically, if the candidate clock sources have the same power consumption, the clock jitter of the candidate clock sources is further compared, and the clock source with smaller jitter is selected, or the stability history of the candidate clock sources is queried, and the clock source with a higher switching success rate is selected as the target clock source.

[0057] Sa4: Calculates the adaptive frequency multiplication factor of the target clock source based on the link real-time rate and the preset frequency division factor of the target clock source.

[0058] Specifically, based on the link real-time rate and the preset frequency division coefficient of the target clock source, the formula for calculating the adaptive frequency multiplication coefficient of the target clock source is:

[0059]

[0060] Where N target Indicates the adaptive multiplication factor of the target clock source, v t Indicates the real-time rate of the link, R indicates the reference frequency division coefficient of the target clock source, OD indicates the preset division coefficient of the target clock source, and f ref Indicates the reference clock frequency of the target clock source.

[0061] For example, if the acquired link real-time rate is 6GT / s, while the standard clock source outputs a link clock rate of 8GT / s, this will cause the timing references of the storage device's transmitter and receiver to be inconsistent, necessitating modification of the target clock source's phase-locked loop configuration parameters. The standard clock source provides a fixed reference clock frequency of 100MHz, and accordingly, the reference frequency division factor remains unchanged at 1. Based on the unchanged preset division factor of the target clock source, the adaptive multiplication factor of the target clock source is determined.

[0062] Sa5: Read the phase-locked loop configuration information of the target clock source, where the phase-locked loop configuration information includes the frequency multiplication factor and the preset frequency division factor of the target clock source.

[0063] Specifically, the baseboard management controller obtains the current frequency multiplication coefficient and the preset frequency division coefficient by reading the phase-locked loop configuration parameters of the target clock source.

[0064] Sa6: Write the adaptive frequency multiplication factor into the phase-locked loop configuration information of the target clock source and trigger the phase-locked loop of the target clock source to relock.

[0065] Specifically, the baseboard management controller writes the calculated adaptive frequency multiplication factor into the phase-locked loop configuration register, overwriting the original phase-locked loop configuration information, and sets the lock trigger bit of the phase-locked loop configuration register.

[0066] Sa7: If the phase-locked loop of the target clock source is locked within a preset time, hardware identification information of the target clock source is extracted.

[0067] For example, the PLL lock status register is monitored, and if the lock flag is detected to be set within 1 ms, the hardware identification information of the target clock source is extracted. If the lock times out, the PLL configuration information is reconfigured.

[0068] Sa8: Converts hardware identification information into clock switching instructions according to the communication protocol of the clock source output switching module.

[0069] In summary, during the operation of the storage device, by real-time collection of external card operation information and calculation of the link real-time rate, combined with dynamic detection of the clock source output status, high-precision matching of the clock frequency and link requirements is achieved. If the relative deviation between the link clock rate and the link real-time rate exceeds the first preset threshold, a clock switching instruction is sent to the clock source output switching module to enable the clock source output switching module to switch to the target clock source, so as to ensure that the deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold, thereby reducing the waste of clock resources and reducing the overall energy consumption of the storage device.

[0070] In another embodiment provided by the present application, when a failure of a currently used clock source is detected, a method for switching the clock source includes:

[0071] S301: When it is detected that the current clock source fails, a product data query instruction is sent to the external card to obtain the supported rate of the external card.

[0072] Specifically, when the baseboard management controller detects a clock source failure, such as an inability to output a stable clock signal or frequency deviation outside the acceptable range, it immediately sends a product data query command to the add-in card to obtain the data transmission rate range supported by the add-in card. Upon receiving the command, the add-in card returns the maximum supported rate information to the baseboard management controller.

[0073] Specifically, the process of detecting a clock source failure is as follows:

[0074] Sd1: Send a link status query command to the external card to obtain the link training status of the external card.

[0075] Specifically, the baseboard management controller sends a link status query command to the add-in card. Through periodic polling, typically at intervals of 10ms to 100ms, it obtains the card's link training status, such as L0 (active state), L1 (low-power standby), L2 / L3 (deep sleep), and other states in the PCIe protocol. Under normal circumstances, the add-in card should quickly return to its current state after receiving the query command, and spend most of its time in L0 to ensure data transmission. If the state remains in L1 or a lower power state for multiple consecutive cycles (e.g., 10 cycles) and cannot automatically return to L0, it indicates a link anomaly.

[0076] Sd2: Send an error information query command to the external card to obtain the error increment of the external card within a preset time period.

[0077] The error increment is the difference in error counts between two queries. For example, if 100 errors were recorded in the previous 500ms and 600 errors were recorded in the current 500ms, the error increment is 500.

[0078] Specifically, while querying the link status, an error information query command is sent to the external card to obtain error statistics within a preset time period, such as 500ms. This data includes the number of cyclic redundancy check errors, the number of retransmission requests, and link layer protocol errors. The error increment is compared with a second preset threshold, such as 500 errors per second. If the threshold is exceeded, it indicates a sharp decline in link quality.

[0079] Sd3: If the link training state is in a low power state within a preset period and the error increment within a preset time exceeds a second preset threshold, the clock source output switching module corresponding to the external card is controlled to read the phase-locked loop state of the current clock source.

[0080] Specifically, when the link training state is continuously abnormal, the link training state is in a low power consumption state within a preset period, and the error increment exceeds a second preset threshold, the reading of the clock source phase-locked loop state is triggered.

[0081] Sd4: If the phase-locked loop state of the current clock source is in an unlocked state, it is determined that the current clock source is faulty.

[0082] Specifically, after obtaining the value of the phase-locked loop status register, a final fault determination is performed. If the lock flag indicates unlocked, it is determined that the current clock source has failed.

[0083] S302: Reading the slot rate of the slot of the external card from the configuration information of the storage device connected to the external card.

[0084] Specifically, while sending a product data query instruction to the external card, the storage device connected to the external card is accessed to read the configuration information of the slot where the external card is located, especially the data transmission rate that the slot can support.

[0085] S303: Determine the link required rate of the external card according to the supported rate of the external card and the slot rate of the slot.

[0086] The required link rate must meet both the capabilities of the plug-in card and the slot limitations. Usually, the smaller of the two is used as the required link rate to ensure stable system operation.

[0087] Specifically, the method for determining the link required rate of the external card includes:

[0088] Sc1: Determine whether the slot rate of the slot is not less than the rate supported by the plug-in card.

[0089] Specifically, the baseboard management controller first compares the slot rate of the slot where the external card is located with the supported rate of the external card itself.

[0090] Sc2: If it is determined that the slot rate of the slot is not less than the supported rate of the external card, the supported rate of the external card is determined as the required link rate of the external card.

[0091] Specifically, if the slot rate is not less than the rate supported by the external card, for example, the slot supports a Gen4 rate of 8GT / s, and the external card supports up to Gen4, then the supported rate of the external card is directly determined as the link requirement rate. At this time, the system can fully utilize the performance upper limit of the external card.

[0092] Sc3: If it is determined that the slot rate of the slot is lower than the supported rate of the external card, the preset rate of the slot is determined as the required link rate of the external card.

[0093] Specifically, if the slot rate is lower than the rate supported by the add-in card, the slot's preset rate (i.e., the slot's maximum supported rate) is used as the required link rate. For example, if a Gen3 slot supports up to 8GT / s, even if the add-in card supports Gen4 (16GT / s), the required link rate is capped at 8GT / s.

[0094] S304: Generate a clock switching instruction according to the link required rate, and send the clock switching instruction to the clock source output switching module, so that the clock source output switching module switches the clock source to the target clock source, wherein the link clock rate output by the target clock source is consistent with the link required rate.

[0095] Specifically, after determining the required link rate, a target clock source that meets the required link rate is obtained based on the required link rate. The hardware identification information of the target clock source is converted into a clock switching instruction that adapts to the communication protocol of the clock source output switching module. This clock switching instruction is then sent to the clock source output switching module. Upon receiving the clock switching instruction, the clock source output switching module switches to the target clock source according to the clock switching instruction, maintaining normal operation of the add-in card and ensuring that the link clock rate output by the target clock source is consistent with the required link rate.

[0096] In summary, after detecting clock source failure, the supported rate of the external card is obtained through product data query instructions to avoid performance waste caused by using the default clock configuration; the target clock source that best matches the actual link requirements is selected from multiple available clock sources in combination with the slot rate limit; and accurate clock switching instructions are generated based on the hardware identification information of the target clock source to ensure that the link clock rate output by the new clock source is consistent with the required link rate. This not only ensures communication stability, but also avoids the power consumption and hardware resource waste caused by configuring a clock source for an unsupported high rate.

[0097] In addition, through triple verification of link status monitoring, error increment statistics and phase-locked loop status verification, clock source problems can be accurately located, avoiding frequent clock switching due to misjudgment.

[0098] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0099] Figure 3 This is a schematic diagram of the structure of the external card clock switching control device provided in the embodiment of the present application. Figure 3As shown, an embodiment of the present application also provides an external card clock switching control device, which includes: an operation information acquisition module 301, a link real-time rate acquisition module 302, a link clock rate acquisition module 303 and a clock switching module 304.

[0100] The operation information acquisition module 301 is used to send an operation information query instruction to the external card to obtain the operation information of the external card.

[0101] The link real-time rate acquisition module 302 is used to determine the link real-time rate of the external card according to the operation information.

[0102] The link clock rate acquisition module 303 is used to send a detection instruction to the clock source output switching module corresponding to the external card to detect the link clock rate output by the clock source output switching module to the external card, where the link clock rate is the clock rate output by one of the multiple clock sources to the clock source output switching module.

[0103] The clock switching module 304 is used to send a clock switching instruction to the clock source output switching module if the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, so that the clock source output switching module switches the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

[0104] In one possible embodiment, the device also includes a faulty clock source switching module, which is used to send a product data query instruction to the external card to obtain the supported rate of the external card when a fault is detected in the current clock source; read the slot rate of the slot of the external card from the configuration information of the storage device connected to the external card; determine the link requirement rate of the external card based on the supported rate of the external card and the slot rate of the slot; generate a clock switching instruction based on the link requirement rate, and send the clock switching instruction to the clock source output switching module to enable the clock source output switching module to switch the clock source to the target clock source, wherein the link clock rate output by the target clock source is consistent with the link requirement rate.

[0105] In one possible implementation, the fault clock source switching module is specifically used to determine whether the slot rate of the slot is not less than the supported rate of the external card; if it is determined that the slot rate of the slot is not less than the supported rate of the external card, the supported rate of the external card is determined as the link required rate of the external card; if it is determined that the slot rate of the slot is less than the supported rate of the external card, the preset rate of the slot is determined as the link required rate of the external card.

[0106] In one possible implementation, the faulty clock source switching module is specifically configured to send a link status query instruction to the external card to obtain the link training status of the external card; send an error information query instruction to the external card to obtain the error increment of the external card within a preset time length; if the link training status is in a low power consumption state within a preset period, and the error increment within the preset time length exceeds a second preset threshold, then control the clock source output switching module corresponding to the external card to read the phase-locked loop state of the current clock source; if the phase-locked loop state of the current clock source is in an unlocked state, then it is determined that the current clock source has failed.

[0107] In one possible embodiment, the device also includes an instruction generation module, which is used to match a candidate clock source that supports the link real-time rate from multiple clock sources based on the link real-time rate; if there are multiple candidate clock sources, the power consumption parameters of each candidate clock source are obtained; the candidate clock source with the smallest power consumption parameter is determined as the target clock source; based on the link real-time rate and the preset division coefficient of the target clock source, the adaptive multiplication coefficient of the target clock source is calculated; the phase-locked loop configuration information of the target clock source is read, wherein the phase-locked loop configuration information includes the multiplication coefficient and the preset division coefficient of the target clock source; the adaptive multiplication coefficient is written into the phase-locked loop configuration information of the target clock source, and the phase-locked loop of the target clock source is triggered to relock; if the phase-locked loop of the target clock source is locked within the preset time, the hardware identification information of the target clock source is extracted; according to the communication protocol of the clock source output switching module, the hardware identification information is converted into a clock switching instruction.

[0108] In one possible implementation, the instruction generation module is specifically used to obtain the standard defined rate of each clock source from multiple clock sources; calculate the matching degree between the link real-time rate and the standard defined rate of each clock source; if the matching degree of any clock source exceeds a third preset threshold and the standard defined rate of the clock source is not lower than the link real-time rate, the clock source is determined as a candidate clock source.

[0109] In a possible implementation, the formula for calculating the adaptive frequency multiplication factor of the target clock source in the instruction generation module is:

[0110]

[0111] Where N target Indicates the adaptive multiplication factor of the target clock source, v t Indicates the real-time rate of the link, R indicates the reference frequency division coefficient of the target clock source, OD indicates the preset division coefficient of the target clock source, and f ref Indicates the reference clock frequency of the target clock source.

[0112] For the description of the features in the embodiment corresponding to the external card clock switching control device, reference can be made to the relevant description of the embodiment corresponding to the external card clock switching control method, which will not be repeated here.

[0113] Figure 4 This is a schematic diagram of the structure of the baseboard management controller provided in the embodiment of the present application. Figure 4 As shown, the baseboard management controller provided in this embodiment includes: at least one processor 401 and a memory 402. Optionally, the baseboard management controller also includes a communication component 403. The processor 401, the memory 402 and the communication component 403 are connected via a bus.

[0114] In a specific implementation process, at least one processor 401 executes a computer program stored in the memory 402 , so that the at least one processor 401 executes the above-mentioned embodiment of the clock switching control method for an add-in card.

[0115] The specific implementation process of the processor 401 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0116] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0117] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0118] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0119] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned external card clock switching control method embodiments when running.

[0120] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0121] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned external card clock switching control method embodiments are implemented.

[0122] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned external card clock switching control method embodiments.

[0123] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0124] The above describes in detail the clock switching control method, device, controller, and storage medium for an add-in card provided by this application. This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of this application. It should be noted that those skilled in the art may make various improvements and modifications to this application without departing from the principles of this application, and such improvements and modifications fall within the scope of protection of the claims of this application.

Claims

1. A clock switching control method for an external card, characterized in that: include: Sending an operation information query instruction to the external card to obtain the operation information of the external card; Determining the real-time link rate of the external card according to the operation information; Sending a detection instruction to the clock source output switching module corresponding to the external card to detect the link clock rate output by the clock source output switching module to the external card, wherein the link clock rate is the clock rate output by one of the multiple clock sources to the clock source output switching module; If the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, a clock switching instruction is sent to the clock source output switching module so that the clock source output switching module switches the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

2. The clock switching control method for an external card according to claim 1, wherein: Also includes: When a failure of the current clock source is detected, a product data query instruction is sent to the external card to obtain a supported rate of the external card; Reading the slot rate of the slot of the external card from configuration information of a storage device connected to the external card; Determining a link required rate of the external card according to a supported rate of the external card and a slot rate of the slot; A clock switching instruction is generated according to the link requirement rate, and the clock switching instruction is sent to the clock source output switching module so that the clock source output switching module switches the clock source to the target clock source, wherein the link clock rate output by the target clock source is consistent with the link requirement rate.

3. The clock switching control method for an external card according to claim 2, wherein: The determining the link required rate of the external card according to the supported rate of the external card and the slot rate of the slot includes: Determining whether the slot rate of the slot is not less than the supported rate of the external card; If it is determined that the slot rate of the slot is not less than the supported rate of the external card, the supported rate of the external card is determined as the required link rate of the external card; If it is determined that the slot rate of the slot is lower than the supported rate of the external card, the preset rate of the slot is determined as the required link rate of the external card.

4. The clock switching control method for an external card according to claim 2, wherein: The detecting that the current clock source fails includes: Sending a link status query instruction to the external card to obtain the link training status of the external card; Sending an error information query instruction to the external card to obtain an error increment of the external card within a preset time period; If the link training state is in a low power consumption state within a preset period, and the error increment within a preset time period exceeds a second preset threshold, controlling the clock source output switching module corresponding to the external card to read the phase-locked loop state of the current clock source; If the phase-locked loop state of the current clock source is in an unlocked state, it is determined that the current clock source fails.

5. The clock switching control method for an external card according to claim 1, wherein: Before sending the clock switching instruction to the clock source output switching module, the method further includes: According to the link real-time rate, matching a candidate clock source that supports the link real-time rate from the multiple clock sources; If there are multiple candidate clock sources, obtaining power consumption parameters of each candidate clock source; Determine the candidate clock source with the smallest power consumption parameter as the target clock source; Calculating an adaptive frequency multiplication factor of the target clock source according to the link real-time rate and a preset frequency division factor of the target clock source; Reading phase-locked loop configuration information of the target clock source, wherein the phase-locked loop configuration information includes a frequency multiplication factor and a preset frequency division factor of the target clock source; Writing the adapted frequency multiplication coefficient into the phase-locked loop configuration information of the target clock source, and triggering the phase-locked loop of the target clock source to be relocked; If the phase-locked loop of the target clock source is locked within a preset time, extracting the hardware identification information of the target clock source; The hardware identification information is converted into a clock switching instruction according to the communication protocol of the clock source output switching module.

6. The clock switching control method for an external card according to claim 5, characterized in that: The step of matching a candidate clock source that supports the link real-time rate from the multiple clock sources according to the link real-time rate includes: Obtaining a standard defined rate for each clock source from the plurality of clock sources; Calculating the matching degree between the real-time rate of the link and the standard defined rate of each clock source; If the matching degree of any clock source exceeds a third preset threshold, and the standard-defined rate of the clock source is not lower than the link real-time rate, the clock source is determined as a candidate clock source.

7. The clock switching control method for an external card according to claim 5, wherein: The formula for calculating the adaptive frequency multiplication factor of the target clock source is: Where N target Indicates the adaptive multiplication factor of the target clock source, v t represents the real-time rate of the link, R represents the reference frequency division coefficient of the target clock source, OD represents the preset frequency division coefficient of the target clock source, f ref Indicates the reference clock frequency of the target clock source.

8. A clock switching control device for an external card, characterized in that: include: An operation information acquisition module is used to send an operation information query instruction to the external card to obtain the operation information of the external card; A link real-time rate acquisition module, configured to determine the link real-time rate of the external card based on the operation information; a link clock rate acquisition module, configured to send a detection instruction to a clock source output switching module corresponding to the external card to detect a link clock rate output by the clock source output switching module to the external card, wherein the link clock rate is a clock rate output by one of a plurality of clock sources to the clock source output switching module; A clock switching module is used to send a clock switching instruction to the clock source output switching module if the relative deviation between the link clock rate and the link real-time rate exceeds a first preset threshold, so that the clock source output switching module switches the clock source to the target clock source, and the relative deviation between the link clock rate output by the target clock source and the link real-time rate is within the first preset threshold.

9. A baseboard management controller, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the external card clock switching control method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the clock switching control method for an external card are implemented as claimed in any one of claims 1 to 7.

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