A multi-mode communication network structure for multi-core particle microsystems and a method of manufacturing the same

Abstract

The application relates to the technical field of integrated circuit packaging. The application provides a multi-mode communication network structure for a multi-core microsystem and a preparation method thereof. The structure comprises a silicon adapter plate, vertical through holes, a rewiring layer and a control power supply substrate. The silicon adapter plate is provided with multiple functional core particles, a communication mode selector core particle and one reconfigurable interconnection network core particle. Each functional core particle is connected to one communication mode selector core particle, and all the communication mode selector core particles are connected to the reconfigurable interconnection network core particle. The rewiring layer is located on the surfaces of the silicon adapter plate and the control power supply substrate, and the vertical through holes penetrate through the silicon adapter plate. The control power supply substrate is provided with two power management chips, which supply power for the functional core particles and the communication mode selector core particles and provide a control voltage for the reconfigurable interconnection network core particle. The structure constructed by the application has multi-mode communication and dynamic interconnection scheduling capabilities, and the reconfigurability of the system function and the utilization rate of the functional core particles are improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to a multi-mode communication network structure for a multi-chip microsystem and a preparation method thereof. Background Art

[0002] With the continued scaling of integrated circuit processes, traditional monolithic integrated design approaches have gradually exposed problems such as large design areas, long development cycles, and reduced yields, making it difficult to meet the growing demand for integration, flexibility, and reliability in multifunctional, high-performance electronic systems. In response to the increasing complexity and diversity of applications, microsystem integration technology has been proposed. This technology utilizes three-dimensional heterogeneous integration to combine multiple optimized small-scale functional cores to build a system, thereby improving system functional scalability and integration density. This technology has become a key path to achieving high-performance electronic systems.

[0003] However, existing microsystem integration methods still have limitations. Due to the limited functionality of individual chiplets, building complex system functions typically requires integrating a large number of chiplets, resulting in reduced overall chiplet utilization and increased system volume and mass, making it difficult to meet the requirements of application scenarios with high miniaturization, lightweighting, and high reliability. To alleviate these issues and improve system adaptability, existing technologies have proposed design concepts based on reconfigurable interconnect networks. By dynamically adjusting the interconnection relationships between chiplets, application-driven system function configuration is achieved, thereby optimizing design flexibility and resource utilization efficiency. Most existing reconfigurable interconnect networks are based on time-division multiplexing, that is, transmitting different types of signals in different time slices within the same electrical channel. Although this can improve interconnect resource utilization to a certain extent, since only a single signal can flow through the channel at any one time, large-scale microsystems composed of heterogeneous multi-chiplets still rely on multiple rewiring layers and a large number of vertical vias to establish complete signal pathways. This increases process complexity, reduces manufacturing yield, and causes system latency and energy consumption, making it difficult to meet the development needs of high-performance, multi-functional microsystems.

[0004] Therefore, there is an urgent need to provide a three-dimensional interconnected network structure that supports multi-mode communication and has dynamic reconfiguration capabilities, so as to further improve the functional reconfiguration capability, integration efficiency and overall system performance of multi-chip microsystems in complex application scenarios. Summary of the Invention

[0005] The purpose of the present invention is to address the deficiencies in the above-mentioned prior art and provide a multi-mode communication network structure for a multi-chip microsystem and a preparation method thereof, so as to solve the problems of low resource utilization, low system flexibility and high integration complexity in the prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] The present application provides a multi-mode communication network structure for a multi-chip microsystem, which includes a silicon adapter board, a vertical through-hole, a rewiring layer and a control power substrate. The silicon adapter board is provided with multiple different functional chips, multiple communication mode selector chips and a reconfigurable interconnection network chip. Each functional chip is connected to a corresponding communication mode selector chip, and multiple communication mode selector chips are connected to the reconfigurable interconnection network chip; the reconfigurable interconnection network chip includes multiple switch units for realizing dynamic communication path configuration between functional chips; vertical through-holes are set in the silicon adapter board, passing through the two side surfaces of the silicon adapter board, and connecting the rewiring layer; the rewiring layer is located on the surface of the silicon adapter board and the control power substrate, and is used to realize electrical connection between modules; a first power management chip and a second power management chip are provided on the control power substrate, the first power management chip supplies power to the functional chips and the communication mode selector chips, and the second power management chip provides control voltage to the reconfigurable interconnection network chip.

[0008] This application achieves multi-frequency modulation and dynamic reconfiguration of communication paths by constructing a multi-chip interconnect structure coordinated by a communication mode selector chip and a reconfigurable interconnect network chip. This solves the problems of fixed interconnect structures, low resource utilization, and lack of system reconfiguration capabilities in the prior art. Specifically, multiple functional chips are arranged on a silicon adapter board, and each functional chip is equipped with a communication mode selector chip, giving the functional chips independent communication access capabilities. The communication mode selector chip integrates modules such as mixers, filters, and power amplifiers to achieve frequency conversion and amplitude control of communication signals, enabling the functional chips to adapt to multiple communication frequency bands. Multiple switching units are arranged within the reconfigurable interconnect network chip to control the conduction and disconnection of signal transmission paths between functional chips, enabling flexible configuration and dynamic switching of communication paths. Vertical through-holes in the silicon adapter board run through the upper and lower surfaces and work in conjunction with the rewiring layers on each surface. This allows the first power management chip on the control power substrate to power the functional chips and the communication mode selector chip, and the second power management chip to provide control voltage to the reconfigurable interconnect network chip, achieving electrical control during the communication path configuration process. This structure not only optimizes the interconnect configuration mechanism but also simplifies overall wiring complexity by hierarchically dividing communication and power paths, improving system integration and adaptability. This structure possesses multi-mode communication capabilities and can support the interconnection of functional cores using time-division multiplexing or frequency-division multiplexing, effectively improving the utilization efficiency of interconnect channels and communication concurrency, thereby enhancing the functional flexibility of the system.

[0009] Furthermore, the communication mode selector core includes a transmit mixer, a receive mixer, a sideband suppression filter, an image filter, a power amplifier, a low-noise amplifier, a duplexer, and a tunable matching network. The transmit mixer's input is connected to the functional core, while its output is sequentially connected to the sideband suppression filter, power amplifier, and duplexer. The receive mixer's output is connected to the functional core, while its input is sequentially connected to the image filter, low-noise amplifier, and duplexer. The other end of the duplexer is connected to the reconfigurable interconnect network core via a tunable matching network. The communication mode selector core performs bidirectional frequency conversion, filtering, and power regulation on the functional core's communication signals, improving the stability and signal integrity of the overall communication link.

[0010] Furthermore, the communication mode selector core also includes an oscillator, which is connected to the transmit mixer and the receive mixer. The oscillator is used to provide a local oscillator signal to support frequency control and communication mode switching during the up and down conversion process.

[0011] Furthermore, the communication mode selector chip includes a frequency synthesizer, whose output is connected to the transmit mixer and receive mixer respectively. The frequency synthesizer includes a phase-locked loop circuit and a voltage-controlled oscillator. The frequency synthesizer provides multiple adjustable local oscillator signals to adapt to the frequency requirements of different communication modes.

[0012] Furthermore, the switch units include Class A and Class B switch units, which are used to construct different signal transmission paths. This multi-type switch unit configuration allows for flexible selection of paths with different transmission characteristics based on different communication requirements, thereby improving the system's signal integrity, communication reliability, and the adaptability of the interconnect structure.

[0013] Furthermore, a redundant switch unit connected in parallel with the switch unit is provided in the reconfigurable interconnection network core particle. The redundant switch unit is turned on when the switch unit fails, maintaining the communication function of the signal path, thereby improving the fault tolerance of the microsystem interconnection network and the continuity of the communication link, and enhancing the data transmission stability and function retention capability of the system in a fault state.

[0014] The present application also provides a method for preparing a multi-mode communication network structure, comprising the following steps:

[0015] S1. Prepare multiple communication mode selector cores and reconfigurable interconnect network cores;

[0016] S2, preparing multiple cavities and tapered vertical through holes on the silicon adapter plate;

[0017] S3, preparing a rewiring layer on the surface of the silicon adapter plate;

[0018] S4, placing multiple functional cores, multiple communication mode selector cores, and reconfigurable interconnect network cores in the chamber and bonding them together;

[0019] S5. Prepare micro bumps on the surface of the silicon adapter plate away from the chamber, and bond the silicon adapter plate to the control power supply substrate;

[0020] S6. Fill the gap between the silicon adapter board and the control power supply substrate, and encapsulate to obtain a multi-mode communication network structure.

[0021] Furthermore, in S1, the communication mode selector core is manufactured using a high-mobility transistor made of GaAs material, and the reconfigurable interconnect network core is manufactured using a silicon-on-insulator process.

[0022] Furthermore, in S2, a bonding auxiliary layer is locally provided at the bottom of multiple cavities. The bonding auxiliary layer includes a low melting point metal layer or a conductive adhesive material, which is used to improve connection reliability and position accuracy during the core particle placement and bonding process.

[0023] Furthermore, in S4, the functional chiplets are placed in the outermost chambers, the communication mode selector chiplets are placed in the inner chambers, and the reconfigurable interconnect network chiplets are placed in the central chamber. By optimizing the chiplet layout, signal transmission paths can be shortened, interconnection complexity can be reduced, and system communication efficiency and wiring regularity can be improved.

[0024] Furthermore, in the S5, the microbumps are plated using a ball-planting process and are cylindrical in shape. These cylindrical microbumps facilitate high-density, low-impedance vertical interconnections, improving the connection reliability between the chip module and the control power substrate.

[0025] Furthermore, the preparation method also includes preparing a control power substrate, installing the first power management chip and the second power management chip on the control power substrate in sequence, and completing the electrical connection between the first power management chip and the second power management chip and the corresponding modules respectively, providing stable energy supply and path control signals for each module.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) This application integrates multiple different functional cores on a silicon adapter board, and configures a communication mode selector core for each functional core, which is uniformly connected to a reconfigurable interconnect network core, to build a communication structure with multi-mode communication capabilities and a dynamic path scheduling mechanism. The communication mode selector core supports multiple modulation modes and frequency configurations. Combined with the reconfigurable interconnect network core, the communication path and mode can be switched on demand. This design solves the problems of fixed interconnection and limited functional configuration in existing microsystems, avoids the addition of redundant modules to adapt to different application scenarios, and improves functional reconfigurability, resource utilization, and system integration efficiency.

[0028] (2) This application constructs a multi-mode communication system that supports modulation, frequency conversion, and routing through the collaborative work of functional core particles, communication mode selector core particles, and reconfigurable interconnect network core particles. The communication mode selector core particle acts as a protocol adapter and signal conversion intermediary to achieve efficient connection between the functional core particles and the reconfigurable interconnect network core particles; the reconfigurable interconnect network core particles dynamically control the path and link resources to achieve flexible task reconstruction. This structure breaks through the problems of independent communication and single link of traditional microsystem modules, improves the system's communication coverage, protocol compatibility, and resource scheduling capabilities, and demonstrates the system innovation of multi-module collaborative enhancement.

[0029] (3) This application achieves interlayer interconnection between multi-chip modules by providing vertical through-holes in the silicon adapter plate and constructing a rewiring layer on its surface and the control power substrate. At the same time, the first and second power management chips are integrated on the control power substrate to provide support for power supply to the functional modules and interconnection path control, respectively. This vertical interconnection and layered power supply structure simplifies wiring complexity, improves signal transmission stability and packaging compactness, enhances the overall reliability and scalability of the system, and overcomes the problems of interconnection redundancy and process difficulties in traditional structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A three-dimensional schematic diagram of a multi-mode communication network structure for a multi-chip microsystem provided by the present invention;

[0031] Figure 2 for Figure 1 Electrical logic diagram of multi-mode communication network structure;

[0032] Figure 3 for Figure 1 The electrical logic diagram of the communication mode selector core in the multi-mode communication network structure;

[0033] Figure 4 for Figure 1 Electrical logic diagram of reconfigurable interconnect network core in multi-mode communication network structure;

[0034] Figure 5 for Figure 1 Schematic diagram of the structure of a Class A switch in a reconfigurable interconnect network core;

[0035] Figure 6 for Figure 1 Schematic diagram of the structure of the Class B switch in the reconfigurable interconnect network core;

[0036] Figure 7 for Figure 1 Flowchart of a method for preparing a multimode communication network structure.

[0037] Icons: 1-silicon adapter board; 2-vertical through hole; 3-rewiring layer; 4-control power substrate; 5-functional core particle; 6-communication mode selector core particle; 7-reconfigurable interconnect network core particle; 8-first power management chip; 9-second power management chip. DETAILED DESCRIPTION

[0038] In order to make the implementation process of the present invention clearer, it will be described in detail below with reference to the accompanying drawings.

[0039] Example 1:

[0040] The present invention provides a multi-mode communication network structure for a multi-chip microsystem, such as Figure 1 As shown, the structure includes a silicon adapter board 1, a vertical through-hole via 2 (TSV), a rewiring layer 3 (RDL) and a control power substrate 4. The silicon adapter board 1 is provided with multiple different functional cores 5, multiple communication mode selector cores 6 and a reconfigurable interconnect network core 7. Each functional core 5 is connected to a corresponding communication mode selector core 6, and multiple communication mode selector cores 6 are connected to the reconfigurable interconnect network core 7; the reconfigurable interconnect network core 7 includes multiple switch units for realizing dynamic communication path configuration between the functional cores 5; the vertical through-hole 2 is set in the silicon adapter board 1, passing through the two side surfaces of the silicon adapter board 1 and connecting the rewiring layer 3; the rewiring layer 3 is located on the surface of the silicon adapter board 1 and the control power substrate 4, for realizing electrical connection between modules; the control power substrate 4 is provided with a first power management chip 8 and a second power management chip 9. The first power management chip 8 supplies power to the functional core 5 and the communication mode selector core 6, and the second power management chip 9 provides control voltage to the reconfigurable interconnect network core 7.

[0041] In this embodiment, a total of six functional cores 5 are provided on the silicon adapter board 1. Each functional core 5 is connected to a communication mode selector core 6, forming six groups of functional interconnection units. All communication mode selector cores 6 are connected to a centrally located reconfigurable interconnect network core 7. This connection relationship is a hierarchical convergence method, with signals transmitted from the functional cores 5 to the communication mode selector cores 6 and finally to the reconfigurable interconnect network core 7, achieving unified signal scheduling and path configuration. Figure 2Figure 1 is a schematic diagram of the electrical connections between the modules in this multimode communication network structure. C1-C6 represent six functional cores 5, SD1-SD6 represent the corresponding six communication mode selector cores 6, and S1-S6 represent the six switch units within the reconfigurable interconnect network core 7. The signal output from each functional core 5 is connected to the reconfigurable interconnect network core 7 via the communication mode selector core 6. Switch units S1-S6 selectively conduct corresponding paths based on control voltages, thereby establishing dynamic point-to-point or multi-point communication channels between the functional cores 5, enabling flexible configuration of communication topologies.

[0042] This multimode communication network structure achieves electrical connections between various cores and the control power substrate 4 through a rewiring layer 3. Each substrate surface is provided with a rewiring layer 3 composed of metal leads for horizontally transmitting data and power signals. Vertical vias 2 running through the upper and lower surfaces of the silicon adapter board 1 form interlayer interconnect channels, enabling vertical electrical connections between different functional layers. The first power management chip 8 and the second power management chip 9 on the control power substrate 4 output operating voltage and switch unit control voltage, respectively. The generated voltage signals are transmitted through the vertical vias 2 and the rewiring layer 3 to the various cores on the upper surface of the silicon adapter board 1, achieving hierarchical power supply. Communication scheduling signals in the reconfigurable interconnect network core 7 can also be transmitted downward to the control power substrate 4 through the vertical vias 2 and further extended to the system's external interface through its internal fan-out vias, completing the closed-loop configuration of the communication path and connecting to external links. Through the three-dimensional interconnect structure formed by the vertical vias 2 and the rewiring layer 3, the system achieves stable electrical coupling between modules, effectively reducing wiring complexity and improving packaging integration efficiency, facilitating the implementation of multi-core interconnect architectures in high-density microsystems.

[0043] like Figure 3As shown, the communication mode selector core 6 forms the interface conversion unit between each functional core 5 and the reconfigurable interconnect network core 7. It integrates an oscillator, a transmit mixer, a sideband suppression filter, a power amplifier, a duplexer, a receive mixer, an image filter, a low-noise amplifier, and a tunable matching network, performing frequency conversion, bandwidth filtering, power regulation, and direction switching for both transmit and receive signals. In the transmit path, the modulated signal from the functional core 5 is mixed with the local oscillator signal output by the transmit mixer to generate an RF signal at a specified frequency. After the modulated sidebands are removed by the sideband suppression filter, it is fed into the power amplifier to enhance its driving capability. Finally, it is output to the reconfigurable interconnect network core 7 through the duplexer and tunable matching network. In the receive path, the external signal enters the low-noise amplifier through the tunable matching network and duplexer. After the signal amplitude is boosted, the image frequency component is filtered out by the image filter. The receive mixer then down-converts the signal with the local oscillator signal, restoring it to baseband before outputting it to the corresponding functional core 5. The transmit and receive paths are combined via a duplexer, and the port impedance is adjusted via a tunable matching network to adapt to the load conditions between different functional cores 5 and the interconnection path. The local oscillator frequency configured for each communication mode selector core 6 can be independently set according to its connection requirements, allowing multiple functional cores 5 to operate in parallel at different frequencies, establishing a frequency-division multiplexed communication channel and achieving channel isolation and concurrent transmission during the interconnection process.

[0044] In this embodiment, the oscillator in the communication mode selector core 6 provides a fixed-frequency local oscillator signal to support frequency conversion in the communication mode. To accommodate multi-band communication requirements, an integrated frequency synthesizer architecture can also be used. The frequency synthesizer includes a phase-locked loop circuit and a voltage-controlled oscillator, which can switch the output frequency based on a control signal. This provides the communication mode selector core 6 with frequency tunability and supports frequency division multiplexing of multiple communication channels. This architecture not only enhances the signal adaptation capabilities between functional cores 5 but also improves the system's compatibility with heterogeneous communication protocols and the multiplexing efficiency of concurrent links.

[0045] The reconfigurable interconnect network core particle 7 constitutes the control center for signal routing between multiple functional core particles 5, such as Figure 4 As shown, its structure consists of a matrix of multiple switch units with configurable states. The reconfigurable interconnect network core 7 is equipped with six communication ports on its periphery, corresponding to the input and output channels of each communication mode selector core 6. The central area is a staggered switch array structure. Each switch unit is used to control the signal path between a group of input ports and output ports, and realizes the selection control and logical configuration of the communication path under the action of the control signal. By adjusting the state combination of each switch unit, a variety of interconnect topologies such as point-to-point, star, and chain can be dynamically constructed between multiple communication mode selector cores 6 to meet the reconfiguration requirements of the multi-functional system structure.

[0046] The switch units include Class A switch units and Class B switch units, which are used to construct signal transmission paths with different characteristics. Among them, Class A switches include S2, S3, S5, and S6, and Class B switches include S1 and S4. Both types of switch units are composed of N-type field effect transistors, and their conduction state is determined by the control voltage provided by the external second power management chip 9. When the gate voltage is greater than the threshold voltage, it is turned on, and when it is less than the threshold voltage, it is turned off. It has good linearity and switching rate. Figure 5 As shown, the Class A switch unit is a bidirectional series path structure, suitable for low-loss, high-isolation point-to-point connection scenarios. It is composed of a series transistor and a ground bypass transistor. When the main channel transistor is turned on, normal signal transmission is achieved. When the main channel is closed and the bypass channel is turned on, the interference signal can be effectively grounded to avoid crosstalk to other paths. Taking the switch unit S3 as an example, it is composed of a series transistor M1 and parallel transistors M2 and M3. When a transmission path from P1 to P2 needs to be established, the control signal increases the gate voltage V C1 Set to high level (i.e. greater than the threshold voltage), the gate voltages V C2 、V C3 Set to a low level to turn on M1 and turn off M2 and M3, thereby establishing a conduction path between the P1 port and the P2 port, and signals can be transmitted in both directions.

[0047] like Figure 6 As shown in Figure 1, the Class B switch unit supports switching connections between multiple input and output terminals, and can build multi-path selection, bypass redundancy or broadcast connection modes. It is suitable for multi-target distribution, dynamic link switching or multiplexing channel configuration scenarios. Taking the switch unit S1 as an example, it is composed of series transistors M4 and M5 and parallel transistors M6 and M7. When a transmission path from P6 to Px needs to be established, the gate voltage V C5 、V C7 Set to high level, the gate voltage of M4 and M6 V C4 and V C6 Set to low level, M5 and M7 are turned on, M4 and M6 are turned off, so that a conductive path is established between the P6 port and the Px port through M5. The interference signal from the P1 port is grounded through the bypass path formed by the turned-on M7, which will not affect the connection path of other ports. Similarly, when a transmission path from P1 to Px needs to be established, the gate voltage V C5 、V C7 Set to high level, the gate voltage of M5 and M7 V C4 and V C6Set to a low level, M4 and M6 are turned on, and M5 and M7 are turned off, so that a conduction path is established between the P1 port and the Px port through M4. The interference signal from other transmission paths is grounded through the bypass path formed by the turned-on transistor M6, eliminating the interference to the connection path between the P1 port and the Px port.

[0048] To improve the stability and fault tolerance of communication links, redundant switch units are installed at the nodes of the main communication paths used to connect different communication mode selector cores 6 in the reconfigurable interconnect network core 7. These redundant switch units are arranged in parallel with the corresponding switch channels, sharing input and output ports and providing independent control channels. In the event of a corresponding path control failure, abnormal signal response, or the switch not turning on in time, the redundant switch can be activated to maintain the path connection state, ensuring the uninterrupted operation of the critical communication link. This redundant structure improves the reliability of the communication paths in the multi-core system and the fault tolerance of the overall interconnect structure, making it suitable for microsystem operating scenarios with high requirements for interconnection stability.

[0049] Example 2:

[0050] like Figure 1 and Figure 2 As shown, in order to further illustrate the specific application of the multi-mode communication network structure in the microsystem, this embodiment takes system function A as an example for description.

[0051] In this Function A scenario, C1 and C2 need to achieve bidirectional communication. That is, C1 sends signals to C2 and C2 also sends signals to C1. To achieve this communication requirement, switch unit S2 between C1 and C2 in the reconfigurable interconnection network core 7 is turned on, while the other switch units are turned off, establishing a bidirectional signal transmission channel. The following describes the signal transmission path from C1 to C2 and the signal reception path for C1.

[0052] In the transmit path, the modulated signal output by C1 first enters the corresponding SD1, where its signal terminal is connected to one input of the transmit mixer. The local oscillator signal provided by the oscillator is simultaneously input to the other port of the transmit mixer. Both are up-converted through spectrum shifting to produce an RF signal at the set frequency. This signal then enters a sideband suppression filter, which removes interference components caused by upper and lower sidebands and local oscillator leakage generated during the mixing process, thereby improving the signal's spectral purity. Since the filtered RF signal has a low amplitude, it is then input to a power amplifier for amplitude amplification. This amplified signal has sufficient driving force to reach the target functional core 5 through the interconnect path. To further suppress higher harmonics introduced during the amplification process and prevent interference with other frequency bands or switch units in the system, the signal is bandpass filtered through a duplexer. Finally, after impedance adjustment by a tunable matching network, the signal is transmitted along the transmission path formed by switch unit S2 to SD2, where it enters the C2 receive link.

[0053] In the receive path, the signal from C2 is transmitted to SD1 via S2. First, the signal passes through a tunable matching network for impedance integration to ensure maximum power transmission. It then enters a duplexer for directional signal separation and preliminary bandpass processing, while also attenuating high-amplitude signals to prevent post-processing modules from entering the nonlinear operating region. The attenuated target frequency band signal is then fed into a low-noise amplifier for linear gain amplification to improve the signal-to-noise ratio of weak signals. The amplified signal then enters an image filter, effectively suppressing image interference in the mixing stage and further improving the signal's spectral accuracy. Finally, the RF signal enters the receive mixer, where it is downconverted with the local oscillator signal. This is converted to an intermediate frequency (IF) or baseband signal and output to C1, completing the receive process.

[0054] Through the above-mentioned communication path design and module collaborative processing mechanism, accurate bidirectional signal transmission between C1 and C2 is achieved, demonstrating the application capability of this communication structure to implement function A in a multi-chip system and verifying its communication path reconfigurability and multi-mode signal processing capability.

[0055] Example 3:

[0056] In this embodiment, in order to demonstrate the adaptability of the multi-mode communication network structure in the scenarios of multi-target concurrent communication and system function reconstruction, the communication configuration process when the system function B is implemented is constructed.

[0057] In the function B scenario, if Figure 1 and Figure 2 As shown, C1 sends a signal to C3, and C2 needs to send signals to C1 and C3 respectively, forming a three-way concurrent multi-mode communication relationship. At this time, when switch units S2 and S3 are turned on and the other switch units are turned off, three communication paths are established: C1-C3, C2-C1, and C2-C3.

[0058] When C1 transmits a signal to C3, the signal first enters SD1. Following the transmit path processing described in Example 2, it sequentially passes through the transmit mixer, sideband filter, power amplifier, duplexer, and tunable matching network, completing frequency conversion, harmonic suppression, and signal amplification. The signal is then transmitted via matching paths from S2 and S3 to the SD3 port. In SD3, downconversion, image suppression, and amplitude recovery are performed according to the receive processing described in Example 2, and the signal is ultimately received by C3. This process fully leverages the gain compensation and anti-interference capabilities of the multi-stage conditioning link in long-distance, multi-node communications, ensuring sufficient signal recognition strength and spectral purity during cross-path transmission.

[0059] When C2 sends signals to C1 and C3, respectively, SD2 performs the same transmission link processing as in Example 2. The former is transmitted to and received by SD1 via switch unit S2, while the latter is transmitted to and received by SD3 via S3. These two communication paths demonstrate both the flexibility of the interconnection path in resource reuse and the system's adaptability to concurrent communication tasks, meeting the application requirements of microsystems that require asynchronous and heterogeneous task scheduling.

[0060] In a multi-chiplet system, when reconfiguring other system functions, one simply configures the on / off states of the switch units in the reconfigurable interconnection network chiplet 7 according to the target communication relationship and completes signal transmission or reception processing in the communication mode selector chiplet 6 to establish the required communication path. This decoupling of path control and signal modulation allows the system to flexibly construct any communication topology based on actual mission requirements, enhancing the reconfiguration adaptability and scalability of the microsystem architecture in complex functional scenarios.

[0061] Example 4:

[0062] The present invention also provides a method for preparing a multi-mode communication network structure. Taking the structure in Example 1 as an example, Figure 7 As shown, the following steps are included:

[0063] S1. Prepare multiple communication mode selector cores 6 and reconfigurable interconnect network cores 7. To meet the signal transmission requirements of high-frequency communication environments, the reconfigurable interconnect network core 7 utilizes a monolithic integrated structure, fabricated using a silicon-on-insulator (SOI) process at a 130nm process node. This process offers excellent device isolation and low parasitic coupling, making it suitable for constructing switch matrix structures and integrating control logic. After wafer fabrication, laser dicing is performed to produce a single reconfigurable interconnect network core 7 with six communication ports. The communication mode selector core 6 utilizes high-electron-mobility transistors based on GaAs as its device structure, offering excellent high-frequency gain and linear modulation capabilities, making it suitable for integrating RF front-end functions such as signal modulation and frequency synthesis. In this embodiment, the communication mode selector core 6 is fabricated on-chip using a 130nm process node. Six communication mode selector cores 6 for multimode communication configuration are obtained through laser dicing.

[0064] S2, prepare multiple chambers and tapered vertical through holes 2 on the silicon adapter plate 1; use dry etching process to process 13 rectangular chambers on the silicon adapter plate 1 with a thickness of 200 μm. The chambers adopt an annular structure and are symmetrically distributed, such as Figure 1As shown, the six outer chambers house functional cores 5, the six central chambers house communication mode selector cores 6, and the central chamber houses reconfigurable interconnect network cores 7. The length and width of each chamber are 1.5 times the size of the corresponding core, and the depth is 1.5-2.5μm to meet the structural requirements for the packaging and positioning of each core. This layout helps optimize the spacing between cores and signal paths, improving the compactness of the interconnect structure.

[0065] After the cavity structure is prepared, a tapered vertical through hole 2 is prepared in the silicon adapter plate 1. The vertical through hole 2 has a wide end on the side where the cavity is located and has an inverted cone structure. It is used to achieve cross-layer electrical connection and ensure the spatial adaptability and electrical reliability of the packaging structure. The preparation process is as follows:

[0066] 1) Using a laser with a wavelength of 300 nm, a frequency of 150 kHz, a pulse width of 30 ns, and a pulse energy of 300 μJ, four vertical through holes 2 are etched in the silicon adapter plate 1;

[0067] 2) Injecting polymer material into the hole and ablating it with a 1kW laser power to obtain a thermally stable polymer inner wall;

[0068] 3) Deposit an insulating barrier layer on the hole wall using a sputtering process under argon gas, using Si3N4 as the sputtering target, a RF source frequency of 13.56 MHz, a power of 25 W, a pre-sputtering power of 30 W, and a processing time of 5 minutes;

[0069] 4) A metal seed layer is constructed on the surface of the barrier layer through a physical vapor deposition process. Subsequently, copper metal is filled using an electroplating process with a current density of 30A / cm² and a CuSO4 concentration of 0.5mol / L. The upper and lower surfaces of the silicon adapter plate 1 are mechanically polished to form conductive vias with stable electrical performance and complete structure.

[0070] S3. Prepare a rewiring layer 3 on the surface of the silicon adapter board 1; to achieve electrical interconnection between the various functional modules, after completing the cavity and vertical through-hole 2 structure, construct a rewiring layer 3 on the upper and lower surfaces of the silicon adapter board 1. The rewiring layer 3 is composed of metal leads, which extend along the plane direction to connect various core pins, vertical through-hole 2 electrodes and the docking points of the lower control power substrate 4, forming a complete signal and power transmission path. The preparation of the rewiring layer 3 includes depositing silicon nitride as a diffusion barrier layer at the bottom and surface area of ​​the cavity to limit the diffusion of metal ions and enhance metal adhesion, and then continuing to deposit silicon dioxide to form an electrical insulation layer to ensure that subsequent metal leads do not interfere with each other. Subsequently, the Damascus process is used to pattern the interconnection channel in the insulation layer, and after filling the metal material, chemical mechanical polishing is combined to form a continuous wiring structure to complete the interlayer interconnection and path closure. Finally, a passivation protective layer is applied to the entire surface to enhance the structure's oxidation resistance and long-term working stability.

[0071] S4, place multiple functional core particles 5, multiple communication mode selector core particles 6 and reconfigurable interconnect network core particles 7 in the chamber and bond them together; place 6 functional core particles 5, 6 communication mode selector core particles 6 and 1 reconfigurable interconnect network core particle 7 in the corresponding position chambers in sequence according to the chamber layout in step S2. In order to improve the accuracy and stability of the placement of various core particles, a cross-shaped alignment mark is preset at the center of each cavity using a positive mark process. The mark line length is 100μm and the line width is 50μm to assist in the precise positioning of each core particle. After the various core particles are placed, a hot pressing bonding process is used to ensure that the pins of various core particles form reliable contact with the prefabricated metal interconnect structure of the silicon adapter board 1, thereby achieving electrical connection and completing preliminary fixation. After bonding, epoxy resin is injected into the gap area between each core particle and the chamber and cured to further enhance the fixing strength of each core particle and the sealing performance of the packaging structure, thereby improving the environmental stability and mechanical reliability of the system in actual application.

[0072] S5. Microbumps are prepared on the surface of the silicon adapter plate 1 away from the chamber, and the silicon adapter plate 1 is bonded and fixed to the control power supply substrate 4. Multiple microbump structures for connecting to the control power supply substrate 4 are set on the lower surface of the silicon adapter plate 1 away from the chamber. This structure is used to complete vertical electrical interconnection and enhance mechanical support. The microbumps are made of copper material and formed into a regular array in the pad area using an electroplating process. The electroplating rate is controlled at 0.5μm / min, and a cylindrical microbump structure is finally formed. After the microbumps are formed, the silicon adapter plate 1 is aligned with the pad area of ​​the control power supply substrate 4 and bonded by hot pressing. The bonding pressure is set to 500kPa and the bonding temperature is set to 300℃ to ensure that each microbump forms a stable contact with the corresponding pad, achieving interlayer structural bonding and establishing a conductive path. This structure provides a channel for cross-layer transmission of system signals and power, while also having good thermal compatibility and mechanical connection stability, which is conducive to the long-term operation of the system in different working environments.

[0073] S6. Fill the gap between the silicon adapter board 1 and the control power substrate 4, and encapsulate to obtain a multi-mode communication network structure. After the silicon adapter board 1 and the control power substrate 4 are bonded, in order to improve the structural stability and adaptability to the working environment, an epoxy filling material is injected into the bonding gap using a potting process. The material fills all gaps in a flowing state and then solidifies to form a continuous support layer. This filling layer can enhance the mechanical support effect and isolate moisture and dust from entering the interior of the structure, thereby ensuring the long-term reliability of the electrical connection within the package. After completing the filling of the internal gaps, the overall structure is assembled into a metal shell to form a complete package module. The shell is made of aluminum alloy material and has good thermal conductivity and electromagnetic shielding capabilities, so that the multi-mode communication network structure has electrical interfaces, power supply ports and heat dissipation support functions, and can be directly integrated into the target microsystem platform.

[0074] In this embodiment, to further improve the connection quality and long-term reliability between the various core particles and the silicon adapter board 1, a bonding auxiliary layer is applied to localized areas at the bottom of each of the 13 cavities in step S2. This bonding auxiliary layer provides excellent interface contact performance, thermal conductivity, and electrical connection stability during the placement and bonding of the various core particles, thereby improving the mechanical strength and electrical continuity of the overall interconnect structure. Specifically, the bonding auxiliary layer can be composed of a low-melting-point metal material (such as SnAgCu alloy or AuSn alloy) or a conductive adhesive material (such as silver paste or conductive epoxy resin). The low-melting-point metal layer rapidly melts and flows during the thermocompression bonding process, filling the micro-nano gaps between the bottom of the various core particles and the bottom of the cavity, forming a continuous metal weld layer, reducing interfacial resistance and enhancing thermal conductivity. The conductive adhesive material achieves strong adhesion and reliable conductivity under normal or low-pressure curing conditions, making it suitable for thermally sensitive components or complex interconnect configurations. To improve the uniformity and interfacial bonding performance of the auxiliary layer, the auxiliary material can be deposited locally in the center of the cavity bottom surface by screen printing, dispensing, or sputtering. In material selection, performance parameters such as melting point, conductivity and thermal expansion coefficient can be comprehensively considered based on the size of various core particles, current load requirements and thermal diffusion path to ensure the electrical stability and structural integrity of various core particles during subsequent use.

[0075] The preparation method in this embodiment also includes a prefabrication process of the control power substrate 4. Specifically, the installation operations of the first power management chip 8 and the second power management chip 9 are completed in sequence on the control power substrate 4 on which the rewiring layer 3 is prepared, and the first power management chip 8 and the second power management chip 9 are fixed in a preset position by surface mounting or bonding connection, and the electrical connection between the first power management chip 8 and the second power management chip 9 and each target module in the silicon adapter board 1 is completed. The first power management chip 8 is mainly responsible for providing working voltage for the multi-chip functional core 5 and the communication mode selector core 6, and the second power management chip 9 is used to provide adjustable control voltage to the reconfigurable interconnect network core 7 to realize the energy supply control of the path configuration and communication switching function. Through the hierarchical configuration design of the above-mentioned power module, the independence of the power supply path and the response efficiency of the communication control in the multi-core system can be effectively improved, and the operation stability of the overall structure in a complex working environment can be enhanced.

[0076] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A multi-mode communication network structure for a multi-chip microsystem, comprising a silicon adapter plate, vertical vias, a redistribution layer, and a control power substrate, characterized in that: The silicon adapter board is provided with multiple different functional cores, multiple communication mode selector cores and a reconfigurable interconnect network core, each of the functional cores is connected to a corresponding communication mode selector core, and multiple communication mode selector cores are connected to the reconfigurable interconnect network core; the reconfigurable interconnect network core includes multiple switch units for realizing dynamic communication path configuration between the functional cores; the vertical through hole is arranged in the silicon adapter board, passing through the two side surfaces of the silicon adapter board, and connecting the rewiring layer; the rewiring layer is located on the surface of the silicon adapter board and the control power substrate, for realizing electrical connection between modules; the control power substrate is provided with a first power management chip and a second power management chip, the first power management chip supplies power to the functional core and the communication mode selector core, and the second power management chip provides control voltage to the reconfigurable interconnect network core.

2. The multi-mode communication network structure for a multi-chip microsystem according to claim 1, characterized in that: The communication mode selector core comprises a transmitting mixer, a receiving mixer, a sideband suppression filter, a mirror filter, a power amplifier, a low-noise amplifier, a duplexer and a tunable matching network; the input end of the transmitting mixer is connected to the functional core, and the output end is connected to the sideband suppression filter, the power amplifier and the duplexer in sequence; the output end of the receiving mixer is connected to the functional core, and the input end is connected to the mirror filter, the low-noise amplifier and the duplexer in sequence, and the other end of the duplexer is connected to the reconfigurable interconnection network core through the tunable matching network.

3. The multi-mode communication network structure for a multi-chip microsystem according to claim 2, characterized in that: The communication mode selector core also includes an oscillator, which is connected to the transmit mixer and the receive mixer.

4. The multi-mode communication network structure for a multi-chip microsystem according to claim 2, characterized in that: A frequency synthesizer is provided in the communication mode selector core particle, and its output end is connected to the transmitting mixer and the receiving mixer respectively. The frequency synthesizer includes a phase-locked loop circuit and a voltage-controlled oscillator.

5. The multi-mode communication network structure for a multi-chip microsystem according to claim 1, characterized in that: The switch units include type A switch units and type B switch units, which are used to construct different signal transmission paths.

6. The multi-mode communication network structure for a multi-chip microsystem according to claim 5, characterized in that: The reconfigurable interconnect network core is provided with a redundant switch unit connected in parallel with the switch unit. When the switch unit fails, the redundant switch unit is turned on to maintain the communication function of the signal path.

7. A method for preparing a multimode communication network structure, characterized in that: The method comprises the following steps: S1. Prepare multiple communication mode selector cores and reconfigurable interconnect network cores; S2, preparing multiple cavities and tapered vertical through holes on the silicon adapter plate; S3, preparing a rewiring layer on the surface of the silicon adapter plate; S4, placing multiple functional core particles, multiple communication mode selector core particles, and the reconfigurable interconnect network core particle in the chamber and bonding them together; S5, preparing micro bumps on the surface of the silicon adapter plate away from the chamber, and bonding the silicon adapter plate to the control power supply substrate; S6. Fill and package the gap between the silicon adapter board and the control power supply substrate to obtain the multi-mode communication network structure.

8. The method for preparing a multimode communication network structure according to claim 7, wherein: In S1, the communication mode selector core is manufactured using a high-mobility transistor made of GaAs material, and the reconfigurable interconnect network core is manufactured using a silicon-on-insulator process.

9. The method for preparing a multimode communication network structure according to claim 8, characterized in that: In S2, a bonding auxiliary layer is partially provided on the bottom of the plurality of cavities, and the bonding auxiliary layer includes a low melting point metal layer or a conductive adhesive material.

10. The method for preparing a multi-mode communication network structure according to claim 9, characterized in that: In S4, the functional core is placed in the outermost cavity, the communication mode selector core is placed in the inner cavity, and the reconfigurable interconnect network core is placed in the central cavity.

11. The method for preparing a multi-mode communication network structure according to claim 10, characterized in that: In S5, the micro-bumps are electroplated using a ball planting process and have a cylindrical shape.

12. The method for preparing a multi-mode communication network structure according to claim 11, characterized in that: The preparation method also includes preparing the control power substrate, sequentially installing a first power management chip and a second power management chip on the control power substrate, and completing the electrical connection between the first power management chip and the second power management chip and the corresponding modules respectively.

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