Laminated electronic device

Abstract

The laminated electronic device includes a first inductor, a second inductor, a capacitor, and a laminated body. The first inductor and the second inductor are disposed such that the first opening of the first inductor and the second opening of the second inductor do not face each other. The capacitor includes a capacitor conductor layer. The capacitor conductor layer includes a first overlapping portion that overlaps at least one first inductor conductor layer constituting the first inductor when viewed from the lamination direction.

Description

Technical Field

[0001] The present invention relates to an electronic device including an inductor and a capacitor. Background Art

[0002] Various filters such as low-pass filters, high-pass filters, and band-pass filters are composed of a plurality of resonators. As the resonators used in these filters, for example, LC resonators composed of an inductor and a capacitor are known. As the inductor, an inductor composed of a line is known. Generally, a plurality of inductors and a plurality of capacitors are provided in a filter.

[0003] In Japanese Patent Application Laid-Open No. 2010-178380, a high-frequency switching module is disclosed in which a low-pass filter and a high-pass filter are formed in a laminate, and a band-pass filter is mounted on the laminate. A plurality of transmission lines and a plurality of capacitors are provided in the laminate.

[0004] In recent years, there has been a market demand for miniaturization and space saving of small mobile communication devices, and also for miniaturization of filters used in such communication devices. In a filter composed of a laminate, it is required to miniaturize the laminate while satisfying desired characteristics. In order to further miniaturize the filter, it is necessary to efficiently arrange a plurality of inductors and a plurality of capacitors in the laminate. However, there is a limit to miniaturizing the laminate by optimizing the arrangement of a plurality of inductors and a plurality of capacitors without impairing the respective functions of the plurality of inductors and the plurality of capacitors.

[0005] The above problems are not limited to filters, but apply to all electronic devices including inductors and capacitors. Summary of the Invention

[0006] (I) Technical Problem to be Solved

[0007] An object of the present invention is to provide a laminated electronic device that can be miniaturized without impairing the respective functions of an inductor and a capacitor.

[0008] (II) Technical Solution

[0009] The stacked electronic device according to the first aspect of the present invention includes: a first inductor; a second inductor; a capacitor; and a stacked body which is a stacked body for integrating the first inductor, the second inductor, and the capacitor and includes a plurality of dielectric layers stacked. The first inductor includes at least one first inductor conductor layer which is wound around a first axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The second inductor includes at least one second inductor conductor layer which is wound around a second axis extending in a direction parallel to the stacking direction. The first inductor and the second inductor are arranged such that when viewed from the stacking direction, a first opening surrounded by at least one first inductor conductor layer does not overlap with a second opening surrounded by at least one second inductor conductor layer. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from at least one second inductor conductor layer toward at least one first inductor conductor layer when viewed from the stacking direction, and includes a first overlapping portion which overlaps with at least one first inductor conductor layer when viewed from the stacking direction.

[0010] The stacked electronic device according to the second aspect of the present invention includes: an inductor; a capacitor; and a stacked body which is a stacked body for integrating the inductor and the capacitor and includes a plurality of dielectric layers stacked. The inductor includes at least one inductor conductor layer which is wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The at least one inductor conductor layer includes an extending portion having a specified length and a smooth outer edge. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from the outside of at least one inductor conductor layer toward an opening surrounded by at least one inductor conductor layer when viewed from the stacking direction, and includes a first overlapping portion which overlaps with the extending portion when viewed from the stacking direction.

[0011] (III) Advantageous Effects

[0012] In the stacked electronic device according to the first aspect of the present invention, the capacitor conductor layer includes a first overlapping portion which overlaps with at least one first inductor conductor layer when viewed from the stacking direction. Thus, the stacked electronic device according to the first aspect of the present invention can be miniaturized without impairing the respective functions of the inductor and the capacitor.

[0013] In the stacked electronic device according to the second aspect of the present invention, the capacitor conductor layer includes a first overlapping portion which overlaps with at least one inductor conductor layer when viewed from the stacking direction. Thus, the stacked electronic device according to the second aspect of the present invention can be miniaturized without impairing the respective functions of the inductor and the capacitor.

[0014] Other objects, features, and advantages of the present invention will become fully apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit diagram showing the circuit structure of an electronic device in one embodiment of the present invention.

[0016] Figure 2 is a perspective view showing an electronic device in one embodiment of the present invention.

[0017] Figure 3 is a perspective view showing a stacked electronic device in one embodiment of the present invention.

[0018] Figure 4 is a perspective view showing a stacked electronic device in one embodiment of the present invention.

[0019] Figures 5A to 5C is an explanatory view showing the pattern formation surfaces of the first to third dielectric layers in the stack of a stacked electronic device in one embodiment of the present invention.

[0020] Figure 6A is an explanatory view showing the pattern formation surface of the fourth dielectric layer in the stack of a stacked electronic device in one embodiment of the present invention.

[0021] Figure 6B is an explanatory view showing the pattern formation surfaces of the fifth and sixth dielectric layers in the stack of a stacked electronic device in one embodiment of the present invention.

[0022] Figure 6C is an explanatory view showing the pattern formation surface of the seventh dielectric layer in the stack of a stacked electronic device in one embodiment of the present invention.

[0023] Figure 7A is an explanatory view showing the pattern formation surfaces of the eighth and ninth dielectric layers in the stack of a stacked electronic device in one embodiment of the present invention.

[0024] Figure 7B and Figure 7C is an explanatory view showing the pattern formation surfaces of the tenth and eleventh dielectric layers in the stack of a stacked electronic device in one embodiment of the present invention.

[0025] Figures 8A to 8C is an explanatory view showing the pattern formation surfaces of the twelfth to fourteenth dielectric layers in the stack of a stacked electronic device in one embodiment of the present invention.

[0026] Figures 9A to 9CIt is an explanatory diagram showing the pattern formation surfaces of the fifteenth to seventeenth dielectric layers in the stack of the stacked electronic device according to an embodiment of the present invention.

[0027] Figure 10A And Figure 10B It is an explanatory diagram showing the pattern formation surfaces of the eighteenth and nineteenth dielectric layers in the stack of the stacked electronic device according to an embodiment of the present invention.

[0028] Figure 10C It is an explanatory diagram showing the electrode formation surface of the nineteenth dielectric layer.

[0029] Figure 11 It is a perspective view showing the inside of the stack of the stacked electronic device according to an embodiment of the present invention.

[0030] Figure 12 It is a top view showing the inside of the stacked electronic device according to an embodiment of the present invention.

[0031] Figure 13 It is a circuit diagram showing the structure of an inductor in an embodiment of the present invention.

[0032] Figure 14 It is a top view showing two inductors and a capacitor in an embodiment of the present invention.

[0033] Figure 15 It is a top view showing two inductors and a capacitor in an embodiment of the present invention.

[0034] Figure 16 It is an explanatory diagram showing the arrangement of two inductors and a capacitor in the stack in an embodiment of the present invention.

[0035] Figure 17 It is a characteristic diagram showing an example of the passing attenuation characteristics of the electronic device in an embodiment of the present invention. Detailed Embodiments

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, the schematic structure of the electronic device 1 including the stacked electronic device according to an embodiment of the present invention will be described. The electronic device 1 in the present embodiment is a band-pass filter that selectively passes signals of frequencies within a specified passband.

[0037] The electronic device 1 in the present embodiment is a so-called hybrid filter, which includes at least one LC resonator composed of at least one inductor and at least one capacitor, and an elastic wave resonator composed of at least one elastic wave element. The at least one elastic wave element can be, for example, a bulk acoustic wave element or a surface acoustic wave element.

[0038] Next, with reference to Figure 1 , an example of the circuit structure of the electronic device 1 will be described. Figure 1 FIG. is a circuit diagram showing the circuit structure of the electronic device 1. The electronic device 1 includes: a first input / output terminal 2, a second input / output terminal 3, and a filter circuit provided between the first input / output terminal 2 and the second input / output terminal 3 in the circuit structure. In addition, in the present application, the expression "in the circuit structure" is used to indicate the configuration on the circuit diagram, rather than the configuration in the physical structure.

[0039] The first input / output terminal 2 and the second input / output terminal 3 are terminals for inputting or outputting signals, respectively. That is, when a signal is input to the first input / output terminal 2, the signal is output from the second input / output terminal 3. When a signal is input to the second input / output terminal 3, the signal is output from the first input / output terminal 2.

[0040] The filter circuit includes inductors L1, L2, L3, L5, L6, L7 and capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11. One end of the inductor L1 is connected to the first input / output terminal 2. One end of the inductor L2 is connected to the other end of the inductor L1.

[0041] One end of the capacitor C4 is connected to the other end of the inductor L2. One end of the capacitor C5 is connected to the other end of the capacitor C4. One end of the capacitor C6 is connected to the other end of the capacitor C5. One end of the capacitor C7 is connected to the other end of the capacitor C6. One end of the capacitor C8 is connected to the other end of the capacitor C7.

[0042] One end of the capacitor C11 is connected to the other end of the capacitor C8. One end of the inductor L7 is connected to the other end of the capacitor C11. The other end of the inductor L7 is connected to the second input / output terminal 3.

[0043] The capacitor C1 is connected in parallel with respect to the inductor L1. One end of the capacitor C2 is connected to the connection point of the inductor L1 and the inductor L2. One end of the capacitor C3 is connected to the connection point of the inductor L2 and the capacitor C4. The other ends of the capacitors C2 and C3 are connected to the ground member.

[0044] One end of the inductor L3 is connected to the connection point of the capacitor C4 and the capacitor C5. One end of the inductor L5 is connected to the connection point of the capacitor C6 and the capacitor C7. The other ends of the inductors L3 and L5 are connected to the ground member.

[0045] One end of inductor L6 is connected to the connection point of capacitor C8 and capacitor C11. One end of capacitor C10 is connected to the other end of inductor L6. The other end of capacitor C10 is connected to the grounding member.

[0046] One end of capacitor C9 is connected to one end of inductor L3 and capacitor C5 respectively. The other end of capacitor C9 is connected to one end of inductor L6 and the other end of capacitor C8.

[0047] The filter circuit further includes: signal terminals 81, 82, 83, 84; a surface acoustic wave element 31 disposed between signal terminals 81 and 82 in the circuit structure; and a surface acoustic wave element 32 disposed between signal terminals 83 and 84 in the circuit structure.

[0048] The filter circuit further includes signal terminals 11, 12, 13, 14 respectively connected to signal terminals 81, 82, 83, 84. In addition, in Figure 1 For convenience, signal terminal 12 is depicted as being between one end of capacitor C9 and one end of capacitor C5. However, signal terminal 12 may not be between one end of capacitor C9 and one end of capacitor C5.

[0049] Capacitor C4 is connected in parallel with respect to surface acoustic wave element 31. The other end of inductor L2 and one end of capacitors C3 and C4 are sequentially connected to one end of surface acoustic wave element 31 via signal terminal 11 and 81. One end of inductor L3, the other end of capacitor C4 and one end of capacitor C5 are sequentially connected to the other end of surface acoustic wave element 31 via signal terminal 12 and 82.

[0050] The other end of capacitor C5 and one end of capacitor C6 are sequentially connected to one end of surface acoustic wave element 32 via signal terminal 13 and 83. The filter circuit further includes inductor L4. One end of inductor L4 is sequentially connected to the other end of surface acoustic wave element 32 via signal terminal 14 and 84. The other end of inductor L4 is connected to the grounding member.

[0051] Next, with reference to Figures 2 to 4 , the structure of the stacked electronic device of the present embodiment will be described. Figure 2 is a perspective view showing the electronic device 1. Figure 3 And Figure 4 is a perspective view showing the stacked electronic device of the present embodiment.

[0052] The electronic device 1 includes the stacked electronic device 5 of the present embodiment. The stacked electronic device 5 includes a stacked body 50, and the stacked body 50 includes a plurality of dielectric layers and a plurality of conductors (a plurality of conductor layers and a plurality of vias) stacked thereon. The stacked body 50 is Figure 1Components for integrating inductors L1 to L7 and capacitors C1 to C11 in the filter circuit shown. The inductors L1 to L7 and the capacitors C1 to C11 are formed of multiple conductors. The multiple dielectric layers are each made of a dielectric material. As the dielectric material, for example, low-temperature co-fired ceramics (LTCC) can be used.

[0053] The laminate 50 has: a first surface 50A and a second surface 50B, which are located at both ends in the lamination direction T of the multiple dielectric layers; and four side surfaces 50C to 50F, which connect the first surface 50A and the second surface 50B. The side surfaces 50C and 50D face opposite sides, and the side surfaces 50E and 50F also face opposite sides. The side surfaces 50C to 50F are perpendicular to the first surface 50A and the second surface 50B.

[0054] Here, as Figures 2 to 4 shown, the X direction, Y direction, and Z direction are defined. The X direction, Y direction, and Z direction are orthogonal to each other. In the present embodiment, one direction parallel to the lamination direction T is defined as the Z direction. In addition, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. In addition, the expression "when observed from a specified direction (for example, the Z direction)" means observing an object from a separated position along the specified direction or a direction parallel to the specified direction.

[0055] As Figure 3 and Figure 4 shown, the first surface 50A is located at the end in the Z direction of the laminate 50. The first surface 50A is both the upper surface of the laminate 50 and the mounting surface for mounting a mounting device described later. The second surface 50B is located at the end in the -Z direction of the laminate 50. The second surface 50B is also the bottom surface of the laminate 50. Figure 3 Shows the laminate 50 as viewed from the side of the first surface 50A. Figure 4 Shows the laminate 50 as viewed from the side of the second surface 50B.

[0056] The side surface 50C is located at the end in the -X direction of the laminate 50. The side surface 50D is located at the end in the X direction of the laminate 50. The side surface 50E is located at the end in the -Y direction of the laminate 50. The side surface 50F is located at the end in the Y direction of the laminate 50.

[0057] The laminate 50 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, 119 provided on the second surface 50B of the laminate 50. Compared with the side surface 50F, the electrodes 111, 112, 113 are arranged in this order along the X direction at a position closer to the side surface 50E. Compared with the side surface 50E, the electrodes 115, 116, 117 are arranged in this order along the -X direction at a position closer to the side surface 50F.

[0058] The electrode 114 is disposed between the electrode 113 and the electrode 115. The electrode 118 is disposed between the electrode 111 and the electrode 117. The electrode 119 is disposed between the electrode 112 and the electrode 116. In addition, the electrode 119 is disposed at substantially the center of the second surface 50B.

[0059] The electrode 118 corresponds to the first input / output terminal 2. The electrode 114 corresponds to the second input / output terminal 3. Accordingly, the first input / output terminal 2 and the second input / output terminal 3 are provided on the second surface 50B of the laminate 50. The electrodes 111 to 113, 115 to 117, and 119 are respectively connected to the grounding members.

[0060] The laminate 50 further includes a plurality of electrodes 121, 122, 123, and 124 provided on the first surface 50A of the laminate 50. The electrodes 121 and 122 are arranged in this order along the X direction at a position closer to the side surface 50E than the side surface 50F. The electrodes 123 and 124 are arranged in this order along the -X direction at a position closer to the side surface 50F than the side surface 50E.

[0061] The electrode 121 corresponds to the signal terminal 11. The electrode 122 corresponds to the signal terminal 12. The electrode 123 corresponds to the signal terminal 13. The electrode 124 corresponds to the signal terminal 14. Accordingly, the signal terminals 11 to 14 are provided on the first surface 50A of the laminate 50.

[0062] The electronic device 1 further includes a mounting device 80 mounted on the first surface 50A of the laminate 50. The mounting device 80 includes Figure 1 the surface acoustic wave elements 31 and 32 in the filter circuit shown.

[0063] The mounting device 80 further includes four electrodes respectively constituting the signal terminals 81, 82, 83, and 84. In addition, in Figure 2 for convenience, the four electrodes are denoted by reference numerals 81 to 84. In a state where the mounting device 80 is mounted on the laminate 50, the four electrodes denoted by reference numerals 81 to 84 are respectively opposed to the electrodes 121 to 124 of the laminate 50. The four electrodes denoted by reference numerals 81 to 84 are physically connected to the electrodes 121 to 124 through solder bumps 7, for example.

[0064] In Figure 2 the example shown, the mounting device 80 is arranged to overlap with the center of gravity of the first surface 50A when viewed from the stacking direction T. The center of gravity of the mounting device 80 when viewed from the stacking direction T may coincide with the center of gravity of the first surface 50A or may not coincide.

[0065] The electronic device 1 further includes a sealing portion 90 that seals the mounted device 80. The sealing portion 90 covers at least a part of the periphery of the mounted device 80 and the first surface 50A of the laminate 50. The sealing portion 90 may also cover the side surfaces 50C to 50F of the laminate 50. The sealing portion 90 is made of, for example, resin.

[0066] Next, with reference to Figures 5A to 10C , an example of a plurality of dielectric layers, a plurality of conductor layers, and a plurality of through-holes constituting the laminate 50 will be described. In this example, the laminate 50 includes nineteen dielectric layers that are laminated. Hereinafter, the nineteen dielectric layers will be sequentially referred to as the first to nineteenth dielectric layers from the bottom. In addition, the first to nineteenth dielectric layers are denoted by reference numerals 51 to 69.

[0067] In Figures 5A to 10B , a plurality of circles represent a plurality of through-holes. A plurality of through-holes are formed on each of the dielectric layers 51 to 69. Each of the plurality of through-holes is formed by filling a hole for a through-hole with a conductive paste. Each of the plurality of through-holes is connected to an electrode, a conductor layer, or another through-hole.

[0068] In Figures 5A to 10B , reference numerals are assigned to a plurality of specific through-holes among the plurality of through-holes. Regarding the connection relationship of each of the plurality of specific through-holes with an electrode, a conductor layer, or another through-hole, the connection relationship in a state where the first to nineteenth dielectric layers 51 to 69 are laminated will be described.

[0069] Figure 5A represents the pattern formation surface of the first dielectric layer 51. Electrodes 111 to 119 are formed on the pattern formation surface of the dielectric layer 51.

[0070] Figure 5B represents the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern formation surface of the dielectric layer 52. The conductor layer 525 is connected to the conductor layer 523. In Figure 5B , the boundary between the conductor layer 523 and the conductor layer 525 is indicated by a dashed line.

[0071] Figure 5C represents the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, and 533 are formed on the pattern formation surface of the dielectric layer 53. In Figure 5C , the through-hole labeled with reference numeral 53T1a is connected to the conductor layer 531. In addition, in the following description, the through-hole labeled with reference numeral 53T1a will be simply referred to as the through-hole 53T1a. In addition, the through-holes labeled with reference numerals other than the through-hole 53T1a will be described in the same manner as the through-hole 53T1a.

[0072] Figure 6AIndicates the pattern formation surface of the fourth dielectric layer 54. A conductor layer 541 is formed on the pattern formation surface of the dielectric layer 54. Figure 6A The through-hole 54T1b shown is connected to the conductor layer 541. The through-hole 53T1a is connected to Figure 6A the through-hole 54T1a shown.

[0073] Figure 6B Indicates the pattern formation surfaces of the fifth and sixth dielectric layers 55 and 56, respectively. The through-holes 54T1a and 54T1b are respectively connected to the through-holes 55T1a and 55T1b formed in the dielectric layer 55. In addition, in the dielectric layers 55 and 56, the through-holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0074] Figure 6C Indicates the pattern formation surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the pattern formation surface of the dielectric layer 57. The through-holes 55T1a and 55T1b formed in the dielectric layer 56 are respectively connected to Figure 6C the through-holes 57T1a and 57T1b shown.

[0075] Figure 7A Indicates the pattern formation surfaces of the eighth and ninth dielectric layers 58 and 59, respectively. The through-holes 57T1a and 57T1b are respectively connected to the through-holes 58T1a and 58T1b formed in the dielectric layer 58. In addition, in the dielectric layers 58 and 59, the through-holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0076] Figure 7B Indicates the pattern formation surface of the tenth dielectric layer 60. Conductor layers 602, 606, and 607 for inductors are formed on the pattern formation surface of the dielectric layer 60. The through-holes 58T1a and 58T1b formed in the dielectric layer 59 are respectively connected to Figure 7B the through-holes 60T1a and 60T1b shown.

[0077] Figure 7C Indicates the pattern formation surface of the eleventh dielectric layer 61. Conductor layers 612, 614, 616, and 617 for inductors are formed on the pattern formation surface of the dielectric layer 61. The through-holes 60T1a and 60T1b are respectively connected to Figure 7C the through-holes 61T1a and 61T1b shown.

[0078] Figure 8A Indicates the pattern formation surface of the twelfth dielectric layer 62. Conductor layers 622, 623, 626, and 627 for inductors are formed on the pattern formation surface of the dielectric layer 62. The through-holes 61T1a and 61T1b are respectively connected to Figure 8A the through-holes 62T1a and 62T1b shown.

[0079] Figure 8B Denotes the pattern formation surface of the thirteenth dielectric layer 63. On the pattern formation surface of the dielectric layer 63, conductor layers 632, 633, 635, 636, 637 for an inductor are formed. Through holes 62T1a and 62T1b are respectively connected to Figure 8B the through holes 63T1a and 63T1b shown.

[0080] Figure 8C Denotes the pattern formation surface of the fourteenth dielectric layer 64. On the pattern formation surface of the dielectric layer 64, conductor layers 641a, 641b, 642, 643, 644, 646, 647, 648 and a conductor layer 645 for an inductor are formed. The conductor layer 646 is connected to the conductor layer 644. In Figure 8C it, the boundary between the conductor layer 644 and the conductor layer 646 is indicated by a dashed line. The through hole 63T1a and Figure 8C the through hole 64T1a shown are connected to the conductor layer 641a. The through hole 63T1b and Figure 8C the through hole 64T1b shown are connected to the conductor layer 641b. Figure 8C The through hole 64T5 shown is connected to the conductor layer 647.

[0081] Figure 9A Denotes the pattern formation surface of the fifteenth dielectric layer 65. On the pattern formation surface of the dielectric layer 65, conductor layers 651, 652, 653, 654 are formed. The conductor layer 654 is connected to the conductor layer 653. In Figure 9A it, the boundary between the conductor layer 653 and the conductor layer 654 is indicated by a dashed line. The through holes 64T1a and 64T1b are respectively connected to Figure 9A the through holes 65T1a and 65T1b shown. The through hole 64T5 and Figure 9A the through hole 65T5 shown are connected to the conductor layer 651.

[0082] Figure 9B Denotes the pattern formation surface of the sixteenth dielectric layer 66. On the pattern formation surface of the dielectric layer 66, conductor layers 661, 662, 663 are formed. The conductor layer 662 is connected to the conductor layer 661. In Figure 9B it, the boundary between the conductor layer 661 and the conductor layer 662 is indicated by a dashed line. The through holes 65T1a and 65T1b are respectively connected to Figure 9B the through holes 66T1a and 66T1b shown. Figure 9B The through hole 66T3 shown is connected to the conductor layer 661. The through hole 65T5 is connected to Figure 9B the through hole 66T5 shown.

[0083] Figure 9CIndicates the pattern formation surface of the seventeenth dielectric layer 67. On the pattern formation surface of the dielectric layer 67, conductor layers 671, 672, 673, 675, 676, 677 for an inductor are formed. The conductor layer 671 has a first end and a second end that are located on opposite sides in the long side direction of the conductor layer 671. The via hole 66T1a and Figure 9C The via hole 67T1a shown is connected to a portion near the first end of the conductor layer 671. The via hole 66T1b and Figure 9C The via hole 67T1b shown is connected to a portion near the second end of the conductor layer 671. The via hole 66T3 is connected to Figure 9C The via hole 67T3 shown. The via hole 66T5 is connected to the conductor layer 673.

[0084] Figure 10A Indicates the pattern formation surface of the eighteenth dielectric layer 68. On the pattern formation surface of the dielectric layer 68, conductor layers 681, 682, 683, 684, 685, 686, 687 for an inductor are formed. The conductor layer 681 has a first end and a second end that are located on opposite sides in the long side direction of the conductor layer 681. The via hole 67T1a is connected to a portion near the first end of the conductor layer 681. The via hole 67T1b is connected to a portion near the second end of the conductor layer 681. Figure 10A The via holes 68T1, 68T2, 68T4 shown are respectively connected to the conductor layers 682, 683, 684. The via hole 67T3 is connected to Figure 10A The via hole 68T3 shown.

[0085] Figure 10B Indicates the pattern formation surface of the nineteenth dielectric layer 69. On the pattern formation surface of the dielectric layer 69, conductor layers 691, 692, 693, 694 are formed. The via hole 68T1 and Figure 10B The via hole 69T1 shown are connected to the conductor layer 691. The via hole 68T2 and Figure 10B The via hole 69T2 shown are connected to the conductor layer 692. The via hole 68T3 and Figure 10B The via hole 69T3 shown are connected to the conductor layer 693. The via hole 68T4 and Figure 10B The via hole 69T4 shown are connected to the conductor layer 694.

[0086] Figure 10C Indicates the surface of the nineteenth dielectric layer 69 that is opposite to the pattern formation surface. Hereinafter, the surface opposite to the pattern formation surface of the dielectric layer 69 is referred to as the electrode formation surface of the dielectric layer 69. Electrodes 121, 122, 123, 124 are formed on the electrode formation surface of the dielectric layer 69. The via holes 69T1, 69T2, 69T3, 69T4 are respectively connected to the electrodes 121, 122, 123, 124.

[0087] The laminate 50 is formed by laminating the first to the nineteenth dielectric layers 51 to 69 such that the pattern forming surface of the first dielectric layer 51 becomes the second surface 50B of the laminate 50, and the electrode forming surface of the nineteenth dielectric layer 69 becomes the first surface 50A of the laminate 50.

[0088] Figures 5A to 10B Each of the plurality of through holes shown is connected to a conductor layer overlapping in the lamination direction T or another through hole overlapping in the lamination direction T when the first to the nineteenth dielectric layers 51 to 69 are laminated. Further, Figures 5A to 10B Among the plurality of through holes shown, the through holes located within the electrode or the conductor layer are connected to the electrode or the conductor layer.

[0089] Figure 11 It shows the inside of the laminate 50 formed by laminating the first to the nineteenth dielectric layers 51 to 69. As Figure 11 shown, within the laminate 50, Figures 5A to 10C a plurality of conductor layers and a plurality of through holes shown are laminated.

[0090] Next, Figure 1 the correspondence between the components of the circuit of the electronic device 1 shown and Figures 5A to 10C the components inside the laminate 50 shown will be described. The inductor L1 is composed of the conductor layers 671, 681 for inductor, the conductor layers 641a, 641b, and the through holes 53T1a, 54T1a, 54T1b, 55T1a, 55T1b, 57T1a, 57T1b, 58T1a, 58T1b, 60T1a, 60T1b, 61T1a, 61T1b, 62T1a, 62T1b, 63T1a, 63T1b, 64T1a, 64T1b, 65T1a, 65T1b, 66T1a, 66T1b, 67T1a, 67T1b.

[0091] The inductor L2 is composed of the conductor layers 602, 612, 622, 632, 672, 682 for inductor and a plurality of through holes connecting these conductor layers. The conductor layer 682 is connected to the electrode 121 via the through hole 68T1, the conductor layer 691, and the through hole 69T1.

[0092] The inductor L3 is composed of the conductor layers 623, 633, 673, 683 for inductor and a plurality of through holes connecting these conductor layers. The conductor layer 683 is connected to the electrode 122 via the through hole 68T2, the conductor layer 692, and the through hole 69T2.

[0093] The inductor L4 is composed of conductor layers 614 and 684 for the inductor, conductor layers 533 and 571, a plurality of vias connecting the conductor layers 614 and 684, a plurality of vias connecting the conductor layers 571 and 614, a plurality of vias connecting the conductor layers 533 and 571, and a via connecting the conductor layers 525 and 533. The conductor layer 684 is connected to the electrode 124 via the via 68T4, the conductor layer 694, and the via 69T4.

[0094] The inductor L5 is composed of conductor layers 635, 645, 675, and 685 for the inductor and a plurality of vias connecting these conductor layers. The inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, and 686 for the inductor and a plurality of vias connecting these conductor layers. The inductor L7 is composed of conductor layers 607, 617, 627, 637, 677, and 687 for the inductor and a plurality of vias connecting these conductor layers.

[0095] The capacitor C1 is composed of conductor layers 521, 522, 531, 541 and dielectric layers 52 and 53 between these conductor layers. The capacitor C2 is composed of electrodes 111 and 117, conductor layers 521 and 522, and a dielectric layer 51 between the electrodes 111 and 117 and the conductor layers 521 and 522.

[0096] The capacitor C3 is composed of conductor layers 633 and 642 and a dielectric layer 63 between these conductor layers. The capacitor C4 is composed of conductor layers 643 and 651 and a dielectric layer 64 between these conductor layers.

[0097] The capacitor C5 is composed of conductor layers 651 and 661 and a dielectric layer 65 between these conductor layers. The conductor layer 661 is connected to the electrode 123 via vias 66T3, 67T3, 68T3, the conductor layer 693, and the via 69T3.

[0098] The capacitor C6 is composed of conductor layers 652 and 662 and a dielectric layer 65 between these conductor layers. The capacitor C7 is composed of conductor layers 644 and 652 and a dielectric layer 64 between these conductor layers. The capacitor C8 is composed of conductor layers 646 and 653 and a dielectric layer 64 between these conductor layers.

[0099] The capacitor C9 is composed of conductor layers 636 and 647 and a dielectric layer 63 between these conductor layers. The conductor layer 647 is connected to the conductor layer 673 for the inductor constituting the inductor L3 via vias 64T5, 65T5, and 66T5.

[0100] The capacitor C10 is composed of conductor layers 523 and 532 and a dielectric layer 52 between these conductor layers. The capacitor C11 is composed of conductor layers 648, 654, 663 and dielectric layers 64 and 65 between these conductor layers.

[0101] Next, with reference to Figures 2 to 12 , the structural features of the stacked electronic device 5 of the present embodiment will be described. Figure 12 FIG. is a top view showing the inside of the stacked electronic device 5.

[0102] First, two regions of the stacked electronic device 5 defined by the mounted device 80 will be described. As described above, the mounted device 80 is mounted on the first surface 50A of the stacked body 50. The stacked electronic device 5 includes a first region R1 and a second region R2. The first region R1 overlaps with the mounted device 80 when viewed from the stacking direction T, and the second region R2 does not overlap with the mounted device 80 when viewed from the stacking direction T. The first region R1 is defined as the following three-dimensional region: the end in the Z direction exists on the first surface 50A, and the end in the -Z direction exists on the second surface 50B. In Figure 12 , the outer edge portion of the first region R1 is indicated by a double-dot chain line of a rectangle labeled with the reference numeral R1, which includes the end in the X direction, the end in the -X direction, the end in the Y direction, and the end in the -Y direction of the first region R1.

[0103] The second region R2 is defined as a region substantially obtained by removing the first region R1 from the three-dimensional region surrounded by the outer peripheral surface of the stacked body 50. The second region R2 covers at least a part of the outer peripheral portion of the first region R1. In the present embodiment, in particular, the second region R2 covers a part of the outer peripheral portion of the first region R1 other than the end in the Z direction (the first surface 50A) and the end in the -Z direction (the second surface 50B). In Figure 12 , the outer edge portion of the second region R2 is indicated by a double-dot chain line of a rectangle labeled with the reference numeral R2, which includes the end in the X direction, the end in the -X direction, the end in the Y direction, and the end in the -Y direction of the second region R2. Further, in Figure 12 , for convenience, the outer edge portion of the second region R2 is depicted separately from the side surfaces 50C to 50F of the stacked body 50.

[0104] The planar shape of the mounted device 80 (the shape viewed from the stacking direction T) may be the same as the shape of the first region R1. Alternatively, the mounted device 80 may include: a first part whose planar shape is the same as the shape of the first region R1; and a second part whose planar size is different from the planar size of the first region R1. In this case, the mounted device 80 is mounted on the stacked body 50 in a posture where the first part is located between the stacked body 50 and the second part.

[0105] Next, features related to inductors L2, L3, L5, L6, and L7 will be described. Inductor L2 is wound around an axis extending in a direction parallel to the stacking direction T to form an opening surrounded by inductor L2. Hereinafter, the opening surrounded by inductor L2 will be referred to as the opening of inductor L2. The opening of inductor L2 faces the first surface 50A of the laminate 50. In addition, the entire opening of inductor L2 is present in the second region R2. Hereinafter, for inductors other than inductor L2, the opening surrounded by the inductor will also be referred to as the opening of the inductor.

[0106] Similarly, inductors L3, L5, L6, and L7 are each wound around an axis extending in a direction parallel to the stacking direction T to form openings surrounded by inductors L3, L5, L6, and L7, respectively. The openings of inductors L3, L5, L6, and L7 each face the first surface 50A of the laminate 50. Most of the openings of inductors L3 and L5 are present in the second region R2. The entire openings of inductors L6 and L7 are present in the second region R2.

[0107] Inductor L2 includes a plurality of conductor layers 602, 612, 622, 632, 672, and 682 for inductors arranged at a predetermined interval in the stacking direction T. The conductor layers 602, 612, 622, 632, 672, and 682 are each wound around an axis extending in a direction parallel to the stacking direction T to surround the opening of inductor L2.

[0108] Inductor L3 includes a plurality of conductor layers 623, 633, 673, and 683 for inductors arranged at a predetermined interval in the stacking direction T. The conductor layers 623, 633, 673, and 683 are each wound around an axis extending in a direction parallel to the stacking direction T to surround the opening of inductor L3.

[0109] Inductor L5 includes a plurality of conductor layers 635, 645, 675, and 685 for inductors arranged at a predetermined interval in the stacking direction T. The conductor layers 635, 645, 675, and 685 are each wound around an axis extending in a direction parallel to the stacking direction T to surround the opening of inductor L5.

[0110] Inductor L6 includes a plurality of conductor layers 606, 616, 626, 636, 676, and 686 for inductors arranged at a predetermined interval in the stacking direction T. The conductor layers 626, 636, 676, and 686 are each wound around an axis extending in a direction parallel to the stacking direction T to surround the opening of inductor L6. The conductor layers 606 and 616 extend along the opening of inductor L6.

[0111] The inductor L7 includes a plurality of inductor conductor layers 607, 617, 627, 637, 677, and 687 arranged at predetermined intervals in the stacking direction T. The conductor layers 627, 637, 677, and 687 are respectively wound around an axis extending in a direction parallel to the stacking direction T so as to surround an opening of the inductor L7. The conductor layers 607 and 617 extend along the opening of the inductor L7.

[0112] Next, features related to the inductors L1 and L4 are described. The inductor L1 is wound around an axis extending in a direction perpendicular to the stacking direction T to form an opening surrounded by the inductor L1. The opening of the inductor L1 faces the side surface 50C of the stacked body 50.

[0113] The inductor L4 has a shape in which no opening portion surrounded by the inductor L4 is formed.

[0114] Next, the characteristics of the relationship between the inductors L3, L6 and the capacitor C9 are described. Figure 1 As shown, between the inductor L3 and the inductor L6, the elastic wave element 32, the inductors L4 and L5, and the capacitors C5, C6, C7, and C8 are provided in the circuit structure. In addition, the inductor L3 and the inductor L6 realize capacitive leap coupling through the capacitor C9.

[0115] Here, refer to Figure 13 , the connection between the inductor L6 and the capacitor C9 is described. Figure 13 is a circuit diagram showing the structure of the inductor L6. The inductor L6 can be divided into two inductor parts L61 and L62. The two inductor parts L61 and L62 are connected in series. Figure 13 , reference numeral L6a denotes a first end of the inductor L6, reference numeral L6b denotes a second end of the inductor L6, and reference numeral L6c denotes a node between the two inductor portions L61 and L62. The second end L6b of the inductor L6 is connected to the ground.

[0116] exist Figure 1 In the figure, for convenience, one end of the capacitor C9 is depicted as being connected to the first end L6a of the inductor L6. However, one end of the capacitor C9 may be connected to the first end L6a of the inductor L6 in the circuit structure, or may be connected between the first end L6a and the second end L6b of the inductor L6 in the circuit structure. Figures 5A to 12 In the example of multiple conductive layers and multiple through-holes shown, one end of the capacitor C9 is connected between the first end L6a and the second end L6b of the inductor L6 in the circuit structure.

[0117] When one end of capacitor C9 is connected to node L6c of inductor L6 located between the first end L6a and the second end L6b of inductor L6, by adjusting the physical connection position of capacitor C9 in inductor L6, the inductances of inductor portions L61 and L62 can be adjusted. Additionally, in this case, the substantial impedance of inductor L6 is determined by the inductance of inductor portion L62. By adjusting the physical connection position of capacitor C9 in inductor L6, the substantial impedance of inductor L6 can be adjusted.

[0118] Next, with reference to Figures 14 to 16 , the characteristics of the configurations of inductors L3, L6, and capacitor C9 will be described. Figure 14 And Figure 15 are top views showing inductors L3, L6, and capacitor C9. Figure 16 is an explanatory diagram showing the configurations of inductors L3, L6, and capacitor C9 in laminate 50. In Figure 14 and Figure 15 , reference numeral L3o denotes the opening of inductor L3, and reference numeral L6o denotes the opening of inductor L6.

[0119] As described above, inductor L3 is composed of conductor layers 623, 633, 673, 683 for inductors and a plurality of through holes connected to these conductor layers. In Figures 14 to 16 , reference numeral A3 denotes an axis that passes through the opening L3o of inductor L3 and extends in a direction parallel to the stacking direction T. The conductor layers 623, 633, 673, 683 are wound as a whole around axis A3. In the present embodiment, in particular, the conductor layers 623, 633, 673, 683 are wound around axis A3 respectively.

[0120] As described above, inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, 686 for inductors and a plurality of through holes connected to these conductor layers. In Figures 14 to 16 , reference numeral A6 denotes an axis that passes through the opening L6o of inductor L6 and extends in a direction parallel to the stacking direction T. The conductor layers 606, 616, 626, 636, 676, 686 are wound as a whole around axis A6. In the present embodiment, in particular, the conductor layers 606, 616, 626, 636, 676, 686 are wound around axis A6 respectively.

[0121] Inductors L3 and L6 are arranged such that the opening L3o of inductor L3 and the opening L6o of inductor L6 do not face each other. In the present embodiment, in particular, inductors L3 and L6 are arranged along the X direction in a posture with the openings L3o, L6o facing the first surface 50A of laminate 50.

[0122] Here, the third region R3 and the fourth region R4 defined by the inductors L3 and L6 will be described. As Figure 14 well as Figure 15 shown, the third region R3 is a planar region, which is a hypothetical rectangular region having four sides R3a, R3b, R3c, and R3d. When viewed from the stacking direction T, the four sides R3a, R3b, R3c, and R3d respectively overlap with the outer edges of one of the conductor layers constituting the inductor L3 and the inductor L6, but do not overlap with parts other than the outer edges of the other conductor layer constituting the inductor L3 and the inductor L6.

[0123] The first side R3a is located at the -X direction side end of the third region R3 and extends along a direction parallel to the Y direction. When viewed from the stacking direction T, the first side R3a overlaps with the outer edges of the conductor layers 673 and 683 respectively.

[0124] The second side R3b is located at the X direction side end of the third region R3 and extends along a direction parallel to the Y direction. When viewed from the stacking direction T, the second side R3b overlaps with the outer edges of the conductor layers 626, 636, 676, and 686 respectively.

[0125] The third side R3c is located at the -Y direction side end of the third region R3 and extends along a direction parallel to the X direction. When viewed from the stacking direction T, the third side R3c overlaps with the outer edges of the conductor layers 623, 626, 633, 636, 673, 676, 683, and 686 respectively.

[0126] The fourth side R3d is located at the Y direction side end of the third region R3 and extends along a direction parallel to the X direction. When viewed from the stacking direction T, the fourth side R3d overlaps with the outer edges of the conductor layers 606 and 616.

[0127] As Figure 16 shown, the fourth region R4 is a planar region, which is a hypothetical rectangular region having four sides R4a, R4b, R4c, and R4d. When viewed from the -Y direction of the direction orthogonal to the stacking direction T, the four sides R4a, R4b, R4c, and R4d respectively overlap with the outer edges or surfaces of one of the conductor layers constituting the inductor L3 and the inductor L6, but do not overlap with parts other than the outer edges or surfaces of the other conductor layer constituting the inductor L3 and the inductor L6.

[0128] The first side R4a is located at the -X direction side end of the fourth region R4 and extends along a direction parallel to the Z direction. When viewed from the -Y direction, the first side R4a overlaps with the outer edges of the conductor layers 673 and 683 respectively.

[0129] The second side R4b is located at the end on the X-direction side in the fourth region R4 and extends along a direction parallel to the Z direction. When viewed from the -Y direction, the second side R4b overlaps with the outer edges of the conductor layers 626, 636, 676, and 686 respectively.

[0130] The third side R4c is located at the end on the -Z direction side in the fourth region R4 and extends along a direction parallel to the X direction. When viewed from the -Y direction, the third side R4c overlaps with the surface of the conductor layer 606. In addition, in Figure 16 for convenience, the third side R4c is depicted separately from the conductor layer 606.

[0131] The fourth side R4d is located at the end on the Z direction side in the fourth region R4 and extends along a direction parallel to the X direction. When viewed from the -Y direction, the fourth side R4d overlaps with the surfaces of the conductor layers 683 and 686 respectively. In addition, in Figure 16 for convenience, the fourth side R4d is depicted separately from the conductor layers 683 and 686.

[0132] Next, with reference to Figures 14 to 16 , the relationship between the capacitor C9 and the third region R3 and the fourth region R4 will be described. As described above, the capacitor C9 is composed of the conductor layers 636, 647 and the dielectric layer 63 between these conductor layers. When viewed from the stacking direction T, the conductor layers 636, 647 are located within the third region R3. In particular, when viewed from the stacking direction T, the conductor layer 647 is located at a position away from the four sides R3a, R3b, R3c, R3d of the third region R3. In addition, when viewed from the -Y direction, the conductor layers 636, 647 are located within the fourth region R4. In particular, when viewed from the -Y direction, the conductor layer 647 is located at a position away from the four sides R4a, R4b, R4c, R4d of the fourth region R4.

[0133] Here, assume a three-dimensional space within a laminate 50, the planar shape of which when viewed from the stacking direction T is the same as that of the third region R3, and the planar shape of which when viewed from the -Y direction is the same as that of the fourth region R4. This three-dimensional space is also the three-dimensional space defined by the inductors L3 and L6. The conductor layers 636, 647 constituting the capacitor C9 exist within this three-dimensional space. In particular, in the stacking direction T, the conductor layer 647 is located between the conductor layer 606 and the conductor layers 683, 686, where the conductor layer 606 is located at the -Z direction end of this three-dimensional space, and the conductor layers 683, 686 are located at the Z direction end of this three-dimensional space. In the stacking direction T, the conductor layer 647 is also located between the conductor layer 623 and the conductor layer 686.

[0134] Next, with reference to Figure 14 and Figure 15, features related to the multiple conductor layers that make up inductors L3, L6, and capacitor C9 are described. The conductor layer 647 that makes up capacitor C9 is electrically connected to the conductor layer 673 that makes up inductor L3 via vias 64T5, 65T5, and 66T5.

[0135] When viewed from the stacking direction T, the conductor layer 647 extends from the conductor layers 623, 633, 673, 683 that make up inductor L3 toward the conductor layers 606, 616, 626, 636, 676, 686 that make up inductor L6. Additionally, the conductor layer 647 extends from the outside of the conductor layers 606, 616, 626, 636, 676, 686 toward the opening L6o of inductor L6.

[0136] In the present embodiment, in particular, when viewed from the stacking direction T, the conductor layer 647 extends in a manner overlapping with the conductor layer 636. The conductor layer 636 is disposed between the conductor layer 606 and the conductor layer 683 in the stacking direction T. The conductor layer 636 and the conductor layer 647 face each other via a dielectric layer 63. The conductor layer 647 includes a first overlapping portion 647B that overlaps with the conductor layer 636 when viewed from the stacking direction T.

[0137] The conductor layer 647 also includes two non - overlapping portions 647A, 647C that do not overlap with the conductor layer 636 when viewed from the stacking direction T. The non - overlapping portion 647A is connected to one end of the first overlapping portion 647B. In Figure 14 , the boundary between the non - overlapping portion 647A and the first overlapping portion 647B is indicated by a dashed line. Additionally, when viewed from the stacking direction T, the non - overlapping portion 647A is disposed outside the conductor layer 636. The non - overlapping portion 647A is connected to the conductor layer 673 that makes up inductor L3 via vias 64T5, 65T5, and 66T5.

[0138] The non - overlapping portion 647C is connected to the other end of the first overlapping portion 647B. In Figure 14 , the boundary between the non - overlapping portion 647C and the first overlapping portion 647B is indicated by a dashed line. Additionally, when viewed from the stacking direction T, the non - overlapping portion 647C overlaps with the opening L6o of inductor L6. The area of the non - overlapping portion 647C is smaller than the area of the first overlapping portion 647B.

[0139] As Figure 14As shown, the conductor layer 647 has a first end edge 647a and a second end edge 647b at both ends in the long side direction of the conductor layer 647. The first end edge 647a is also the end edge of the non-overlapping portion 647A. In the long side direction of the conductor layer 647, the first end edge 647a is located on the side opposite to the boundary between the non-overlapping portion 647A and the first overlapping portion 647B. The second end edge 647b is also the end edge of the non-overlapping portion 647C. In the long side direction of the conductor layer 647, the second end edge 647b is located on the side opposite to the boundary between the non-overlapping portion 647C and the first overlapping portion 647B.

[0140] The conductor layer 636 extends so as to surround the opening L6o of the inductor L6. In particular, in the present embodiment, the conductor layer 636 includes a plurality of bent portions. When viewed from the stacking direction T, the first overlapping portion 647B overlaps with the bent portion. The second end edge 647b of the non-overlapping portion 647C has a shape along the curve of the bent portion of the conductor layer 636. The second end edge 647b may be linear or curved.

[0141] In addition, as Figure 8B shown, the conductor layer 636 includes an extending portion 636a having a predetermined length and a smooth outer edge. The width of the extending portion 636a in the short side direction of the conductor layer 636 may be substantially constant. In addition, the "extending portion with substantially constant width" includes a portion where the width slightly changes in the bent portion and a portion where the width changes due to manufacturing deviation, but does not include a portion where the width is intentionally changed such as a stepped shape. In the present embodiment, the extending portion includes the aforementioned plurality of bent portions. The conductor layer 636 also includes two connecting portions 636b and 636c connected to the extending portion 636a at both ends in the long side direction of the extending portion 636a. Through holes are connected to the two connecting portions 636b and 636c, respectively.

[0142] When viewed from the stacking direction T, the first overlapping portion 647B overlaps with the extending portion 636a of the conductor layer 636. As Figure 15 shown, the extending portion 636a includes a second overlapping portion 636A that overlaps with the first overlapping portion 647B of the conductor layer 647 when viewed from the stacking direction T and forms a capacitor C9 together with the first overlapping portion 647B. In Figure 15 order to facilitate understanding, the second overlapping portion 636A is hatched. In addition, since the extending portion 636a is a part of the conductor layer 636, it can also be said that the conductor layer 636 includes the second overlapping portion 636A.

[0143] Next, an example of the characteristics of the electronic device 1 in the present embodiment is shown. Figure 17 is a characteristic diagram showing an example of the attenuation characteristic of the electronic device 1. InFigure 17 In this case, the horizontal axis represents frequency and the vertical axis represents attenuation. According to Figure 17 it can be seen that the electronic device 1 has sufficient characteristics as a band-pass filter in practical applications.

[0144] Next, the functions and effects of the stacked electronic device 5 of the present embodiment will be described. The stacked electronic device 5 of the present embodiment includes an inductor L3 and an inductor L6. Between the inductor L3 and the inductor L6, a plurality of elements are provided in the circuit structure. In such a structure, if the inductive coupling between the inductor L3 and the inductor L6 becomes stronger, sometimes the desired characteristics cannot be obtained. In this regard, in the present embodiment, the inductor L3 and the inductor L6 are arranged such that the opening L3o of the inductor L3 and the opening L6o of the inductor L6 do not face each other. Thus, according to the present embodiment, it is possible to suppress the impairment of the functions of the inductors L3 and L6 respectively and achieve the desired characteristics.

[0145] In addition, the stacked electronic device 5 of the present embodiment includes a capacitor C9 that realizes a capacitive leap coupling between the inductor L3 and the inductor L6. In the present embodiment, although a plurality of elements are provided between the inductor L3 and the inductor L6, the inductor L3 and the inductor L6 are arranged in parallel. Thus, according to the present embodiment, it is easy to provide the capacitor C9 in the stacked body 50 of the stacked electronic device 5.

[0146] In addition, in the present embodiment, the conductor layer 647 constituting the capacitor C9 includes a first overlapping portion 647B that overlaps the inductor conductor layer 636 constituting the inductor L6 when viewed from the stacking direction T. Thus, according to the present embodiment, a capacitor C9 having a specified function can be realized without using a conductor layer other than the conductor layer 636 facing the conductor layer 647. In addition, according to the present embodiment, by making a part of the conductor layer 636 face the first overlapping portion 647B, the capacitor C9 can be realized without impairing the function of the inductor L6. In addition, according to the present embodiment, compared with the case where the capacitor C9 is formed without using the conductor layer 636, the stacked electronic device 5 can be miniaturized.

[0147] In addition, in the present embodiment, when viewed from the stacking direction T, the conductor layer 647 is located in the third region R3 defined by the inductors L3 and L6. Thus, according to the present embodiment, compared with the case where the conductor layer 647 is located outside the third region R3, the stacked electronic device 5 can be miniaturized. Similarly, when viewed from the -Y direction, the conductor layer 647 is located in the fourth region R4 defined by the inductors L3 and L6. Thus, according to the present embodiment, compared with the case where the conductor layer 647 is located outside the fourth region R4, the stacked electronic device 5 can be miniaturized.

[0148] In addition, in the present embodiment, the conductor layer 636 overlapping with the first overlapping portion 647B is disposed between the other two conductor layers constituting the inductor L6, i.e., the conductor layers 606 and 686, in the stacking direction T. According to the present embodiment, compared with the case where the conductor layer constituting the capacitor C9 is disposed closer to the second surface 50B of the laminate 50 than the conductor layer 606, or the case where the conductor layer constituting the capacitor C9 is disposed closer to the first surface 50A of the laminate 50 than the conductor layer 686, the laminated electronic device 5 can be miniaturized.

[0149] In addition, in the present embodiment, in addition to the first overlapping portion 647B, the conductor layer 647 further includes non-overlapping portions 647A and 647C. Thus, according to the present embodiment, even when the conductor layers 636 and 647 are respectively displaced in a direction orthogonal to the stacking direction T due to stacking displacement during manufacturing, the area change of the first overlapping portion 647B can be suppressed. As a result, according to the present embodiment, the characteristic deviation of the laminated electronic device 5 due to stacking displacement during manufacturing can be suppressed.

[0150] In addition, in the present embodiment, the group of the inductors L2 and L3 and the capacitor C3 has the same characteristics as the group of the inductors L3, L6 and the capacitor C9. That is, in the present embodiment, the inductors L2 and L3 are arranged such that the opening of the inductor L2 and the opening L3o of the inductor L3 are not opposed to each other. The conductor layer 642 constituting the capacitor C3 includes an overlapping portion that overlaps with the inductor conductor layer 633 for the inductor L3 when viewed from the stacking direction T. Thus, according to the present embodiment, the functions of the inductors L2 and L3 can be suppressed from being impaired, and the laminated electronic device 5 can be miniaturized.

[0151] Next, other effects of the laminated electronic device 5 of the present embodiment will be described. In the present embodiment, most of the opening L3o of the inductor L3 exists in the second region R2, and the entire opening L6o of the inductor L6 exists in the second region R2. Thus, according to the present embodiment, the interaction of the electromagnetic field between each of the inductors L3 and L6 and the mounted device 80 can be suppressed, and the desired characteristics can be achieved.

[0152] Similarly, in the present embodiment, the entire openings of the inductors L2 and L7 respectively exist in the second region R2, and most of the opening of the inductor L5 exists in the second region R2. Thus, according to the present embodiment, the interaction of the electromagnetic field between each of the inductors L2, L5 and L7 and the mounted device 80 can be suppressed, and the desired characteristics can be achieved.

[0153] In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the electronic device including the stacked electronic device of the present invention is not limited to a band-pass filter, and can be applied to other filters such as a low-pass filter and a high-pass filter, a demultiplexer that separates a plurality of signals having different frequency bands, and other electronic devices including a plurality of resonators.

[0154] As described above, the stacked electronic device according to the first aspect of the present invention includes: a first inductor; a second inductor; a capacitor; and a laminate for integrating the first inductor, the second inductor, and the capacitor, and including a plurality of dielectric layers stacked. The first inductor includes at least one first inductor conductor layer wound around a first axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The second inductor includes at least one second inductor conductor layer wound around a second axis extending in a direction parallel to the stacking direction. The first inductor and the second inductor are arranged such that, when viewed from the stacking direction, a first opening surrounded by at least one first inductor conductor layer does not overlap with a second opening surrounded by at least one second inductor conductor layer. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from at least one second inductor conductor layer toward at least one first inductor conductor layer when viewed from the stacking direction, and includes a first overlapping portion that overlaps with at least one first inductor conductor layer when viewed from the stacking direction.

[0155] In addition, in the stacked electronic device according to the first aspect of the present invention, at least one first inductor conductor layer may be one first inductor conductor layer or a plurality of first inductor conductor layers. As long as the whole of the plurality of first inductor conductor layers is wound around the first axis, the plurality of first inductor conductor layers may each be a shape that is not wound around the first axis, such as a straight shape. Similarly, at least one second inductor conductor layer may be one second inductor conductor layer or a plurality of second inductor conductor layers. As long as the whole of the plurality of inductor conductor layers is wound around the second axis, the plurality of second inductor conductor layers may each be a shape that is not wound around the second axis, such as a straight shape.

[0156] In the stacked electronic device according to the first aspect of the present invention, the capacitor conductor layer may be electrically connected to at least one second inductor conductor layer.

[0157] Further, in the stacked electronic device according to the first aspect of the present invention, at least one first inductor conductor layer may include a second overlapping portion that overlaps with the first overlapping portion when viewed from the stacking direction and forms a capacitor together with the first overlapping portion. At least one first inductor conductor layer may include an extending portion having a predetermined length and a smooth outer edge. The second overlapping portion may be a part of the extending portion.

[0158] Further, in the stacked electronic device according to the first aspect of the present invention, when viewed from the stacking direction, the capacitor conductor layer may be located within a hypothetical region of a rectangle having four sides. When viewed from the stacking direction, the four sides may respectively overlap with the outer edge of one of at least one first inductor conductor layer and at least one second inductor conductor layer, but do not overlap with portions other than the outer edge of the other of at least one first inductor conductor layer and at least one second inductor conductor layer.

[0159] Further, in the stacked electronic device according to the first aspect of the present invention, at least one first inductor conductor layer may also be a plurality of first inductor conductor layers. The plurality of first inductor conductor layers may include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a predetermined interval in the stacking direction. The capacitor conductor layer may be arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The plurality of first inductor conductor layers may further include a third specific inductor conductor layer arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. When viewed from the stacking direction, the first overlapping portion may overlap with the third specific inductor conductor layer. At least one second inductor conductor layer may be a plurality of second inductor conductor layers. The plurality of second inductor conductor layers may include: a third specific inductor conductor layer located in front of one direction parallel to the stacking direction; and a fourth specific inductor conductor layer located in front of the direction opposite to one direction. The capacitor conductor layer may be arranged between the third specific inductor conductor layer and the fourth specific inductor conductor layer in the stacking direction.

[0160] Further, in the stacked electronic device according to the first aspect of the present invention, the capacitor conductor layer may further include a non-overlapping portion that is connected to the first overlapping portion and overlaps with the first opening portion when viewed from the stacking direction. The area of the non-overlapping portion may be smaller than the area of the first overlapping portion. The non-overlapping portion may have an end edge shaped along the curve of at least one first inductor conductor layer.

[0161] Further, in the stacked electronic device according to the first aspect of the present invention, the first inductor may have a first end and a second end. The capacitor may be connected between the first end and the second end of the first inductor in the circuit structure.

[0162] The stacked electronic device according to the second aspect of the present invention includes: an inductor; a capacitor; and a stacked body which is a stacked body for integrating the inductor and the capacitor and includes a plurality of dielectric layers stacked thereon. The inductor includes at least one inductor conductor layer which is wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The at least one inductor conductor layer includes an extending portion having a predetermined length and a smooth outer edge. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from the outside of the at least one inductor conductor layer toward an opening surrounded by the at least one inductor conductor layer when viewed from the stacking direction, and includes a first overlapping portion which overlaps with the extending portion when viewed from the stacking direction.

[0163] In addition, in the stacked electronic device according to the second aspect of the present invention, the at least one inductor conductor layer may be one inductor conductor layer or a plurality of inductor conductor layers. As long as the entire plurality of inductor conductor layers are wound around the above-mentioned axis, the plurality of inductor conductor layers may also be in shapes that are not wound around the above-mentioned axis, such as a linear shape.

[0164] In the stacked electronic device according to the second aspect of the present invention, the extending portion may include a second overlapping portion which overlaps with the first overlapping portion when viewed from the stacking direction and forms a capacitor together with the first overlapping portion.

[0165] In addition, in the stacked electronic device according to the second aspect of the present invention, the at least one inductor conductor layer may be a plurality of inductor conductor layers. The plurality of inductor conductor layers may include a first specific inductor conductor layer and a second specific inductor conductor layer which are arranged at a predetermined interval in the stacking direction. The capacitor conductor layer may be arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The plurality of inductor conductor layers may further include a third specific inductor conductor layer which is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. When viewed from the stacking direction, the first overlapping portion may overlap with the third specific inductor conductor layer.

[0166] In addition, in the stacked electronic device according to the second aspect of the present invention, the capacitor conductor layer may further include a non-overlapping portion which is connected to the first overlapping portion and overlaps with the opening when viewed from the stacking direction. The area of the non-overlapping portion may be smaller than the area of the first overlapping portion. The non-overlapping portion may have an end edge shaped along the curve of the at least one inductor conductor layer.

[0167] In addition, in the stacked electronic device according to the second aspect of the present invention, the inductor may have a first end and a second end. The capacitor may be connected between the first end and the second end of the inductor in a circuit configuration.

[0168] Based on the above description, various embodiments and modifications of the present invention can be implemented. Therefore, within the scope equivalent to the claims, the present invention can also be implemented in a manner other than the above-described optimal manner.

Claims

1. A stacked electronic device, characterized in that, Comprising: A first inductor; A second inductor; A capacitor; And A laminate for integrating the first inductor, the second inductor, and the capacitor, including a plurality of dielectric layers laminated, The first inductor includes at least one first inductor conductor layer wound around a first axis extending in a direction parallel to the lamination direction of the plurality of dielectric layers, The second inductor includes at least one second inductor conductor layer wound around a second axis extending in a direction parallel to the lamination direction, The first inductor and the second inductor are configured such that, when viewed from the lamination direction, a first opening surrounded by the at least one first inductor conductor layer does not overlap with a second opening surrounded by the at least one second inductor conductor layer, The capacitor includes a capacitor conductor layer, The capacitor conductor layer, when viewed from the lamination direction, extends from the at least one second inductor conductor layer toward the at least one first inductor conductor layer and includes a first overlapping portion that overlaps with the at least one first inductor conductor layer when viewed from the lamination direction.

2. The laminated electronic device according to claim 1, wherein The capacitor conductor layer is electrically connected to the at least one second inductor conductor layer.

3. The laminated electronic device according to claim 1, wherein The at least one first inductor conductor layer includes a second overlapping portion that overlaps with the first overlapping portion when viewed from the lamination direction and together with the first overlapping portion constitutes the capacitor.

4. The laminated electronic device according to claim 3, wherein The at least one first inductor conductor layer includes an extending portion having a specified length and a smooth outer edge, The second overlapping portion is a part of the extending portion.

5. The laminated electronic device according to claim 1, wherein When viewed from the lamination direction, the capacitor conductor layer is located within a hypothetical region of a rectangle having four sides, When viewed from the lamination direction, the four sides respectively overlap with the outer edge of one of the at least one first inductor conductor layer and the at least one second inductor conductor layer, but do not overlap with portions other than the outer edge of the other of the at least one first inductor conductor layer and the at least one second inductor conductor layer.

6. The laminated electronic device according to claim 1, wherein The at least one first inductor conductor layer is a plurality of first inductor conductor layers, The plurality of first inductor conductor layers include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a specified interval in the lamination direction, The capacitor conductor layer is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the lamination direction.

7. The laminated electronic device according to claim 6, wherein The plurality of first inductor conductor layers further includes a third specific inductor conductor layer that is disposed between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. When viewed from the stacking direction, the first overlapping portion overlaps with the third specific inductor conductor layer.

8. The stacked electronic device according to claim 6, wherein: The at least one second inductor conductor layer is a plurality of second inductor conductor layers. The plurality of second inductor conductor layers includes: a third specific inductor conductor layer that is in front of one direction parallel to the stacking direction; and a fourth specific inductor conductor layer that is in front of the direction opposite to the one direction. The capacitor conductor layer is disposed between the third specific inductor conductor layer and the fourth specific inductor conductor layer in the stacking direction.

9. The stacked electronic device according to claim 1, wherein: The capacitor conductor layer further includes a non-overlapping portion that is connected to the first overlapping portion and overlaps with the first opening portion when viewed from the stacking direction.

10. The stacked electronic device according to claim 9, wherein: The area of the non-overlapping portion is smaller than the area of the first overlapping portion.

11. The stacked electronic device according to claim 9, wherein: The non-overlapping portion has an edge in the shape of a curve along the at least one first inductor conductor layer.

12. The stacked electronic device according to any one of claims 1 to 11, wherein: The first inductor has a first end and a second end. The capacitor is connected between the first end and the second end of the first inductor in a circuit configuration.

13. A stacked electronic device, characterized in that, Comprising: An inductor; A capacitor; and A stacked body that is a stacked body for integrating the inductor and the capacitor and includes a plurality of dielectric layers that are stacked. The inductor includes at least one inductor conductor layer that is wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The at least one inductor conductor layer includes an extending portion having a predetermined length and a smooth outer edge. The capacitor includes a capacitor conductor layer. When viewed from the stacking direction, the capacitor conductor layer extends from the outside of the at least one inductor conductor layer toward an opening surrounded by the at least one inductor conductor layer and includes a first overlapping portion that overlaps with the extending portion when viewed from the stacking direction.

14. The stacked electronic device according to claim 13, wherein: The extending portion includes a second overlapping portion that overlaps with the first overlapping portion when viewed from the stacking direction and constitutes the capacitor together with the first overlapping portion.

15. The stacked electronic device according to claim 13, wherein: The at least one inductor conductor layer is a plurality of inductor conductor layers. The plurality of inductor conductor layers include a first specific inductor conductor layer and a second specific inductor conductor layer that are arranged at a prescribed interval in the stacking direction. The capacitor conductor layer is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction.

16. The stacked electronic device according to claim 15, wherein: The plurality of inductor conductor layers further include a third specific inductor conductor layer, and the third specific inductor conductor layer is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. When viewed from the stacking direction, the first overlapping portion overlaps with the third specific inductor conductor layer.

17. The stacked electronic device according to claim 13, wherein: The capacitor conductor layer further includes a non-overlapping portion, the non-overlapping portion is connected to the first overlapping portion, and overlaps with the opening portion when viewed from the stacking direction.

18. The stacked electronic device according to claim 17, wherein: The area of the non-overlapping portion is smaller than the area of the first overlapping portion.

19. The stacked electronic device according to claim 17, wherein: The non-overlapping portion has an edge with a shape following the curve of the at least one inductor conductor layer.

20. The stacked electronic device according to any one of claims 13 to 19, wherein: The inductor has a first end and a second end. The capacitor is connected between the first end and the second end of the inductor in the circuit structure.

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