Signal processing method and device, equipment, storage medium and chip

Abstract

The invention provides a signal processing method comprising the following steps: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal; determining a second phase shift angle of the first signal; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle; and performing direct current offset compensation on the transmitting path and / or the feedback path based on the first direct current offset coefficient and the second direct current offset coefficient. According to the method disclosed by the invention, the compensation coefficient of the transmitting path and / or the feedback path is obtained by determining the first direct-current offset coefficient and the second direct-current offset coefficient in the loop at two different phase shifting angles, so that direct-current offset compensation can be performed on the transmitting path and / or the feedback path in real time under the condition that the first signal works; the application range of the signal processing method is expanded, and the convenience of direct current offset compensation is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of signal calibration, and in particular, to a signal processing method, apparatus, device, storage medium, and chip. Background Art

[0002] In a signal processing system, DC offset is a common problem, which is mainly caused by local oscillator leakage and circuit interference. The DC offset will cause the average level of the signal to no longer be zero, thereby leading to a decline in the performance of the system, such as causing decision-making errors and an increase in the bit error rate. In addition, the DC offset will also cause an increase in the error of the device, thereby reducing its accuracy and reliability. Therefore, how to effectively eliminate or compensate the DC offset of the signal has become an urgent problem to be solved. Summary of the Invention

[0003] The present disclosure provides a signal processing method, apparatus, device, storage medium, and chip to achieve real-time compensation for the DC offset of the transmit path and / or the feedback path.

[0004] In a first aspect embodiment of the present disclosure, a signal processing method is proposed. The method includes: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal. The first loop includes a transmit path and a feedback path at the first phase shift angle. The transmit path is used to transmit the first signal, and the feedback path is used to transmit a feedback signal of the first signal; determining a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle. The second loop includes a transmit path and a feedback path at the second phase shift angle; performing DC offset compensation on the transmit path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0005] In some embodiments, determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal includes: determining a second signal based on the first signal and the first phase shift angle, where the second signal is a feedback signal of the first signal at the first phase shift angle; determining the first DC offset coefficient of the first loop based on the first signal and the second signal.

[0006] In some embodiments, determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle includes: determining a third signal based on the first signal and the second phase shift angle, where the third signal is a feedback signal of the first signal at the second phase shift angle; determining the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0007] In some embodiments, determining a second DC offset coefficient of a second loop based on a first signal and a second phase shift angle includes: determining a third signal based on the first signal and the second phase shift angle, where the third signal is a feedback signal of the first signal at the second phase shift angle; and determining the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0008] In some embodiments, the method further includes: determining a third compensation coefficient and a fourth compensation coefficient based on a first compensation coefficient and a second compensation coefficient, where the third compensation coefficient is used to calibrate and compensate a transmit path, and the fourth compensation coefficient is used to calibrate and compensate a feedback path; performing DC offset compensation on the compensated transmit path based on the third compensation coefficient; and performing DC offset compensation on the compensated feedback path based on the fourth compensation coefficient.

[0009] In some embodiments, the method further includes: determining a third compensation coefficient and a fourth compensation coefficient based on a first compensation coefficient and a second compensation coefficient, where the third compensation coefficient is used to calibrate and compensate a transmit path, and the fourth compensation coefficient is used to calibrate and compensate a feedback path; performing DC offset compensation on the compensated transmit path based on the third compensation coefficient; and performing DC offset compensation on the compensated feedback path based on the fourth compensation coefficient.

[0010] An embodiment of the second aspect of the present disclosure provides a signal processing device, including: a first processing unit configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, where the first loop includes a transmit path and a feedback path at the first phase shift angle, the transmit path is configured to transmit the first signal, and the feedback path is configured to transmit a feedback signal of the first signal; a second processing unit configured to determine a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; a third processing unit configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, where the second loop includes a transmit path and a feedback path at the second phase shift angle; and a fourth processing unit configured to perform DC offset compensation on the transmit path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0011] An embodiment of the third aspect of the present disclosure provides a communication device, including a processor and a memory, where a computer program is stored in the memory, and the processor executes the computer program stored in the memory to enable the device to perform the method described in the first aspect above.

[0012] An embodiment of the fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in the first aspect of the present disclosure.

[0013] An embodiment of the fifth aspect of the present disclosure provides a chip, which includes at least one processor and a communication interface; the communication interface is configured to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in the first aspect of the present disclosure through logic circuits or by executing code instructions.

[0014] In summary, according to the signal processing method proposed by the present disclosure, it includes: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, where the first loop includes a transmission path and a feedback path at the first phase shift angle, the transmission path is used to transmit the first signal, and the feedback path is used to transmit a feedback signal of the first signal; determining a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, where the second loop includes a transmission path and a feedback path at the second phase shift angle; and performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient. In the method of the present disclosure, by determining the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, and then obtaining the compensation coefficients of the transmission path and / or the feedback path, DC offset compensation can be performed on the transmission path and / or the feedback path in real time when the first signal is working, expanding the applicable range of the signal processing method proposed by the present method and improving the convenience of DC offset compensation.

[0015] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.

[0017] Figure 1 It is a diagram of an application scenario of a signal processing method provided by an embodiment of the present disclosure;

[0018] Figure 2 It is a flowchart of a signal processing method provided by an embodiment of the present disclosure;

[0019] Figure 3 It is a flowchart of another signal processing method provided by an embodiment of the present disclosure;

[0020] Figure 4 It is a flowchart of still another signal processing method provided by an embodiment of the present disclosure;

[0021] Figure 5Schematic structural diagram of a signal processing device provided by an embodiment of the present disclosure;

[0022] Figure 6 Schematic structural diagram of a communication device provided by an embodiment of the present disclosure;

[0023] Figure 7 Schematic structural diagram of a chip provided by an embodiment of the present disclosure. Detailed implementation manners

[0024] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure as detailed in the appended claims.

[0025] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a" and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0026] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "when" as used herein may be interpreted as "when" or "when" or "in response to a determination".

[0027] For ease of understanding, the background art related to the present application is first introduced.

[0028] In a signal processing system, DC offset is a common problem, which is mainly caused by local oscillator leakage and circuit interference. DC offset will cause the average level of the signal to no longer be zero, thereby causing the performance of the system to decline, such as causing decision-making errors and increasing the bit error rate. In addition, DC offset will also cause an increase in the error of the device, thereby reducing its accuracy and reliability. Therefore, how to effectively eliminate or compensate the DC offset of the signal has become an urgent problem to be solved.

[0029] For a single transmitter or receiver, the DC offset cancellation or compensation schemes mainly include methods such as hardware calibration, software calibration, and filtering. However, in an actual chip digital front end, in order to ensure the signal transmission quality, the transmission link is usually calibrated by borrowing the feedback channel. However, usually the same local oscillator is used for the transmitter path (TX) and the feedback receive path (FbRX), which will cause the DC offsets of TX and FbRX to be at the same frequency point and cannot be decoupled.

[0030] Separating TX and FbRX under the same local oscillator is a challenging task because for the feedback receive channel, only the overall DC offset impact of TX and FbRX can be sensed. For this problem, the industry has tried various solutions. One solution is to first independently calibrate the DC offset on the feedback channel, and then calibrate the DC offset of the entire TX and FbRX channels. Then the calibration coefficient obtained in the second time is considered as the DC offset of the TX path. However, when this method is used for calibration, the service signal needs to be turned off, and real-time calibration during the service process cannot be achieved.

[0031] Before introducing the detailed solution of the present disclosure, the scenarios to which the solution of the present disclosure is applied will be described first.

[0032] An application scenario of a signal processing method, for example Figure 1 As shown, the data represents the service signal, which consists of a digital-to-analog converter (DAC), Figure 1 the IQ modulator on the upper side to form the transmission path, and an analog-to-digital converter (ADC), Figure 1 the IQ demodulator on the lower side to form the feedback path. Among them, the phase shifter is used to phase-shift the IQ-modulated signal to calculate the TX coefficient and the FB coefficient, and the power amplifier (PA) is used to convert the service signal into a radio frequency signal for transmission in the radio frequency path.

[0033] It can be understood that the description of the embodiments of the present disclosure is to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and does not constitute a limitation on the signal processing method, device, equipment, storage medium, and chip proposed in the embodiments of the present disclosure. Those of ordinary skill in the art know that with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions proposed in the embodiments of the present disclosure are equally applicable to similar technical problems.

[0034] Figure 2 This is a flowchart of a signal processing method provided by an embodiment of the present disclosure. As Figure 2As shown, the signal processing method includes steps 201-204.

[0035] Step 201: Determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal.

[0036] In some embodiments, a feedback signal of the first signal at the first phase shift angle may be determined based on the first signal and the first phase shift angle of the first signal, and then a first DC offset coefficient of the first loop may be determined based on the first signal and the feedback signal at the first phase shift angle.

[0037] In some embodiments, the first loop includes a transmission path and a feedback path at the first phase shift angle. For example Figure 1 As shown, when the phase shift angle of the phase shifter is the first phase shift angle, the loop formed by the transmission path composed of a DAC and an upper-side IQ modulator and the feedback path composed of a lower-side IQ demodulator and an ADC is the first loop.

[0038] In some embodiments, the transmission path is used to transmit the first signal, and the feedback path is used to transmit the feedback signal of the first signal.

[0039] In some embodiments, the first signal may be a service signal sent by a transmission source. For example Figure 1 As shown, the signal output by the upper-side IQ modulator.

[0040] In some embodiments, the specific angle value of the first phase shift angle is not limited. For example, it is the phase shift angle after initializing the phase shifter, or it may also be a preset phase shift angle.

[0041] In some embodiments, the first phase shift angle may be determined by setting the phase shift angle of the phase shifter, but not limited thereto. The first phase shift angle may also be determined by other phase modulation methods.

[0042] In some embodiments, the first DC offset coefficient is a coefficient regarding the overall DC offset of the first loop, that is, the first DC offset coefficient is the DC offset coefficient of the overall DC offset of the first loop composed of the DC offset of the transmission path and the DC offset of the feedback path at the first phase shift angle.

[0043] Step 202: Determine a second phase shift angle of the first signal.

[0044] In some embodiments, the second phase shift angle may be determined by setting the phase shift angle of the phase shifter, but not limited thereto. The second phase shift angle may also be determined by other phase modulation methods.

[0045] In some embodiments, the second phase shift angle should satisfy a first preset condition. The present disclosure does not limit the specific content of the first preset condition. For example, the second phase shift angle should be at least 1° greater than the first phase shift angle and at most 179° greater than the first phase shift angle. For example: the second phase shift angle is different from the first phase shift angle.

[0046] Step 203: Based on the first signal and the second phase shift angle, determine the second DC offset coefficient of the second loop.

[0047] In some embodiments, the feedback signal of the first signal at the second phase shift angle can be determined based on the second phase shift angle of the first signal, and then the second DC offset coefficient of the second loop can be determined based on the first signal and the feedback signal at the second phase shift angle.

[0048] In some embodiments, the second loop includes a transmission path and a feedback path at the second phase shift angle. For example Figure 1 As shown, when the phase shift angle of the phase shifter is the second phase shift angle, the loop formed by the transmission path composed of the DAC and the upper-side IQ modulator and the feedback path composed of the lower-side IQ demodulator and the ADC is the second loop.

[0049] In some embodiments, the second DC offset coefficient is a coefficient regarding the overall DC offset of the second loop, that is, the second DC offset coefficient is the DC offset coefficient of the overall DC offset of the second loop composed of the DC offset of the transmission path and the DC offset of the feedback path at the second phase shift angle.

[0050] Step 204: Based on the first DC offset coefficient and the second DC offset coefficient, perform DC offset compensation on the transmission path and / or the feedback path.

[0051] In some embodiments, the DC offset situations of the transmission path and the feedback path can be determined respectively based on the first DC offset coefficient and the second DC offset coefficient, and then the transmission path and / or the feedback path can be compensated for DC offset through the DC offset situations of the transmission path and the feedback path, so as to achieve real-time DC offset compensation for the transmission path and / or the feedback path.

[0052] In summary, the signal processing method proposed according to the present disclosure includes: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, where the first loop includes a transmission path and a feedback path at the first phase shift angle, the transmission path is used to transmit the first signal, and the feedback path is used to transmit a feedback signal of the first signal; determining a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, where the second loop includes a transmission path and a feedback path at the second phase shift angle; and performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient. The method of the present disclosure determines the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, and then obtains the compensation coefficient of the transmission path and / or the feedback path, so that the DC offset compensation can be performed on the transmission path and / or the feedback path in real time when the first signal is working, expanding the applicable range of the signal processing method and improving the convenience of DC offset compensation.

[0053] Figure 3 FIG. is a schematic flowchart of a signal processing method proposed in an embodiment of the present disclosure. As Figure 3 shown, on the basis of the embodiment shown in Figure 2 the following is a further explanation, including steps 301-307. Figure 2

[0054] Step 301: Determine a second signal based on the first signal and the first phase shift angle.

[0055] In some embodiments, the second signal is a feedback signal of the first signal at the first phase shift angle. For example, Figure 1 as shown, the second signal may be the signal output by the ADC when the phase shift angle of the phase shifter is the first phase shift angle.

[0056] In some embodiments, the first signal may be phase-shifted based on the first phase shift angle, and the phase-shifted first signal may be subjected to IQ modulation and analog-to-digital conversion to determine the signal output by the ADC as the second signal. It should be understood that the signal lengths of the second signal and the first signal are the same.

[0057] Step 302: Determine a first DC offset coefficient of the first loop based on the first signal and the second signal.

[0058] ​In some embodiments, before determining the first DC offset coefficient, it is also necessary to perform time delay alignment on the first signal and the second signal to reduce the error of the first DC offset coefficient. The present disclosure does not limit the method of time delay alignment, for example: performing time delay alignment on the first signal and the second signal through fourth-order delay spectrum estimation; for example: performing time delay alignment on the first signal and the second signal by calculating the second-order conjugate complex correlation of the first signal and the second signal, etc.

[0059] In some embodiments, the first DC offset coefficient of the first loop can be determined by the following formula:

[0060]

[0061] wherein, dc1 represents the first DC offset coefficient, N represents the signal length of the first signal, x(t) represents the first signal, and fb1(t) represents the second signal.

[0062] Step 303: Determine a third signal based on the first signal and the second phase shift angle.

[0063] In some embodiments, the third signal is a feedback signal of the first signal at the second phase shift angle. For example Figure 1 as shown, the third signal can be the signal output by the ADC when the phase shift angle of the phase shifter is the second phase shift angle.

[0064] In some embodiments, based on the second phase shift angle, the first signal can be phase-shifted, and the phase-shifted first signal can be subjected to IQ modulation and analog-to-digital conversion to determine the signal output by the ADC as the third signal. It should be understood that the third signal has the same signal length as the first signal.

[0065] Step 304: Determine the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0066] In some embodiments, before determining the second DC offset coefficient, it is also necessary to perform time delay alignment on the first signal and the third signal to reduce the error of the second DC offset coefficient. The present disclosure does not limit the method of time delay alignment, for example: performing time delay alignment on the first signal and the second signal through fourth-order delay spectrum estimation; for example: performing time delay alignment on the first signal and the second signal by calculating the second-order conjugate complex correlation of the first signal and the second signal, etc.

[0067] In some embodiments, the second DC offset coefficient of the second loop can be determined by the following formula:

[0068]

[0069] Wherein, dc2 represents the second DC offset coefficient, N represents the signal length of the first signal, x(t) represents the first signal, and fb2(t) represents the third signal.

[0070] Step 305, determine the loop gain of the first loop and the loop gain of the second loop.

[0071] In some embodiments, the method for determining the loop gain of the first loop and the loop gain of the second loop is not limited, such as the voltage injection method, the current injection method, etc.

[0072] Step 306, based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop, determine the first compensation coefficient of the transmit path and / or the second compensation coefficient of the feedback path.

[0073] In some embodiments, the first compensation coefficient of the transmit path and / or the second compensation coefficient of the feedback path can be determined by the following formula:

[0074]

[0075] Wherein, g1 represents the loop gain of the first loop, g2 represents the loop gain of the second loop, d tx represents the first compensation coefficient of the transmit path, d fb represents the second compensation coefficient of the feedback path, dc1 represents the first DC offset coefficient, and dc2 represents the second DC offset coefficient.

[0076] Furthermore, by solving the equation shown in Equation 2, the above-mentioned first compensation coefficient and / or second compensation coefficient can be determined.

[0077] Wherein, the solution result is expressed as follows:

[0078]

[0079] Step 307, based on the first compensation coefficient, perform DC offset compensation on the transmit path to obtain a compensated transmit path; and / or based on the second compensation coefficient, perform DC offset compensation on the feedback path to obtain a compensated feedback path.

[0080] In some embodiments, the transmit path can be compensated for DC offset by the first compensation coefficient to obtain a compensated transmit path, so as to achieve DC offset compensation for the transmit path.

[0081] For example Figure 1 as shown, input the first DC offset coefficient d tx into the TX DC offset compensation module, so as to achieve DC offset compensation for the transmit path, where the TX DC offset compensation module and the transmit path form a compensated transmit path.

[0082] In some embodiments, the direct current (DC) offset of the feedback path can be compensated by a second compensation coefficient to obtain a compensated feedback path, so as to achieve the DC offset compensation of the feedback path.

[0083] For example Figure 1 as shown, the second DC offset coefficient d fb is input into the FB DC offset compensation module, thereby realizing the DC offset compensation of the feedback path, where the FB DC offset compensation module and the transmit path form a compensated transmit path.

[0084] In some embodiments, the DC offset of the transmit path and / or the feedback path can be compensated by the following formula:

[0085] sig out = sig in - dc (Equation 5)

[0086] where sig out represents the output signal of the TX DC offset compensation module or the FB DC offset compensation module, sig in represents the input signal of the TX DC offset compensation module, and dc represents the first compensation coefficient or the second compensation coefficient. For example, when compensating the DC offset of the transmit path, sig out represents the output signal of the TX DC offset compensation module, sig in represents the input signal of the output signal of the FB DC offset compensation module, and dc represents the first compensation coefficient, that is, dc is equivalent to d tx obtained by solving Equation 4. For example, when compensating the DC offset of the feedback path, sig out represents the output signal of the FB DC offset compensation module, sig in represents the input signal of the FB DC offset compensation module, and dc represents the second compensation coefficient, that is, dc is equivalent to d fb obtained by solving Equation 4.

[0087] In summary, the signal processing method proposed according to the present disclosure includes: determining a second signal based on a first signal and a first phase shift angle, where the second signal is a feedback signal of the first signal at the first phase shift angle; determining a first DC offset coefficient of a first loop based on the first signal and the second signal; determining a third signal based on the first signal and a second phase shift angle, where the third signal is a feedback signal of the first signal at the second phase shift angle; determining a second DC offset coefficient of a second loop based on the first signal and the third signal; determining the loop gain of the first loop and the loop gain of the second loop; determining a first compensation coefficient for the transmit path and / or a second compensation coefficient for the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop; performing DC offset compensation on the transmit path based on the first compensation coefficient to obtain a compensated transmit path; and / or performing DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path. In the method of the present disclosure, by setting two different phase shift angles, the first DC offset coefficient and the second DC offset coefficient in the loop are determined at the two different phase shift angles, and by obtaining the loop gains of the first loop and the second loop, an equation is established using the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop, and the solution result of the equation is determined as the first compensation coefficient for the transmit path and / or the second compensation coefficient for the feedback path, so that the DC offset compensation of the transmit path and / or the feedback path is realized using the first compensation coefficient and / or the second compensation coefficient, expanding the applicable range of the signal processing method and improving the convenience of DC offset compensation.

[0088] Figure 4 FIG. is a schematic flow chart of a signal processing method proposed in an embodiment of the present disclosure. As Figure 4 shown, on the basis of the embodiment shown in Figure 3 FIG., it is further explained that when the temperature, humidity, etc. of the compensated transmit path and / or the compensated feedback path change, in order to ensure the accuracy of the DC offset compensation of the compensated transmit path and / or the compensated feedback path, steps 401-403 are further included.

[0089] Step 401: Determine a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient.

[0090] In some embodiments, a third DC offset coefficient of a third loop may be determined based on the first compensation coefficient, where the third loop includes the compensated transmit path and the compensated feedback path at a third phase shift angle.

[0091] For example Figure 1As shown, the first compensation coefficient is configured in the TX DC offset compensation module, the second compensation coefficient is configured in the FB DC offset compensation module, and the phase shift angle of the phase shifter is set to the third phase shift angle. By obtaining the first signal in the compensated transmission path and the feedback signal of the first signal in the compensated feedback path, and using the formula shown in Equation 1, the third DC offset coefficient can be determined.

[0092] In some embodiments, the third phase shift angle may be the same as or different from the first phase shift angle, and the present disclosure does not limit this.

[0093] In some embodiments, the fourth DC offset coefficient of the fourth loop may be determined based on the second compensation coefficient, where the fourth loop includes a compensated transmission path and a compensated feedback path at the fourth phase shift angle.

[0094] For example Figure 1 As shown, the first compensation coefficient is configured in the TX DC offset compensation module, the second compensation coefficient is configured in the FB DC offset compensation module, and the phase shift angle of the phase shifter is set to the fourth phase shift angle. By obtaining the first signal in the compensated transmission path and the feedback signal of the first signal in the compensated feedback path, and using the formula shown in Equation 2, the fourth DC offset coefficient can be determined.

[0095] In some embodiments, the third phase shift angle and the fourth phase shift angle satisfy a second preset condition. The present disclosure does not limit the specific content of the second preset condition. For example, the second phase shift angle should be at least 1° greater than the first phase shift angle and at most 179° greater than the first phase shift angle. For example, the second phase shift angle is different from the first phase shift angle. In other words, in some embodiments, the first preset condition may have the same content as the second preset condition.

[0096] Step 402, perform DC offset compensation on the compensated transmission path based on the third compensation coefficient.

[0097] In some embodiments, the first compensation coefficient may be calibrated based on the third compensation coefficient, and the calibrated first compensation coefficient is configured in the TX DC offset compensation module to achieve DC offset compensation for the compensated transmission path.

[0098] In some embodiments, the calibration of the first compensation coefficient can be achieved through the following formula:

[0099] d txr =d tx +dc txerr (Equation 6)

[0100] Where, d txr represents the calibrated first compensation coefficient, d tx represents the first compensation coefficient, and dc txerrRepresents the third compensation coefficient.

[0101] Step 403: Based on the fourth compensation coefficient, perform DC offset compensation on the compensation feedback path.

[0102] In some embodiments, the second compensation coefficient can be calibrated based on the fourth compensation coefficient, and the calibrated second compensation coefficient can be configured in the FB DC offset compensation module, so as to achieve DC offset compensation for the compensation feedback path.

[0103] In some embodiments, the calibration of the first compensation coefficient can be achieved through the following formula:

[0104] d fbr = d fb + dc fberr (Equation 7)

[0105] Wherein, d fbr represents the calibrated second compensation coefficient, d fb represents the second compensation coefficient, and dc fberr represents the fourth compensation coefficient.

[0106] In summary, the signal processing method proposed according to the present disclosure includes: determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, where the third compensation coefficient is used to calibrate the compensation transmission path, and the fourth compensation coefficient is used to calibrate the compensation feedback path; performing DC offset compensation on the compensation transmission path based on the third compensation coefficient; performing DC offset compensation on the compensation feedback path based on the fourth compensation coefficient, so as to achieve DC offset compensation for the compensation transmission path and / or the compensation feedback path, and ensure the accuracy of DC offset compensation for the compensation transmission path and / or the compensation feedback path when external conditions change.

[0107] Therefore, the present solution has the following beneficial effects:

[0108] 1. It can perform DC offset compensation on the transmission path and / or the feedback path in real time when the first signal is working, expanding the applicable range of the signal processing method and improving the convenience of DC offset compensation.

[0109] 2. Ensure the accuracy of DC offset compensation when external conditions change.

[0110] Figure 5 FIG. 43 is a schematic structural diagram of a signal processing device 500 provided by an embodiment of the present disclosure. The communication device includes:

[0111] A first processing unit 510 is configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal. The first loop includes a transmission path and a feedback path at the first phase shift angle. The transmission path is used to transmit the first signal, and the feedback path is used to transmit a feedback signal of the first signal.

[0112] A second processing unit 520 is configured to determine a second phase shift angle of the first signal, and the second phase shift angle satisfies a first preset condition.

[0113] A third processing unit 530 is configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle. The second loop includes a transmission path and a feedback path at the second phase shift angle.

[0114] A fourth processing unit 540 is configured to perform DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0115] In some embodiments, the first processing unit 510 is further configured to determine a second signal based on the first signal and the first phase shift angle, where the second signal is a feedback signal of the first signal at the first phase shift angle; and determine the first DC offset coefficient of the first loop based on the first signal and the second signal.

[0116] In some embodiments, the third processing unit 530 is further configured to determine a third signal based on the first signal and the second phase shift angle, where the third signal is a feedback signal of the first signal at the second phase shift angle; and determine the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0117] In some embodiments, the fourth processing unit 540 is further configured to determine the loop gain of the first loop and the loop gain of the second loop; determine a first compensation coefficient of the transmission path and / or a second compensation coefficient of the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop; perform DC offset compensation on the transmission path based on the first compensation coefficient to obtain a compensated transmission path; and / or perform DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path.

[0118] In some embodiments, the fourth processing unit 540 is further configured to determine a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient. The third compensation coefficient is used to calibrate the compensated transmission path, and the fourth compensation coefficient is used to calibrate the compensated feedback path; perform DC offset compensation on the compensated transmission path based on the third compensation coefficient; and perform DC offset compensation on the compensated feedback path based on the fourth compensation coefficient.

[0119] In some embodiments, the fourth processing unit 540 is further configured to determine a third DC offset coefficient of the third loop and a fourth offset coefficient of the fourth loop based on a first compensation coefficient and a second compensation coefficient. The third loop includes a compensated transmission path and a compensated feedback path at a third phase shift angle, and the fourth loop includes a compensated transmission path and a compensated feedback path at a fourth phase shift angle. The third phase shift angle and the fourth phase shift angle satisfy a second preset condition; determine the loop gain of the third loop and the loop gain of the fourth loop; and determine a third compensation coefficient and a fourth compensation coefficient based on the third DC offset coefficient, the fourth DC offset coefficient, the loop gain of the third loop, and the loop gain of the fourth loop.

[0120] In summary, the signal processing apparatus according to the present disclosure includes: a first processing unit configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal. The first loop includes a transmission path and a feedback path at the first phase shift angle. The transmission path is configured to transmit the first signal, and the feedback path is configured to transmit a feedback signal of the first signal; a second processing unit configured to determine a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; a third processing unit configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle. The second loop includes a transmission path and a feedback path at the second phase shift angle; and a fourth processing unit configured to perform DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient. By determining the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, the apparatus of the present disclosure further obtains the compensation coefficients of the transmission path and / or the feedback path, so that DC offset compensation can be performed on the transmission path and / or the feedback path in real time when the first signal is working, expanding the applicable range of the signal processing method and improving the convenience of DC offset compensation.

[0121] Since the apparatus provided in the embodiments of the present disclosure corresponds to the methods provided in the above several embodiments, the implementation manners of the methods are also applicable to the apparatus provided in this embodiment and will not be described in detail in this embodiment.

[0122] In the above embodiments provided by the present application, the methods and apparatuses provided by the embodiments of the present application are introduced. To implement each function in the methods provided by the embodiments of the present application, a communication device may include a hardware structure and software modules, and implement the above functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. A certain function among the above functions may be executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module.

[0123] Figure 6FIG. 0 is a schematic structural diagram of a communication device 600 provided by an embodiment of the present application. The communication device 600 may be a network device, a terminal device, a chip, a chip system, or a processor that supports the network device to implement the above method, or a chip, a chip system, or a processor that supports the terminal device to implement the above method. The device can be used to implement the method described in the above method embodiment, and for details, reference can be made to the description in the above method embodiment.

[0124] The communication device 600 may include one or more processors 601. The processor 601 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processing unit may be used to control a communication device (such as a base station, a baseband chip, a terminal device, a terminal device chip, a DU or a CU, etc.), execute a computer program, and process data of the computer program.

[0125] Optionally, the communication device 600 may further include one or more memories 602, on which a computer program 604 may be stored. The processor 601 executes the computer program 604 to cause the communication device 600 to execute the method described in the above method embodiment. Optionally, data may also be stored in the memory 602. The communication device 600 and the memory 602 may be provided separately or integrated together.

[0126] Optionally, the communication device 600 may further include a transceiver 605 and an antenna 606. The transceiver 605 may be referred to as a transceiver unit, a transceiver, or a transceiver circuit, etc., and is used to implement transceiver functions. The transceiver 605 may include a receiver and a transmitter. The receiver may be referred to as a receiver or a receiving circuit, etc., and is used to implement receiving functions; the transmitter may be referred to as a transmitter or a transmitting circuit, etc., and is used to implement transmitting functions.

[0127] Optionally, the communication device 600 may further include one or more interface circuits 606. The interface circuit 606 is used to receive code instructions and transmit them to the processor 601. The processor 601 runs the code instructions to cause the communication device 600 to execute the method described in the above method embodiment.

[0128] In one implementation, the processor 601 may include a transceiver for implementing receiving and transmitting functions. For example, the transceiver may be a transceiver circuit, an interface, or an interface circuit. The transceiver circuit, interface, or interface circuit for implementing receiving and transmitting functions may be separate or integrated together. The above transceiver circuit, interface, or interface circuit may be used for reading and writing code / data, or the above transceiver circuit, interface, or interface circuit may be used for signal transmission or transfer.

[0129] In one implementation, the processor 601 may store a computer program 603, which runs on the processor 601 and enables the communication device 600 to perform the method described in the above method embodiment. The computer program 603 may be fixed in the processor 601, in which case the processor 601 may be implemented by hardware.

[0130] In one implementation, the communication device 600 may include a circuit that can implement the functions of sending or receiving or communicating in the aforementioned method embodiments. The processor and transceiver described in the present application may be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit RFIC, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver may also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0131] The communication device described in the above embodiments may be a network device or a terminal device, but the scope of the communication device described in this application is not limited thereto, and the structure of the communication device may not be limited thereto. Figure 6 The communication device may be a stand-alone device or may be part of a larger device. For example, the communication device may be:

[0132] (1) Independent integrated circuit IC, or chip, or chip system or subsystem;

[0133] (2) having a set of one or more ICs, and optionally, the IC set may also include a storage component for storing data and computer programs;

[0134] (3) ASIC, such as modem;

[0135] (4) Modules that can be embedded in other devices;

[0136] (5) Receivers, terminal devices, intelligent terminal devices, cellular phones, wireless devices, handsets, mobile units, vehicle-mounted devices, network devices, cloud devices, artificial intelligence devices, etc.;

[0137] (6) Others, etc.

[0138] For the case where the communication device can be a chip or a chip system, reference can be made to Figure 7 the structural schematic diagram of the chip shown.

[0139] Embodiments of the present disclosure also propose a chip, such as Figure 7 the chip shown includes at least one processor 701 and a communication interface 702. Among them, the communication interface 702 is used to receive signals input to the chip or signals output from the chip, and the processor 701 communicates with the communication interface 702 and implements the methods described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0140] Optionally, the chip further includes a memory 703, and the memory 703 is used to store necessary computer programs and data.

[0141] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.

[0142] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope protected by the embodiments of the present application.

[0143] It should be noted that the terms "first", "second", etc. in the specification, claims, and the above drawings of the present disclosure are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0144] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0145] Any process or method description shown in the flowchart or described in other ways herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations, where the functions may be executed in a manner that is not shown or discussed, including substantially simultaneously according to the involved functions or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0146] The logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (control method), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0147] It should be understood that each part of the embodiments of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0148] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0149] In addition, in each embodiment of the present invention, each functional unit can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0150] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations on the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A signal processing method, characterized in that, The method includes: Determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, where the first loop includes a transmission path and a feedback path at the first phase shift angle, the transmission path is used to transmit the first signal, and the feedback path is used to transmit a feedback signal of the first signal; Determining a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; Determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, where the second loop includes a transmission path and a feedback path at the second phase shift angle; Performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

2. The method according to claim 1, characterized in that The determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal includes: Determining a second signal based on the first signal and the first phase shift angle, where the second signal is a feedback signal of the first signal at the first phase shift angle; Determining the first DC offset coefficient of the first loop based on the first signal and the second signal.

3. The method according to claim 1, characterized in that, The determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle includes: Determining a third signal based on the first signal and the second phase shift angle, where the third signal is a feedback signal of the first signal at the second phase shift angle; Determining the second DC offset coefficient of the second loop based on the first signal and the third signal.

4. The method according to claim 1, characterized in that, The performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient includes: Determining the loop gain of the first loop and the loop gain of the second loop; Determining a first compensation coefficient of the transmission path and / or a second compensation coefficient of the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop; Performing DC offset compensation on the transmission path based on the first compensation coefficient to obtain a compensated transmission path; and / or Performing DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path.

5. The method according to claim 4, wherein The method further includes: Determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, where the third compensation coefficient is used to calibrate the compensated transmission path, and the fourth compensation coefficient is used to calibrate the compensated feedback path; Performing DC offset compensation on the compensated transmission path based on the third compensation coefficient; Performing DC offset compensation on the compensated feedback path based on the fourth compensation coefficient.

6. The method according to claim 5, characterized in that, The determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient includes: Based on the first compensation coefficient and the second compensation coefficient, determine a third DC offset coefficient of a third loop and a fourth offset coefficient of a fourth loop. The third loop includes the compensated transmit path and the compensated feedback path at a third phase shift angle, and the fourth loop includes the compensated transmit path and the compensated feedback path at a fourth phase shift angle. The third phase shift angle and the fourth phase shift angle satisfy a second preset condition; Determine the loop gain of the third loop and the loop gain of the fourth loop; Based on the third DC offset coefficient, the fourth DC offset coefficient, the loop gain of the third loop, and the loop gain of the fourth loop, determine the third compensation coefficient and the fourth compensation coefficient.

7. A signal processing device, characterized in that, Comprising: A first processing unit, configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal. The first loop includes a transmit path and a feedback path at the first phase shift angle. The transmit path is configured to transmit the first signal, and the feedback path is configured to transmit a feedback signal of the first signal; A second processing unit, configured to determine a second phase shift angle of the first signal, where the second phase shift angle satisfies a first preset condition; A third processing unit, configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle. The second loop includes a transmit path and a feedback path at the second phase shift angle; A fourth processing unit, configured to perform DC offset compensation on the transmit path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

8. A communication device, characterized in that, The device includes a processor and a memory. The memory stores a computer program, and the processor executes the computer program stored in the memory to cause the device to execute: the method according to any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-6.

10. A chip, characterized in that, Comprising at least one processor and a communication interface; the communication interface is configured to receive a signal input to the chip or a signal output from the chip, and the processor communicates with the communication interface and implements the method according to any one of claims 1-6 through a logic circuit or by executing code instructions.

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