1553B bus transceiver device implemented by discrete components and implementation method

Abstract

The invention relates to the field of communication devices, and particularly discloses a 1553B bus transceiver device implemented by discrete components and an implementation method, and the device comprises a transmitter module which is used for receiving a control digital signal, converting the control digital signal into a differential signal after the control digital signal is subjected to level conversion, linear integration and amplification processing in sequence, and outputting the differential signal; the receiver module is used for receiving an input signal, performing level adjustment and voltage comparison on the input signal and then outputting a differential voltage signal; the bus controller module is respectively in signal connection with the transmitter module and the receiver module, and is used for executing a working flow comprising controller initialization, remote terminal resetting, polling instruction sending, data transmission and message sending confirmation, and realizing serial port configuration of a 1553B bus; and the receiving rate self-adaptive module is embedded in the bus controller module. By the adoption of the technical scheme, maintenance is convenient, and relevant parameters can be flexibly adjusted.

Description

Technical Field

[0001] The present invention relates to the field of communication devices, and particularly to a 1553B bus transceiver device and implementation method implemented by discrete components. Background Art

[0002] In modern avionics systems, the high efficiency and stability of data transmission have become key requirements in many fields. In the 1960s, as the complexity of airborne electronic systems increased, traditional communication methods gradually became difficult to meet the requirements. For this reason, the US military led the research and development of a standardized multiplexing system, and promulgated the MIL-STD-1553B standard in the 1970s. This standard quickly became an international common data bus specification. 1553B bus chips, with high reliability, are widely used in military, aerospace and other fields, undertaking the stable data transmission tasks between key components in aircraft, missiles and other systems, and are the core technology to ensure flight safety and mission execution. With the development of technology, the application scope of 1553B bus chips has been continuously expanded to civilian fields such as industrial automation and rail transit, showing wide adaptability.

[0003] The rapid development of China's national defense modernization and aerospace industry has promoted a significant increase in the demand for 1553B bus chips.

[0004] Currently, when applying the MIL-STD-1553 data bus in China, most use the HI-1573PSI single-chip dual 3.3V transceiver. This chip uses a compact SOIC package, and the size is reduced to 0.5*0.4 inches, but it causes heat dissipation problems. Its bottom integrated metal radiator has extremely high requirements for the precision and materials of the packaging process. And it needs to be matched with a MIL-STD-1553 transformer that meets strict standards. Such transformers are scarce in the market, resulting in a further increase in the overall cost.

[0005] Existing 1553B buses mostly adopt a dual-redundancy bus system. This design improves reliability. Through the standby bus, it can quickly take over when the main bus fails, ensuring stable data transmission and enhancing anti-interference ability. However, from the perspective of chips, there are significant defects in foreign integrated all-in-one hybrid package interface circuits such as the BU-61580.

[0006] First, the high integration degree makes it difficult to repair. When a failure occurs, the whole needs to be replaced, which is costly and causes waste of resources. Second, the parameters of internal components are fixed, and signal rise time, electrical parameters, etc. cannot be adjusted flexibly, restricting function expansion. Therefore, there is an urgent need for a 1553B bus transceiver device and method implemented by discrete components to solve problems such as poor maintainability and insufficient parameter flexibility. Summary of the Invention

[0007] The present invention provides a 1553B bus transceiver device and method implemented by discrete components.

[0008] To solve the above technical problems, the present application provides the following technical solutions:

[0009] A 1553B bus transceiver device implemented by discrete components, comprising:

[0010] A transmitter module, configured to receive a control digital signal, and convert it into a differential signal for output after successively performing level conversion, linear integration, and amplification processing;

[0011] A receiver module, configured to receive an input signal, and output a differential voltage signal after performing level adjustment and voltage comparison on the input signal;

[0012] A bus controller module, respectively signal-connected to the transmitter module and the receiver module, configured to execute a workflow including controller initialization, resetting a remote terminal, sending a polling instruction, data transmission, and confirmation message sending, to implement serial port configuration of the 1553B bus;

[0013] A receive rate adaptive module, embedded in the bus controller module, configured to adjust the output signal frequency in real time according to the actual clock through dynamic PLL reconfiguration technology, estimate the input clock frequency using a frequency meter state machine, adjust PLL parameters using the PLL dynamic reconfiguration function, optimize the clock switching jitter problem using a finite state machine, and perform asynchronous cross-frequency data processing using a FIFO buffer to reduce the probability of metastability.

[0014] The principle and beneficial effects of the basic solution are as follows: Designed with discrete components, the units are connected in a detachable manner. When a certain unit fails, the unit can be directly replaced without replacing the entire module, greatly reducing the maintenance cost and time. The parameters of the transmitter module and the receive rate adaptive module can be adjusted through an external configuration interface. For example, parameters such as the amplification factor and integration time of the operational amplifier unit can be set according to actual requirements; the receive rate adaptive module can adjust the output signal frequency in real time through dynamic PLL reconfiguration technology to adapt to different input frequency conditions.

[0015] Further, the transmitter module specifically includes:

[0016] A control signal input unit, configured to receive a control digital signal, and convert the control digital signal into a level signal that can be processed by an operational amplifier unit through a level converter;

[0017] A linear integration unit, connected to the control signal input unit, configured to perform linear integration processing on the level signal after level conversion to suppress high-frequency noise therein;

[0018] The operational amplifier unit includes an integration module and a difference calculation module, which are used to amplify the level signal after linear integration, and realize the forward and reverse processing of the level signal through a bidirectional integration reference level unit;

[0019] The differential output unit is connected to the operational amplifier unit and is used to convert the amplified level signal into a differential signal for output, so as to improve the anti-interference ability during signal transmission;

[0020] The output protection unit is connected in parallel with the differential output unit and is used to prevent the circuit system from being damaged in case of overload or short circuit;

[0021] The output unit provides electrical isolation in a transformer-coupled manner to avoid the impact of terminal faults on the entire bus system;

[0022] The power supply unit provides a stable power supply for the transmitter module. It uses a ±5V dual power supply to ensure sufficient current and voltage to maintain the normal operation of the system. It adopts an independent heat dissipation design, including a heat sink and a fan, to ensure power supply stability when operating at high load and generating heat.

[0023] Furthermore, the receiver module specifically includes:

[0024] The level control unit is used to adjust the level of the input signal so that the level of the input signal meets the requirements of subsequent processing;

[0025] The voltage comparison unit includes two comparators and is used to receive the output signal adjusted by the level control unit, perform voltage comparison on this signal, and output a differential voltage signal to realize further processing and conversion of the input signal;

[0026] Among them, the receiver module adopts a discrete component design, and the constituent units are connected in a detachable manner.

[0027] Furthermore, the software design of the bus controller module adopts a modular design, is built based on the PySide6 framework, and includes a bus configuration module, a message management module, a real-time monitoring module, and a serial port communication module. The bus configuration module is used to initialize the parameters of the 1553B bus; the message management module is used to organize and schedule the messages sent and received; the real-time monitoring module is used to monitor the working state of the bus in real time; the serial port communication module is used to realize serial port communication with external devices.

[0028] Furthermore, the working process of the bus controller module includes the following steps:

[0029] Controller initialization: Preset the internal registers and parameters;

[0030] Reset remote terminals: Send instructions to restore all remote terminals to their initial states;

[0031] Periodic polling: Periodically send polling instructions to query the status and data requirements of each remote terminal;

[0032] Data transmission: Transfer data among the transmitter module, receiver module, and remote terminals according to requirements;

[0033] Confirmation message sending: Verify the completion of data transmission and feedback the results.

[0034] Furthermore, the bus controller module is respectively connected to the transmitter module and the receiver module through standard communication interfaces. The communication interfaces use optocoupler components to achieve electrical isolation functions, and low-pass filters are constructed by setting capacitive and inductive passive components in the interface circuits to block high-frequency noise and achieve signal buffering functions; the optocoupler components are based on the principle of photoelectric conversion to form a physical isolation barrier between the input and output ends.

[0035] Furthermore, the receive rate adaptive module uses Quartus software and Verilog language to implement corresponding functions; the frequency counter state machine in the receive rate adaptive module uses the multi-cycle synchronous frequency measurement method to reduce measurement errors by counting multiple clock cycles. In each measurement cycle, the frequency counter state machine counts the input clock signal and calculates the frequency of the input clock based on the counting results, thereby providing an accurate basis for subsequent adjustment of the PLL parameters.

[0036] Furthermore, the dynamic reconfiguration function of the PLL in the receive rate adaptive module adjusts the PLL parameters based on an adaptive algorithm; the adaptive algorithm dynamically calculates appropriate PLL parameters according to the input clock frequency estimated by the frequency counter state machine and the preset output frequency requirements; and it has a feedback adjustment mechanism. After adjusting the PLL parameters, it will monitor the output signal frequency in real time and fine-tune the parameters according to the monitoring results, so as to ensure that the output signal frequency can quickly and accurately track the change of the input clock frequency and achieve adaptive adjustment to different input clock conditions.

[0037] Furthermore, the finite state machine in the receiving rate adaptive module adopts state prediction and compensation technology to optimize the jitter problem generated during clock switching; before clock switching, the finite state machine predicts the possible jitter situation during clock switching based on the current clock state and historical data, and calculates the corresponding compensation value in advance; during clock switching, the finite state machine adjusts the output signal in real time according to the calculated compensation value; the first-in-first-out buffer in the receiving rate adaptive module adopts a dual-port design, which is used for efficient data transmission between different clock domains and automatically corrects errors when errors are detected during data transmission. Description of the Drawings

[0038] Figure 1 It is a logic block diagram of a 1553B bus transceiver device implemented by discrete components;

[0039] Figure 2 It is a logic block diagram of the transmitter module;

[0040] Figure 3 It is a circuit diagram of the transmitter module;

[0041] Figure 4 It is a circuit diagram of the control signal input unit and the linear integration unit;

[0042] Figure 5 It is a circuit diagram of the operational amplifier unit and the differential output unit;

[0043] Figure 6 It is a circuit diagram of the output unit;

[0044] Figure 7 It is a circuit diagram of the power supply unit;

[0045] Figure 8 It is a circuit diagram of the receiver module;

[0046] Figure 9 It is a flowchart of the operation of the bus controller module;

[0047] Figure 10 It is a screenshot of the upper computer interface;

[0048] Figure 11 It is a screenshot of the upper computer interface;

[0049] Figure 12 It is a screenshot of the upper computer interface;

[0050] Figure 13 It is a screenshot of the upper computer interface. Detailed Implementation Modes

[0051] The following is a further detailed description through specific implementation modes:

[0052] The embodiment is basically as follows Figure 1 shown, a 1553B bus transceiver device implemented by discrete components, characterized in that it includes:

[0053] A transmitter module, configured to receive a control digital signal, and convert it into a differential signal for output after sequentially performing level conversion, linear integration, and amplification processing;

[0054] A receiver module, configured to receive an input signal, and output a differential voltage signal after performing level adjustment and voltage comparison on the input signal;

[0055] A bus controller module, which is respectively signal-connected to the transmitter module and the receiver module, and is configured to execute work processes including controller initialization, resetting a remote terminal, sending a polling instruction, data transmission, and confirmation message sending, so as to implement serial port configuration of the 1553B bus;

[0056] A receive rate adaptive module, embedded in the bus controller module, is configured to adjust the output signal frequency in real time according to the actual clock through dynamic PLL reconfiguration technology, estimate the input clock frequency by using a frequency meter state machine, adjust the PLL parameters by using the PLL dynamic reconfiguration function, optimize the clock switching jitter problem by using a finite state machine, and perform asynchronous cross-frequency data processing by using a FIFO buffer to reduce the probability of metastability occurrence.

[0057] Specifically, the transmitter module is configured to receive a control digital signal, and convert it into a differential signal for output after sequentially performing level conversion, linear integration, and amplification processing. The specific composition is as follows (as shown in Figure 2 、 Figure 3 ):

[0058] A control signal input unit: This unit is responsible for receiving a control digital signal, and converting it into a level signal that can be processed by an operational amplifier unit through a level converter. The function of the level converter is to match the input control digital signal with the level requirements of the subsequent processing circuit to ensure that the signal can be correctly processed.

[0059] A linear integration unit (as shown in Figure 4 ): It is connected to the control signal input unit, and performs linear integration processing on the level signal after level conversion. The purpose of linear integration is to suppress high-frequency noise in the signal, improve the signal quality, and provide a more stable input signal for subsequent amplification processing.

[0060] An operational amplifier unit (as shown in Figure 5 ) includes an integration module and a difference module, and performs amplification processing on the level signal after linear integration. At the same time, forward and reverse processing of the level signal is realized through a bidirectional integration reference level unit to enhance the signal processing ability and flexibility.

[0061] The differential output unit is connected to the operational amplifier unit and converts the amplified level signal into a differential signal for output. The differential signal has strong anti-interference ability, can effectively reduce the interference of the signal during transmission, and improve the reliability of data transmission.

[0062] The output protection unit is connected in parallel with the differential output unit. When abnormal situations such as overload or short circuit occur, it can prevent damage to the circuit system. The output protection unit can adopt circuits such as overcurrent protection and overvoltage protection to ensure the safety of the device under abnormal conditions.

[0063] The output unit (as shown in Figure 6 ) provides electrical isolation by means of transformer coupling, avoiding the impact of terminal faults on the entire bus system. Transformer coupling can effectively isolate the electrical connections between different circuits, prevent the spread of faults, and improve the reliability of the system.

[0064] The power supply unit (as shown in Figure 7 ) provides a stable power supply for the transmitter module, uses ±5V dual power supplies to ensure sufficient current and voltage to maintain the normal operation of the system. At the same time, an independent heat dissipation design is adopted, including a heat sink and a fan, to ensure power supply stability when operating at high load and generating heat. The heat sink can increase the heat dissipation area and improve the heat dissipation efficiency, while the fan further accelerates the air flow and reduces the operating temperature of the components.

[0065] The receiver module (as shown in Figure 8 ) is used to receive the input signal, and after performing level adjustment and voltage comparison on the input signal, it outputs a differential voltage signal. The specific composition is as follows:

[0066] The level control unit consists of a transformer and is used to adjust the level of the input signal so that the level of the input signal meets the requirements of subsequent processing. The transformer can perform step-up or step-down processing on the input signal according to needs to ensure that the signal can be correctly processed.

[0067] The voltage comparison unit includes two comparators, which are used to receive the output signal adjusted by the level control unit, perform voltage comparison on this signal, and output a differential voltage signal. The voltage comparator can compare the input signal with a reference voltage and output a high-level or low-level signal, thereby realizing further processing and conversion of the input signal.

[0068] The bus controller module (the working process is as shown in Figure 9 ) is respectively signal-connected to the transmitter module and the receiver module, and is used to execute the working processes including controller initialization, resetting the remote terminal, sending polling instructions, data transmission, and confirmation message sending, to realize the serial port configuration of the 1553B bus.

[0069] Adopting a modular design, it is built based on the PySide6 framework and includes a bus configuration module, a message management module, a real-time monitoring module, and a serial communication module. Each module works together to achieve the serial configuration of the 1553B bus. Among them, the bus configuration module is used to initialize the parameters of the 1553B bus; the message management module is responsible for organizing and scheduling the messages sent and received; the real-time monitoring module monitors the working status of the bus in real time; the serial communication module realizes the serial communication with the host computer.

[0070] The host computer design uses an intuitive graphical interface (such as Figure 10 , Figure 11 , Figure 12 , Figure 13 shown), which simplifies the operation process of users. It supports multiple bus modes, ensuring the flexibility and reliability of the system; realizes the real-time monitoring function, ensuring the stability of the system and the real-time nature of data; integrates the serial communication function to meet the interaction requirements with external devices. The host computer is divided into multiple core modules, including the main window, the bus configuration module, the message management module, the real-time monitoring module, the serial communication module, and the dialog box module, etc.

[0071] At startup, first, the controller is initialized, and the internal registers and parameters are preset; then, a reset remote terminal instruction is sent to restore all remote terminals to the initial state; then, polling instructions are sent periodically to query the status and data requirements of each remote terminal; after determining the data transmission requirements, data transmission is carried out to ensure that the data is accurately transmitted between the transmitter module, the receiver module, and the remote terminal; finally, a confirmation message is sent to confirm the completion of the data transmission to ensure the reliability of the entire communication process.

[0072] Specifically, the working process is as follows:

[0073] Controller initialization: Start the controller and initialize it (default set to dual-redundant bus mode), and check whether the electrical parameters are successful. If it fails, repeat the check or switch to the standby bus according to different modes.

[0074] Reset all remote terminals (RT): Send a reset instruction to reset all RTs to the initial state.

[0075] According to the polling table preset by the system, send polling instructions to each RT in turn to check their existence and status.

[0076] According to the status word returned by the RT, judge whether data needs to be transmitted. If so, prepare for data transmission.

[0077] Construct a data transmission instruction word to specify that the RT sends or receives data. The RT sends or receives data words according to the instruction word, and the BC receives and verifies the correctness of the data words.

[0078] BC sends a confirmation message to the RT, indicating that the data has been successfully received or sent. The RT updates the status word according to the confirmation message, indicating that the data transmission is complete.

[0079] BC updates the polling table, records the status of the RTs for which the transmission has been completed, continues to poll the next RT, and repeats the above process.

[0080] Send the mode code instruction as needed to perform specific operations such as reset, synchronization, self-test, etc.

[0081] Send a shutdown instruction to stop the bus activity and reset all RTs.

[0082] The data packet is decoded bit by bit, ensuring the accuracy and reliability of the data transmission.

[0083] Command word:

[0084] Bits 1-3: Synchronization header (110)

[0085] Bits 4-8: Remote terminal address (5 bits)

[0086] Bit 9: T / R (1 bit; 1 means transmit, 0 means receive)

[0087] Bits 10-14: Sub-address (5 bits)

[0088] Bits 15-19: Data word count or mode code (5 bits)

[0089] Bit 20: Parity bit (1 bit; used for parity check)

[0090] Data word:

[0091] Bits 1-3: Synchronization header (3 bits, 110)

[0092] Bits 4-19: Valid data (16 bits)

[0093] Bit 20: Parity bit (1 bit; used for parity check)

[0094] Status word:

[0095] Bits 1-3: Synchronization header (110)

[0096] Bits 4-8: Remote terminal address (5 bits)

[0097] Bit 9: Message error (1 bit)

[0098] Bit 10: Measurement segment (1 bit)

[0099] Bit 11: Service request (1 bit)

[0100] Bits 12-14: Reserved (3 bits)

[0101] Bit 15: Broadcast instruction (1 bit)

[0102] Bit 16: Busy waiting (1 bit)

[0103] Bit 17: Subsystem flag (1 bit)

[0104] Bit 18: Master station bus control acceptance (1 bit)

[0105] Bit 19: Terminal flag (1 bit)

[0106] Bit 20: Parity check (1 bit)

[0107] Import polling table data packet: The polling table quantity packet is composed of the following several data packets bit by bit: 0xFF, 0xA0, message quantity, 0xFE, 0xA0 Message packet 1:

[0108] Packet header: 0xFF, 0xA1

[0109] RT address: RT address of message 1

[0110] Direction: Direction of message 1

[0111] Sub-address: Sub-address of message 1

[0112] Data length: Data length of message 1

[0113] Period: Period of message 1

[0114] Packet tail: 0xFE, 0xA1

[0115] Message packet 2:

[0116] Packet header: 0xFF, 0xA2

[0117] RT address: RT address of message 2

[0118] Direction: Direction of message 2

[0119] Sub-address: Sub-address of message 2

[0120] Data length: Data length of message 2

[0121] Period: Period of message 2

[0122] Packet tail: 0xFE, 0xA2

[0123] And so on, starting from A1 and accumulating

[0124] Message status data packet:

[0125] Packet header (2 bits): 0xFF, 0xB0;

[0126] Total number of messages: (this bit is empty, and the host computer processes it by itself);

[0127] Number of errors (1 bit): 0x00 or 0x01, (0 means no, 1 means yes, and the host computer message accumulates by itself);

[0128] Number of timeouts (1 bit): 0x00 or 0x01 (0 means no, 1 means yes, and the host computer accumulates by itself);

[0129] Bus load (1 bit): (number of RT responses);

[0130] Packet tail (2 bits): 0xFE, 0xB0;

[0131] Message log data packet:

[0132] Packet header (2 bits): 0xFF, 0xB1;

[0133] Time: (printed by the host computer itself);

[0134] Data 1 (1 bit): Hexadecimal of the synchronization header (converted from 3-bit binary number);

[0135] Data 2 (1 bit): (0x00 - 0xFF) (8-bit binary number, maximum is 0xFF, compressed in the order of bits from 4 to 11);

[0136] Data 3 (1 bit): (0x00 - 0xFF) (8-bit binary number, maximum is 0xFF, compressed in the order of bits from 12 to 19);

[0137] Data 4 (1 bit): Odd parity check (converted from 1-bit binary number to hexadecimal);

[0138] Packet tail (2 bits): 0xFE, 0xB1;

[0139] Protocol toolbox data packet:

[0140] Packet header (2 bits): 0xFF, 0xC0;

[0141] RT address (1 bit): User-defined, specifying the address of the target RT (0 - 30);

[0142] Sub-address / Mode field (1 bit): Specifying the sub-address of the RT or enabling a certain mode code;

[0143] Data word count / Mode code field (1 bit): Specifying the number of data words that the RT should send or receive, or specifying a certain mode code;

[0144] Odd parity bit: 0x00 or 0x01 for detecting transmission errors;

[0145] Trailer (2 digits): 0xFE, 0xC0;

[0146] Hardware response: 0xFF, 0xFF, 0 or 1, 0xFE, 0xFE; (0: failure; 1: success) (This item has not been added to the host computer yet).

[0147] The bus controller module is signal-connected to the transmitter module and the receiver module respectively through a standard communication interface. This communication interface uses optocoupler components to achieve the electrical isolation function, and a low-pass filter is constructed by setting passive components such as capacitors and inductors in the interface circuit to block high-frequency noise and achieve the signal buffering function. Based on the photoelectric conversion principle, the optocoupler components form a physical isolation barrier between the input and output ends, effectively preventing the interference caused by electrical connection from being conducted between modules, ensuring that the bus controller module, the transmitter module and the receiver module operate independently of each other without interference. At the same time, the low-pass filter composed of capacitors and inductors shapes the transmitted signal, filters out high-frequency interference components such as glitches and spikes in the signal, making the signal transmitted to each module smoother and more stable, thereby ensuring the accuracy and reliability of data interaction.

[0148] The receive rate adaptive module is embedded in the bus controller module and is used to adjust the output signal frequency in real time according to the actual clock through dynamic PLL reconfiguration technology. It uses the frequency meter state machine to estimate the input clock frequency, the PLL dynamic reconfiguration function to adjust the PLL parameters, the finite state machine to optimize the clock switching jitter problem, and the FIFO buffer to perform asynchronous cross-frequency data processing to reduce the probability of metastability.

[0149] The multi-period synchronous frequency measurement method is used to estimate the input clock frequency. This method reduces the measurement error by counting multiple clock cycles and improves the accuracy of frequency estimation. In each measurement period, the frequency meter state machine counts the input clock signal and calculates the frequency of the input clock based on the counting result, thereby providing an accurate basis for subsequent adjustment of the phase-locked loop (PLL) parameters.

[0150] The PLL parameters are adjusted based on an adaptive algorithm. This adaptive algorithm dynamically calculates appropriate PLL parameters according to the input clock frequency estimated by the frequency meter state machine and the preset output frequency requirements. Moreover, this function has a feedback adjustment mechanism. After adjusting the PLL parameters, it will monitor the output signal frequency in real time and fine-tune the parameters according to the monitoring results, so as to ensure that the output signal frequency can quickly and accurately track the change of the input clock frequency and achieve adaptive adjustment to different input clock conditions.

[0151] The state prediction and compensation technology is adopted to optimize the jitter problem generated during clock switching. Before clock switching, the finite state machine predicts the possible jitter situation during clock switching based on the current clock state and historical data, and calculates the corresponding compensation value in advance. During clock switching, the finite state machine adjusts the output signal in real time according to the calculated compensation value, thereby effectively reducing the jitter during clock switching and ensuring the stability of the signal.

[0152] Adopting a dual-port design with asynchronous read and write functions, it can efficiently transfer data between different clock domains. At the same time, a data verification and error correction mechanism is set inside the FIFO buffer. When an error occurs during data transmission, it can automatically perform error correction processing, further reducing the probability of metastability and ensuring reliable data transmission.

[0153] When specifically used: First, write a frequency counter state machine to estimate the input clock frequency.

[0154]

[0155] Among them, N is the number of counts, clc_fx is the frequency of the signal to be measured, sys_clk is the reference clock frequency, and cnt is the number of counts. Therefore, the measurement error E is

[0156]

[0157] Use the MegaWizard tool in the Quartus software to generate a Phase-Locked Loop (PLL) IP core. By pre-storing multiple groups of specific frequency parameters (1MHz, 2MHz, and 4MHz), it can provide configuration options for subsequent dynamic frequency adjustment.

[0158] The dynamic adjustment of the clock frequency is achieved through the Dynamic Reconfiguration Port (DRP) function of the PLL. During actual operation, this module first accurately calculates the deviation value between the current clock frequency and the preset target frequency based on the measured real-time data. Based on this deviation value, the module can intelligently make decisions and determine new PLL parameters, which mainly include key indicators such as the multiplication factor or division factor. In this way, the PLL can flexibly and accurately generate the received frequency that meets the expected requirements according to different input frequency conditions.

[0159] To further optimize the frequency adaptation process, a Finite State Machine (FSM) is used in the frequency adaptation module. In the critical link of clock switching, the finite state machine can effectively handle the possible clock jitter problem and can perform targeted optimization processing in combination with the actual design details of the circuit.

[0160] Regarding the metastability problem, this module adopts a synchronous processing method for asynchronous signals to ensure the stability and reliability of the signals; in the design of the reset circuit, the asynchronous reset and synchronous release method is adopted to avoid the unstable factors that may be caused by the reset operation. A First In First Out (FIFO) buffer is used to process cross-frequency data. When the data stream is transmitted from one clock domain to another clock domain, the FIFO serves as an intermediate buffer unit. By buffering the data with dual clocks, the probability of metastability occurrence can be significantly reduced, thus ensuring the stable transmission of data and the overall performance of the system.

[0161] This embodiment uses differential signals for data transmission, that is, the potential difference between two signal lines is used to represent the data "1" and "0". This method has strong anti-interference ability, can reduce the influence of external electromagnetic interference on data transmission, and improve the stability and accuracy of signal transmission.

[0162] The transmission module of this embodiment supports the transformer coupling method. This method can achieve electrical isolation, protect the bus device from the impact of excessive voltage or current, and at the same time help reduce common-mode interference, improving the reliability and safety of the system.

[0163] During use, the data transmission rate supports a minimum of 1 Mbps. The transmission module can accurately send data to the bus within the specified time to meet the system's requirements for data transmission speed. It has a low transmission delay to ensure that data can be transmitted from the sending end to the receiving end in a timely manner. The electrical parameters of some modules are adjustable, and users can adjust and set the working parameters of the module according to specific application requirements to adapt to different application scenarios and system requirements.

[0164] The receiving module adopts level adaptation in the transformer coupling mode to ensure the accuracy and stability of signals during transmission. It supports the 1Mbps transmission rate specified by the 1553B bus, ensuring that data transmitted on the bus can be received in a timely manner without data loss or receiving errors caused by rate mismatches. It has a low receiving delay and can quickly respond to data receiving requests on the bus within the specified time, ensuring the real-time nature of data and meeting the application requirements with high real-time requirements. It has good anti-electromagnetic interference ability and can work normally in a complex electromagnetic environment, ensuring the stability and reliability of data transmission. It has high stability and reliability and can maintain stable performance during long-term operation, reducing the probability of faults and errors.

[0165] The technical features of the bus controller module mainly include the following aspects:

[0166] 1. It has increased the transmission rate and the level elevation rate, meeting the requirements of high-speed communication.

[0167] 2. It has solved the timing alignment problem, ensuring the correct transmission of data.

[0168] 3. It provides high-reliability communication guarantee and supports dual-redundant bus connection.

[0169] 4. It has realized the real-time monitoring function, visually presenting the bus status and signal quality.

[0170] 5. It has integrated the serial communication function, facilitating the interaction with external devices.

[0171] The receiving rate adaptive module has the adaptive ability and can automatically adjust according to the change of the external clock frequency. It ensures that the output frequency is always stable, meeting the preset design requirements. Through real-time monitoring and adjustment, it reduces errors and instability caused by frequency fluctuations. It enhances the reliability and stability of the system under various working conditions. Without reprogramming the FPGA, the working frequency can be conveniently changed. It saves the time and resources required for reprogramming and improves the flexibility of the system. It supports quick switching under different working modes or application scenarios. It provides higher flexibility and adaptability for the system, meeting diverse application requirements. It uses a finite state machine to optimize the jitter problem during clock switching. It processes the reset circuit through asynchronous reset and synchronous release, reducing the occurrence of metastability. It uses a FIFO for asynchronous cross-frequency data processing to ensure the stable transmission of data between different clock domains and improve the accuracy of data transmission.

[0172] Generally speaking, this embodiment has:

[0173] 1. It adopts a modular circuit design, facilitating fault location.

[0174] 2. The electrical parameters can be adjusted according to different functional requirements.

[0175] 3. Domestic electrical components are used to reduce the manufacturing cost.

[0176] 4. A brand-new serial port configuration 1553B bus controller module is proposed, which realizes functions such as parameter setting, status switching, error checking, and waveform monitoring.

[0177] 5. A new serial port protocol is specified, which has the characteristics of high efficiency and strong expandability, and has a certain coverage and error correction ability.

[0178] 6. The adaptive reception frequency is realized, which can flexibly adapt to and adjust the reception frequency. Without reprogramming the FPGA, the working frequency can be conveniently changed, saving the time and resources required for reprogramming; it supports quick switching in different working modes or application scenarios, providing higher flexibility and adaptability for the system and meeting diverse application requirements.

[0179] The above are only embodiments of the present invention. The invention is not limited to the fields involved in this embodiment. Common knowledge such as the specific structures and characteristics known in the art are not described in detail here. Those of ordinary skill in the art know all the common technical knowledge in the technical field to which the invention belongs before the application date or the priority date, can know all the existing technologies in this field, and have the ability to apply the conventional experimental means before this date. Those of ordinary skill in the art can, under the inspiration given in this application, combine their own abilities to improve and implement this solution. Some typical well-known structures or well-known methods should not be an obstacle for those of ordinary skill in the art to implement this application. It should be noted that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can still be made, and these should also be regarded as the protection scope of the present invention, which will not affect the implementation effect of the present invention and the practicality of the patent. The protection scope required by this application should be based on the content of its claims, and the specific implementation manners described in the specification can be used to interpret the content of the claims.

Claims

1. A 1553B bus transceiver device implemented by discrete components, characterized in that, Including: A transmitter module, which is used to receive a control digital signal, and after sequentially performing level conversion, linear integration, and amplification processing on it, convert it into a differential signal for output; A receiver module, which is used to receive an input signal, and after performing level adjustment and voltage comparison on the input signal, output a differential voltage signal; A bus controller module, which is respectively signal-connected to the transmitter module and the receiver module, and is used to execute work processes including controller initialization, resetting a remote terminal, sending a polling instruction, data transmission, and confirmation message sending, so as to realize the serial port configuration of the 1553B bus; A receive rate adaptive module, which is embedded in the bus controller module, and is used to adjust the output signal frequency in real time according to the actual clock through dynamic PLL reconfiguration technology, estimate the input clock frequency by using a frequency meter state machine, adjust the PLL parameters through the PLL dynamic reconfiguration function, optimize the clock switching jitter problem through a finite state machine, and perform asynchronous cross-frequency data processing through a FIFO buffer to reduce the probability of metastability occurrence.

2. The discrete-component-implemented 1553B bus transceiver device according to claim 1, wherein The transmitter module specifically includes: A control signal input unit, which is used to receive a control digital signal, and convert the control digital signal into a level signal that can be processed by an operational amplifier unit through a level converter; A linear integration unit, which is connected to the control signal input unit, and is used to perform linear integration processing on the level signal after level conversion to suppress the high-frequency noise therein; An operational amplifier unit, which includes an integration module and a difference module, and is used to amplify the level signal after linear integration, and realize the forward and reverse processing of the level signal through a bidirectional integration reference level unit; A differential output unit, which is connected to the operational amplifier unit, and is used to convert the amplified level signal into a differential signal for output, so as to improve the anti-interference ability during signal transmission; An output protection unit, which is connected in parallel with the differential output unit, and is used to prevent the circuit system from being damaged in case of overload or short circuit; An output unit, which provides electrical isolation in a transformer-coupled manner to avoid the influence of terminal faults on the entire bus system; A power supply unit, which provides a stable power supply for the transmitter module, uses a ±5V dual power supply to ensure that there is enough current and voltage to maintain the normal operation of the system, and adopts an independent heat dissipation design, including a heat sink and a fan, to ensure power supply stability when operating at high load and generating heat..

3. The discrete-component-implemented 1553B bus transceiver device according to claim 2, wherein, The receiver module specifically includes: A level control unit, which is used to adjust the level of the input signal so that the level of the input signal meets the requirements of subsequent processing; A voltage comparison unit, which includes two comparators, and is used to receive the output signal adjusted by the level control unit, perform voltage comparison on the signal, and output a differential voltage signal to realize further processing and conversion of the input signal; Among them, the receiver module adopts a discrete component design, and the constituent units are connected in a detachable manner.

4. The 1553B bus transceiver device implemented by discrete components according to claim 3, wherein The software design of the bus controller module adopts a modular design and is built based on the PySide6 framework. It includes a bus configuration module, a message management module, a real-time monitoring module, and a serial communication module. The bus configuration module is used to initialize the parameters of the 1553B bus; the message management module is used to organize and schedule the messages sent and received; the real-time monitoring module is used to monitor the working status of the bus in real time; The serial communication module is used to implement serial communication with external devices.

5. The discrete component-implemented 1553B bus transceiver device according to claim 4, wherein The working process of the bus controller module includes the following steps: Controller initialization: Preset internal registers and parameters; Reset remote terminals: Send instructions to make all remote terminals return to the initial state; Periodic polling: Periodically send polling instructions to query the status and data requirements of each remote terminal; Data transmission: Transmit data among the transmitter module, receiver module, and remote terminals according to requirements; Confirm message sending: Verify the completion of data transmission and feedback the results.

6. The discrete-component-implemented 1553B bus transceiver device according to claim 5, wherein The bus controller module is signal-connected to the transmitter module and receiver module respectively through a standard communication interface. This communication interface uses optocoupler components to achieve electrical isolation function, and a low-pass filter is constructed by setting capacitive and inductive passive components in the interface circuit to block high-frequency noise and achieve signal buffering function; The optocoupler components are based on the principle of photoelectric conversion to form a physical isolation barrier between the input and output ends.

7. The discrete-component-implemented 1553B bus transceiver device according to claim 6, characterized in that, The receive rate adaptive module uses Quartus software and adopts Verilog language to implement corresponding functions; The frequency counter state machine in the receive rate adaptive module uses the multi-cycle synchronous frequency measurement method to reduce measurement errors by counting multiple clock cycles. In each measurement cycle, the frequency counter state machine counts the input clock signal and calculates the frequency of the input clock based on the counting result, thereby providing an accurate basis for subsequent adjustment of the PLL parameters.

8. The discrete-component-implemented 1553B bus transceiver device according to claim 7, wherein The PLL dynamic reconfiguration function of the receive rate adaptive module adjusts the PLL parameters based on an adaptive algorithm; The adaptive algorithm dynamically calculates appropriate PLL parameters according to the input clock frequency estimated by the frequency counter state machine and the preset output frequency requirement; Moreover, it has a feedback adjustment mechanism. After adjusting the PLL parameters, it will monitor the output signal frequency in real time and fine-tune the parameters according to the monitoring results, so as to ensure that the output signal frequency can quickly and accurately track the change of the input clock frequency and achieve adaptive adjustment under different input clock conditions.

9. The discrete component-implemented 1553B bus transceiver device according to claim 8, wherein The finite state machine in the receive rate adaptive module uses state prediction and compensation technology to optimize the jitter problem generated during clock switching; Before clock switching, the finite state machine predicts the possible jitter situation generated by clock switching based on the current clock state and historical data, and calculates the corresponding compensation value in advance; During clock switching, the finite state machine adjusts the output signal in real time according to the calculated compensation value; The first-in-first-out buffer in the receive rate adaptation module adopts a dual-port design, which is used for efficiently transmitting data between different clock domains and automatically performing error correction when an error occurs during the data transmission process.

10. A method for implementing a 1553B bus transceiver using discrete components, characterized in that, The device described in any one of claims 1-9 is adopted.

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