Storage unit, memory and access method thereof, and electronic equipment

Abstract

A memory cell, a memory and a manufacturing method thereof, and an electronic device, the memory may include: a vertically stacked multi-layer memory array, the memory array including a plurality of memory cells distributed in an array, the memory further including a plurality of second common word lines corresponding to rows of the multi-layer memory array, and a plurality of second common word lines corresponding to rows of the multi-layer memory array, a plurality of first common word lines corresponding to columns of the multilayer memory array; the first gate electrodes of the storage units are connected to the first common word lines corresponding to the columns where the storage units are located, and the second gate electrodes of the storage units are connected to the second common word lines corresponding to the rows where the storage units are located. According to the scheme provided by the embodiment of the invention, the memory units at the same positions of different layers can be selected through the first common word line and the second common word line, the number of word line drivers is reduced, gating transistors can be omitted, the process is simplified, the cost is reduced, and the control logic is simple.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance. In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the needs of current products. In a memory device, in order to enable the selection of a memory cell, it is usually necessary to implement it through a relatively complex driving circuit, which is not conducive to the integration of the device. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] This application provides a memory cell, a memory, an access method thereof, and an electronic device, which simplify the process and reduce the cost.

[0005] This application provides a memory cell, including a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second gate electrode, a third electrode, and a fourth electrode. The first gate electrode of the first transistor is connected to a first word line, the first electrode is connected to one end of the capacitor, the second electrode is connected to the third electrode of the second transistor, the fourth electrode of the second transistor is connected to a bit line, the second gate electrode of the second transistor is connected to a second word line, the other end of the capacitor is connected to a preset voltage terminal, and the first word line and the second word line are connected to different signal terminals.

[0006] Embodiments of the present disclosure provide a memory, including:

[0007] A multi-layer memory array stacked in a third direction perpendicular to the substrate, each layer of the memory array including a plurality of memory cells arrayed in a first direction parallel to the substrate and in a second direction parallel to the substrate, the memory further including a plurality of second common word lines corresponding to rows of the multi-layer memory array, and a plurality of first common word lines corresponding to columns of the multi-layer memory array; the same row of the multi-layer memory array corresponds to the same second common word line, and the same column of the multi-layer memory array corresponds to the same first common word line; a first gate electrode of the memory cell is connected to the first common word line corresponding to the column where the memory cell is located, and a second gate electrode of the memory cell is connected to the second common word line corresponding to the row where the memory cell is located.

[0008] In some embodiments, each layer of the memory array further includes a plurality of first word lines extending in the third direction, and first gate electrodes of memory cells in the same row and the same column of different layers are connected to the same first word line, first gate electrodes of different memory cells in the same layer are connected to different first word lines, and a plurality of first word lines in the same column are connected to the same first common word line.

[0009] In some embodiments, each layer of the memory array further includes a plurality of second word lines extending in the third direction, and second gate electrodes of memory cells in the same row and the same column of different layers are connected to the same second word line, second gate electrodes of different memory cells in the same layer are connected to different second word lines, and a plurality of second word lines in the same row are connected to the same second common word line.

[0010] In some embodiments, each layer of the memory array further includes: a plurality of bit lines extending in the second direction; the memory further includes: a plurality of common bit lines; each bit line connects memory cells in the same column of the layer where the bit line is located, bit lines in the same layer are connected to the same common bit line, and bit lines in different layers are connected to different common bit lines.

[0011] In some embodiments, each bit line is connected to the common bit line through a gating sub-circuit, the gating sub-circuit is further connected to a gating control line, and a plurality of gating sub-circuits respectively connected to a plurality of bit lines in the same column of different layers are connected to the same gating control line, and the gating sub-circuit is configured to: connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0012] In some embodiments, the gating control line connected to a plurality of gating sub-circuits respectively connected to a plurality of bit lines in the j-th column is connected to the first common word line corresponding to the memory cells in the j-th column.

[0013] Embodiments of the present disclosure provide a method for accessing a memory, including:

[0014] In the data read / write phase, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word lines other than the target row; an activation signal is loaded on the first common word line corresponding to the target column, and a non-activation signal is loaded on the first common word lines other than the target column.

[0015] In some embodiments, the method further includes, in the data read / write phase, loading an enabling level signal on the strobe control line connected to the bit line of the target column, and loading a disabling level signal on the strobe control lines connected to the bit lines other than the target column.

[0016] In some embodiments, the method further includes, in the pre-charge phase, for each storage unit, loading a non-activation signal on at least one of the first word line and the second word line connected to the storage unit, and loading an enabling level signal on all the strobe control lines.

[0017] An embodiment of the present disclosure provides a memory, including: a multi-layer storage array stacked along a third direction perpendicular to the substrate, and a plurality of first common word lines corresponding to the multi-layer storage arrays one by one, wherein the storage array includes a plurality of storage units arranged in an array along a first direction parallel to the substrate and a second direction parallel to the substrate, and the memory further includes a plurality of second common word lines corresponding to the rows of the multi-layer storage arrays, the same row of the multi-layer storage arrays corresponds to the same second common word line, the first gate electrode of the first transistor of the storage units in the same layer is connected to the first common word line corresponding to the layer, and the second gate electrode of the second transistor of the storage units in the same row distributed along the first direction of the multi-layers is connected to the second common word line corresponding to the row.

[0018] In some embodiments, each layer of the storage array further includes a plurality of first word lines extending along the second direction, the first gate electrodes of the storage units in the same column of the same layer are connected to the same first word line, the first gate electrodes of the storage units in different columns of the same layer are connected to different first word lines, and the plurality of first word lines in the same layer are connected to the same first common word line.

[0019] In some embodiments, each layer of the storage array further includes a plurality of first word lines extending along the first direction, the first gate electrodes of the storage units in the same row of the same layer are connected to the same first word line, the first gate electrodes of the storage units in different rows of the same layer are connected to different first word lines, and the plurality of first word lines in the same layer are connected to the same first common word line.

[0020] In some embodiments, each layer of the memory array further includes a plurality of second word lines extending along the first direction. The second gate electrodes of the memory cells in the same row of the same layer are connected to the same second word line, and the second gate electrodes of the memory cells in different rows of the same layer are connected to different second word lines. The plurality of second word lines in the same row of different layers are connected to the same second common word line.

[0021] In some embodiments, the memory further includes: a plurality of bit lines extending along the third direction and a plurality of common bit lines extending along the second direction. The memory cells at the same position of multiple layers of the memory array are connected to the same bit line, and the bit lines in the same column distributed along the second direction are connected to the same common bit line, and the bit lines in different columns are connected to different common bit lines.

[0022] In some embodiments, each bit line is connected to the common bit line through a gating sub-circuit, and the gating sub-circuit is also connected to a gating control line. The plurality of first gating sub-circuits respectively connected to the plurality of bit lines distributed along the first direction are connected to the same gating control line. The gating sub-circuit is configured to: connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0023] In some embodiments, the gating control lines connected to the plurality of gating sub-circuits respectively connected to the bit lines of the i-th row are connected to the second common word line corresponding to the memory cells of the i-th row.

[0024] An embodiment of the present disclosure provides a method for accessing a memory, including:

[0025] In the data reading and writing stage, according to the target layer and the target row where the memory cell to be operated is located, an activation signal is loaded on the first common word line corresponding to the target layer, and a non-activation signal is loaded on the first common word line corresponding to the non-target layer; an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word line corresponding to the non-target row.

[0026] In some embodiments, the method further includes, in the data reading and writing stage, an enabling level signal is loaded on the gating control line connected to the bit line of the target row, and a disabling level signal is loaded on the gating control line connected to the bit line of the non-target row.

[0027] In some embodiments, the method further includes, in the pre-charge stage, a non-activation signal is loaded on at least one of the first word line and the second word line connected to each memory cell, and an enabling level signal is loaded on all the gating control lines.

[0028] An embodiment of the present disclosure provides an electronic device, including the memory according to any one of the above embodiments.

[0029] Embodiments of the present application include a storage unit, a memory, a method for accessing the memory, and an electronic device. The memory includes: a multi-layer storage array stacked in a third direction perpendicular to the substrate. Each layer of the storage array includes a plurality of storage units arrayed in a first direction parallel to the substrate and a second direction parallel to the substrate. The memory further includes a plurality of second common word lines corresponding to the rows of the multi-layer storage array, and a plurality of first common word lines corresponding to the columns of the multi-layer storage array; the same row of the multi-layer storage array corresponds to the same second common word line, and the same column of the multi-layer storage array corresponds to the same first common word line; a first gate electrode of the storage unit is connected to the first common word line corresponding to the column where the storage unit is located, and a second gate electrode of the storage unit is connected to the second common word line corresponding to the row where the storage unit is located. The solution provided by this embodiment can select storage units at the same position in different layers through the first common word line and the second common word line, reduce the number of word line drivers, omit the selection transistors, simplify the process, reduce the cost, and have a simple control logic.

[0030] Other features and advantages of the present application will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings.

[0031] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0032] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0033] Figure 1 Schematic diagram of the equivalent circuit of the storage unit provided for some embodiments;

[0034] Figure 2 Schematic diagram of the equivalent circuit of the memory provided for some embodiments;

[0035] Figure 3 Schematic diagram of the equivalent circuit of the memory provided for other embodiments;

[0036] Figure 4 Schematic diagram of the equivalent circuit of the memory provided for still other embodiments. Detailed Embodiments

[0037] The embodiments of the present disclosure will be described in detail below in conjunction with the drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0038] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains.

[0039] The embodiments of this disclosure do not necessarily limit the dimensions shown in the drawings. The shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.

[0040] The ordinal numbers such as "first", "second", "third", etc. in this disclosure are set to avoid confusion of components and do not indicate any order, quantity, or importance.

[0041] In this disclosure, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this disclosure. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the circumstances.

[0042] In this disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0043] In this disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region where current mainly flows.

[0044] In this disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this disclosure, the "source electrode" and "drain electrode" can swap with each other.

[0045] In the present disclosure, "connection" includes a case where constituent elements are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0046] In the present disclosure, "parallel" means approximately parallel or almost parallel. For example, a state where the angle formed by two straight lines is 10° or less above -10°, and thus, it also includes a state where the angle is 5° or less above -5°. In addition, "perpendicular" means approximately perpendicular. For example, a state where the angle formed by two straight lines is 100° or less above 80°, and thus, it also includes a state where the angle is 95° or less above 85°.

[0047] In an embodiment of the present disclosure, two transistors are connected in series in a storage unit, and the gate electrodes of the two transistors are respectively connected to different word lines. The selection of a group of storage units is directly achieved through two word lines, so that a selection transistor for the word line can be omitted, and the driving method of the word line is simplified, thereby simplifying the driving circuit and being more conducive to integration.

[0048] Figure 1 Schematic diagram of an equivalent circuit of a storage unit provided for some embodiments. As Figure 1As shown in the figure, the storage unit provided in this embodiment includes a first transistor T1, a second transistor T2, and a capacitor C. The first transistor T1 includes a first gate electrode, a first electrode, and a second electrode. The second transistor T2 includes a second gate electrode, a third electrode, and a fourth electrode (here, the second gate electrode is only for distinguishing from the first gate electrode. The second transistor T2 may have only one gate electrode. The third electrode and the fourth electrode are only for distinguishing from the first electrode and the second electrode. One of the third electrode and the fourth electrode represents the source electrode of the second transistor T2, and the other represents the drain electrode of the second transistor T2). Among them, the first gate electrode of the first transistor T1 is connected to the first word line W1, the first electrode is connected to the first end of the capacitor C, the second electrode is connected to the third electrode of the second transistor T2, the fourth electrode of the second transistor T2 is connected to the bit line BL, the second gate electrode of the second transistor T2 is connected to the second word line WL2, and the second end of the capacitor C is connected to a preset voltage terminal, such as a ground terminal. The first end of the capacitor C serves as a storage node to store data. The first word line WL1 and the second word line WL2 are connected to different signal terminals, that is, the first word line WL1 and the second word line WL2 are independently controlled. The storage unit can be applied to a 3D stacked 2T1C memory so as to enable the selection of a group of storage units through the first word line WL1 and the second word line WL2 without the need to select a transistor. The solution provided in this embodiment can simplify the driving circuit and provide support for realizing a 3D stacked 2T1C memory with a simpler process.

[0049] In some embodiments, the first transistor T1 and the second transistor T2 can be N-type transistors or P-type transistors.

[0050] Taking the first transistor T1 and the second transistor T2 as N-type transistors as an example. When high-level signals are applied to both the first word line WL1 and the second word line WL2, that is, when a high-level signal is applied to the first gate electrode of the first transistor T1 and a high-level signal is applied to the second gate electrode of the second transistor T2, the first transistor T1 is turned on, the second transistor T2 is turned on, and the data stored at the first end of the capacitor C is loaded onto the bit line BL through the first transistor T1 and the second transistor T2, realizing the access to the storage unit. When at least one of the first word line WL1 and the second word line WL2 is applied with a low-level signal, that is, when at least one of the first gate electrode of the first transistor T1 and the second gate electrode of the second transistor T2 is applied with a low level, at least one of the first transistor T1 and the second transistor T2 is turned off, so that the storage unit cannot be accessed.

[0051] When the first transistor T1 and the second transistor T2 are P-type transistors, when the first word line WL1 and the second word line WL2 are both loaded with low-level signals, the first transistor T1 and the second transistor T2 are turned on. When at least one of the first word line WL1 and the second word line WL2 is loaded with a high-level signal, at least one of the first transistor T1 and the second transistor T2 is turned off, so that the memory cell cannot be accessed.

[0052] Figure 2 Schematic diagram of the equivalent circuit of the memory provided for some embodiments. As Figure 2 shown, the memory may include: a multi-layer stacked memory array (k layers, memory arrays L1 to Lk), and the multi-layer memory arrays are stacked along the third direction z. The memory may further include: a plurality of first word lines WL1 extending along the third direction z, and a plurality of second word lines WL2 extending along the third direction z. The plurality of first word lines WL1 are arranged in an array along the first direction x and the second direction y. The plurality of second word lines WL2 are arranged in an array along the first direction x and the second direction y. Each layer of the memory array may include a plurality of memory cells 100 respectively arranged in an array along the first direction x and the second direction y, and a plurality of bit lines BL extending along the second direction y. The plurality of bit lines BL in each layer are spaced apart along the first direction x. The structure of the memory cell 100 refers to Figure 1 , which will not be elaborated here.

[0053] The first direction x and the second direction y are parallel to the substrate ( Figure 2 the substrate is not shown in the figure), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first direction x is also referred to as the row direction, and the second direction y is also referred to as the column direction.

[0054] Each layer of the memory array may include n rows and m columns of memory cells 100, and m bit lines BL. Among them, the bit line BL of the j-th column in the r-th layer is BL_j_r, where j ranges from 1 to m, and r ranges from 1 to k.

[0055] The memory may include n rows and m columns of first word lines WL1. The first word line of the i-th row and the j-th column is WL1_i_j, where i ranges from 1 to n and j ranges from 1 to m. The memory may include n rows and m columns of second word lines WL2. The second word line of the i-th row and the j-th column is WL2_i_j, where i ranges from 1 to n and j ranges from 1 to m. Among them, the first gate electrode of the first transistor T1 of the memory cell C_i_j_r in the i-th row, j-th column, and r-th layer is connected to the first word line WL1_i_j, the second gate electrode of the second transistor T2 is connected to the second word line WL2_i_j, and the fourth electrode of the second transistor T2 is connected to the bit line BL_j_r.

[0056] In some embodiments, multiple first word lines WL1 in the same column (i.e., multiple first word lines WL1 distributed along the second direction y) are connected to the same first common word line CWL1. The memory cells in the same column of different layers are connected to the same first common word line CWL1. That is, n first word lines WL1_1_j to WL1_n_j in the j-th column are connected to the j-th first common word line CWL1_j, where j ranges from 1 to m. For example, n first word lines WL1_1_1 to WL1_n_1 in the first column are connected to the first first common word line CWL1_1, and n first word lines WL1_1_m to WL1_n_m in the m-th column are connected to the m-th first common word line CWL1_m. Each first common word line CWL1_j is connected to a first word line driver. Different first common word lines CWL1_j are connected to different first word line drivers. The multiple first word line drivers respectively connected to the multiple first common word lines CWL1_j can be arranged on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto, and the multiple first word line drivers can be arranged on different sides of the memory array.

[0057] In some embodiments, multiple first word lines WL1 in the same column can be connected through a connection line extending along the second direction y provided on the side of the memory array away from the substrate. However, the embodiments of the present disclosure are not limited thereto, and multiple first word lines WL1 in the same column can be connected in other ways.

[0058] In some embodiments, multiple second word lines WL2 in the same row are connected to the same second common word line CWL2. The memory cells in the same row of different layers are connected to the same second common word line CWL2. That is, m second word lines WL2_i_1 to WL2_i_m in the i-th row are connected to the i-th second common word line CWL2_i, where i ranges from 1 to n. The m second word lines WL2_1_1 to WL2_1_m in the first row are connected to the first second common word line CWL2_1, and the m second word lines WL2_n_1 to WL2_n_m in the n-th row are connected to the n-th second common word line CWL2_n. Each second common word line CWL2_i is connected to a second word line driver. The multiple second word line drivers respectively connected to the multiple second common word lines CWL2_i can be arranged on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto, and the multiple second word line drivers can be arranged on different sides of the memory array.

[0059] In some embodiments, multiple second word lines WL2 in the same row can be connected through a connection line extending along the first direction x provided on the side of the memory array away from the substrate. However, the embodiments of the present disclosure are not limited thereto, and multiple second word lines WL2 in the same row can be connected in other ways.

[0060] The memory provided in this embodiment can select a vertical column of memory cells (i.e., a group of memory cells at the same position in different layers) by activating a first common word line and a second common word line. For example, when the target row is the p-th row and the target column is the q-th column, an activation signal can be loaded on the second common word line CWL2_p and the first common word line CWL1_q, so as to select k memory cells at the p-th row and q-th column from the first layer to the k-th layer. The solution provided in this embodiment can select a vertical column of memory cells without setting a selection transistor for the first common word line and the second common word line. Compared with the solution of setting selection transistors for the first common word line and the second common word line, the process steps of manufacturing the selection transistors can be omitted, and the number of word line drivers is not large. The number of the first word line drivers is m, and the number of the second word line drivers is n. Moreover, as the number of stacked layers increases, the number of word line drivers remains unchanged. In addition, the circuit control logic is simple.

[0061] In some embodiments, the memory may further include multiple common bit lines CBL. Multiple bit lines BL in the same layer can be connected to the same common bit line CBL, and the bit lines BL in different layers are connected to different common bit lines CBL. For example, multiple bit lines BL in the first layer are connected to the first common bit line CBL1, multiple bit lines BL in the second layer are connected to the second common bit line CBL2, and multiple bit lines BL in the k-th layer are connected to the k-th common bit line CBLk. One common bit line CBL can be connected to a sense amplifier SA. The solution provided in this embodiment can greatly reduce the number of sense amplifiers SA by using the common bit line CBL compared with the solution where each bit line BL is connected to a sense amplifier SA. Adjacent memory arrays can share the same SA. However, the embodiments of the present disclosure are not limited thereto, and each bit line BL can be connected to a sense amplifier SA.

[0062] In some embodiments, each bit line BL can be connected to the common bit line CBL through a gating sub-circuit 10. The gating sub-circuit 10 can also be connected to a gating control line, and the gating sub-circuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (i.e., electrically connect or disconnect the bit line BL and the common bit line CBL). That is, under the control of the gating control line, the signal of the common bit line CBL is loaded or not loaded onto the bit line BL. The solution provided in this embodiment can reduce the capacitive reactance of the CBL, reduce power consumption, and improve the reading speed by setting the gating sub-circuit. However, the embodiments of the present disclosure are not limited thereto. In another exemplary embodiment, the gating sub-circuit 10 may not be provided.

[0063] In some embodiments, the gating sub-circuits 10 connected to the bit lines BL in the same column of different layers may be connected to the same gating control line, and the gating sub-circuits connected to the bit lines BL in different columns of different layers are connected to different gating control lines. The m columns of bit lines BL are respectively connected to m different gating control lines. For example, as Figure 2 shown, the gating sub-circuits 10 connected to the bit lines BL in the first column are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the bit lines BL in the second column are all connected to the second gating control line S_2, and so on. The gating sub-circuits 10 connected to the bit lines BL in the m-th column are all connected to the m-th gating control line S_m. Thus, a bit line BL can be selected through the common bit line CBL and the gating control line. For example, when the r-th common bit line CBLr loads an activation signal (the remaining common bit lines CBL load non-activation signals), and the j-th gating control line S_j gates the corresponding gating sub-circuit 10 (the remaining gating control lines do not gate the corresponding gating sub-circuits 10), then the bit line BL_j_r in the r-th layer and the j-th column is loaded with an activation signal. Or, the bit lines BL in the same column of different layers can be selected through the gating control line.

[0064] In some embodiments, only the bit lines BL in the same column of different layers can be gated at the same time, which can reduce the capacitive load of the SA and, moreover, reduce the capacitance of the storage unit.

[0065] In some embodiments, the gating sub-circuit 10 may include a third transistor T3. The third transistor T3 may include a third gate electrode, a fifth electrode, and a sixth electrode. The third gate electrode of the third transistor T3 is connected to the gating control line, the fifth electrode is connected to the bit line BL, and the sixth electrode is connected to the common bit line CBL. The structure of the gating sub-circuit 10 described in this embodiment is only an example and may be other circuits that can achieve gating.

[0066] In some embodiments, the third transistor T3 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The third transistor T3 may be a P-type transistor.

[0067] In some embodiments, when the first common word line CWL1_j corresponding to the storage units in the j-th column of different layers loads an activation signal, the gating control line S_j connected to the gating sub-circuit 10 connected to the bit line BL in the j-th column loads an enabling level signal to connect the gating sub-circuit 10 connected to the bit line BL in the j-th column. When the second common word line CWL2_i corresponding to the i-th row loads an activation signal, at this time, the storage units in the i-th row and the j-th column of different layers are gated, and the storage units in the i-th row and the j-th column can be accessed (read or written) through the bit line BL in the j-th column.

[0068] In some embodiments, the first common word line CWL1_j may be connected to the gating control line S_j to which the gating sub-circuit 10 connected to the bit line BL of the j-th column is connected, where j ranges from 1 to m. That is, the same signal driver may be used to load the same signal onto the first common word line CWL1_j and the gating control line S_j. That is, the activation signal and the turn-on level signal of the gating sub-circuit use the same signal. The solution provided in this embodiment can reduce the number of control lines, and further reduce the control circuit for generating control signals, reduce the device occupation area, and simplify the control logic.

[0069] An embodiment of the present disclosure provides a method for accessing a memory, which is applied to the memory described in any of the above embodiments. The access method may include:

[0070] In the data reading and writing stage, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word line corresponding to a row other than the target row; an activation signal is loaded on the first common word line corresponding to the target column, and a non-activation signal is loaded on the first common word line corresponding to a column other than the target column (at this time, only the first gate electrode and the second gate electrode of the storage unit at the target row and target column of each layer are loaded with the activation signal, so that the first transistor and the second transistor of the storage unit at the target row and target column of each layer can be turned on).

[0071] In some embodiments, the access method may further include: loading a turn-on level signal on the gating control line connected to the bit line of the target column (so that the gating sub-circuit connected to the bit line of the target column is in a connected state), and loading a turn-off level signal on the gating control line connected to the bit line of a column other than the target column (so that the gating sub-circuit connected to the bit line of a column other than the target column is in a turned-off state).

[0072] This embodiment provides a method for accessing a memory. The access to the storage units in a vertical column can be realized through the first common word line, the second common word line, and the gating control line, and the control logic is simple.

[0073] The turn-on level signal is a signal that can make the corresponding gating sub-circuit in a connected state, and the turn-off level signal is a signal that can make the corresponding gating sub-circuit in a turned-off state. The data reading and writing stage may include a data reading stage and a data writing stage.

[0074] In some embodiments, it may further include:

[0075] During the pre-charge stage, a non-activation signal is loaded on all the second common word lines, an activation signal or a non-activation signal is loaded on all the first common word lines, and an enable level signal is loaded on all the strobe control lines. The solution provided in this embodiment can turn off all the first transistors and second transistors, turn on all the strobe sub-circuits, and pre-charge the bit lines.

[0076] In some embodiments, the activation signal loaded on the first word line corresponding to the target column and the enable level signal loaded on the strobe control line connected to the bit line of the target column are the same signal, and the non-activation signal loaded on the first common word line corresponding to the non-target column and the disable level signal loaded on the strobe control line connected to the bit line of the non-target column are the same signal.

[0077] That is, the strobe control line connected to the bit line of the target column and the first common word line corresponding to the target column can be controlled by the same signal, reducing the control signals, making the control simpler, and reducing the signal driver, which is beneficial to reducing the cost and the device area. At this time, the strobe control lines Sj connected to the strobe sub-circuit 10 connected to the first common word line CWL1_j and the bit line BL of the j-th column can be connected together, where j is from 1 to m, and m is the number of columns of the memory cells included in each layer of the memory array.

[0078] In some embodiments, a first control circuit is further provided, and the first control circuit is configured to access the memory according to the above access method. The first control circuit may include drivers for generating control signals to the first common word line, the second common word line, and the strobe control line, etc. The first control circuit and the SA, etc., together implement the access to the memory.

[0079] The working process of the memory is described below through an embodiment. Taking Figure 2 the shown memory as an example, in this embodiment, the memory cell 100 is Figure 1 the 2T1C structure shown, the first transistor T1 and the second transistor T2 are N-type MOS transistors, the third transistor T3 is an N-type MOS transistor, and the strobe control line Sj is connected to the first common word line CWL1_j ( Figure 2 the connection relationship between the strobe control line Sj and the first common word line CWL1_j is not shown in the figure), j is from 1 to m, and the common bit line CBL may also be connected to a pre-charge sub-circuit. The working stages of the memory may include a pre-charge stage, a read data stage, and a data write-back stage, where:

[0080] In the pre-charge stage, low-level signals are loaded onto all the second common word lines CWL2_1 to CWL2_n. These low-level signals are loaded onto the second word line WL2. High-level signals are loaded onto all the first common word lines CWL1_1 to CWL1_m (i.e., the strobe control line S_j is loaded with a high-level signal). At this time, the strobe sub-circuit is turned on, the second transistors T2 of all the memory cells are turned off, the pre-charge sub-circuit is turned on, and a pre-charge voltage of 1 / 2VDD is loaded onto each common bit line CBL. Each common bit line CBL loads the pre-charge voltage onto the bit lines BL in the same layer that it is connected to.

[0081] In the data read stage, the pre-charge sub-circuit is turned off. Taking the data reading of the memory cell 100 in the p-th row and q-th column as an example, among the first common word lines CWL1_1 to CWL1_m, the first common word line CWL1_q corresponding to the q-th column is loaded with a high-level signal, and the remaining first common word lines CWL1_j (where j is from 1 to m and j≠q) are loaded with low-level signals. Among the second common word lines CWL2_1 to CWL2_n, the second common word line CWL2_p corresponding to the p-th row is loaded with a high-level signal, and the remaining CWL2_i (where i is from 1 to n and i≠p) are loaded with low-level signals. Thus, the first transistor T1 and the second transistor T2 of the memory cell 100 in the p-th row and q-th column are turned on, and the first transistor T1 and the second transistor T2 of the remaining memory cells 100 are turned off. The strobe sub-circuit 10 connected to the bit lines of the q-th column is turned on, and the common bit lines CBL1 to CBLk are respectively connected to k bit lines BL of the q-th column, and charge sharing is respectively performed with the storage nodes of k memory cells 100 in the p-th row and q-th column of the first layer to the k-th layer. The sense amplifiers respectively connected to CBL1 to CBLk sense the voltages of CBL1 to CBLk to determine the data stored in the memory cell 100 in the p-th row and q-th column.

[0082] In the data write-back stage, among the first common word lines CWL1_1 to CWL1_m, CWL1_q is loaded with a high-level signal, and the remaining CWL1_j (where j is from 1 to m and j≠q) are loaded with low-level signals. Among the second common word lines CWL2_1 to CWL2_n, CWL2_p is loaded with a high-level signal, and the remaining CWL2_i (where i is from 1 to n and i≠p) are loaded with low-level signals. The common bit lines CBL1 to CBLk are respectively connected to k bit lines BL of the q-th column, and charge sharing is respectively performed with the storage nodes of k memory cells 100 in the p-th row and q-th column of the first layer to the k-th layer to achieve data write-back.

[0083] The solution provided by this embodiment does not require a select transistor to select a storage unit. The first common word line and the second common word line can be used to select a vertical column of storage units. The structure is simple, the control logic is simple, and the same control signal is used to control the select control line and the second common word line of the same column, reducing the number of control signal lines, reducing the required control circuit, and making the control logic simpler.

[0084] Figure 3 Schematic diagram of a memory equivalent circuit provided for some embodiments. As Figure 3 shown, the memory may include: a multi-layer stacked memory array (k layers, memory arrays L1 to Lk), and the multi-layer memory array is stacked along the third direction z. Each layer of the memory array includes a plurality of storage units 100 arrayed along the first direction x and the second direction y, and a plurality of first word lines WL1 extending along the second direction y, and a plurality of second word lines WL2 extending along the first direction x. The structure of the storage unit 100 refers to Figure 1 , which will not be elaborated here. The plurality of first word lines WL1 of each layer are spaced apart along the first direction x, and the plurality of second word lines WL2 of each layer are spaced apart along the second direction y. The memory further includes a plurality of bit lines BL extending along the third direction z, and the plurality of bit lines BL are arrayed along the first direction x and the second direction y. Each layer of the memory array includes n rows and m columns of storage units 100, and includes m first word lines WL1 and n second word lines WL2. Among them, the first word line of the j-th column of the r-th layer is WL1_Cj_r, where j is from 1 to m and r is from 1 to k; the second word line of the i-th row of the r-th layer is WL2_Ri_r, where i is from 1 to n and r is from 1 to k. The memory includes n rows and m columns of bit lines BL, and the bit line of the i-th row and the j-th column is bit line BL_i_j, where i is from 1 to n and j is from 1 to m. Among them, the first gate electrode of the storage unit C_i_j_r of the i-th row, the j-th column, and the r-th layer is connected to the first word line WL1_Cj_r, the second gate electrode is connected to the second word line WL2_Ri_r, and the fourth electrode is connected to the bit line BL_i_j.

[0085] In some embodiments, multiple first word lines WL1 of the same layer are connected to the same first common word line, that is, the m first word lines WL1_C1_r to WL1_Cm_r of the rth layer are connected to the rth first common word line CWL1_r, where r is 1 to k. Each layer of memory cells corresponds to a first common word line, that is, each layer of memory cells is connected to a first common word line. For example, the m first word lines WL1_C1_1 to WL1_Cm_1 of the 1st layer are connected to the 1st first common word line CWL1_1, and the m first word lines WL1_C1_k to WL1_Cm_k of the kth layer are connected to the kth first common word line CWL1_k. Each first common word line CWL1_r is connected to a first word line driver. Different first common word lines CWL1_r are connected to different first word line drivers.

[0086] In some embodiments, the plurality of first word line drivers connected to the plurality of first common word lines CWL1_r may be disposed on the same side of the memory array, but the embodiments of the present disclosure are not limited thereto and may be disposed on different sides as required.

[0087] In some embodiments, the first word lines WL1 in the same layer may be connected by one or two connection lines disposed at the periphery of the memory array and extending along the first direction x. However, the disclosed embodiments are not limited thereto, and the first word lines WL1 in the same layer may be connected by other methods.

[0088] In some embodiments, multiple second word lines WL2 of the same row of different layers are connected to the same second common word line, and storage cells of the same row of different layers correspond to one second common word line (storage cells of the same row of different layers are connected to the same second common word line), that is, k second word lines WL2_Ri_1 to WL2_Ri_k of the i-th row of the 1st to k-th layers are connected to the i-th second common word line CWL2_i, where i is 1 to n. k second word lines WL2_R1_1 to WL2_R1_k of the 1st row of the 1st to k-th layers are connected to the 1st second common word line CWL2_1, and k second word lines WL2_Rn_1 to WL2_Rn_k of the nth row of the 1st to k-th layers are connected to the nth second common word line CWL2_n, where i is 1 to n. Each second common word line CWL2_i is connected to a second word line driver.

[0089] In some embodiments, the second common word line CWL2_i can be connected to the second word line driver on the side of the storage array facing the substrate, but the embodiments of the present disclosure are not limited thereto. The second common word line CWL2_i can be connected to the second word line driver on the side of the storage array facing away from the substrate.

[0090] In some embodiments, multiple second word lines WL2 of the same row in different layers may be connected by one or two connection lines extending along the third direction Z and disposed outside the memory array. However, the embodiments of the present disclosure are not limited thereto, and multiple second word lines WL2 of the same row in different layers may be connected by other means.

[0091] The memory provided in this embodiment can select a row of memory cells in one layer by activating one first common word line and one second common word line. For example, when the target layer is the p-th layer and the target row is the q-th row, an activation signal can be loaded on the second common word line CWL2_q and the first common word line CWL1_p, so as to select m memory cells in the i-th row of the r-th layer. The solution provided in this embodiment can select a row of memory cells without setting a select transistor for the first common word line and the second common word line. Compared with the solution of setting a select transistor for the first common word line and the second common word line, the process steps of manufacturing the select transistor can be omitted, and the number of word line drivers is not large. The number of the first word line drivers is k, and the number of the second word line drivers is n. Moreover, as the number of stacked layers increases, the increased quantity is very small (one first word line driver corresponds to each layer). In addition, the circuit control logic is simple.

[0092] In some embodiments, the memory may further include multiple common bit lines CBL. Multiple bit lines BL in the same column distributed along the second direction y may be connected to the same common bit line CBL, and bit lines BL in different columns are connected to different common bit lines CBL. For example, the bit lines BL in the first column are connected to the first common bit line CBL1, the bit lines BL in the second column are connected to the second common bit line CBL2, and the bit lines BL in the m-th column are connected to the m-th common bit line CBLm. One common bit line CBL may be connected to one sense amplifier SA. Compared with the solution in which each bit line BL is connected to one sense amplifier SA, the solution provided in this embodiment can greatly reduce the number of sense amplifiers SA by using the common bit line CBL. Adjacent memory arrays may share the same SA.

[0093] In some embodiments, the common bit line CBL may be disposed on the side of the memory array away from the substrate, as Figure 3 shown, or on the side of the memory array facing the substrate. When the memory includes multiple stacked memory arrays, the common bit line CBL may be disposed on the side of the stacked memory arrays facing the substrate or on the side away from the substrate.

[0094] In some embodiments, each bit line BL may be connected to the common bit line CBL through a gating sub-circuit 10. The gating sub-circuit 10 may also be connected to a gating control line, and the gating sub-circuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (i.e., electrically connect the bit line BL and the common bit line CBL, or disconnect them). That is, under the control of the gating control line, the signal of the common bit line CBL is loaded or not loaded onto the bit line BL. The solution provided in this embodiment sets a gating sub-circuit, which can only gate the target bit line to be read and turn off the non-target bit lines, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving the reading speed. However, the embodiments of the present disclosure are not limited thereto. In another exemplary embodiment, the gating sub-circuit 10 may not be provided. The structure of the gating sub-circuit 10 may refer to the previous embodiment and will not be described in detail again.

[0095] In some embodiments, the gating sub-circuit 10 may be disposed between the bit line BL and the common bit line CBL on the side of the memory array away from the substrate. However, the embodiments of the present disclosure are not limited thereto. The gating sub-circuit 10 may be disposed on the side of the memory array facing the substrate.

[0096] In some embodiments, the gating sub-circuits 10 connected to the bit lines BL in the same row distributed along the first direction x may be connected to the same gating control line, and the gating sub-circuits of the bit lines BL in different rows are connected to different gating control lines. The n rows of bit lines BL are respectively connected to n different gating control lines. For example, as Figure 3 shown, the gating sub-circuits 10 connected to the bit lines BL in the first row are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the bit lines BL in the second row are all connected to the second gating control line S_2, and so on. The gating sub-circuits 10 connected to the bit lines BL in the nth row are all connected to the nth gating control line S_n. Thus, one bit line BL can be selected through the common bit line CBL and the gating control line. For example, when the jth common bit line CBLj loads an activation signal (the remaining common bit lines load non-activation signals), and the ith gating control line S_i gates the corresponding gating sub-circuit 10 (the remaining gating control lines do not gate the corresponding gating sub-circuits 10), the bit line BL_i_j in the ith row and the jth column is loaded with the activation signal.

[0097] In some embodiments, only one bit line BL is gated at the same time, which can reduce the capacitive load of the SA and the capacitance of the memory cell.

[0098] In some embodiments, when the second common word line CWL2_i corresponding to the i-th row is loaded with an activation signal, the gating control line S_i connected to the gating sub-circuit 10 connected to the bit line BL of the i-th row is loaded with a turn-on level signal to turn on the gating sub-circuit 10 connected to the bit line BL of the i-th row. When the first common word line CWL1_r corresponding to the r-th layer is loaded with an activation signal, at this time, the storage cell of the i-th row of the r-th layer is gated, and the storage cell of the i-th row of the r-th layer can be accessed (read or written) through the BL of the i-th row.

[0099] In some embodiments, the second common word line CWL2_i can be connected to the selection control line S_i connected to the selection subcircuit 10 connected to the bit line BL of the i-th row, i is 1 to n, that is, the same signal driver can be used to load the same signal to the second common word line CWL2_i and the selection control line S_i, that is, the activation signal and the start-level signal of the selection subcircuit use the same signal. The solution provided in this embodiment can reduce the number of control lines, as well as reduce the control circuit that generates the control signal, reduce the area occupied by the device, and simplify the control logic. At this time, the selection subcircuit 10 can be set on the side of the storage array facing the substrate. The disclosed embodiment is not limited to this, and the selection subcircuit 10 can be set on the side of the storage array away from the substrate, and the second common word line CWL2_i can be connected to the second word line driver on the side of the storage array away from the substrate.

[0100] Figure 4 Schematic diagram of memory provided for other embodiments. Figure 4 As shown, in the memory provided by this embodiment, the extension direction of the first word line WL1 can be consistent with the extension direction of the second word line WL2, that is, in this embodiment, the memory can include a plurality of first word lines WL1 extending along the first direction x, and the plurality of first word lines WL1 of each layer are spaced along the second direction y, and the first word line of the i-th row of the r-th layer is WL1_Ri_r, i is 1 to n, and r is 1 to k. The storage cell C_i_j_r of the i-th row and j-th column of the r-th layer is connected to the first word line WL1_Ri_r. The plurality of first word line drivers connected to the plurality of first common word lines CWL1_r can be arranged on the same side of the memory. The plurality of first word lines WL1 of the same layer can be connected by two connecting lines extending along the second direction y arranged on the periphery of the memory array. Figure 4 The memory cell, the second common word line, etc. are referenced Figure 3 The embodiment shown in the figure will not be described in detail. Figure 3 The solution in which the first word line and the second word line extend in different directions is easier to manufacture.

[0101] In some embodiments, multiple first word lines WL1 in the same layer are connected to the same first common word line, and the memory cells in each layer correspond to one first common word line (i.e., the memory cells in the same layer are connected to one first common word line). That is, n first word lines WL1_R1_r to WL1_Rn_r in the r-th layer are connected to the r-th first common word line CWL1_r, where r ranges from 1 to k. The n first word lines WL1_R1_1 to WL1_Rn_1 in the first layer are connected to the first first common word line CWL1_1, and the n first word lines WL1_R1_k to WL1_Rn_k in the k-th layer are connected to the k-th first common word line CWL1_k. Each first common word line CWL1_r is connected to a first word line driver.

[0102] Embodiments of the present disclosure provide a method for accessing a memory, which is applied to the memory shown above Figure 3 and Figure 4 The access method may include:

[0103] In the data reading and writing stage, according to the target layer and the target row where the memory cell to be operated is located, an activation signal is loaded on the first common word line corresponding to the target layer, and a non-activation signal is loaded on the first common word line corresponding to the non-target layer; an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word line corresponding to the non-target row (at this time, only the first gate electrode and the second gate electrode of the memory cell in the target row of the target layer are loaded with the activation signal, so that the memory cell in the target row of the target layer can be turned on); an enabling level signal is loaded on the strobe control line connected to the bit line of the target row (so that the strobe sub-circuit connected to the bit line of the target row is in a connected state), and a disabling level signal is loaded on the strobe control line connected to the bit line of the non-target row (so that the strobe sub-circuit connected to the bit line of the non-target row is in a turned-off state).

[0104] The present embodiment provides a method for accessing a memory. By using the first common word line, the second common word line, and the strobe control line, the access to a row of memory cells can be realized, and the control logic is simple.

[0105] In some embodiments, it may further include:

[0106] In the pre-charge stage, for each memory cell, a non-activation signal is loaded on at least one of the first common word line and the second common word line to which the memory cell is connected, and an enabling level signal is loaded on all the strobe control lines. Thus, all memory cells can be turned off, all strobe sub-circuits can be connected, and the bit line can be pre-charged.

[0107] In some embodiments, the activation signal loaded on the second common word line corresponding to the target row and the turn-on level signal loaded on the strobe control line connected to the bit line of the target row are the same signal, and the non-activation signal loaded on the second common word line corresponding to the non-target row and the turn-off level signal loaded on the strobe control line connected to the bit line of the non-target row are the same signal.

[0108] That is, the strobe control line connected to the bit line of the same row and the corresponding second common word line can be controlled by the same signal, reducing the control signals, making the control simpler, and reducing the signal driver, which is beneficial to reducing costs and the device area. At this time, the strobe control line S_i connected to the strobe sub-circuit 10 connected to the second common word line CWL2_i and the bit line of the i-th row can be connected together, where i ranges from 1 to n, and n is the number of rows of memory cells included in each layer of the memory array.

[0109] In some embodiments, a second control circuit is further provided. The second control circuit is configured to access the memory according to the above access method. The second control circuit may include drivers for generating control signals to the first common word line, the second common word line, and the strobe control line, etc. The second control circuit, together with the SA, etc., realizes the access to the memory.

[0110] The working process of the memory is described below through an embodiment. Taking Figure 3 the shown memory as an example, in this embodiment, the memory cell 100 has a 2T1C structure. The first transistor T1 and the second transistor T2 may be N-type MOS transistors, the third transistor T3 may be an N-type MOS transistor, and the strobe control line S_i may be connected to the second common word line CWL2_i ( Figure 3 the connection relationship in which the strobe control line S_i can be connected to the second common word line CWL2_i is not shown), i ranges from 1 to n, and the common bit line CBL may also be connected to a precharge sub-circuit. The working phases of the memory may include a precharge phase, a read data phase, and a data write-back phase, where:

[0111] In the precharge phase, low-level signals are loaded on the first common word lines CWL1_1 to CWL1_k, and these low-level signals are loaded onto the first word line WL1. High-level signals are loaded on the second common word lines CWL2_1 to CWL2_n (i.e., the strobe control line S_i is loaded with a high-level signal). At this time, the strobe sub-circuit is turned on, the first transistors T1 of all memory cells are turned off, the precharge sub-circuit is turned on, and a precharge voltage of 1 / 2VDD is loaded on each common bit line CBL. Each common bit line CBL loads the precharge voltage onto the connected column of bit lines BL.

[0112] In the data reading stage, the precharge electronic circuit is turned off. Taking the example of reading the data of the memory cell 100 in the p-th layer and the q-th row, among the first common word lines CWL1_1 to CWL1_k, the first common word line CWL1_p corresponding to the p-th layer is loaded with a high-level signal, and the remaining first common word lines CWL1_r (where r is from 1 to k and r≠p) are loaded with low-level signals. Among the second common word lines CWL2_1 to CWL2_n, the second common word line CWL2_q corresponding to the q-th row is loaded with a high-level signal, and the remaining CWL2_i (where i is from 1 to n and i≠q) are loaded with low-level signals. Thus, the first transistor T1 and the second transistor T2 of the memory cell 100 in the p-th layer and the q-th row are turned on, and the first transistors T1 and the second transistors T2 of the remaining memory cells 100 are turned off. The gating sub-circuit 10 connected to the bit line BL of the q-th row is turned on. The common bit lines CBL1 to CBLm are respectively connected to the m bit lines BL of the q-th row, and charge sharing is respectively performed with the storage nodes of the m memory cells 100 in the p-th layer and the q-th row. The sense amplifiers respectively connected to CBL1 to CBLm sense the voltages of CBL1 to CBLm to determine the data stored in the memory cell 100 in the p-th layer and the q-th row.

[0113] In the data writing-back stage, among the first common word lines CWL1_1 to CWL1_k, CWL1_p is loaded with a high-level signal, and the remaining CWL1_r (where r is from 1 to k and r≠p) are loaded with low-level signals. Among the second common word lines CWL2_1 to CWL2_n, CWL2_q is loaded with a high-level signal, and the remaining CWL2_i (where i is from 1 to n and i≠q) are loaded with low-level signals. The common bit lines CBL1 to CBLm are respectively connected to the m bit lines BL of the q-th row, and charge sharing is respectively performed with the storage nodes of the m memory cells 100 in the p-th layer and the q-th row to achieve the writing-back of data.

[0114] The solution provided in this embodiment does not require the use of a gating transistor to gate the memory cell. Using the first common word line and the second common word line can select a row of memory cells. The structure is simple, the control logic is simple, and the same control signal is used to control the gating control line and the second common word line of the same row, reducing the number of control signal lines, reducing the required control circuit, and making the control logic simpler.

[0115] The present disclosure embodiment also provides an electronic device, including the memory described in any of the foregoing embodiments. The electronic device can be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device can include the memory in a computer, etc., which is not limited herein.

[0116] In some embodiments, the electronic device may further include a first control circuit or a second control circuit.

[0117] Although the embodiments disclosed in the present invention are as described above, the content described is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A storage unit, characterized in that, Comprising a first transistor, a second transistor, and a capacitor, the first transistor comprising a first gate electrode, a first electrode, and a second electrode, the second transistor comprising a second gate electrode, a third electrode, and a fourth electrode, wherein the first gate electrode of the first transistor is connected to a first word line, the first electrode is connected to one end of the capacitor, the second electrode is connected to the third electrode of the second transistor, the fourth electrode of the second transistor is connected to a bit line, the second gate electrode of the second transistor is connected to a second word line, the other end of the capacitor is connected to a preset voltage terminal, and the first word line and the second word line are connected to different signal terminals.

2. A memory, characterized in that, Comprising: A multi-layer memory array stacked in a third direction perpendicular to the substrate, each layer of the memory array comprising a plurality of memory cells as described in claim 1 arrayed in a first direction parallel to the substrate and a second direction parallel to the substrate, the memory further comprising a plurality of second common word lines corresponding to rows of the multi-layer memory array and a plurality of first common word lines corresponding to columns of the multi-layer memory array; The same row of the multi-layer memory array corresponds to the same second common word line, and the same column of the multi-layer memory array corresponds to the same first common word line; The first gate electrode of the memory cell is connected to the first common word line corresponding to the column where the memory cell is located, and the second gate electrode of the memory cell is connected to the second common word line corresponding to the row where the memory cell is located.

3. The memory according to claim 2, wherein Each layer of the memory array further comprises a plurality of first word lines extending in the third direction, the first gate electrodes of memory cells in the same row and same column of different layers being connected to the same first word line, the first gate electrodes of different memory cells in the same layer being connected to different first word lines, and a plurality of first word lines in the same column being connected to the same first common word line.

4. The memory according to claim 2, wherein Each layer of the memory array further comprises a plurality of second word lines extending in the third direction, the second gate electrodes of memory cells in the same row and same column of different layers being connected to the same second word line, the second gate electrodes of different memory cells in the same layer being connected to different second word lines, and a plurality of second word lines in the same row being connected to the same second common word line.

5. The memory according to claim 3, wherein Each layer of the memory array further comprises: a plurality of bit lines extending in the second direction; the memory further comprises: a plurality of common bit lines; each bit line is connected to memory cells in the same column of the layer where the bit line is located, bit lines in the same layer are connected to the same common bit line, and bit lines in different layers are connected to different common bit lines.

6. The memory according to claim 5, wherein Each bit line is connected to the common bit line through a gating sub-circuit, the gating sub-circuit is further connected to a gating control line, and a plurality of gating sub-circuits respectively connected to a plurality of bit lines in the same column of different layers are connected to the same gating control line, the gating sub-circuit being configured to: connect or disconnect the bit line and the common bit line according to the control of the gating control line.

7. The memory according to claim 6, wherein The gating control line connected to a plurality of gating sub-circuits respectively connected to the bit lines in the j-th column is connected to the first common word line corresponding to the memory cells in the j-th column.

8. A method for accessing a memory according to any one of claims 2 to 7, characterized in that, Comprising: In the data read / write phase, according to the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word lines corresponding to non-target rows; An activation signal is loaded on the first common word line corresponding to the target column, and a non-activation signal is loaded on the first common word lines corresponding to non-target columns.

9. The access method of the memory according to claim 8, wherein The memory is the memory according to claim 6 or 7, and the method further includes, in the data read / write phase, loading an on-level signal on the strobe control line connected to the bit line of the target column, and loading an off-level signal on the strobe control line connected to the bit line of non-target columns.

10. The access method of the memory according to claim 9, wherein, The method further includes, in the precharge phase, for each storage unit, loading a non-activation signal on at least one of the first word line and the second word line connected to the storage unit, and loading an on-level signal on all the strobe control lines.

11. A memory, characterized in that, Comprising: A multi-layer storage array stacked in a third direction perpendicular to the substrate, and a plurality of first common word lines corresponding to the multi-layer storage arrays one by one, wherein the storage array includes a plurality of storage units according to claim 1 arrayed in a first direction parallel to the substrate and a second direction parallel to the substrate, and the memory further includes a plurality of second common word lines corresponding to the rows of the multi-layer storage arrays, the same row of the multi-layer storage arrays corresponds to the same second common word line, the first gate electrodes of the first transistors of the storage units in the same layer are connected to the first common word line corresponding to the layer, and the second gate electrodes of the second transistors of the storage units in the same row distributed in the first direction of multiple layers are connected to the second common word line corresponding to the row.

12. The memory according to claim 11, wherein, Each layer of the storage array further includes a plurality of first word lines extending in the second direction, the first gate electrodes of the storage units in the same column of the same layer are connected to the same first word line, the first gate electrodes of the storage units in different columns of the same layer are connected to different first word lines, and the plurality of first word lines in the same layer are connected to the same first common word line.

13. The memory according to claim 11, characterized in that Each layer of the storage array further includes a plurality of first word lines extending in the first direction, the first gate electrodes of the storage units in the same row of the same layer are connected to the same first word line, the first gate electrodes of the storage units in different rows of the same layer are connected to different first word lines, and the plurality of first word lines in the same layer are connected to the same first common word line.

14. The memory according to claim 11, characterized in that, Each layer of the storage array further includes a plurality of second word lines extending in the first direction, the second gate electrodes of the storage units in the same row of the same layer are connected to the same second word line, the second gate electrodes of the storage units in different rows of the same layer are connected to different second word lines, and the plurality of second word lines in the same row of different layers are connected to the same second common word line.

15. The memory according to claim 14, wherein, The memory further includes: a plurality of bit lines extending in the third direction and a plurality of common bit lines extending in the second direction, the storage units at the same position of the multi-layer storage arrays are connected to the same bit line, the bit lines in the same column distributed in the second direction are connected to the same common bit line, and the bit lines in different columns are connected to different common bit lines.

16. The memory according to claim 15, characterized in that, Each of the bit lines is connected to the common bit line through a gating sub-circuit, and the gating sub-circuit is further connected to a gating control line. Multiple first gating sub-circuits respectively connected to multiple bit lines distributed along the first direction are connected to the same gating control line. The gating sub-circuit is configured to: connect or disconnect the bit line and the common bit line according to the control of the gating control line.

17. The memory according to claim 16, wherein The gating control lines connected to multiple gating sub-circuits respectively connected to multiple bit lines in the i-th row are connected to the second common word line corresponding to the memory cells in the i-th row.

18. A method for accessing a memory according to any one of claims 11 to 17, characterized in that, Comprising: In the data reading and writing stage, according to the target layer and the target row where the memory cell to be operated is located, an activation signal is loaded on the first common word line corresponding to the target layer, and a non-activation signal is loaded on the first common word line corresponding to a non-target layer; an activation signal is loaded on the second common word line corresponding to the target row, and a non-activation signal is loaded on the second common word line corresponding to a non-target row.

19. The access method of the memory according to claim 18, characterized in that, The memory is the memory according to claim 16 or 17, and the method further includes, in the data reading and writing stage, loading an enabling level signal on the gating control line connected to the bit line of the target row, and loading a disabling level signal on the gating control line connected to the bit line of a non-target row.

20. The access method of the memory according to claim 19, characterized in that, The method further includes, in the pre-charge stage, loading a non-activation signal on at least one of the first word line and the second word line connected to each memory cell, and loading an enabling level signal on all the gating control lines.

21. An electronic device, characterized in that, Comprising the memory according to any one of claims 2 to 7, or the memory according to any one of claims 11 to 17.

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