Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a bit line, a transistor structure and a capacitor structure which are sequentially arranged along a first direction, the capacitor structure extends along the first direction, the transistor structure comprises a semiconductor layer, and the semiconductor layer extends along the first direction; the bit line contact layer is located on the end face, away from the capacitor structure, of the semiconductor layer, the bit line covers the end face, away from the semiconductor layer, of the bit line contact layer and at least covers part of the side wall, extending in the first direction, of the bit line contact layer, and the bit line, the semiconductor layer and the bit line contact layer comprise the same semiconductor material; and the material of the bit line is doped with phosphorus. The embodiment of the invention is at least beneficial to reducing the contact resistance between the transistor structure and the bit line and reducing the preparation difficulty of the bit line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same. Background Art

[0002] Due to advantages such as small volume, high integration degree, and fast transmission speed, memories are widely used in mobile devices such as mobile phones and tablet computers. A memory includes a plurality of chip units integrated on a wafer. However, during the manufacturing process, affected by the manufacturing process, the number of chip units integrated on a single wafer is small, and the storage density is low.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), which usually includes a plurality of transistors stacked on a substrate, meets the above requirements. In 3D DRAM, the process window of the bit line structure is relatively small. Especially when the number of stacked layers increases continuously, the formation process of the bit line faces greater challenges, and the performance of the formed bit line structure needs to be improved.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, which are at least beneficial to simplifying the formation process of the bit line structure and improving the performance of the formed bit line structure.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor structure, including: A bit line, a transistor structure, and a capacitor structure arranged in sequence along a first direction, the capacitor structure extends along the first direction, and the transistor structure includes a semiconductor layer that extends along the first direction; A bit line contact layer located at an end face of the semiconductor layer away from the capacitor structure; The bit line extends along a third direction and covers an end face of the bit line contact layer away from the semiconductor layer, and at least covers a part of a side wall of the bit line contact layer extending along the first direction; Wherein, the bit line, the semiconductor layer, and the bit line contact layer include the same semiconductor material, and phosphorus is doped in the material of the bit line.

[0007] In an exemplary embodiment of the present disclosure, the materials of the semiconductor layer and the bit line contact layer are silicon.

[0008] In an exemplary embodiment of the present disclosure, the material of the bit line is phosphorus-doped silicon.

[0009] In an exemplary embodiment of the present disclosure, the bit line contact layer and the semiconductor layer are of an integral structure.

[0010] In an exemplary embodiment of the present disclosure, a plurality of the bit lines, a plurality of the transistor structures, and a plurality of the capacitor structures are all arranged along a second direction, and the bit lines correspond to the transistor structures one by one, the transistor structures correspond to the capacitor structures one by one. A plurality of the transistor structures all include partial gate structures, the gate structures extend along the second direction, and the first direction and the second direction intersect.

[0011] In an exemplary embodiment of the present disclosure, the transistor structure includes a plurality of sub-transistor structures arranged at intervals along a third direction, the capacitor structure includes a plurality of sub-capacitor structures arranged at intervals along the third direction, the semiconductor layer includes a plurality of sub-semiconductor layers arranged at intervals along the third direction. The sub-transistor structures correspond to the sub-capacitor structures one by one, and the sub-transistor structures and the corresponding sub-capacitor structures both include partial sub-semiconductor layers; Moreover, the bit line is electrically connected to a plurality of the sub-transistor structures arranged at intervals along the third direction in the same transistor structure, and the sub-transistor structures correspond to the bit line contact layer one by one.

[0012] According to another aspect of the present disclosure, there is provided a method for forming a semiconductor structure, including: Forming a transistor structure and a capacitor structure arranged in sequence along a first direction, the capacitor structure extends along the first direction, and the transistor structure includes a semiconductor layer, and the semiconductor layer extends along the first direction; Forming a bit line contact layer, the bit line contact layer is located at an end face of the semiconductor layer away from the capacitor structure; Forming a bit line, the bit line extends along a third direction and covers an end face of the bit line contact layer away from the semiconductor layer, and at least covers a partial side wall of the bit line contact layer extending along the first direction; Wherein, the bit line, the semiconductor layer, and the bit line contact layer include the same semiconductor material, and phosphorus is doped in the material of the bit line.

[0013] In an exemplary embodiment of the present disclosure, a selective epitaxial growth process is used to form the bit line contact layer on an end face of the semiconductor layer away from the capacitor structure.

[0014] In an exemplary embodiment of the present disclosure, the materials of the semiconductor layer and the bit line contact layer are silicon, and the material of the bit line is phosphorus-doped silicon.

[0015] In an exemplary embodiment of the present disclosure, the bit line is formed on an end surface of the bit line contact layer by using a selective epitaxial growth process.

[0016] The embodiments of the present disclosure provide a semiconductor structure and a method for forming the semiconductor structure. There is a bit line contact layer between the bit line and an end surface of the semiconductor layer away from the capacitor structure. It can be understood that the end surface of the semiconductor layer away from the capacitor structure can be an end surface of a source region or a drain region in a transistor structure. Among them, the bit line covers the end surface of the bit line contact layer away from the semiconductor layer and at least covers a part of the side wall of the bit line contact layer extending in a first direction. In this way, it is beneficial to increase the contact area between the bit line contact layer and the bit line, thereby being beneficial to reducing the contact resistance between the bit line and the bit line contact layer, so as to further reduce the contact resistance between the bit line and the transistor structure and improve the electrical performance of the semiconductor structure. In addition, the bit line, the bit line contact layer, and the semiconductor layer include the same semiconductor material, and the bit line is formed on the end surface of the bit line contact layer by using a selective epitaxial growth process, which is beneficial to improving the interface state defects between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, so as to improve the contact performance between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, thereby being beneficial to further reducing the contact resistance between the bit line and the transistor structure.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a partial top view schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0020] Figure 2 is Figure 1 a partial cross-sectional schematic diagram of the semiconductor structure shown along a first cross-sectional direction AA1 and a second cross-sectional direction BB1; Figure 3 is Figure 1 another partial cross-sectional schematic diagram of the semiconductor structure shown along the second cross-sectional direction BB1; Figure 4 is Figure 1A partial cross-sectional schematic view of the semiconductor structure shown along the third cross-sectional direction CC1 and the fourth cross-sectional direction DD1; Figure 5 is Figure 2 and Figure 3 A partially enlarged schematic view of the bit line in the semiconductor structure shown; Figures 6 to 10 A partial cross-sectional schematic view corresponding to each step of the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure. Detailed implementation manners

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0022] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0023] The terms "a", "one", "the", "said" and "at least one" are used to indicate the existence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels and are not a limitation on the quantity of their objects.

[0024] As can be seen from the background art, the contact resistance between the transistor structure and the bit line in the dynamic memory needs to be reduced.

[0025] The present disclosure provides a semiconductor structure and a manufacturing method thereof. There is a bit line contact layer between the bit line and the end face of the semiconductor layer away from the capacitor structure in the semiconductor structure. It can be understood that the end face of the semiconductor layer away from the capacitor structure can be the end face of the source region or the drain region in the transistor structure. Among them, the bit line covers the end face of the bit line contact layer away from the semiconductor layer and at least covers a part of the side wall of the bit line contact layer extending in the first direction. In this way, it is beneficial to increase the contact area between the bit line contact layer and the bit line, thereby being beneficial to reducing the contact resistance between the bit line and the bit line contact layer, further reducing the contact resistance between the bit line and the transistor structure, and improving the electrical performance of the semiconductor structure. In addition, the bit line, the bit line contact layer, and the semiconductor layer include the same semiconductor material, and the bit line is formed on the end face of the bit line contact layer by selective epitaxial growth technology, which is beneficial to improving the interface state defects between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, improving the contact performance between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, and thus being beneficial to further reducing the contact resistance between the bit line and the transistor structure.

[0026] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the drawings. Figure 1 It is a partial top view schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure; Figure 2 is Figure 1 a partial cross-sectional schematic diagram of the semiconductor structure shown along the first cross-sectional direction AA1 and the second cross-sectional direction BB1; Figure 3 is Figure 1 another partial cross-sectional schematic diagram of the semiconductor structure shown along the second cross-sectional direction BB1; Figure 4 is Figure 1 a partial cross-sectional schematic diagram of the semiconductor structure shown along the third cross-sectional direction CC1 and the fourth cross-sectional direction DD1.

[0027] Referring to Figures 1 to 4 , the semiconductor structure includes: a bit line structure 1000, a transistor structure 101, and a capacitor structure 102 arranged in sequence along the first direction X. In some embodiments, such as Figure 1As shown, the transistor structures 101 and capacitor structures 102 located on both sides of the bit line structure 1000 along the first direction X have a mirror-symmetric structure. Among them, the capacitor structure 102 extends along the first direction X, and the transistor structure 101 includes a semiconductor layer 103. In some embodiments, the semiconductor layer 103 extends along the first direction X and extends into the capacitor structure 102. The semiconductor layer 103 extending into the capacitor structure 102 can serve as the conductive layer of the capacitor structure and as the support structure of the capacitor structure; the bit line contact layer 104 is located on the end face of the semiconductor layer 103 away from the capacitor structure 102, and the bit line contact layer 104 and the semiconductor layer 103 are made of the same semiconductor material. As Figure 2 or Figure 3 shown, the bit line structure 1000 includes a bit line 100 and a dielectric layer 140. Among them, the bit line 100 is located on opposite sides of the dielectric layer 140 along the first direction X. The bit line 100 covers the end face of the bit line contact layer 104 away from the semiconductor layer 103 and at least covers a part of the side wall of the bit line contact layer 104 extending along the first direction X. The bit lines 100 located on both sides of the dielectric layer 140 are respectively connected to the semiconductor layers 103 in the transistor structures on the mirror-symmetric two sides. In some embodiments, the bit lines 100 located on both sides of the dielectric layer 140 are electrically insulated from each other, that is, the bit lines on both sides of the dielectric layer 140 are isolated from each other. Thereby, the parasitic capacitance between the bit line and the adjacent bit line (along the second direction Y) can be reduced, and the transmission rate of the device can be improved.

[0028] It can be understood that the end face of the semiconductor layer 103 away from the capacitive structure 102 can be the end face of the source region or the drain region in the transistor structure 101. Then, the bit line 100 covers the end face of the bit line contact layer 104 away from the semiconductor layer 103, that is, the bit line 100 covers the end face of the source region or the drain region in the transistor structure 101. Therefore, when the bit line contact layer 104 is located at the end face of the semiconductor layer 103 away from the capacitive structure 102, and the bit line 100 covers the end face of the source region or the drain region in the transistor structure 101 and at least covers a part of the side wall of the bit line contact layer 104 extending along the first direction X, the bit line 100 is in contact with multiple end faces of the bit line contact layer 104, which is beneficial to increasing the contact area between the bit line contact layer 104 and the bit line 100, thereby being beneficial to reducing the contact resistance between the bit line 100 and the bit line contact layer 104, so as to further reduce the contact resistance between the bit line 100 and the transistor structure 101. In addition, the bit line 100, the bit line contact layer 104, and the semiconductor layer 103 all include the same semiconductor material, which is beneficial to improving the interface state defects between the bit line 100 and the bit line contact layer 104, between the bit line contact layer 104 and the semiconductor layer 103, or between the bit line 100 and the semiconductor layer 103, so as to improve the contact performance between the bit line 100 and the bit line contact layer 104, between the bit line contact layer 104 and the semiconductor layer 103, and between the bit line 100 and the semiconductor layer 103, thereby being beneficial to further reducing the contact resistance between the bit line 100 and the transistor structure 101. Therefore, it is beneficial to improve the electrical performance of the semiconductor structure.

[0029] In some embodiments, the semiconductor material may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, the materials of the bit line contact layer 104 and the semiconductor layer 103 are silicon. The material of the bit line 100 is phosphorus-doped silicon. In the embodiments of the present disclosure, using phosphorus-doped silicon as the bit line material can, on the one hand, reduce the contact resistance between the bit line and the transistor structure, and on the other hand, the bit line 100 can be formed by selective epitaxial growth process, and two adjacent bit lines 100 along the first direction X are isolated from each other, which is beneficial to reducing the preparation difficulty of the bit line and further reducing the parasitic capacitance between the bit lines.

[0030] In some embodiments, the material of the dielectric layer 140 includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, low-K material, ferroelectric material, antiferroelectric material, or a combination thereof. In order to reduce the parasitic capacitance between the bit lines 100 on both sides of the dielectric layer 140, the material of the dielectric layer 140 can be a low-K material, which can be, but is not limited to, one or a combination of two or more of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass). In some embodiments, the dielectric layer 140 can further include air gaps or shielding structures to reduce the parasitic capacitance between the bit lines 100 on both sides of the dielectric layer 140.

[0031] In some embodiments, referring to Figure 2 , Figure 3 and Figure 5 , the bit line 100 can have at least one recessed area 110 that is recessed towards the inside of the bit line structure 1000. It can be seen that the recessed area 110 is used to accommodate at least a part of the bit line contact layer 104, so that the surface area of the side wall of the bit line 100 can be increased through the recessed area 110, realizing that the bit line 100 covers the end face of the source region or the drain region in the transistor structure 101 and at least covers a part of the side wall of the bit line contact layer 104 extending along the first direction X, which is beneficial to increasing the contact area between the bit line 100 and the bit line contact layer 104 to reduce the contact resistance between the bit line 100 and the bit line contact layer 104.

[0032] It should be noted that Figure 2 , Figure 3 and Figure 5 take an example that one bit line 100 includes 4 mutually spaced recessed areas 110, and both sides of each recessed area 110 along the first direction X are recessed towards the inside of the bit line 100. In practical applications, the number of mutually spaced recessed areas 110 included in one bit line 100 is not limited, and for a single recessed area 110, only one of the two sides of the recessed area 110 along the first direction X can be recessed towards the inside of the bit line 100.

[0033] Such as Figure 2As shown, on the cross-section of the plane formed by the first direction X and the third direction Z, the bit line contact layer 104 has an arc-shaped cross-section. In some embodiments, taking the end face of the exposed semiconductor layer 103 as the growth layer, a selective epitaxial growth process is used to form the bit line contact layer 104 on the end face of the semiconductor layer 103. In some embodiments, the material of the semiconductor layer 103 is silicon, and the material of the bit line contact layer 104 formed by the selective epitaxial growth process is also silicon. Therefore, the semiconductor layer 103 and the bit line contact layer 104 are formed of the same material, and there are fewer interface state defects between the two, which can effectively reduce the contact resistance between the semiconductor layer 103 and the bit line contact layer 104.

[0034] As Figure 3 shown, in some other embodiments, on the cross-section of the plane formed by the first direction X and the third direction Z, the bit line contact layer 104 has a rectangular cross-section. In some embodiments, by laterally etching the dielectric layers above and below the semiconductor layer 103 to expose the end portion of the semiconductor layer 103 along the first direction X, and using this exposed end portion as the bit line contact layer 104, that is, the bit line contact layer 104 and the semiconductor layer 103 are of an integral structure. Through the design of the integral structure, there are no interface state defects between the bit line contact layer 104 and the semiconductor layer 103. Therefore, the contact resistance between the semiconductor layer 103 and the bit line contact layer 104 can be effectively reduced.

[0035] In some embodiments, referring to Figure 1 , a plurality of bit line structures 1000, a plurality of transistor structures 101, and a plurality of capacitor structures 102 are all arranged along the second direction Y, and the bit lines 100 correspond to the transistor structures 101 one by one, the transistor structures 101 correspond to the capacitor structures 102 one by one, and a plurality of transistor structures 101 all include partial gate structures 111. The gate structures 111 extend along the second direction Y, and the first direction X intersects with the second direction Y.

[0036] It can be understood that the gate structures 111 are used to control the transistor structures 101. Since a plurality of transistor structures 101 all include partial gate structures 111, the gate structures 111 can control a plurality of transistor structures 101 arranged along the second direction Y. In this way, it is beneficial to improve the integration density of the transistor structures 101, the bit lines 100, and the capacitor structures 102 in the semiconductor structure while reducing the control complexity of each device in the semiconductor structure.

[0037] It should be noted that Figures 1 to 4 takes the semiconductor structure including 5 bit line structures 1000 arranged along the second direction Y as an example. In actual applications, the number of bit line structures 1000 included in the semiconductor structure is not limited, as long as the number of bit lines 100 is equal to the number of transistor structures 101.

[0038] In some embodiments, referring to Figures 1 to 4 , the transistor structure 101 may include a plurality of sub-transistor structures 121 arranged at intervals along the third direction Z, the capacitor structure 102 includes a plurality of sub-capacitor structures 112 arranged at intervals along the third direction Z, the semiconductor layer 103 includes a plurality of sub-semiconductor layers 113 arranged at intervals along the third direction Z, the sub-transistor structures 121 and the sub-capacitor structures 112 are in one-to-one correspondence, and both the sub-transistor structure 121 and the corresponding sub-capacitor structure 112 include a part of the sub-semiconductor layer 113; and, the bit line 100 extends along the third direction Z, and the bit line 100 is electrically connected to a plurality of sub-transistor structures 121 arranged at intervals along the third direction in the same transistor structure 101, and the sub-transistor structures 121 and the bit line contact layer 104 are in one-to-one correspondence.

[0039] It can be understood that a plurality of sub-transistor structures 121 and a plurality of sub-capacitor structures 112 can be arranged along the third direction Z. A sub-transistor structure 121 can independently serve as a transistor unit, a sub-capacitor structure 112 can independently serve as a capacitor unit, and a transistor unit and a capacitor unit can form a storage unit. In this way, it is beneficial to improve the layout density of the storage units in the semiconductor structure by stacking the sub-transistor structures 121 and the sub-capacitor structures 112 along the third direction Z, thereby improving the integration density of the semiconductor structure.

[0040] It should be noted that Figures 2 to 4 taking the number of sub-transistor structures 121 stacked along the third direction Z in a transistor structure 101 as 4 as an example, in practical applications, the number of sub-transistor structures 121 stacked along the third direction Z in a transistor structure 101 is not limited and can be designed according to actual needs, as long as the numbers of the sub-transistor structures 121, the sub-capacitor structures 112, and the sub-semiconductor layers 113 are the same.

[0041] In one example, the number of sub-transistor structures 121 stacked along the third direction Z in a transistor structure 101 can be 1, then the sub-transistor structure 121 is the transistor structure 101. The number of sub-capacitor structures 112 stacked along the third direction Z in a capacitor structure 102 is 1, then the sub-capacitor structure 112 is the capacitor structure 102. The number of sub-semiconductor layers 113 stacked along the third direction Z in a semiconductor layer 103 is 1, then the sub-semiconductor layer 113 is the semiconductor layer 103.

[0042] In some embodiments, continuing to refer to Figures 2 to 4, along the first direction X, the sub-semiconductor layer 113 includes a first region 123, a second region 133, and a third region 143. The end face of the first region 123 away from the second region 133 is in contact with the bit line contact layer 104; the sub-transistor structure 121 includes the first region 123, the second region 133, and the gate structure 111. The gate structure 111 surrounds the side wall of the second region 133 extending along the first direction X; the sub-capacitor structure 112 includes the third region 143 and a sub-bottom electrode layer 122, a capacitor dielectric layer 132, and a top electrode layer 142 stacked in sequence. The sub-bottom electrode layer 122 surrounds the side wall of the third region 143 extending along the first direction X.

[0043] In some embodiments, referring to Figure 2 and Figure 3 , the gate structure 111 may include a gate dielectric layer 131 and a gate conductive layer 141. Wherein, the gate dielectric layer 131 surrounds the side wall of the second region 133 extending along the first direction X, and the gate conductive layer 141 surrounds the side wall of the gate dielectric layer 131 away from the second region 133 and extending along the first direction X, and the gate conductive layer 141 extends along the second direction, such that one gate conductive layer 141 is in contact connection with the gate dielectric layer 131 in a plurality of sub-transistor structures 121 arranged at intervals along the second direction Y. It can be understood that the material of the gate conductive layer 141 may be at least one of conductive materials such as titanium nitride, tungsten, or silver, and the material of the gate dielectric layer 131 may be at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0044] In some embodiments, continuing to refer to Figure 2 and Figure 3 , the semiconductor layer 103 in the transistor structure 101 sequentially includes, along the first direction X: a first region 123, a second region 133, and a fourth region 153. Wherein, the first region 123 may be one of the source region or the drain region in the transistor structure 101, the fourth region 153 may be the other of the source region or the drain region, the second region 133 may serve as the channel region, and the fourth region 153 is in contact connection with the third region 143 to realize the electrical connection between the sub-transistor structure 121 and the sub-capacitor structure 112.

[0045] In some embodiments, the bottom electrode layer in the sub-capacitor structure 112 includes the third region 143 and the sub-bottom electrode layer 122. Wherein, the sub-bottom electrode layer 122 surrounds at least a part of the side wall of the third region 143 extending along the first direction X; the capacitor dielectric layer 132 surrounds the side wall of the sub-bottom electrode layer 122 away from the third region 143 and extending along the first direction X; the top electrode layer 142 surrounds the side wall of the sub-capacitor dielectric layer 132 away from the sub-bottom electrode layer 122 and extending along the first direction X.

[0046] In some embodiments, the upper electrode layer 142 may include a diffusion barrier layer (not shown in the figure) and a sub-upper electrode layer (not shown in the figure) stacked in sequence. The diffusion barrier layer surrounds the sidewalls of the capacitive dielectric layer 132 that are far from the lower electrode layer 122 and extend along the first direction X. The sub-upper electrode layer surrounds the sidewalls of the diffusion barrier layer that are far from the capacitive dielectric layer 132 and extend along the first direction X. The diffusion barrier layer is conducive to blocking the diffusion of the conductive material in the sub-upper electrode layer into the capacitive dielectric layer 132, so as to ensure the good insulation performance of the capacitive dielectric layer 132 and the good conductive performance of the sub-upper electrode layer. In one example, the material of the diffusion barrier layer may be titanium nitride, and the materials of the sub-upper electrode layer and the sub-lower electrode layer 122 may be at least one of conductive materials such as polysilicon, titanium nitride or tungsten. The material of the capacitive dielectric layer 132 may be a high-k dielectric material such as strontium titanate, hafnium oxide, chromium oxide or zirconium oxide.

[0047] In some embodiments, referring to Figure 1 and Figure 4 , along the second direction Y, partial sub-transistor structures 121 in different transistor structures 101 all include partial regions of the same gate structure 111. The gate structure 111 extends along the second direction Y, and the number of sub-transistor structures 121 in the same transistor structure 121 is the same as the number of gate structures 111. The first direction X, the second direction Y and the third direction Z intersect pairwise. The semiconductor structure may further include: a word line ladder structure 105, electrically connected to the multiple gate structures 111 respectively.

[0048] It can be understood that the second regions 133 in the multiple sub-transistor structures 121 arranged at intervals along the second direction Y on the same layer are all in contact connection with the same gate structure 111, and the second regions 133 in the sub-transistor structures 121 in different layers in the same transistor structure 101 are in contact connection with different gate structures 111. In this way, the word line ladder structure 105 is electrically connected to the multiple gate structures 111 respectively. It is beneficial to realize independent control of different gate structures 111 through the word line ladder structure 105.

[0049] In one example, the first direction X, the second direction Y and the third direction Z may be perpendicular to each other pairwise.

[0050] In some embodiments, continuing to refer to Figure 1 and Figure 4 , the word line ladder structure 105 may include multiple step structures 115 arranged at intervals along the third direction Z. The step structures 115 extend along the second direction Y, and the lengths of the multiple step structures 115 in the second direction Y are different. The step structures 115 correspond to the gate structures 111 one by one.

[0051] Among them, the gate structures 111 are connected to the step structures 115 in a one-to-one correspondence, and the lengths of the multiple step structures 115 in the second direction Y are different. In this way, different gate structures 111 can be controlled by different step structures 115 to achieve the independence between different sub-transistor structures 121 in the same transistor structure 101.

[0052] It should be noted that Figures 2 to 4 taking the gate structure 111 extending along the second direction Y as an example, in practical applications, the extension direction of the gate structure 111 can be designed according to actual requirements In some embodiments, referring to Figures 2 to 4 , the semiconductor structure may further include: a substrate 170, located directly below the bit line structure 1000, the transistor structure 101, the capacitor structure 102, and the word line stepped structure 105 in the third direction Z, and is used as a support base for the bit line structure 1000, the transistor structure 101, the capacitor structure 102, and the word line stepped structure 105.

[0053] In some embodiments, referring to Figure 4 , the step structure 115 may include a support layer 163, a dielectric layer 125, and an electrically connecting layer 135. Among them, the support layer 163 and the semiconductor layer 103 may be an integrally formed structure, the dielectric layer 125 and the gate dielectric layer 131 may be an integrally formed structure, the electrically connecting layer 135 and the gate conductive layer 141 may be an integrally formed structure, and the electrically connecting layer 135 is in contact connection with the gate conductive layer 141.

[0054] In other embodiments, the step structure may only include the electrically connecting layer, and the electrically connecting layer is in contact connection with the gate conductive layer.

[0055] In some embodiments, referring to Figures 2 to 4, the semiconductor structure may further include: a first dielectric layer 116, a second dielectric layer 126, and a third dielectric layer 136. Among them, the first dielectric layer 116 and the second dielectric layer 126 jointly cover the sidewalls of the first region 123 extending along the first direction X to achieve electrical isolation between the bit line 100 and the sub-transistor structure 121; the first dielectric layer 116 and the second dielectric layer 126 also jointly cover the sidewalls of the fourth region 153 extending along the first direction X to achieve electrical isolation between the sub-transistor structure 121 and the sub-capacitor structure 112; the first dielectric layer 116 is also located between adjacent sub-transistor structures 121 to achieve electrical isolation between adjacent sub-transistor structures 121, the first dielectric layer 116 is also located between adjacent step structures 115 to achieve electrical isolation between adjacent step structures 115, the first dielectric layer 116 is also located between the bit line 100 and the substrate 170 to achieve electrical isolation between the bit line 100 and the substrate 170, and the second dielectric layer 126 may also be located on the side of the first dielectric layer 116 away from the substrate 170 and on the side of the third dielectric layer 136 away from the substrate 170; the third dielectric layer 136 is located between adjacent sub-capacitor structures 112 to achieve electrical isolation between adjacent sub-capacitor structures 112.

[0056] It should be noted that in one embodiment of the present disclosure, there is no limitation on whether the first dielectric layer 116, the second dielectric layer 126, and the third dielectric layer 136 are single-layer structures or stacked structures. In actual applications, they can be set according to actual needs.

[0057] In some embodiments, the materials of the first dielectric layer 116, the second dielectric layer 126, and the third dielectric layer 136 may all include at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In one example, the material of the first dielectric layer 116 may be silicon oxide, the material of the second dielectric layer 126 may be silicon nitride, and the material of the third dielectric layer 136 may be silicon oxynitride.

[0058] In summary, the bit line 100 is in contact with multiple end faces of the bit line contact layer 104, which is beneficial to increasing the contact area between the bit line contact layer 104 and the bit line 100, thereby being beneficial to reducing the contact resistance between the bit line 100 and the bit line contact layer 104, and further reducing the contact resistance between the bit line 100 and the transistor structure 101; in addition, the bit line, the bit line contact layer, and the semiconductor layer include the same semiconductor material, and the bit line is formed on the end face of the bit line contact layer by selective epitaxial growth technology, which is beneficial to improving the interface state defects between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, so as to improve the contact performance between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, and thus is beneficial to further reducing the contact resistance between the bit line and the transistor structure.

[0059] Another embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure for preparing the semiconductor structure provided in the foregoing embodiment. The following will be combined with Figures 1 to 10 to describe in detail the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure. Figures 6 to 10 FIG. 4 is a partial cross-sectional schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure. It should be noted that the same or corresponding parts as those in the foregoing embodiment will not be described herein again.

[0060] Referring to Figures 6 to 10 , the manufacturing method of the semiconductor structure includes: forming a transistor structure 101 and a capacitor structure 102 arranged along a first direction X, the capacitor structure 102 extends along the first direction X, and the transistor structure 101 includes a semiconductor layer 103, and the semiconductor layer 103 extends along the first direction X; forming a bit line contact layer 104, the bit line contact layer 104 is located on an end surface of the semiconductor layer 103 away from the capacitor structure 102; forming a bit line 100, the bit line 100 extends along a third direction Z and covers an end surface of the bit line contact layer 104 away from the semiconductor layer 103, and at least covers a part of a side wall of the bit line contact layer 104 extending along the first direction X. Among them, the bit line 100, the semiconductor layer 103, and the bit line contact layer 104 include the same semiconductor material, and phosphorus is doped in the material of the bit line 100.

[0061] In some embodiments, referring to Figure 1 , the step of forming the transistor structure 101 and the capacitor structure 102 may include: along a second direction Y, forming a plurality of spaced-apart transistor structures 101 and a plurality of spaced-apart capacitor structures 102, and the bit line 100 corresponds to the transistor structure 101 one by one, the transistor structure 101 corresponds to the capacitor structure 102 one by one, and a plurality of transistor structures 101 all include a part of a gate structure 111, the gate structure 111 extends along the second direction Y, and the first direction X and the second direction Y intersect.

[0062] In some embodiments, referring to Figure 6 and Figure 7 , the step of forming the transistor structure 101 and the capacitor structure 102 may further include: along a third direction Z, forming a plurality of spaced-apart sub-transistor structures 121, a plurality of spaced-apart sub-capacitor structures 112, and a plurality of spaced-apart sub-semiconductor layers 113. Among them, at least a part of the sub-transistor structures 121 arranged along the third direction Z constitutes the transistor structure 101, at least a part of the sub-capacitor structures 112 arranged along the third direction Z constitutes the capacitor structure 102, and at least a part of the sub-semiconductor layers 113 arranged along the third direction Z constitutes the semiconductor layer 103.

[0063] In this way, it is beneficial to form the sub-transistor structures 121, sub-capacitor structures 112, and sub-semiconductor layers 113 that are arranged at intervals along the second direction X and / or the third direction Y, so as to improve the integration density of the transistor structures 101, bit lines 100, and capacitor structures 102 in the semiconductor structure.

[0064] In some embodiments, with continued reference to Figure 6 and Figure 7 , forming the sub-transistor structures 121 and sub-capacitor structures 112 may include the following steps: providing a substrate 170; forming a sacrificial layer 106 and a plurality of initial sub-semiconductor layers 173 arranged at intervals along the third direction Z on the substrate 170 along the third direction Z. Along the first direction X, the initial sub-semiconductor layers 173 include a bit line region 183, a first region 123, a second region 133, a fourth region 153, and a third region 143; etching the sacrificial layer 106 opposite to the second region 133 to expose the second region 133, and forming a gate structure 111, the gate structure 111 surrounding the sidewalls of the second region 133 extending along the first direction X; etching the sacrificial layer 106 opposite to the third region 143 to expose the third region 143, and forming a sub-bottom electrode layer 122, the sub-bottom electrode layer 122 surrounding the sidewalls of the third region 143 extending along the first direction X; sequentially stacking a capacitor dielectric layer 132 and an upper electrode layer 142 on the sidewalls of the sub-bottom electrode layer 122 extending along the first direction X; wherein, the first region 123, the second region 133, and the fourth region 153 and the gate structure 111 constitute the sub-transistor structure 121, and the third region 143, the sub-bottom electrode layer 122, the capacitor dielectric layer 132, and the upper electrode layer 142 constitute the sub-capacitor structure 112.

[0065] It should be noted that another embodiment of the present disclosure does not limit the specific formation method and formation sequence of the sub-transistor structure 121 and the sub-capacitor structure 112. In addition, after forming the sub-transistor structure 121 and the sub-capacitor structure 112, part of the first dielectric layer 116, part of the second dielectric layer 126, and the third dielectric layer 136 have been formed, and the remaining part of the sacrificial layer 106 opposite to the bit line region 183 after subsequent etching also constitutes the first dielectric layer 116 and the second dielectric layer 126. For the specific descriptions of the first dielectric layer 116, the second dielectric layer 126, and the third dielectric layer 136, please refer to the foregoing embodiments and will not be elaborated herein. In addition, for the details of the sub-transistor structure 121 and the sub-capacitor structure 112, please also refer to the foregoing embodiments and will not be elaborated herein.

[0066] It can be understood that the sacrificial layer 106 directly opposite to the second region 133 refers to the part of the sacrificial layer 106 whose orthographic projection on the substrate 170 coincides with the orthographic projection of the second region 133 on the substrate 170. The sacrificial layer 106 directly opposite to the third region 143 refers to the part of the sacrificial layer 106 whose orthographic projection on the substrate 170 coincides with the orthographic projection of the third region 143 on the substrate 170.

[0067] In some embodiments, with reference to Figure 1 and Figure 7 , along the second direction Y, partial sub-transistor structures 121 in different transistor structures 101 may each include a partial region of the same gate structure 111. The gate structure 111 extends along the second direction Y, and the number of sub-transistor structures 121 in the same transistor structure 121 is the same as the number of gate structures 111. The first direction X, the second direction Y, and the third direction Z intersect pairwise; the manufacturing method may further include: forming a word line stepped structure 105, and the word line stepped structure 105 is electrically connected to the multiple gate structures 111 respectively.

[0068] It should be noted that another embodiment of the present disclosure does not limit the specific formation method of the word line stepped structure 105. In addition, for the specific description of the word line stepped structure 105, please refer to the foregoing embodiments, and details are not described herein again.

[0069] The following details how to form the bit line 100 and the bit line contact layer 104 through two specific embodiments.

[0070] In some embodiments, forming the bit line contact layer 104 and the bit line 100 may include the following steps: With reference to Figure 6 and Figure 8 , etch the bit line region 183 and the sacrificial layer 106 directly opposite to the bit line region 183 to form a first groove 107 and a semiconductor layer 103 (refer to Figure 1 ), and the semiconductor layer 103 includes a plurality of sub-semiconductor layers 113 arranged at intervals along the third direction Z. Along the first direction X, the sub-semiconductor layers 113 include a first region 123, a second region 133, and a third region 143. The first groove 107 exposes the end face of the first region 123 away from the second region 133.

[0071] It can be understood that the sacrificial layer 106 directly opposite to the bit line region 183 refers to the part of the sacrificial layer 106 whose orthographic projection on the substrate 170 coincides with the orthographic projection of the bit line region 183 on the substrate 170. The first groove 107 is used to form the bit line contact layer 104 and the bit line 100 subsequently.

[0072] With reference to Figure 9, a bit line contact layer 104 is formed on the exposed end surface of the first region 123. The bit line contact layer 104 is located in the first groove 107, and the bit line contact layer 104 and the sub-semiconductor layer 113 are made of the same semiconductor material. In one example, the materials of both the bit line contact layer 104 and the sub-semiconductor layer 113 are silicon materials.

[0073] In some embodiments, the step of forming the bit line contact layer 104 may include: forming the bit line contact layer 104 on the exposed end surface of the first region 123 by using selective epitaxial growth technology.

[0074] It can be understood that using the selective epitaxial growth technology is beneficial to improving the continuity between the bit line contact layer 104 and the first region 123, reducing the contact defects caused by different lattice characteristics or lattice misalignment, reducing the contact resistance caused by contact defects, improving the carrier transmission ability and moving speed, and thus improving the electrical conductivity between the bit line contact layer 104 and the first region 123, facilitating subsequent improvement of the electrical conductivity between the bit line 100 formed based on the bit line contact layer 104 and the first region 123, and reducing the heat generation during the operation of the semiconductor structure.

[0075] It can be understood that since the end surface of the bit line contact layer 104 far from the first region 123 and at least part of the side walls of the bit line contact layer 104 are exposed in the first groove 107, this is beneficial for the bit line 100 to cover the end surface of the bit line contact layer 104 far from the first region 123 and at least cover part of the side walls of the bit line contact layer 104 extending along the first direction X. In this way, it is beneficial to increase the contact area between the bit line contact layer 104 and the bit line 100, thereby being beneficial to reducing the contact resistance between the bit line 100 and the bit line contact layer 104, and further reducing the contact resistance between the bit line 100 and the transistor structure 101.

[0076] With reference to Figure 9 and Figure 2 , the bit line 100 is formed. The bit line 100 extends along the third direction Z, and the bit line 100 is electrically connected to a plurality of sub-transistor structures 121 arranged at intervals along the third direction Z in the same transistor structure 101. The sub-transistor structures correspond to the bit line contact layers one by one.

[0077] In some embodiments, the selective epitaxial growth technology is adopted, and the bit line contact layer 104 is used as the epitaxial growth layer for epitaxial growth. The material for epitaxial growth includes phosphorus-doped silicon. During the process of selectively epitaxially growing to form the bit line 100, a plurality of bit line contact layers 104 arranged at intervals along the third direction Z simultaneously serve as the epitaxial growth layer, and phosphorus-doped silicon material is selectively epitaxially formed along the third direction Z. And in the third direction Z, the epitaxial materials are connected to each other to form the bit line 100. As Figure 9As shown, since selective epitaxial growth process is used for epitaxy, the bottom of the first groove 107 is the first dielectric layer 116. Therefore, the selective epitaxial growth process of the bit line material cannot be carried out. Therefore, after the bit line 100 is formed by epitaxial growth, the bit lines 100 on both sides of the first groove 107 (along the first direction X) are isolated from each other. At the same time, the bit lines 100 cannot be formed on both sides of the first groove along the second direction Y. In this way, on the one hand, the process difficulty of forming the bit line 100 can be reduced and the preparation efficiency can be improved. On the other hand, the parasitic capacitance between adjacent bit lines along the second direction Y can be effectively reduced, the access speed of the formed memory device can be effectively improved, and the electrical performance of the memory device can be improved.

[0078] In some other embodiments, forming the bit line contact layer 104 and the bit line 100 may include the following steps: With reference to Figure 6 and Figure 8 , etch the bit line region 183 and the sacrificial layer 106 opposite to the bit line region 183 to form the first groove 107 and the semiconductor layer 103 (refer to Figure 1 ), and the semiconductor layer 103 includes a plurality of sub-semiconductor layers 113 arranged at intervals along the third direction Z. Along the first direction X, the sub-semiconductor layer 113 includes a first region 123, a second region 133, and a third region 143. The first groove 107 exposes the end face of the first region 123 away from the second region 133.

[0079] It can be understood that the sacrificial layer 106 opposite to the bit line region 183 refers to the part of the sacrificial layer 106 whose orthographic projection on the substrate 170 coincides with the orthographic projection of the bit line region 183 on the substrate 170. The first groove 107 is used to form the bit line contact layer 104 and the bit line 100 subsequently.

[0080] With reference to Figure 8 and Figure 10 , perform lateral etching on the sacrificial layer 106 exposed by the first groove 107 to form the second groove 117. The second groove 117 exposes a part of the side wall of the first region 123 extending along the first direction X, and the first groove 107 and the second groove 117 communicate with each other.

[0081] In this way, it is beneficial to expose the end face of the first region 123 away from the second region 133 and a part of the side wall of the first region 123 extending along the first direction X through both the first groove 107 and the second groove 117. At the same time, the first region 123 jointly exposed by the first groove 107 and the second groove 117 is used as the bit line contact layer 104, that is, the bit line contact layer 104 and the sub-semiconductor layer 113 are of an integral structure.

[0082] In addition, the formed bit line contact layer 104 is at least partially located in the first groove 107. When the bit line 100 is formed in the remaining first groove 107 and the remaining second groove 117 subsequently, it is beneficial to make the bit line 100 cover the end face of the bit line contact layer 104 away from the first region 123 and at least cover a part of the side wall of the bit line contact layer 104 extending along the first direction X. In this way, it is beneficial to increase the contact area between the bit line contact layer 104 and the bit line 100, thereby being beneficial to reducing the contact resistance between the bit line 100 and the bit line contact layer 104, so as to further reduce the contact resistance between the bit line 100 and the transistor structure 101.

[0083] With reference to Figure 10 and Figure 3 , the bit line 100 is formed. The selective epitaxial growth process is adopted, and the bit line contact layer 104 is used as the epitaxial growth layer for epitaxial growth. The material for epitaxial growth includes phosphorus-doped silicon. During the process of selectively epitaxially growing to form the bit line 100, multiple bit line contact layers 104 arranged at intervals along the third direction Z simultaneously serve as the epitaxial growth layer, and phosphorus-doped silicon material is selectively epitaxially formed along the third direction Z. Moreover, in the third direction Z, the epitaxial materials are connected to each other to form the bit line 100.

[0084] In summary, in the semiconductor structure formed by using the manufacturing method improved by another embodiment of the present disclosure, the bit line 100 is in contact with multiple end faces of the bit line contact layer 104, which is beneficial to increasing the contact area between the bit line contact layer 104 and the bit line 100, thereby being beneficial to reducing the contact resistance between the bit line 100 and the bit line contact layer 104, so as to further reduce the contact resistance between the bit line 100 and the transistor structure 101; in addition, the bit line, the bit line contact layer, and the semiconductor layer include the same semiconductor material, and the bit line is formed on the end face of the bit line contact layer by using the selective epitaxial growth process, which is beneficial to improving the interface state defects between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, so as to improve the contact performance between the bit line and the bit line contact layer and between the bit line contact layer and the semiconductor layer, thereby being beneficial to further reducing the contact resistance between the bit line and the transistor structure.

[0085] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

[0086] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the shown steps must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

Claims

1. A semiconductor structure, characterized in that, Including: A bit line, a transistor structure, and a capacitor structure arranged in sequence along a first direction. The capacitor structure extends along the first direction, and the transistor structure includes a semiconductor layer that extends along the first direction. A bit line contact layer located on an end face of the semiconductor layer away from the capacitor structure. The bit line extends along a third direction and covers an end face of the bit line contact layer away from the semiconductor layer, and at least covers a part of a side wall of the bit line contact layer extending along the first direction. Wherein, the bit line, the semiconductor layer, and the bit line contact layer are made of the same semiconductor material, and phosphorus is doped in the material of the bit line.

2. The semiconductor structure according to claim 1, wherein The materials of the semiconductor layer and the bit line contact layer are silicon.

3. The semiconductor structure according to claim 1, characterized in that, The material of the bit line is phosphorus-doped silicon.

4. The semiconductor structure according to claim 1, wherein The bit line contact layer and the semiconductor layer are of an integral structure.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, A plurality of the bit lines, a plurality of the transistor structures, and a plurality of the capacitor structures are all arranged along a second direction, and the bit lines correspond to the transistor structures one by one, the transistor structures correspond to the capacitor structures one by one. A plurality of the transistor structures all include a part of a gate structure that extends along the second direction, and the first direction and the second direction intersect.

6. The semiconductor structure according to claim 5, characterized in that The transistor structure includes a plurality of sub-transistor structures arranged at intervals along a third direction, the capacitor structure includes a plurality of sub-capacitor structures arranged at intervals along the third direction, the semiconductor layer includes a plurality of sub-semiconductor layers arranged at intervals along the third direction. The sub-transistor structures correspond to the sub-capacitor structures one by one, and the sub-transistor structures and the corresponding sub-capacitor structures both include a part of the sub-semiconductor layer. Moreover, the bit line is electrically connected to the plurality of sub-transistor structures arranged at intervals along the third direction in the same transistor structure, and the sub-transistor structures correspond to the bit line contact layer one by one.

7. A method for forming a semiconductor structure, characterized in that, Including: Forming a transistor structure and a capacitor structure arranged in sequence along a first direction. The capacitor structure extends along the first direction, and the transistor structure includes a semiconductor layer that extends along the first direction. Forming a bit line contact layer, and the bit line contact layer is located on an end face of the semiconductor layer away from the capacitor structure. Forming a bit line, and the bit line extends along a third direction and covers an end face of the bit line contact layer away from the semiconductor layer, and at least covers a part of a side wall of the bit line contact layer extending along the first direction. Wherein, the bit line, the semiconductor layer, and the bit line contact layer are made of the same semiconductor material, and phosphorus is doped in the material of the bit line.

8. The forming method according to claim 7, characterized in that Using a selective epitaxial growth process to form the bit line contact layer on an end face of the semiconductor layer away from the capacitor structure.

9. The forming method according to claim 7, wherein The materials of the semiconductor layer and the bit line contact layer are silicon, and the material of the bit line is phosphorus-doped silicon.

10. The forming method according to any one of claims 7-9, characterized in that, Using a selective epitaxial growth process to form the bit line on an end face of the bit line contact layer.

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