Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a storage unit region; the selection gate structure is located on the substrate of the storage unit region; the floating gate structure is positioned on the substrate of the storage unit region at the side part of the selection gate structure, and is arranged at an interval with the selection gate structure; the control gate structure is positioned on the floating gate structure and is insulated from the floating gate structure; the drain region is located in the substrate of the storage unit region on one side, back to the floating gate structure, of the selection gate structure; the source region is located in the substrate of the storage unit region on one side, back to the selection gate structure, of the floating gate structure; the doped region is located at the bottom of the selection gate structure and in the substrate of the storage unit region close to one side of the floating gate structure; a gap is formed between the doped region and the source region, and the doped ion type of the doped region is opposite to the doped ion type of the drain region and the source region. According to the doping layer, electrons in the unselected storage unit region are difficult to enter the floating gate structure from the selection gate structure, so that programming errors are difficult to occur.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three major types: logic devices, memory devices, and analog circuits. Among them, memory devices account for a quite large proportion in integrated circuit products. With the development of semiconductor technology, for a more extensive application of memory devices, it is necessary to form the memory devices and other device areas on a chip simultaneously to form an embedded semiconductor memory device. For example, when embedding the memory device in a central processing unit, it is necessary to make the memory device compatible with the embedded central processing unit platform and maintain the specifications and corresponding electrical properties of the original memory device.

[0003] A non-volatile memory is a memory that can still retain the on-chip information after the power supply is turned off, including electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. The non-volatile memory has advantages such as system electrical erasability, repeatable programmability, low operating voltage, and low cost, making it widely used in various fields, such as embedded systems (including PCs, network interconnection devices, and instrumentation, etc.) and emerging voice, image, and data storage products, etc. Currently, flash memory has become the mainstream of non-volatile memory.

[0004] However, the performance of flash memory still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a memory cell region; a select gate structure located on the substrate of the memory cell region; a floating gate structure located on the substrate of the memory cell region at a side of the select gate structure and spaced from the select gate structure; a control gate structure located on the floating gate structure and insulated from the floating gate structure; a drain region located in the substrate of the memory cell region on a side of the select gate structure facing away from the floating gate structure; a source region located in the substrate of the memory cell region on a side of the floating gate structure facing away from the select gate structure; a doped region located at the bottom of the select gate structure and in the substrate of the memory cell region near the floating gate structure; there is a gap between the doped region and the source region, and the type of doping ions in the doped region is opposite to the type of doping ions in the drain region and the source region.

[0007] Optionally, along a direction perpendicular to the sidewall of the selection gate structure, the width of the doped region is 1 / 2 to 1 times the width of the selection gate structure.

[0008] Optionally, the doping ion concentration in the doped region is lower than that in the source region and lower than that in the drain region.

[0009] Optionally, the doping ion concentration in the doped region is 1.5×10 13 atom / cm 3 to 2.1×10 13 atom / cm 3 。

[0010] Optionally, the doping ion concentration in the source region is 1.5×10 15 atom / cm 3 to 2.5×10 15 atom / cm 3 and the doping ion concentration in the drain region is 2.0×10 13 atom / cm 3 to 3.0×10 13 atom / cm 3 。

[0011] Optionally, the number of the memory cell regions is multiple, and adjacent memory cell regions share a common source region.

[0012] Optionally, the semiconductor structure further includes: an erase gate structure located on the source region.

[0013] Optionally, in the same memory cell region, along a direction perpendicular to the sidewall of the selection gate structure, the distance between adjacent doped regions and the drain region is less than 1 / 2 of the width of the selection gate structure.

[0014] Optionally, in the same memory cell region, along a direction perpendicular to the sidewall of the selection gate structure, the distance between adjacent doped regions and the source region is the sum of the spacing between the adjacent floating gate structure and the selection gate structure and the width of the floating gate structure.

[0015] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, where the substrate includes a memory cell region; forming a selectively spaced selection gate structure and a floating gate structure on the substrate in the memory cell region, and forming a control gate structure on the floating gate structure, where the control gate structure is insulated from the floating gate structure; forming a drain region in the substrate of the memory cell region on a side of the selection gate structure facing away from the floating gate structure; forming a source region in the substrate of the memory cell region on a side of the floating gate structure facing away from the selection gate structure; forming a doped region in the substrate of the memory cell region at the bottom of the selection gate structure and close to the floating gate structure, where there is a gap between the doped region and the source region, and the type of doping ions in the doped region is opposite to the type of doping ions in the drain region and the source region.

[0016] Optionally, in the step of forming the doped region, the doped region is formed by ion implantation; when the implanted ions are P-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV; when the implanted ions are N-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV.

[0017] Optionally, in the step of providing the substrate, the number of the memory cell regions is multiple; in the step of forming the source region, adjacent memory cell regions share the source region.

[0018] Optionally, in the step of forming the doped region, along a direction perpendicular to the sidewall of the floating gate structure, the width range of the doped region is 1 / 2 times to 1 times the width of the selection gate structure.

[0019] Optionally, in the step of forming the selection gate structure, an erase gate structure is formed on the source region, and the erase gate structure is spaced from the floating gate structure.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] In the semiconductor structure provided by an embodiment of the present invention, a doped region is formed in the substrate of the storage cell region on one side of the floating gate structure, and a source region is formed in the substrate of the storage cell region on the other side of the floating gate structure. The doping ion type of the source region is opposite to that of the doped region. A select gate structure is formed on the doped region, and a drain region is formed in the substrate of the storage cell region on the side of the select gate structure facing away from the floating gate structure. During writing, the number of inverted electrons in the source side injection (SSI) region is reduced due to the cancellation of positive and negative charges. Also, because the doped region has a certain width, in the unselected storage cell region, the depletion region at the position of the source region is elongated, and the pinch-off point moves in the direction of the drain region, that is, the pinch-off point is away from the substrate region between the floating gate structure and the select gate structure. As a result, in the unselected storage cell region, it is not easy for electrons to tunnel through the select gate structure, enter the substrate, and then enter the floating gate structure under the action of the transverse electric field acceleration of the source side injection. Therefore, programming errors are not likely to occur, and the performance of the semiconductor structure is correspondingly improved.

[0022] In the method for forming the semiconductor structure provided by an embodiment of the present invention, a doped region is formed in the substrate of the storage cell region on one side of the floating gate structure, and a source region is formed in the substrate of the storage cell region on the other side of the floating gate structure. The doping ion type of the source region is opposite to that of the doped region. A select gate structure is formed on the doped region, and a drain region is formed in the substrate of the storage cell region on the side of the select gate structure facing away from the floating gate structure. During writing, the number of inverted electrons in the source side injection (SSI) region is reduced due to the cancellation of positive and negative charges. Also, because the doped region has a certain width, in the unselected storage cell region, the depletion region at the position of the source region is elongated, and the pinch-off point moves in the direction of the drain region, that is, the pinch-off point is away from the substrate region between the floating gate structure and the select gate structure. As a result, in the unselected storage cell region, it is not easy for electrons to tunnel through the select gate structure, enter the substrate, and then enter the floating gate structure under the action of the transverse electric field acceleration of the source side injection. Therefore, programming errors are not likely to occur, and the performance of the semiconductor structure is correspondingly improved. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0024] Figure 2 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention;

[0025] Figures 3 to 7 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0026] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved. Figure 1 It is a structural diagram of a semiconductor structure.

[0027] refer to Figure 1 The semiconductor structure includes: a substrate 10, wherein the substrate 10 includes a memory cell region i′; a selection gate structure 11, located on the substrate 10 of the memory cell region i′; a floating gate structure 12, located on the substrate 10 of the memory cell region i′ at the side of the selection gate structure 11, and spaced apart from the selection gate structure 11; a control gate structure 13, located on the floating gate structure 12, and insulated from the floating gate structure 12; a drain region 14, located in the substrate 10 of the memory cell region i′ on the side of the selection gate structure 11 facing away from the floating gate structure 12; and a source region 15, located in the substrate 10 of the memory cell region i′ on the side of the floating gate structure 12 facing away from the selection gate structure 11.

[0028] Through research, it is found that the selection gate structure 11 is used to connect to the word line (word line). When writing, in the storage cell area connected to the same word line but not selected, there is usually a potential difference between the source area 15 and the drain area 14, which accordingly makes the substrate 10 of the storage cell area i′ located between the source area 15 and the drain area 14 and close to the side of the floating gate structure 12 also have a certain potential; and the potential of this area is often greater than the potential loaded on the selection gate structure 11, so that the electrons e in the selection gate structure 11 - It is easy to enter the substrate 10 of the storage cell area i′ close to the side of the floating gate structure 12 through the tunneling effect, and then enter the floating gate structure 12 from the substrate 10 of the storage cell area i′ through the lateral electric field acceleration of the small-scale integrated circuit, thereby causing programming errors, which correspondingly makes the performance of the semiconductor structure poor.

[0029] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a memory cell region; a select gate structure located on the substrate of the memory cell region; a floating gate structure located on the substrate of the memory cell region on the side of the select gate structure and spaced apart from the select gate structure; a control gate structure located on the floating gate structure and insulated from the floating gate structure; a drain region located in the substrate of the memory cell region on the side of the select gate structure facing away from the floating gate structure; a source region located in the substrate of the memory cell region on the side of the floating gate structure facing away from the select gate structure; a doped region located at the bottom of the select gate structure and in the substrate of the memory cell region close to the floating gate structure side; there is a gap between the doped region and the source region, and the type of doped ions in the doped region is opposite to the type of doped ions in the drain region and the source region.

[0030] In the semiconductor structure provided by the embodiment of the present invention, there is a doped region at the bottom of the select gate structure, and in the substrate of the memory cell region close to the floating gate structure side of the doped region. Since there is a doped region at the bottom of the select gate structure, and the type of doped ions in the doped region is opposite to the type of doped ions in the drain region and the source region, during writing, the number of inverted electrons in the source-side injection region decreases due to the cancellation of positive and negative charges. Also, because the doped region has a certain width, in the unselected memory cell region, the depletion region at the source region position is elongated, and the pinch-off point moves towards the drain region, that is, the pinch-off point moves away from the substrate region between the floating gate structure and the select gate structure. Thus, in the unselected memory cell region, it is not easy for electrons to tunnel through the select gate structure, enter the substrate, and then enter the floating gate structure under the action of the lateral electric field acceleration of the source-side injection. Therefore, it is not easy to occur programming errors, and the performance of the semiconductor structure is correspondingly improved.

[0031] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention with reference to the accompanying drawings.

[0032] Figure 2 It is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0033] Reference Figure 2, in this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a storage cell region i; a select gate (SG) structure 110, located on the substrate 100 in the storage cell region i; a floating gate (FG) structure 120, located on the substrate 100 in the storage cell region i on the side of the select gate structure 110, and spaced from the select gate structure 110; a control gate (CG) structure 130, located on the floating gate structure 120 and insulated from the floating gate structure 120; a drain region 140, located in the substrate 100 in the storage cell region i on the side of the select gate structure 110 facing away from the floating gate structure 120; a source region 150, located in the substrate 100 in the storage cell region i on the side of the floating gate structure 120 facing away from the select gate structure 110; a doped region 160, located at the bottom of the select gate structure 110 and in the substrate 100 in the storage cell region i near the floating gate structure 120; there is a gap between the doped region 160 and the source region 150, and the type of doping ions in the doped region 160 is opposite to the type of doping ions in the drain region 140 and the source region 150.

[0034] The substrate 100 is used to provide a process platform for the formation of the semiconductor structure.

[0035] In this embodiment, the substrate 100 is used to form MOS transistors and constitute a non-volatile memory.

[0036] Specifically, the non-volatile memory includes an electrically programmable read-only memory, an electrically erasable programmable read-only memory, a flash memory, etc. In this embodiment, the non-volatile memory is taken as an example of a flash memory for illustration.

[0037] In this embodiment, the material of the substrate 100 is silicon. In some other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0038] As an example, the substrate 100 is a planar substrate. In other embodiments, the substrate can also be a substrate with a channel raised structure.

[0039] The storage cell region i refers to the part of the substrate 100 used for storing data, and is usually used to form a storage cell. The storage cell region i usually has a specific storage cell structure and circuit design to meet the requirements of data storage.

[0040] In this embodiment, the number of the storage cell regions i is multiple.

[0041] The number of the storage cell regions i is multiple, which is convenient to meet the design requirements of data storage.

[0042] The selection gate structure 110 is used to determine the storage cell to be edited. For example, when writing data to the selected storage cell, an operating current is applied to the corresponding drain 140, and an operating voltage is applied to the corresponding selection gate structure 110, so that the MOS transistor corresponding to the selection gate structure 110 is in an on state.

[0043] In this embodiment, the selection gate structure 110 includes a first gate dielectric layer (not shown in the figure) located on the substrate 100 of the storage cell region i, and a selection gate electrode layer (not labeled) located on the first gate dielectric layer.

[0044] The first gate dielectric layer is used to isolate the selection gate electrode layer from the channel at its bottom.

[0045] It should be noted that the material of the first gate dielectric layer includes dielectric materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0046] It should also be noted that the material of the selection gate electrode layer includes one or more of polysilicon, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0047] The floating gate structure 120 can capture and store electrons, and after power-off, the electrons stored in the floating gate structure 120 will not be lost, thus realizing information storage.

[0048] In this embodiment, the floating gate structure 120 includes a second gate dielectric layer (not shown in the figure) located on the substrate 100 of the storage cell region i, and a floating gate layer (not labeled) located on the second gate dielectric layer.

[0049] The second gate dielectric layer is a tunnel oxide layer of the flash memory, which is used to achieve electrical isolation between the floating gate layer and the substrate 100, so that electrons enter the floating gate layer through the second gate dielectric layer by tunneling effect.

[0050] It should be noted that the material of the second gate dielectric layer includes dielectric materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0051] It should also be noted that the material of the floating gate layer includes polysilicon.

[0052] The control gate structure 130 is used to allow electrons to enter the floating gate structure 120 or to pull electrons out of the floating gate structure 120 during the process of data writing or erasing. When reading the flash memory, by applying a working voltage to the control gate structure 130, the on / off state of the channel region at the bottom of the floating gate structure 120 is controlled by the charged state of the floating gate structure 120.

[0053] In this embodiment, the control gate structure 130 includes a gate dielectric layer (not shown in the figure) located on the floating gate structure 120 and a control gate electrode layer (not labeled) located on the gate dielectric layer.

[0054] The gate dielectric layer is used for isolation between the floating gate structure 120 and the control gate electrode layer. Correspondingly, the control gate structure 130 is insulated from the floating gate structure 120.

[0055] It should be noted that the material of the gate dielectric layer is a dielectric material. As an example, the gate dielectric layer is an ONO (Oxide-Nitride-Oxide) structure, that is, the gate dielectric layer includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0056] It should also be noted that the material of the control gate electrode layer includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0057] In this embodiment, the semiconductor structure further includes: sidewalls (not shown in the figure), located on the sidewalls of the floating gate structure 120 and the control gate structure 130.

[0058] The sidewalls are used to protect the sidewalls of the select gate structure 110, the floating gate structure 120, and the control gate structure 130, and can also be used to define the positions of the drain region 140 and the source region 150.

[0059] It should be noted that the sidewalls can also be located on the sidewalls of the select gate structure 110. The sidewalls are used to protect the select gate structure 110 and can also be used to define the position of the drain region 140.

[0060] Specifically, the sidewalls can be a single-layer structure or a stacked structure; the material of the sidewalls includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0061] The drain region 140 and the source region 150 are used to provide a carrier source when the MOS transistor is operating.

[0062] In this embodiment, adjacent memory cell regions i share the source region 150.

[0063] Adjacent memory cell regions i sharing the source region 150 means that the source region 150 is located between adjacent floating gate structures 120 and at the junction of adjacent memory cell regions i, which is beneficial to saving the area of the semiconductor structure.

[0064] In this embodiment, the doped ions in the drain region 140 and the source region 150 can be P-type ions or N-type ions; the P-type ions include P, As, or Sb, and the N-type ions include B, Ga, or In.

[0065] It should be noted that the doped ion concentrations in the drain region 140 and the source region 150 should neither be too small nor too large. If the doped ion concentrations in the drain region 140 and the source region 150 are too small, it is easy for the MOS transistor to fail to meet the design requirements; if the doped ion concentrations in the drain region 140 and the source region 150 are too large, it is easy to increase the probability of the doped ions in the drain region 140 and the source region 150 diffusing into the channel region, which is not conducive to improving the short-channel effect of the semiconductor structure. Also, the doped ion concentration in the source region 150 is greater than that in the drain region 140, which is beneficial to realizing source-side injection. Therefore, in this embodiment, the doped ion concentration in the source region 150 is 1.5×10 15 atom / cm 3 to 2.5×10 15 atom / cm 3 ; the doped ion concentration in the drain region 140 is 2.0×10 13 atom / cm 3 to 3.0×10 13 atom / cm 3 .

[0066] The bottom of the selection gate structure 110 has a doped region 160, and the type of doping ions in the doped region 160 is opposite to that of the doping ions in the drain region 140 and the source region 150. During writing, the number of inverted electrons in the source-side injection region is reduced due to the cancellation of positive and negative charges. Also, because the doped region 160 has a certain width, in the unselected memory cell region i, the depletion region at the position of the source region 150 is elongated, and the pinch-off point moves towards the drain region 140, that is, the pinch-off point moves away from the substrate 100 region between the floating gate structure 120 and the selection gate structure 110. As a result, in the unselected memory cell region i, it is not easy for electrons to tunnel through the selection gate structure 110, enter the substrate 100, and then enter the floating gate structure 120 under the action of the lateral electric field acceleration of the source-side injection. Therefore, programming errors are not likely to occur, and the performance of the semiconductor structure is correspondingly improved.

[0067] For example: According to the value of the operating voltage applied to the selection gate structure 110 during writing, the concentration of the doping ions in the doped region 160 is correspondingly set, so as to further reduce the potential difference between the selection gate structure 110 and the substrate 100 below it.

[0068] It should be noted that along the direction perpendicular to the sidewall of the selection gate structure 110, the width w1 of the doped region 160 should not be too small or too large. If the width w1 of the doped region 160 is too small, it is likely that the effect of reducing the number of inverted electrons in the source-side injection region is not good, and it is also likely that in the unselected memory cell region i, the elongation of the depletion region at the position of the source region 150 and the movement of the pinch-off point towards the drain region are not ideal; if the width w1 of the doped region 160 is too large, it is likely that the distance between the doped region 160 and the source region 150 is too small, thereby increasing the difficulty for electrons to enter the floating gate structure 120 when the memory cell region i is selected. Therefore, in this embodiment, along the direction perpendicular to the sidewall of the selection gate structure 110, the width w1 of the doped region 160 ranges from 1 / 2 times to 1 times the width w2 of the selection gate structure 110.

[0069] It should also be noted that in the same memory cell region i, along the direction perpendicular to the sidewall of the selection gate structure 110, the distance between the adjacent doping region 160 and the drain region 140 should not be too large. If the distance between the adjacent doping region 160 and the drain region 140 is too large, it is likely to make the width w1 of the doping region 160 too small, thus increasing the difficulty of forming the doping region 160. Or, when the width w1 of the doping region 160 remains unchanged, it is likely to make the distance w4 between the doping region 160 and the source region 150 too small, thus increasing the difficulty for electrons to enter the floating gate structure 120 when the memory cell region i is selected. Therefore, in this embodiment, in the same memory cell region i, along the direction perpendicular to the sidewall of the selection gate structure 110, the distance w6 between the adjacent doping region 160 and the drain region 140 is less than 1 / 2 of the width w2 of the selection gate structure.

[0070] In this embodiment, the ion doping concentration of the doping region 160 is lower than that of the source region 150 and lower than that of the drain region 140. This is beneficial to reducing the voltage of the doping region 160, thereby further reducing the probability of programming errors.

[0071] It should be noted that the doping ion concentration of the doping region 160 should not be too small or too large. If the doping ion concentration of the doping region 160 is too small, the effect of reducing the number of inverted electrons in the source-side injection region is likely to be poor; if the doping ion concentration of the doping region 160 is too large, the probability of damage to the substrate 100 is likely to increase. Therefore, in this embodiment, the doping ion concentration of the doping region 160 is 1.5×10 13 atom / cm 3 to 2.1×10 13 atom / cm 3 .

[0072] It should also be noted that in the same storage cell region i, along the direction perpendicular to the side wall of the selection gate structure 110, the distance w4 between the adjacent doping region 160 and the source region 150 should not be too small or too large. If the distance w4 between the adjacent doping region 160 and the source region 150 is too small, it is easy to increase the difficulty for electrons to enter the floating gate structure 120 when the storage cell region i is selected; if the distance w4 between the adjacent doping region 160 and the source region 150 is too large, it is easy to make the width w1 of the doping region 160 too small, thus making the effect of reducing the number of inverted electrons in the source-side injection region poor. Therefore, in this embodiment, in the same storage cell region i, along the direction perpendicular to the side wall of the selection gate structure 110, the distance w4 between the adjacent doping region 160 and the source region 150 is: the sum of the spacing w5 between the adjacent floating gate structure 120 and the selection gate structure 110 and the width w3 of the floating gate structure 120.

[0073] In this embodiment, the semiconductor structure further includes: an erase gate structure 170 (Erase gate), located on the source region 150.

[0074] The erase gate structure 170 is used to implement signal erasure of the memory. By applying a high voltage to the end of the erase gate structure 170, a potential difference is created between the erase gate structure 170 and the floating gate structure 120, so that electrons in the floating gate structure 120 can be pulled into the erase gate structure 170 through the tunneling effect, thereby realizing signal erasure of the memory.

[0075] Correspondingly, the sidewall is also located on the sidewall of the erase gate structure 170. The sidewall is also used to protect the sidewall of the erase gate structure 170.

[0076] As an example, the material of the erase gate structure 170 includes polysilicon.

[0077] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention.

[0078] Refer to Figure 3 , provide a substrate 500, and the substrate 500 includes a storage cell region I.

[0079] The substrate 500 is used to provide a process platform for the subsequent formation of the semiconductor structure.

[0080] In this embodiment, the substrate 500 is used to form MOS transistors and constitute a non-volatile memory.

[0081] Specifically, the non-volatile memory includes electrically programmable read-only memory, electrically erasable programmable read-only memory, flash memory, etc. In this embodiment, the non-volatile memory is taken as an example of flash memory for illustration.

[0082] In this embodiment, the material of the substrate 500 is silicon. In some other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0083] As an example, the substrate 500 is a planar substrate. In other embodiments, the substrate can also be a substrate with a channel raised structure.

[0084] The storage unit area I refers to the part of the substrate 500 used for storing data, which is usually used to form storage units. The storage unit area I usually has a specific storage unit structure and circuit design to meet the requirements of data storage.

[0085] In this embodiment, in the step of providing the substrate 500, the number of the storage unit areas I is multiple.

[0086] The multiple number of the storage unit areas I is convenient to meet the design requirements of data storage.

[0087] Reference Figure 4 , a floating gate structure 520 is formed on the substrate 500 of the storage unit area I, and a control gate structure 530 is formed on the floating gate structure 520. The control gate structure 530 is insulated from the floating gate structure 520.

[0088] In this embodiment, the floating gate structure 520 includes a second gate dielectric layer (not shown in the figure) located on the substrate 500 of the storage unit area I and a floating gate layer (not labeled) located on the second gate dielectric layer.

[0089] The second gate dielectric layer serves as a tunneling oxide layer of the flash memory, which is used to achieve electrical isolation between the floating gate layer and the substrate 500, so that electrons can enter the floating gate layer via the second gate dielectric layer by using the tunneling effect.

[0090] It should be noted that the materials of the second gate dielectric layer include dielectric materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0091] It should also be noted that the material of the floating gate layer includes polysilicon.

[0092] The control gate structure 530 is configured to allow electrons to enter the floating gate structure 520 or to be pulled out of the floating gate structure 520 during the data writing or erasing process. When reading the flash memory, by applying an operating voltage to the control gate structure 530, the on / off state of the channel region at the bottom of the floating gate structure 520 is controlled by the charged state of the floating gate structure 520.

[0093] In this embodiment, the control gate structure 530 includes an inter-gate dielectric layer (not shown in the figure) located on the floating gate structure 520 and a control gate electrode layer (not labeled) located on the inter-gate dielectric layer.

[0094] The inter-gate dielectric layer is used for isolating the floating gate structure 520 and the control gate electrode layer. Correspondingly, the control gate structure 530 is insulated from the floating gate structure 520.

[0095] It should be noted that the material of the inter-gate dielectric layer is a dielectric material. As an example, the inter-gate dielectric layer has an ONO (Oxide-Nitride-Oxide) structure, and the inter-gate dielectric layer includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0096] It should also be noted that the material of the control gate electrode layer includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0097] It should be noted that the forming method may further include: forming sidewalls (not shown in the figure) on the sidewalls of the floating gate structure 520 and the control gate structure 530.

[0098] The sidewalls are used to protect the sidewalls of the floating gate structure 520 and the control gate structure 530, and can also be used to define the position of the subsequent source region.

[0099] Specifically, the sidewall can be a single-layer structure or a stacked structure; the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitroxide, silicon oxynitride, boron nitride, and boron carbonitride.

[0100] Reference Figure 5 , a doped region 560 is formed in the substrate 500 of the storage cell region I on one side of the floating gate structure 520.

[0101] A doped region 560 is formed in the substrate 500 of the memory cell region I on one side of the floating gate structure 520, and a source region is formed in the substrate 500 of the memory cell region I on the other side of the floating gate structure 520. The doping ion type of the source region is opposite to that of the doped region. Subsequently, a select gate structure is formed on the doped region, and a drain region is formed in the substrate of the memory cell region on the side of the select gate structure facing away from the floating gate structure, such that during writing, the number of inverted electrons in the source-side injection region is reduced due to the cancellation of positive and negative charges. Also, because the doped region 560 has a certain width, in the unselected memory cell region I, the depletion region at the position of the source region 550 is elongated, and the pinch-off point moves towards the drain region 540, that is, the pinch-off point moves away from the substrate 500 region between the floating gate structure 520 and the select gate structure 510. As a result, in the unselected memory cell region I, it is not easy for electrons to tunnel through the select gate structure 510, enter the substrate 500, and then enter the floating gate structure 520 under the action of the lateral electric field acceleration of the source-side injection, and thus it is not easy to occur programming errors, correspondingly improving the performance of the semiconductor structure.

[0102] Subsequently, a select gate structure is formed on the doped region 560, and the concentration of the doping ions in the doped region 560 can be correspondingly set according to the value of the operating voltage applied to the select gate structure during writing, thereby further reducing the potential difference between the select gate structure and the substrate 500 below it.

[0103] It should be noted that along the direction perpendicular to the sidewall of the floating gate structure 520, the width W1 of the doped region 560 should not be too small or too large. If the width W1 of the doped region 560 is too small, it is likely that the effect of reducing the number of inverted electrons in the source-side injection region is not good, and it is also likely that in the unselected memory cell region I, the elongation of the depletion region at the position of the source region 550 and the movement of the pinch-off point towards the drain region 540 are not ideal; if the width W1 of the doped region 560 is too large, it is likely that the distance between the doped region 560 and the source region 550 is too small, thereby increasing the difficulty for electrons to enter the floating gate structure 510 when the memory cell region I is selected. Therefore, in this embodiment, in the step of forming the doped region 560, along the direction perpendicular to the sidewall of the floating gate structure 520, the width W1 of the doped region 560 ranges from 1 / 2 times to 1 times the width of the subsequently formed select gate structure.

[0104] In this embodiment, in the step of forming the doped region 560, the doped region 560 is formed by ion implantation. When the implanted ions are P-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV. When the implanted ions are N-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV.

[0105] It should be noted that the energy of the ion implantation should not be too small or too large. If the energy of the ion implantation is too small, it is easy to make the depth of the doped region 560 too small, so that the effect of reducing the number of inverted electrons in the source-side injection region is not good. If the energy of the ion implantation is too large, the probability of damage to the substrate 500 is increased. Therefore, in this embodiment, when the implanted ions are P-type ions, the energy of the ion implantation is 50 keV to 70 keV. When the implanted ions are N-type ions, the energy of the ion implantation is 50 keV to 70 keV.

[0106] It should also be noted that the doping ion concentration of the doped region 560 should not be too small or too large. If the doping ion concentration of the doped region 560 is too small, the effect of reducing the number of inverted electrons in the source-side injection region is not good. If the doping ion concentration of the doped region 560 is too large, the probability of damage to the substrate 500 is increased. Therefore, in this embodiment, the doping ion concentration of the doped region 560 is 1.5×10 13 atom / cm 3 to 2.1×10 13 atom / cm 3 .

[0107] Continuing to refer to Figure 5 , a source region 550 is formed in the substrate 500 of the storage unit area I on the other side of the floating gate structure 520. There is a gap between the source region 550 and the doped region 560. The type of doping ions in the source region 550 is opposite to that of the doped region 560.

[0108] The source region 550 and the drain region are used to provide a carrier source when the MOS transistor is working.

[0109] In this embodiment, the doping ions in the source region 550 and the drain region can be P-type ions or N-type ions. The P-type ions include P, As or Sb, and the N-type ions include B, Ga or In.

[0110] In this embodiment, in the step of forming the source region 550, the source region 550 is formed by ion implantation. When the implanted ions are P-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 30 keV to 50 keV. When the implanted ions are N-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 30 keV to 50 keV.

[0111] It should be noted that in the step of forming the source region 550, the energy of the ion implantation should not be too small or too large. If the energy of the ion implantation is too small, it is easy to make the depth of the source region 550 too small, so that it is easy for the MOS transistor to fail to meet the design requirements. If the energy of the ion implantation is too large, it is easy to make the depth of the source region 550 too large, so that it is also easy for the MOS transistor to fail to meet the design requirements. Therefore, in this embodiment, when the implanted ions are P-type ions, the energy of the ion implantation is 30 keV to 50 keV. When the implanted ions are N-type ions, the energy of the ion implantation is 30 keV to 50 keV.

[0112] It should also be noted that the doping ion concentration of the source region 550 should not be too small or too large. If the doping ion concentration of the source region 550 is too small, it is easy for the MOS transistor to fail to meet the design requirements. If the doping ion concentration of the source region 550 is too large, it is easy to increase the probability of the doping ions in the source region 550 diffusing into the channel region, which is not conducive to improving the short-channel effect of the semiconductor structure. Therefore, in this embodiment, the doping ion concentration of the source region 550 is 1.5×10 15 atom / cm 3 to 2.5×10 15 atom / cm 3 .

[0113] In this embodiment, in the step of forming the source region 550, adjacent memory cell regions I share the source region 550.

[0114] Adjacent memory cell regions I sharing the source region 550 is beneficial to saving the area of the semiconductor structure.

[0115] In this embodiment, the source region 550 can be formed after the doping region 560 is formed, or the doping region 560 can be formed after the source region 550 is formed.

[0116] Reference Figure 6 , a selection gate structure 510 is formed on the doping region 560, and the selection gate structure 510 and the floating gate structure 520 are arranged at intervals.

[0117] The selection gate structure 510 is used to determine the memory cells to be edited. For example, when writing data to the selected memory cells, an operating current is applied to the corresponding drain, and an operating voltage is applied to the corresponding selection gate structure 510, so that the MOS transistor corresponding to the selection gate structure 510 is in an on state.

[0118] In this embodiment, the selection gate structure 510 includes a first gate dielectric layer (not shown in the figure) on the substrate 500 in the memory cell region I, and a selection gate electrode layer (not labeled) on the first gate dielectric layer.

[0119] The first gate dielectric layer is used to isolate the selection gate electrode layer from the channel at its bottom.

[0120] It should be noted that the material of the first gate dielectric layer includes dielectric materials such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0121] It should also be noted that the material of the selection gate electrode layer includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0122] The floating gate structure 520 can capture and store electrons, and after power-off, the electrons stored in the floating gate structure 520 will not be lost, thus realizing information storage.

[0123] It should be noted that the width W1 of the doping region 560 is 1 / 2 to 1 times the width W2 of the selection gate structure; correspondingly, the width W2 of the selection gate structure is 1 to 2 times the width W1 of the doping region 560.

[0124] In the same memory cell region I, along the direction perpendicular to the sidewall of the selection gate structure 510, the distance W4 between the adjacent doping region 560 and the source region 550 should not be too small or too large. If the distance W4 between the adjacent doping region 560 and the source region 550 is too small, it is easy to increase the difficulty of electrons entering the floating gate structure 520 when the memory cell region I is selected; if the distance W4 between the adjacent doping region 560 and the source region 550 is too large, it is easy to make the width W1 of the doping region 560 too small, thus making the effect of reducing the number of inverted electrons in the source-side injection region poor. Therefore, in this embodiment, in the same memory cell region I, along the direction perpendicular to the sidewall of the selection gate structure 510, the distance W4 between the adjacent doping region 560 and the source region 550 is: the sum of the spacing W5 between the adjacent floating gate structure 520 and the selection gate structure 510 and the width W3 of the floating gate structure 520.

[0125] In this embodiment, in the step of forming the select gate structure 510, an erase gate structure 570 is formed on the source region 550, and the erase gate structure 570 is disposed at an interval from the floating gate structure 520.

[0126] The erase gate structure 570 is used to implement signal erasure of the memory. By applying a high voltage to the end of the erase gate structure 570, a potential difference exists between the erase gate structure 570 and the floating gate structure 520, so that electrons in the floating gate structure 520 can be pulled into the erase gate structure 570 through the tunneling effect, thereby realizing signal erasure of the memory.

[0127] As an example, the material of the erase gate structure 570 includes polysilicon.

[0128] In other embodiments, the select gate structure and the erase gate structure may also be formed in different steps. Specifically, after the doped region is formed, the select gate structure is formed; after the source region is formed, the erase gate structure is formed.

[0129] In this embodiment, after the select gate structure 510, the floating gate structure 520, the control gate structure 530, and the erase gate structure 570 are formed, it may further include: forming a spacer (not shown in the figure) on the sidewall of the select gate structure 510.

[0130] For example, a spacer may be formed on the sidewall of the select gate structure 510 on the side facing away from the floating gate structure 520.

[0131] The spacer is used to protect the sidewall of the select gate structure 510 and can also be used to define the position of the subsequent drain region. Specifically, the spacer may be a single-layer structure or a stacked structure; the material of the spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0132] Reference Figure 7 , a drain region 540 is formed in the substrate 500 of the memory cell region I on the side of the select gate structure 510 facing away from the floating gate structure 520.

[0133] In this embodiment, in the step of forming the drain region 540, the drain region 540 is formed by ion implantation; when the implanted ions are P-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 12 keV to 18 keV; when the implanted ions are N-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 12 keV to 18 keV.

[0134] In the step of forming the drain region 540, the energy of ion implantation should not be too small or too large. The reasons why the energy of ion implantation should not be too small or too large are similar to those in the step of forming the source region 550, and will not be elaborated here.

[0135] It should be noted that the doping ion concentration of the drain region 540 should not be too small or too large. The reasons why the doping ion concentration of the drain region 540 should not be too small or too large are similar to those in the step of forming the source region 550, so they will not be elaborated here. Moreover, the doping ion concentration of the drain region 540 is less than that of the source region 550, that is, the doping ion concentration of the source region 550 is greater than that of the drain region 540, which is conducive to realizing source-side injection. Therefore, in this embodiment, the doping ion concentration of the drain region 540 is 2.0×10 13 atom / cm 3 to 3.0×10 13 atom / cm 3 .

[0136] In this embodiment, the ion doping concentration of the doping region 560 is lower than that of the source region 550, and the ion doping concentration of the doping region 560 is lower than that of the drain region 540.

[0137] The ion doping concentration of the doping region 560 being lower than that of the source region 550 and lower than that of the drain region 540 is conducive to reducing the voltage of the doping region 560, thereby being conducive to further reducing the probability of programming errors.

[0138] It should be noted that in the same memory cell region I, along the direction perpendicular to the sidewall of the select gate structure 510, the distance between adjacent doping regions 560 and drain regions 540 should not be too large. If the distance between adjacent doping regions 560 and drain regions 540 is too large, it is easy to make the width W1 of the doping region 560 too small, thus increasing the difficulty of forming the doping region 560. Or, when the width W1 of the doping region 560 remains unchanged, it is easy to make the distance W4 between the doping region 560 and the source region 550 too small, thus making it difficult for electrons to enter the floating gate structure 520 when the memory cell region I is selected. Therefore, in this embodiment, in the same memory cell region I, along the direction perpendicular to the sidewall of the select gate structure 510, the distance W6 between adjacent doping regions 560 and drain regions 540 is less than 1 / 2 of the width W2 of the select gate structure.

[0139] It should also be noted that the semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For a specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate comprising a memory cell region; A select gate structure located on the substrate of the memory cell region; A floating gate structure located on the substrate of the memory cell region on the side of the select gate structure and spaced apart from the select gate structure; A control gate structure located on the floating gate structure and insulated from the floating gate structure; A drain region located in the substrate of the memory cell region on the side of the select gate structure facing away from the floating gate structure; A source region located in the substrate of the memory cell region on the side of the floating gate structure facing away from the select gate structure; A doped region located at the bottom of the select gate structure and in the substrate of the memory cell region close to the side of the floating gate structure; there is a gap between the doped region and the source region, and the type of doped ions in the doped region is opposite to the type of doped ions in the drain region and the source region.

2. The semiconductor structure according to claim 1, wherein Along a direction perpendicular to the sidewall of the select gate structure, the width of the doped region is 1 / 2 to 1 times the width of the select gate structure.

3. The semiconductor structure according to claim 1, wherein The doped ion concentration in the doped region is lower than the doped ion concentration in the source region, and the doped ion concentration in the doped region is lower than the doped ion concentration in the drain region.

4. The semiconductor structure according to claim 3, wherein, The doping ion concentration of the doped region is 1.5×10 13 atom / cm 3 to 2.1×10 13 atom / cm 3 .

5. The semiconductor structure according to claim 3, wherein, The doping ion concentration of the source region is 1.5×10 15 atom / cm 3 to 2.5×10 15 atom / cm 3 , and the doping ion concentration of the drain region is 2.0×10 13 atom / cm 3 to 3.0×10 13 atom / cm 3 .

6. The semiconductor structure according to claim 1, wherein The number of the memory cell regions is multiple, and adjacent memory cell regions share a source region.

7. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: an erase gate structure located on the source region.

8. The semiconductor structure according to claim 1, wherein In the same memory cell region, along a direction perpendicular to the sidewall of the select gate structure, the distance between the adjacent doped region and the drain region is less than 1 / 2 of the width of the select gate structure.

9. The semiconductor structure according to claim 1, wherein In the same memory cell region, along a direction perpendicular to the sidewall of the select gate structure, the distance between the adjacent doped region and the source region is the sum of the spacing between the adjacent floating gate structure and the select gate structure and the width of the floating gate structure.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate comprising a memory cell region; Forming a floating gate structure on the substrate of the memory cell region, and forming a control gate structure on the floating gate structure, the control gate structure being insulated from the floating gate structure; Forming a doped region in the substrate of the memory cell region on one side of the floating gate structure; Forming a source region in the substrate of the memory cell region on the other side of the floating gate structure, there is a gap between the source region and the doped region, and the type of doped ions in the source region is opposite to the type of doped ions in the doped region; Forming a select gate structure on the doped region, the select gate structure being spaced apart from the floating gate structure; Forming a drain region in the substrate of the memory cell region on the side of the select gate structure facing away from the floating gate structure.

11. The method for forming a semiconductor structure according to claim 10, wherein, In the step of forming the doped region, the doped region is formed by ion implantation; When the implanted ions are P-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV; When the implanted ions are N-type ions, the parameters of the ion implantation include: the energy of the ion implantation is 50 keV to 70 keV.

12. The method for forming a semiconductor structure according to claim 10, wherein, In the step of providing the substrate, the number of the memory cell regions is multiple; In the step of forming the source region, adjacent memory cell regions share a source region.

13. The method for forming a semiconductor structure according to claim 10, wherein, In the step of forming the doped region, in a direction perpendicular to the sidewall of the floating gate structure, the width range of the doped region is from 1 / 2 times to 1 time the width of the select gate structure.

14. The method for forming a semiconductor structure according to claim 10, wherein, In the step of forming the select gate structure, an erase gate structure is formed on the source region, and the erase gate structure is spaced apart from the floating gate structure.

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