Self-aligned trench bottom protection region for trench gate metal oxide semiconductor field effect transistor

Abstract

The invention relates to a self-aligned trench bottom protection region for trench gate metal oxide semiconductor field effect transistors. A trench gate MOSFET and a method of forming a self-aligned trench bottom protection region at a bottom surface of a trench gate in the trench gate MOSFET are provided. The method includes forming a semiconductor source region having a first conductivity type within a semiconductor body region having a second conductivity type, the semiconductor body region separating the semiconductor source region from the semiconductor epitaxial layer. The method further includes etching a trench gate opening in the exposed surface of the semiconductor source region, wherein a bottom surface of the trench gate opening is within the semiconductor epitaxial layer. The method further includes implanting a shielding dopant having a second conductivity type through a channel implantation process. During the channel implantation process, the exposed surface of the semiconductor source region is exposed to the shielding dopant, and the shielding dopant forms a trench bottom protection region at the bottom surface of the trench gate opening.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to trench gate metal oxide semiconductor field effect transistor (MOSFET) devices, and more particularly, to forming a trench bottom protection region at a bottom surface of a trench gate of a trench gate MOSFET. Background Art

[0002] A trench gate MOSFET includes a trench gate that is vertically positioned in a semiconductor material to conduct and turn off current passing through the MOSFET. Certain advantages can be achieved by utilizing a trench gate MOSFET. Among them, the trench gate configuration particularly enables the fabrication of higher density MOSFET devices on a semiconductor substrate. In addition, adjacent cells can be easily connected to operate in parallel. Trench gate MOSFETs have been shown to exhibit further advantages such as low specific on-resistance, high power density, fast switching speed, and low switching loss. Such advantages make trench gate MOSFETs a promising solution in semiconductor devices.

[0003] The applicant has discovered many technical challenges and difficulties associated with the fabrication and operation of trench gate MOSFETs. Through application of effort, ingenuity, and innovation, the applicant has solved problems related to the fabrication and operation of trench gate MOSFETs embodied in the present disclosure, which will be described in detail hereinafter. Summary of the Invention

[0004] Various embodiments are directed to example methods for forming a self-aligned trench bottom protection region at a bottom surface of a trench gate in a trench gate MOSFET. In some embodiments, the method may include forming a semiconductor body region at a top surface of and within a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes a first conductivity type and the semiconductor body region includes a second conductivity type. The method further includes forming a semiconductor source region within the semiconductor body region, wherein the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer, and the semiconductor source region includes the first conductivity type. The method further includes etching a trench gate opening in an exposed surface of the semiconductor source region, wherein the trench gate opening includes a bottom surface, and the bottom surface includes the semiconductor epitaxial layer. The method further includes injecting a shield dopant having a second conductivity type through a channel implantation process, wherein an exposed surface of the semiconductor source region is exposed to the shield dopant during the channel implantation process, and the shield dopant forms a trench bottom protection region at the bottom surface of the trench gate opening.

[0005] In some embodiments, the channel implantation process accelerates the shield dopant toward the MOSFET device with low ion energy.

[0006] In some embodiments, the low ion energy is between 30 keV and 3000 keV.

[0007] In some embodiments, the channel implantation process accelerates the shield dopant towards the MOSFET device at an implantation angle, where the implantation angle is measured with respect to the normal direction of the surface of the MOSFET device.

[0008] In some embodiments, the implantation angle is between 3.5 degrees and 4.5 degrees.

[0009] In some embodiments, the method further includes forming a body contact region of a second conductivity type within the semiconductor source region, where the body contact region is electrically coupled to the semiconductor body region.

[0010] In some embodiments, the body contact region is doped at a body contact doping concentration.

[0011] In some embodiments, the semiconductor body region is doped at a semiconductor body concentration.

[0012] In some embodiments, the body contact doping concentration is greater than the semiconductor body concentration.

[0013] In some embodiments, the first conductivity type is an n-type semiconductor.

[0014] In some embodiments, the second conductivity type is a p-type semiconductor.

[0015] In some embodiments, the semiconductor epitaxial layer is doped at a first doping concentration.

[0016] In some embodiments, the semiconductor source region is doped at a second doping concentration.

[0017] In some embodiments, the first doping concentration is less than the second doping concentration.

[0018] In some embodiments, the semiconductor source region is formed using an ion implantation process.

[0019] In some embodiments, the source region lattice structure of the semiconductor source region is deliberately damaged during the ion implantation process.

[0020] In some embodiments, the body contact region is formed using an ion implantation process.

[0021] In some embodiments, the body contact region lattice structure of the body contact region is deliberately damaged during the ion implantation process.

[0022] An example trench gate MOSFET device is also provided. The example trench gate MOSFET device includes: a semiconductor body region including a first conductivity type; a semiconductor source region formed at a top surface of the semiconductor body region and including a second conductivity type; and a semiconductor epitaxial layer including the second conductivity type, wherein the semiconductor epitaxial layer is separated from the semiconductor source region by the semiconductor body region. The example trench gate MOSFET device further includes a trench gate opening etched in an exposed surface of the semiconductor source region, wherein the trench gate opening includes a bottom surface, and wherein the bottom surface includes the semiconductor epitaxial layer. The example trench gate MOSFET device further includes a trench bottom protection region formed in the semiconductor epitaxial layer at the bottom surface of the trench gate opening, wherein the trench gate opening is formed by injecting a shielding dopant of the second conductivity type through a channel implantation process, wherein the exposed surface of the semiconductor source region is exposed to the shielding dopant during the channel implantation process, and wherein the shielding dopant forms the trench bottom protection region at the bottom surface of the trench gate opening.

[0023] A process product of the example trench gate MOSFET device is also provided. The example MOSFET device is produced by a method including forming a semiconductor body region at a top surface of and within the semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes the first conductivity type and the semiconductor body region includes the second conductivity type. The method further includes forming a semiconductor source region within the semiconductor body region, wherein the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer and the semiconductor source region includes the first conductivity type. The method further includes etching a trench gate opening in an exposed surface of the semiconductor source region, wherein the trench gate opening includes a bottom surface and the bottom surface includes the semiconductor epitaxial layer. The method further includes injecting a shielding dopant of the second conductivity type through a channel implantation process, wherein the exposed surface of the semiconductor source region is exposed to the shielding dopant during the implantation process, and the shielding dopant forms the trench bottom protection region at the bottom surface of the trench gate opening. Description of the Drawings

[0024] Reference will now be made to the drawings. Some of the components shown in the figures may or may not be present in certain embodiments described herein. According to example embodiments of the present disclosure, some embodiments may include fewer (or more) components than those shown in the figures.

[0025] Figure 1 A cross-sectional view of an example trench gate MOSFET device including a trench bottom protection region, in accordance with an example embodiment of the present disclosure, is illustrated.

[0026] Figure 2Illustrated is a less desirable example method that requires a hard mask to implant a trench bottom protection region at the bottom of a trench gate in an example trench gate MOSFET.

[0027] Figures 3A to 3D A cross-sectional view of an example process for manufacturing a trench gate MOSFET according to an example embodiment of the present disclosure is illustrated.

[0028] Figure 4 An example channel implantation process on an example silicon carbide lattice structure according to an example embodiment of the present disclosure is depicted.

[0029] Figure 5 An example flowchart is depicted that illustrates a process for forming a self-aligned trench bottom protection region at the bottom surface of a trench gate of a trench gate MOSFET according to an example embodiment of the present disclosure. Detailed Description

[0030] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention of the present disclosure are shown. In fact, the embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals always refer to like elements.

[0031] As used herein, in the examples provided below, for purposes of explanation, terms such as "front", "rear", "back", "top", "vertical", "horizontal", "above", "below", "over", "under" are used to describe the relative position of certain components or portions of components with respect to a local reference frame of a diode with respect to an arbitrary global reference frame.

[0032] In some examples, a Cartesian (three-axis) reference frame is provided. Unless otherwise specified, generally, the positive y-direction corresponds to "up", "above", or "top". Conversely, the negative y-direction corresponds to "down", "below", "under", or "lower".

[0033] Various example embodiments address technical problems associated with forming a trench bottom protection region on the bottom surface of a trench gate opening in a trench gate MOSFET device. As will be understood by those skilled in the art in the field of the present disclosure, there are many example scenarios in which a user may need to form a trench gate protection region to protect components of a trench gate MOSFET from a damaging electric field.

[0034] Now referring to Figure 1 , an example trench gate MOSFET 100 is provided. As Figure 1Depicted therein, a doped semiconductor body region 112 having a first doping type (e.g., p-type) and a heavily doped semiconductor source region 104 having a second doping type (e.g., n-type) are formed on a semiconductor epitaxial layer 110. A trench gate opening is etched in the surface of the semiconductor source region 104 such that the bottom surface of the trench gate opening reaches the semiconductor epitaxial layer 110. The trench gate opening is coated with a dielectric layer (e.g., oxide layer 116) and filled with a conductive material (such as polysilicon) to produce a trench gate 102. As Figure 1 Further depicted therein, the semiconductor source region 104 is electrically coupled to a source conductive contact 106, while a semiconductor substrate region 114 on the surface of the semiconductor epitaxial layer 110 opposite the semiconductor body region 112 is electrically coupled to a conductive drain layer 108.

[0035] During operation, changing the voltage of the trench gate 102 changes the electron density at the surface of the trench gate 102. The change in electron density enables or disables current to flow through the semiconductor body region 112. Thus, current is allowed to flow vertically through the trench gate MOSFET 100, between the source conductive contact 106 and the conductive drain layer 108.

[0036] Trench gate MOSFETs are widely used in electrical devices, especially in high-power applications. Compared to planar gate MOSFETs, the main advantage of a trench gate MOSFET (such as, Figure 1 the exemplary trench gate MOSFET 100 depicted therein) is the reduction in on-resistance. The reduction in on-resistance enables the trench gate MOSFET to operate more efficiently by reducing the voltage drop across the trench gate MOSFET. Due to the vertical configuration of the trench gate MOSFET, a greater density of MOSFET devices can be fabricated on an electrical device. Additionally, adjacent cells can be connected to operate in parallel. The trench gate MOSFET is also shown to exhibit high power density, fast switching speed, and low switching losses, making the trench gate MOSFET a common solution in semiconductor devices.

[0037] In some embodiments, the semiconductor substrate region 114 and the semiconductor epitaxial layer 110 may include silicon carbide (SiC). SiC substrates can provide several benefits, especially in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more tolerant of higher frequencies, have low reverse leakage current and power dissipation, be more stable over a wide temperature range, have lower electromagnetic radiation, and provide other related advantages.

[0038] In some examples, the trench gate MOSFET 100 may experience a high electric field at the dielectric layer of the trench gate 102. This high electric field may be particularly strong between the bottom surface of the trench gate 102 and the semiconductor epitaxial layer 110, especially at the corners of the trench gate 102 and at the contact surface between the semiconductor body region 112 and the trench gate 102. As Figure 1 depicted, an oxide layer 116 is deposited between the trench gate 102 and the surrounding semiconductor layers. The high electric field in the oxide layer 116 can cause dielectric breakdown in the oxide layer 116. The breakdown of the oxide layer 116 can have an adverse effect on the performance of the trench gate MOSFET 100.

[0039] Due to the increased electric field in the oxide layer 116 at the bottom surface of the trench gate 102, many trench gate MOSFET devices 100 require a shielding region to be placed at the bottom surface of the trench gate 102. The shielding region protects the oxide layer 116 from excessive and damaging electric fields. Additionally, the shielding region is used to shield the semiconductor body region 112 from the high potential difference that may exist between the conductive drain layer 108 and the source conductive contact 106. Thus, the shielding region can prevent excessive depletion in the body layer, which enhances the blocking ability of the body layer during operation.

[0040] Now referring to Figure 2 , in a less desirable process, shielding regions 220a, 220b can be formed at the bottom surfaces of trench gate openings 222a, 222b by protecting the top surface of the semiconductor device 200 with a hard mask 224 and performing ion implantation using a high energy implantation process 226.

[0041] As Figure 2 depicted, the hard mask 224 is deposited on the top layer of the semiconductor device 200 (including the semiconductor source region 204). To create the trench gates of the trench gate MOSFET, the trench gate openings 222a, 222b are etched through the hard mask 224, the semiconductor source region 204, the semiconductor body region 212, and into the semiconductor epitaxial layer 210. The hard mask 224 provides a protective coating for the components of the semiconductor device 200 (e.g., the semiconductor source region 204) during the damaging high energy implantation process 226.

[0042] An undesirable method of forming the shielding regions 220a, 220b at the bottom surfaces of the trench gate openings 222a, 222b using the high-energy implantation process 226 may have several disadvantages. During the high-energy implantation process 226, certain types of dopants (e.g., arsenic, phosphorus, boron, etc.) are accelerated in the high-energy beam. In some embodiments, the energy used to accelerate the dopants may be between 1000 keV and 3000 keV. The high-energy ion beam is directed towards the surface of the semiconductor device 200. In the portions of the semiconductor device 200 that are not protected by a protective coating (e.g., the hard mask 224), such as the bottom surfaces of the trench gate openings 222a, 222b, the accelerated ions in the high-energy beam penetrate the surface of the semiconductor.

[0043] In addition to the high energy (1000 keV - 3000 keV) associated with the high-energy implantation process 226, the high-energy implantation process may also be performed at a high temperature (e.g., between 300 degrees Celsius and 500 degrees Celsius). The high energy of the accelerated ions and the high temperature can be damaging to any exposed surface of the semiconductor device 200. Furthermore, the high-energy implantation process 226 may penetrate the sidewalls of the trench gate openings 222a, 222b. This lateral spread of the dopants may have an adverse effect on the performance of the semiconductor device 200. The lateral spread is particularly problematic in the case of a reduced size of the semiconductor device 200. Therefore, the hard mask 224 is deposited on the surface of the semiconductor device 200 to protect the electrical characteristics of the components of the semiconductor device 200 from the accelerated ions in the high-energy implantation process 226.

[0044] The deposition and removal of the hard mask 224 may further cause damage to the surface of the semiconductor device 200 that is in contact with the hard mask 224. For example, the hard mask 224 may cause warping of the surface of the semiconductor source region 204 and other regions of the semiconductor device 200. The warping in the semiconductor source region 204 caused by the hard mask 224 may have many adverse effects on the performance of the semiconductor device 200. For example, the warping in the semiconductor source region 204 results in a non-uniform distribution of the implanted ions, especially in the case of using channel implantation. In addition, the deposition and removal of the hard mask may cause irreparable damage to the lattice structure of the contact regions of the semiconductor device 200, further having an adverse effect on the performance of the semiconductor device 200. Furthermore, the deposition and removal of the hard mask 224 may change the electrical characteristics of the surface of the semiconductor device 200. The change in the electrical characteristics of the components of the semiconductor device may further have an adverse effect on the performance of the semiconductor device 200.

[0045] In addition, the use of the hard mask 224 may limit the critical dimension of the trench gate. For example, the hard mask 224 may be etched to form an opening in the hard mask, and the trench gate opening may be formed within the opening. The minimum size of the opening in the hard mask may be limited based on the hard mask etching accuracy. Accordingly, the minimum size of the trench gate opening may be limited. This characteristic may become a problem when manufacturers seek to further reduce the size of the trench gate MOSFET and, thus, the size of the trench gate including the trench gate MOSFET.

[0046] The various example embodiments described herein utilize various techniques to form a trench bottom protection region at the bottom surface of the trench gate opening of a trench gate MOSFET. For example, in some embodiments, the exposed surface of the trench gate MOSFET may be deliberately damaged, causing the lattice structure of the semiconductor structure (e.g., silicon carbide) to break. The broken lattice structure may minimize the penetration of implanted ions during an ion implantation process, especially when compared to an undamaged semiconductor surface including an intact lattice structure.

[0047] Several techniques may be utilized to deliberately damage the exposed surface of a semiconductor device. For example, a region of the semiconductor device may be ionically heavily doped. The ion implantation process associated with doping, especially at high concentrations, may cause severe damage to the lattice structure of the doped region. Accordingly, semiconductor regions such as semiconductor source regions and body contact regions may be heavily doped to protect such surfaces from severe penetration during the implantation process associated with the formation of the trench bottom protection region. After the ion implantation process, an annealing process is performed to at least partially restore the electrical contact between the respective regions while the doped regions remain deliberately damaged.

[0048] In addition, a low-energy channel implantation process may be used to form the trench bottom protection region. The channel implantation process utilizes the architecture of the target semiconductor to maximize the implantation penetration at low energies. Such channel implantation may accelerate ions toward the target surface (e.g., the bottom surface of the trench gate opening) at a specific rotation and angle measured from the normal of the target surface. The rotation and angle are selected to maximize the penetration of the accelerated ions into the target surface. For example, by aligning the acceleration of the ions with the lattice structure of the semiconductor, the accelerated ions may experience fewer collisions and penetrate deeper into the lattice structure at a lower energy. In addition, the rotation and angle of the channel implantation process may be selected to reduce the impact with the nuclei of the crystal structure. The reduction in the impact with the nuclei of the crystal structure reduces the lateral spread or penetration of the ions into the sidewalls of the trench gate opening.

[0049] At the same time, penetration of low-energy implanted ions into damaged lattice structures (such as those in intentionally damaged regions) is restricted. As a result, deep penetration into the bottom surface of the trench gate opening occurs, and penetration into the intentionally damaged surface (such as the semiconductor source region) is minimized.

[0050] In addition, the low-energy channel implantation process can be performed at a lower temperature (such as room temperature or near room temperature). The reduction in temperature during the implantation process enables the use of simpler and less expensive equipment during semiconductor manufacturing.

[0051] Due to the example embodiments described herein, and in some examples, the manufacturing process associated with creating a trench bottom protection region at the bottom surface of a trench gate opening in a trench gate MOSFET has been greatly improved. For example, by using intentionally damaged regions, a trench bottom protection region can be formed at the bottom surface of the trench gate opening without a hard mask. Elimination of the need for a hard mask simplifies the difficult steps associated with alignment, deposition, and removal of the hard mask layer. In addition, the performance of the trench gate MOSFET produced using the process described herein can be greatly improved. Damage to the surface of the electrical components due to deposition and removal of the hard mask can be avoided. Avoiding such damage can greatly improve the reliability and performance of the trench gate MOSFET.

[0052] Now referring to Figures 3A to 3D , an example process for forming a trench bottom protection region at the bottom surface of a trench gate MOSFET is provided.

[0053] Now referring to Figure 3A , an example semiconductor device 300a during formation of a trench bottom protection region on the bottom surface of a trench gate opening in a trench gate MOSFET device is depicted. As depicted in Figure 3A , the example semiconductor device 300a includes a semiconductor substrate layer 314 having a top surface 314a and a bottom surface 314b. A semiconductor epitaxial layer 310 is formed on the top surface 314a, and a conductive drain layer 308 is formed on the bottom surface 314b opposite the semiconductor epitaxial layer 310. As further depicted in Figure 3A , a semiconductor body region 312 is formed at the top surface 310a of the semiconductor epitaxial layer 310. A semiconductor source region 304 is further formed on the top surface 312a of the semiconductor body region 312. A body contact region 330 is formed within the semiconductor source region 304 such that electrical contact is made between the semiconductor source region 304 and the semiconductor body region 312.

[0054] As in Figure 3AAs depicted, example semiconductor device 300a includes a semiconductor substrate layer 314. The semiconductor substrate layer 314 can be any semiconductor material that serves as a base layer for semiconductor components (e.g., trench gate MOSFETs). The semiconductor substrate layer 314 can include silicon, germanium, gallium arsenide, gallium nitride, silicon carbide (SiC), or other similar semiconductor materials. The semiconductor substrate layer 314 can be used as a base layer for epitaxial growth of additional semiconductor materials. Epitaxial growth can be used to grow additional crystalline layers (such as semiconductor epitaxial layer 310) on the semiconductor substrate layer 314.

[0055] In some embodiments, the semiconductor substrate layer 314 can include SiC. SiC can offer several advantages in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more tolerant of higher frequencies, have low reverse leakage current and power dissipation, be more stable across a wide temperature range, have lower electromagnetic radiation, and offer other related advantages.

[0056] In some embodiments, the semiconductor substrate layer 314 can be doped with a first dopant type to produce a semiconductor with a specific conductivity type. A dopant can be any impurity that is intentionally added to a semiconductor to modify its conductivity. Adding a dopant with extra valence electrons to the semiconductor substrate layer 314 results in an n-type doped semiconductor or n-doped semiconductor. Dopants with extra valence electrons can include phosphorus, arsenic, antimony, etc. Adding a dopant with a shortage of valence electrons to the semiconductor substrate layer 314 results in a p-type doped semiconductor or p-doped semiconductor. Dopants with a shortage of valence electrons can include boron, aluminum, gallium, etc. As Figure 3A shown, the semiconductor substrate layer 314 of example semiconductor device 300a is an n-type semiconductor substrate layer 314.

[0057] In some embodiments, the semiconductor substrate layer 314 can include a doping concentration. The doping concentration can refer to the number of impurities introduced into the semiconductor substrate layer 314 structure relative to the number of intrinsic semiconductor atoms. A high doping concentration means that a greater number of impurities are introduced into the semiconductor substrate layer 314 relative to the number of intrinsic semiconductor atoms. In some embodiments, the doping concentration of the semiconductor substrate layer 314 can be higher than the doping concentration of the semiconductor epitaxial layer 310.

[0058] As Figure 3AFurther depicted in FIG. [FIG. number not provided], example semiconductor device 300a includes a semiconductor epitaxial layer 310 on a top surface 314a of a semiconductor substrate layer 314. The semiconductor epitaxial layer 310 can be any semiconductor material configured such that current can flow from a semiconductor source region 304 to a conductive drain layer 308 due to the drift of majority carriers. When the gate voltage at the trench gate of a trench gate MOSFET exceeds a limit, the semiconductor epitaxial layer 310 enables current to flow from the semiconductor source region 304 to the conductive drain layer 308. Additionally, the semiconductor epitaxial layer 310 blocks or limits the flow of current in the reverse direction, e.g., from the conductive drain layer 308 to the semiconductor source region 304. As Figure 3A depicted in FIG. [FIG. number not provided], the doping type of the semiconductor epitaxial layer 310 is the same as the doping type of the semiconductor substrate layer 314 (e.g., an n-type semiconductor). As Figure 3A further depicted, the semiconductor epitaxial layer 310 can have a different doping concentration than the semiconductor substrate layer 314. For example, the semiconductor epitaxial layer 310 can have a lower doping concentration than the semiconductor substrate layer 314.

[0059] As Figure 3A Further depicted in FIG. [FIG. number not provided], example semiconductor device 300a includes a semiconductor body region 312. The semiconductor body region 312 can be any region positioned between the semiconductor source region 304 and the conductive drain layer 308 such that current flow between the semiconductor source region 304 and the conductive drain layer 308 is blocked when the voltage at the trench gate does not exceed a threshold voltage. The semiconductor body region 312 can be doped with a dopant type opposite to that of the semiconductor source region 304 and the semiconductor epitaxial layer 310. As Figure 3A depicted in FIG. [FIG. number not provided], the semiconductor body region 312 is a p-type semiconductor. As Figure 3A Further depicted, the semiconductor body region 312 can have a different doping concentration (e.g., a semiconductor body concentration) than the semiconductor body contact region 330. For example, the semiconductor body region 312 can have a lower doping concentration than the semiconductor body contact region 330. In some embodiments, the semiconductor body doping concentration can be between 1x10 17 ions per cubic centimeter and 1x10 22 ions per cubic centimeter; more preferably between 1.5x10 17 ions per cubic centimeter and 1.5x10 21 ions per cubic centimeter; most preferably between 1x10 18 ions per cubic centimeter and 1x10 21 ions per cubic centimeter.

[0060] As Figure 3AAs further depicted in, example semiconductor device 300a includes a body contact region 330. The body contact region 330 can be any region having the same doping type as the semiconductor body region 312 and is positioned such that electrical contact can be made with the semiconductor body region 312 from an external surface of the semiconductor device 300a. As Figure 3A depicted in, the semiconductor body contact region 330 can have a different doping concentration (e.g., body contact doping concentration) than the semiconductor body region 312. For example, the semiconductor body region 312 can have a lower doping concentration than the semiconductor body contact region 330. In some embodiments, the body contact doping concentration can be between 1x10 17 ions per cubic centimeter and 1x10 22 ions per cubic centimeter; more preferably between 1.5x10 17 ions per cubic centimeter and 1.5x10 21 ions per cubic centimeter; most preferably between 1x10 18 ions per cubic centimeter and 1x10 21 ions per cubic centimeter. The semiconductor body contact region 330 can enable a voltage to be applied to the semiconductor body region 312, thereby changing the electrical characteristics of the semiconductor device 300a (e.g., changing the barrier voltage of a transistor device).

[0061] In some embodiments, the semiconductor body contact region 330 can include a heavily doped semiconductor material having the same conductivity type (e.g., P+) as the semiconductor body region 312 and is formed using an ion implantation process. The ion implantation process can be any ion implantation process in which the surface of the semiconductor body contact region 330 is deliberately damaged. For example, ions can be accelerated toward the surface of the semiconductor body contact region 330 to change the electrical characteristics of the semiconductor body contact region 330. The accelerated ions will damage the lattice structure of the semiconductor base and remain within the semiconductor material. The damaged lattice structure increases the difficulty of subsequent implantation processes (e.g., formation of a trench bottom protection region) penetrating the semiconductor body contact region 330. In particular, compared to channel implantation in a semiconductor material having an intact lattice structure, ion implantation processes that rely on channels through the lattice structure of the semiconductor material cannot penetrate deeply into the semiconductor material. In some embodiments, ions used to produce n-type doping in a semiconductor material include phosphorus, arsenic, and antimony, etc. In some embodiments, ions used to produce p-type doping in a semiconductor material include boron, indium, aluminum, gallium, and thallium, etc.

[0062] As Figure 3AAs further depicted herein, the semiconductor device 300a includes a semiconductor source region 304. The semiconductor source region 304 can be any conductive material through which current enters the semiconductor device 300a, or equivalently, electrons leave the semiconductor device 300a. In some embodiments, the semiconductor source region 304 can be placed on top of the semiconductor body region 312 and can provide a conduction path from an external contact point through the semiconductor body region 312 to the semiconductor epitaxial layer 310. In a transistor semiconductor device, the semiconductor source region 304 can form a PN junction with the semiconductor body region 312.

[0063] As described herein, the semiconductor source region 304 can include heavily doped semiconductor material having the same conductivity type (e.g., N+) as the semiconductor epitaxial layer 310 and is formed using an ion implantation process. The ion implantation process can be any ion implantation process in which the surface of the semiconductor source region 304 is deliberately damaged. For example, ions can be accelerated towards the surface of the semiconductor source region 304 to change the electrical characteristics of the semiconductor source region 304. The accelerated ions damage the lattice structure of the semiconductor base and remain within the semiconductor material. The damaged lattice structure increases the difficulty of subsequent implantation processes (e.g., forming a trench bottom protection region) penetrating the semiconductor source region 304. In particular, compared to channel implantation in a semiconductor material having an intact lattice structure, an ion implantation process that relies on the lattice structure of the semiconductor material for the channel cannot penetrate deep into the semiconductor material. In some embodiments, the ions used to produce n-type doping in the semiconductor material include phosphorus, arsenic, and antimony, etc. In some embodiments, the ions used to produce p-type doping in the semiconductor material include boron, indium, aluminum, gallium, and thallium, etc.

[0064] As Figure 3A As further depicted herein, the semiconductor device 300a includes a conductive drain layer 308. The conductive drain layer 308 can be any conductive material (e.g., backside metal) through which current leaves the semiconductor device 300a, or equivalently, electrons enter the semiconductor device 300a through this conductive material. In some embodiments, the conductive drain layer 308 can include a metal or a combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the conductive drain layer 308 can be placed under the semiconductor substrate layer 314 and adjacent to the bottom surface of the semiconductor substrate layer 314. As Figure 3A As depicted herein, in some embodiments (such as trench gate MOSFETs), the conductive drain layer 308 can be shared by one or more adjacent trench gate MOSFET devices. Sharing the conductive drain layer 308 can enable a greater concentration of trench gate MOSFET devices in a given area.

[0065] Now refer toFigure 3B , an example semiconductor device 300b is provided that includes trench gate openings 322a and 322b, which have bottom surfaces 340a and 340b that include a semiconductor epitaxial layer 310.

[0066] As Figure 3B depicted, the example semiconductor device 300b includes trench gate openings 322a and 322b. The trench gate openings 322a and 322b are any channels, basins, chambers, holes, notches, grooves, or other trenches formed in the top surface 342 of the semiconductor device 300b and are configured to receive a conductive material (such as polysilicon) to form the gate structure of a vertically oriented MOSFET. In some embodiments, the trench gate openings 322a and 322b can be etched in the top surface 342 of the semiconductor device 300b that includes a semiconductor source region 304.

[0067] The trench gate openings 322a and 322b can be etched in the surface of the semiconductor device 300b using standard etching techniques such as dry etching. The dry etching technique can include depositing a protective layer (such as photoresist) on the top surface 342 of the semiconductor device 300b and patterning the protective layer to expose the portion of the semiconductor device 300b to be etched. The dry etching technique can include chemical dry etching (such as plasma dry etching). The portion of the top surface 342 of the semiconductor device 300b that is not protected by the protective layer is etched to create a chamber in the semiconductor device 300b that includes the trench gate openings 322a and 322b.

[0068] As Figure 3BFurther depicted in FIG. is the etching of trench gate openings 322a and 322b defined in semiconductor device 300b through semiconductor source region 304 and semiconductor body region 312 such that respective bottom surfaces 340a and 340b of trench gate openings 322a and 322b include semiconductor epitaxial layer 310. Bottom surfaces 340a and 340b including semiconductor epitaxial layer 310 formed during the etching process are configured to preserve the lattice structure of the underlying semiconductor material. For example, in an embodiment where the semiconductor epitaxial layer includes a silicon carbide semiconductor material, at the completion of the etching process, the lattice structure of silicon carbide at bottom surfaces 340a and 340b of trench gate openings 322a and 322b remains intact. Trench gate openings 322a and 322b formed through semiconductor source region 304 and semiconductor body region 312 and into semiconductor epitaxial layer 310 create openings for vertical structures to facilitate current transfer from semiconductor source region 304 to conductive drain layer 308.

[0069] Now referring to Figure 3C , example semiconductor device 300c is provided. As Figure 3C depicted in FIG., trench bottom protection regions 350a and 350b are formed on bottom surfaces 340a and 340b of trench gate openings 322a and 322b of semiconductor device 300c. As Figure 3C further depicted in FIG., trench bottom protection region 350a is formed by a low energy channel implant process 352. The channel implant process 352 is performed without the protection of a hard mask (e.g., hard mask 224 as Figure 2 depicted in FIG.) that may cause undesired damage to the surfaces of semiconductor source region 304 and body contact region 330 during deposition and removal. Damage to semiconductor source region 304 and body contact region 330 caused by the deposition and removal of the hard mask may cause warping on top surface 342 of semiconductor device 300c and other physical defects that adversely affect the performance of semiconductor device 300c.

[0070] As described with respect to Figure 3A FIG., semiconductor source region 304 and body contact region 330 are formed using a deliberately damaging ion implant process. Due to the deliberately damaging ion implant process, the lattice structure at top surface 342 of semiconductor source region 304 and body contact region 330 is damaged. Further, as described with respect to Figure 3BAs described, the etching process to form trench gate openings 322a and 322b exposes portions of the semiconductor epitaxial layer 310 at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b, and this portion includes a complete lattice structure.

[0071] During ion implantation, the penetration depth of ions can be greatly affected by the state of the lattice structure of the target semiconductor surface. For example, compared with the penetration depth of accelerated ions when the lattice structure of the target semiconductor surface is complete (e.g., bottom surfaces 340a and 340b), the penetration depth of accelerated ions can be shallower when the lattice structure of the target semiconductor surface is severely damaged (e.g., top surface 342). Therefore, semiconductor devices with a severely damaged semiconductor surface (e.g., top surface 342) and semiconductor devices with a semiconductor surface having a complete lattice structure (e.g., bottom surfaces 340a and 340b) (e.g., semiconductor device 300c) can experience significantly different ion penetration depths.

[0072] As Figure 3C depicted, a deliberately damaged semiconductor surface can be utilized to form self-aligned trench bottom protection regions 350a and 350b at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b without adversely affecting the electrical characteristics of the exposed regions (such as semiconductor source region 304) on the top surface 342 of semiconductor device 300c. In the case where the deliberately damaged top surface 342 of semiconductor device 300c and the complete bottom surfaces 340a and 340b of trench gate openings 322a and 322b are exposed to the ion implantation process, the ion penetration depth at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b is greater than the ion penetration depth at the top surface 342. The ion penetration depth at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b can form trench bottom protection regions 350a and 350b, which provide sufficient protection for the trench gate oxide layers (e.g., Figure 3D the oxide layers 360a and 360b depicted) and the semiconductor body region 312 while preserving the electrical characteristics of the semiconductor source region 304 and the body contact region 330.

[0073] As Figure 3CDepicted in, using a low - energy channel implantation process 352, trench bottom protection regions 350a and 350b are formed on the bottom surfaces 340a and 340b of trench gate opening 322a and trench gate opening 322b. The channel implantation process 352 is any ion implantation process that utilizes the physical properties of the semiconductor lattice structure to maximize the penetration depth of low - energy accelerated ions. The channel implantation process 352 can be configured such that the accelerated ions encounter the target surface at an implantation angle with respect to the target surface normal, aligning the target angle with the opening in the lattice structure of the semiconductor material of the target surface. Regarding Figure 4 An example channel implantation process 352 for a silicon carbide semiconductor material is further described. Utilizing the low - energy channel implantation process 352 ensures sufficient penetration of ions at the bottom surfaces 340a and 340b of trench gate opening 322a and trench gate opening 322b, while penetration in the intentionally damaged region of the top surface 342 is negligible. The low - energy channel implantation process 352 can accelerate ions towards the surface of the semiconductor device 300c using low ion energy. For example, in some embodiments, the low ion energy is between 30 keV and 3000 keV; more preferably between 30 keV and 2000 keV; most preferably between 30 keV and 1000 keV. Additionally, during semiconductor production, a thermal annealing process is performed after each implantation process. Contrary to performing an annealing process once after all implantations, performing an annealing process after each implantation process enables at least partial recovery of the electrical contact between the newly doped region and the adjacent regions of the semiconductor device. However, the doped regions remain intentionally damaged.

[0074] By utilizing the channel implantation process 352 to maximize the penetration depth of accelerated ions in the undamaged region of the semiconductor lattice structure, the channel implantation process 352 can be configured to avoid the high temperatures required during high - energy implantation processes. In some embodiments, the temperature during the channel implantation process 352 can be at or near room temperature, e.g., between 25 degrees Celsius and 30 degrees Celsius; more preferably between 23 degrees Celsius and 24 degrees Celsius; most preferably between 20 degrees Celsius and 22 degrees Celsius. The reduction in the operating temperature during the channel implantation process 352 can enable the use of simpler and cheaper equipment. Additionally, in cases where a hard mask may be desirable, the channel implantation process 352 can enable the use of a thinner hard mask to better control the distribution of implanted ions.

[0075] Now referring to Figure 3D , an example semiconductor device 300d with vertically aligned trench gates 302a and 302b is provided. As Figure 3DAs depicted in [reference], oxide layer 360a and oxide layer 360b are deposited on the inner surfaces of trench gate openings 322a and 322b, which form a barrier between trench gates 302a and 302b and the semiconductor source region 304, semiconductor body region 312, and semiconductor epitaxial layer 310 of semiconductor device 300d. Oxide layers 360a and 360b are also deposited on the top surfaces of trench gates 302a and 302b, which isolate the trench gates from external layers (such as source conductive contacts and body contact regions in electrical contact).

[0076] As Figure 3D As depicted in [reference], protective oxide layer 360a and protective oxide layer 360b are deposited on the surfaces of trench gate openings 322a and 322b to form a dielectric layer between the layers of semiconductor device 300d and trench gates 302a and 302b. Oxide layers 360a and 360b enable the formation of an electric field between trench gates 302a and 302b and the semiconductor source region 304, semiconductor body region 312, and semiconductor epitaxial layer 310. The formation of the electric field establishes a conductive channel through semiconductor body region 312 between semiconductor source region 304 and semiconductor epitaxial layer 310.

[0077] Applying excessive stress to oxide layers 360a and 360b typically results in the failure of semiconductor device 300d (such as a MOSFET device). Failures due to excessive stress in oxide layers 360a and 360b are particularly common in high-power applications. When semiconductor device 300d is in the blocking state, the electric field at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b may reach a damaging level. The continuous electric field at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b may cause oxide layers 360a and 360b to break down, resulting in a performance failure of semiconductor device 300d.

[0078] As Figure 3DAs depicted in, trench bottom protection regions 350a and 350b are formed in exemplary semiconductor device 300d to reduce the electric field at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b, especially in high-power applications. When the semiconductor device 300d is in the blocking state, the electric field may accumulate at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b. Such an electric field may cause premature breakdown of oxide layers 360a and 360b at the bottom surfaces 340a and 340b of trench gate openings 322a and 322b. Trench bottom protection regions 350a and 350b are formed by doping the bottom surfaces 340a and 340b of trench gate openings 322a and 322b with a dopant (e.g., p-type dopant) having a doping type opposite to that of the semiconductor epitaxial layer 310. Trench bottom protection regions 350a and 350b can extend the effective operation of semiconductor device 300d, especially in high-power applications.

[0079] Now referring to Figure 4 , an exemplary channel implantation process 452 on an exemplary silicon carbide lattice structure 400 is provided. As Figure 4 depicted in, exemplary channel implantation process 452 includes accelerating ions 476 toward a silicon carbide surface including silicon atoms 472 and carbon atoms 474, the silicon carbide surface having an intact silicon carbide lattice structure 400. Ions 476 are accelerated toward silicon carbide lattice structure 400 at an implantation angle 470 with respect to the normal 478 of the semiconductor surface such that ions 476 penetrate silicon carbide lattice structure 400 through an opening in silicon carbide lattice structure 400.

[0080] As Figure 4 depicted in, channel implantation process 452 accelerates ions toward silicon carbide lattice structure 400. Generally, the silicon atoms 472 and carbon atoms 474 of silicon carbide are organized in a lattice structure 400 having defined openings and channels. Channel implantation process 452 utilizes knowledge of silicon carbide lattice structure 400 to accelerate ions 476 toward lattice structure 400 in order to minimize interference with silicon atoms 472 and carbon atoms 474.

[0081] As Figure 4 further depicted in, implantation angle 470 is selected such that accelerated ions 476 are aligned with the openings and channels in silicon carbide lattice structure 400. In some embodiments, during reception of accelerated ions 476, the surface of the silicon carbide may be angled such that ions 476 are received at an implantation angle 470 with respect to the normal 478 of the silicon carbide surface.

[0082] In some embodiments, for example, on a silicon carbide semiconductor with a cutoff angle of 4 degrees or close to 4 degrees, the implantation angle 470 can be between 3 degrees and 5 degrees; more preferably between 3.25 degrees and 4.75 degrees; most preferably between 3.5 degrees and 4.5 degrees. By aligning the accelerated ions 476 with the openings in the silicon carbide lattice structure 400, a low-energy channel implantation process 452 can be utilized. This channel implantation process 452 ensures sufficient penetration of the ions in the intact lattice structure for trench bottom protection, while the penetration in the surface with an intentionally damaged lattice structure is negligible.

[0083] The implantation angle 470 can depend on the manufacturing of the semiconductor wafer. Thus, the implantation angle 470 can depend on the semiconductor type (e.g., silicon carbide, silicon, etc.) and the cutoff angle of the semiconductor wafer. Varying manufacturing conditions may result in channel angle tolerances. The channel angle tolerance can be a range of the implantation angle 470 for which the channel implantation process 452 can be configured to operate and still achieve sufficient ion implantation depth.

[0084] Now referring to Figure 5 , an example process 500 is provided for forming a self-aligned trench bottom protection region (e.g., trench bottom protection region 350a, trench bottom protection region 350b) at the bottom surface of a trench gate of a trench gate MOSFET (e.g., trench gate 302a, trench gate 302b). At block 502, a semiconductor body region (e.g., semiconductor body region 312) is formed on the top surface of and within a semiconductor epitaxial layer (e.g., semiconductor epitaxial layer 310); wherein the semiconductor epitaxial layer includes a first conductivity type and wherein the semiconductor body region includes a second conductivity type. As described herein, the trench gate MOSFET can be used to control the current flowing through the MOSFET device in the vertical direction. The semiconductor body region is formed adjacent to the semiconductor epitaxial layer to create a PN junction at the intersection of the semiconductor body region and the semiconductor epitaxial layer. In some embodiments, the semiconductor body region is a p-type doped semiconductor and the semiconductor epitaxial layer is an n-type doped semiconductor.

[0085] At block 504, a semiconductor source region (e.g., semiconductor source region 304) is formed within a semiconductor body region, where the semiconductor body region separates the semiconductor source region from a semiconductor epitaxial layer, and where the semiconductor source region includes a first conductivity type. As described herein, the semiconductor body region may be formed between the semiconductor source region and the semiconductor epitaxial layer to block current from flowing from the semiconductor source region to the semiconductor epitaxial layer through the semiconductor body region when the voltage at the trench gate is below the threshold voltage, and to allow the flow of current when the trench gate voltage is above the threshold voltage. The semiconductor source region may be formed using an ion implantation process designed to deliberately damage the lattice structure of the semiconductor source region. In some embodiments, the semiconductor source region may include a doped semiconductor having a heavily doped semiconductor doping concentration. In some embodiments, the semiconductor source region may include an n-type doping type.

[0086] At block 506, a trench gate opening (e.g., trench gate openings 322a, trench gate openings 322b) is etched in an exposed surface (e.g., top surface 342) of the semiconductor source region, where the trench gate opening includes a bottom surface (e.g., bottom surfaces 340a, bottom surfaces 340b), and where the bottom surface includes the semiconductor epitaxial layer. As described herein, the trench gate opening is etched into the semiconductor epitaxial layer to facilitate the flow of current along the trench gate opening from the semiconductor source region to a conductive drain layer (e.g., conductive drain layer 308). The etching process exposes the bottom surface of the trench gate opening, where the lattice structure of the semiconductor epitaxial layer including the bottom surface is intact. In contrast, the lattice structure of specific regions of the top surface (such as the semiconductor source region and the body contact region) is deliberately damaged.

[0087] At block 508, a shield dopant of a second conductivity type (e.g., dopant forming the trench bottom protection region) is implanted through a channel implantation process (e.g., channel implantation process 352), where an exposed surface of the semiconductor source region is exposed to the shield dopant during the implantation process, and where the shield dopant forms a trench bottom protection region at the bottom surface of the trench gate opening. As described herein, a channel implantation process for forming the trench bottom protection regions of trench gate openings 322a, 322b is formed without using a hard mask to protect top surface structures such as semiconductor source regions and body contact regions. Instead, these structures are protected by deliberately damaging the surfaces of these regions so that the lattice structure of the semiconductor material is damaged and the penetration of ions is minimized. Since the penetration of implanted ions is limited compared to the depth of these doped regions, the effect of the shield dopant on the electrical characteristics of the semiconductor source region and body contact region is negligible. However, the penetration of the shield dopant into the bottom surface of the trench gate opening is sufficient to provide protection against the high electric field at the bottom surface of the trench gate opening during operation of the trench gate MOSFET device. In some embodiments, the implantation angle of the channel implantation process is aligned with the lattice structure of the semiconductor material to maximize the penetration of the shield dopant into the bottom surface of the trench bottom opening, form a trench bottom protection region at the bottom surface of the trench bottom opening, and reduce the damaging electric field at the oxide layer of the trench gate.

[0088] Although this detailed description sets forth some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments in various modifications and improvements. For example, those skilled in the art will recognize that such principles can be applied to any electronic device that utilizes a trench gate MOSFET architecture.

[0089] In the appended claims, unless a particular term “means for...” or “step for...” is used in a given claim, the claim is not intended to be construed under 35 U.S.C. § 112, ¶ 6.

[0090] The use of broader terms such as "comprises", "includes", and "having" should be understood to support narrower terms such as "consisting of", "consisting essentially of", and "comprised substantially of". The use of terms such as "optionally", "may", "might", "possibly", etc. for any element of an embodiment means that the element is not required, or alternatively, that the element is required, and both alternatives are within the scope of the embodiment. Additionally, references to examples are provided for illustrative purposes only and are not intended to be exclusive.

Claims

1. A method of forming a trench bottom protection region in a metal-oxide-semiconductor field-effect transistor (MOSFET) device, the method comprising: forming a semiconductor body region at a top surface of a semiconductor epitaxial layer and within the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer comprises a first conductivity type, and wherein the semiconductor body region comprises a second conductivity type; forming a semiconductor source region within the semiconductor body region, wherein the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer, and wherein the semiconductor source region comprises the first conductivity type; etching a trench gate opening in an exposed surface of the semiconductor source region, wherein the trench gate opening comprises a bottom surface, and wherein the bottom surface comprises the semiconductor epitaxial layer; and injecting a shielding dopant having the second conductivity type through a channel implantation process, wherein during the channel implantation process, the exposed surface of the semiconductor source region is exposed to the shielding dopant, and wherein the shielding dopant forms the trench bottom protection region at the bottom surface of the trench gate opening.

2. The method according to claim 1, wherein the channel implantation process accelerates the shielding dopant towards the MOSFET device at a low ion energy.

3. The method according to claim 2, wherein the low ion energy is between 30 keV and 3000 keV.

4. The method according to claim 1, wherein the channel implantation process accelerates the shielding dopant towards the MOSFET device at an implantation angle, and wherein the implantation angle is measured with respect to a normal direction of a surface of the MOSFET device.

5. The method according to claim 4, wherein the implantation angle is between 3.5 degrees and 4.5 degrees.

6. The method according to claim 1, further comprising: forming a body contact region having the second conductivity type within the semiconductor source region, wherein the body contact region is electrically coupled to the semiconductor body region.

7. The method according to claim 6, wherein the body contact region is doped at a body contact doping concentration.

8. The method according to claim 7, wherein the semiconductor body region is doped at a semiconductor body concentration.

9. The method according to claim 8, wherein the body contact doping concentration is greater than the semiconductor body concentration.

10. The method according to claim 1, wherein the first conductivity type is an n-type semiconductor.

11. The method according to claim 1, wherein the second conductivity type is a p-type semiconductor.

12. The method according to claim 1, wherein the semiconductor epitaxial layer is doped at a first doping concentration.

13. The method according to claim 12, wherein the semiconductor source region is doped at a second doping concentration.

14. The method according to claim 13, wherein the first doping concentration is less than the second doping concentration.

15. The method according to claim 1, wherein the semiconductor source region is formed using an ion implantation process.

16. The method according to claim 15, wherein the source region lattice structure of the semiconductor source region is deliberately damaged during the ion implantation process.

17. The method according to claim 6, wherein the body contact region is formed using an ion implantation process.

18. The method according to claim 17, wherein the body contact region lattice structure of the body contact region is deliberately damaged during the ion implantation process.

19. A trench gate MOSFET device, comprising: A semiconductor body region, comprising a first conductivity type; A semiconductor source region, formed at a top surface of the semiconductor body region, and comprising a second conductivity type; A semiconductor epitaxial layer, comprising the second conductivity type, wherein the semiconductor epitaxial layer is separated from the semiconductor source region by the semiconductor body region; A trench gate opening, etched in an exposed surface of the semiconductor source region, wherein the trench gate opening comprises a bottom surface, and wherein the bottom surface comprises the semiconductor epitaxial layer; and A trench bottom protection region, formed in the semiconductor epitaxial layer at the bottom surface of the trench gate opening, wherein the trench gate opening is formed by: Injecting a shield dopant having the second conductivity type through a channel implantation process, wherein the exposed surface of the semiconductor source region is exposed to the shield dopant during the channel implantation process, and wherein the shield dopant forms the trench bottom protection region at the bottom surface of the trench gate opening.

20. A trench gate MOSFET device, produced by a method comprising: Forming a semiconductor body region at a top surface of and within a semiconductor epitaxial layer; wherein the semiconductor epitaxial layer comprises a first conductivity type, and wherein the semiconductor body region comprises a second conductivity type; Forming a semiconductor source region within the semiconductor body region, wherein the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer, and wherein the semiconductor source region comprises the first conductivity type; Etching a trench gate opening in an exposed surface of the semiconductor source region, wherein the trench gate opening comprises a bottom surface, and wherein the bottom surface comprises the semiconductor epitaxial layer; and Injecting a shield dopant having the second conductivity type through a channel implantation process, wherein during the implantation process, the exposed surface of the semiconductor source region is exposed to the shield dopant, and wherein the shield dopant forms the trench bottom protection region at the bottom surface of the trench gate opening.

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