Chip packaging structure and preparation method thereof, chip and storage system

Abstract

The embodiment of the invention provides a chip packaging structure and a preparation method thereof, a chip and a storage system, and aims to increase the capacity of the chip packaging structure. In the chip packaging structure provided by the embodiment of the invention, one end of the first connecting line extends into the first groove to be connected with the first liner, and the other end of the first connecting line is connected with the substrate, so that the first connecting line is located between the surface, far away from the substrate, of the first chip and the substrate in the thickness direction of the first chip; the first chip and the second chip are stacked, so that the distance between the first chip and the second chip is reduced in the stacking process of the first chip and the second chip, more chips can be stacked on the chip packaging structure in the thickness direction of the first chip, and the capacity of the chip packaging structure is increased.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of chip packaging, and in particular, to a chip packaging structure, a preparation method thereof, a chip, and a storage system. Background Art

[0002] A chip packaging structure can package multiple chips, and each chip is used to store data. The total amount of data that all chips can store is the maximum capacity of the chip packaging structure. During use, due to the influence of size, the number of chips that can be packaged in the packaging area of the chip packaging structure is limited, thereby restricting the maximum capacity of the chip packaging structure. Summary of the Invention

[0003] The embodiments of the present application provide a chip packaging structure, a preparation method thereof, a chip, and a storage system, aiming to increase the capacity of the chip packaging structure.

[0004] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, a chip packaging structure provided by an embodiment of the present application includes a substrate, a first chip and a second chip stacked on the substrate, and a first connection line. The first chip is located between the substrate and the second chip; a first groove is formed on the side surface of the first chip, the first chip includes a first pad located in the first groove, one end of the first connection line is connected to the first pad, and the other end of the first connection line is connected to the substrate.

[0006] In some embodiments, the first groove extends around the first chip in a direction perpendicular to the substrate for one week.

[0007] In some embodiments, there are multiple first grooves, and the multiple first grooves are spaced apart on the first chip in a direction perpendicular to the substrate.

[0008] In some embodiments, there are multiple first grooves, and the multiple first grooves are respectively arranged on opposite sides of the first chip. The first chip includes a first side and a second side.

[0009] In some embodiments, there are multiple first grooves, one first groove is arranged on the first side of the first chip, and the other first grooves are spaced apart on the second side of the first chip.

[0010] In some embodiments, there are multiple first grooves, one first groove is arranged on the second side of the first chip, and the other first grooves are spaced apart on the first side of the first chip.

[0011] In some embodiments, there are multiple first grooves, part of the first grooves are spaced apart on the first side of the first chip, and the other part of the first grooves are spaced apart on the second side of the first chip.

[0012] In some embodiments, the first groove extends in a direction perpendicular to the substrate to the surface of the first chip facing away from the substrate.

[0013] In some embodiments, the first pad is located on the surface parallel to the substrate within the first groove, or the first pad is located on the surface perpendicular to the substrate within the first groove.

[0014] In some embodiments, the length of the first groove extending in a direction parallel to the substrate is greater than the length of the first groove extending in a direction perpendicular to the substrate.

[0015] In some embodiments, the side surface of the second chip has a second groove, and the second chip includes a second pad located within the second groove; the chip package structure further includes a second connection line, one end of the second connection line is connected to the second pad, and the other end of the second connection line is connected to the substrate.

[0016] In some embodiments, a first adhesive layer is provided between the first chip and the second chip, and the first adhesive layer is adhered to both the first chip and the second chip; the thickness of the first adhesive layer is 5um - 10um.

[0017] On the other hand, an embodiment of the present application further provides a chip, the chip includes a groove and a pad, the groove is provided on the side surface of the chip, and the pad is located within the groove.

[0018] In some embodiments, the groove extends around the chip in a circumferential direction along the thickness direction of the chip.

[0019] In some embodiments, there are a plurality of grooves, and the plurality of grooves are spaced apart on the chip in a circumferential direction along the thickness direction of the chip.

[0020] In some embodiments, the groove extends along the thickness direction of the chip to one side surface of the chip.

[0021] On the other hand, an embodiment of the present application further provides a method for manufacturing a chip package structure, including:

[0022] Mount a first chip on the substrate, the side surface of the first chip has a first groove, and the first chip includes a first pad located within the first groove; form a first connection line, connect one end of the first connection line to the first pad, and connect the other end of the first connection line to the substrate; stack and mount a second chip on the first chip.

[0023] In some embodiments, stacking and mounting the second chip on the first chip includes: forming a first adhesive layer between the first chip and the second chip, and spacing the first adhesive layer from the first connection line, and the first adhesive layer is adhered to both the first chip and the second chip.

[0024] In some embodiments, mounting a first chip on a substrate includes: forming a second adhesive layer between the first chip and the substrate, and the second adhesive layer is adhered to both the first chip and the substrate.

[0025] In some embodiments, a side surface of the second chip has a second groove, and the second chip includes a second pad located in the second groove; after mounting the second chip on top of the first chip, it includes: forming a second connection line, connecting one end of the second connection line to the second pad, and connecting the other end of the second connection line to the substrate.

[0026] In another aspect, an embodiment of the present application further provides a storage system, including a controller and the chip packaging structure as described above. The first chip and / or the second chip in the chip packaging structure are used to store data, and the controller is coupled to the chip packaging structure to control the chip packaging structure to store data.

[0027] In another aspect, an embodiment of the present application further provides an electronic device, including a host and the above storage system, and the host is coupled to the chip packaging structure.

[0028] It can be understood that for the semiconductor structure preparation method, storage system, and electronic device provided by the above embodiments of the present application, the beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor structure in the above text, and will not be elaborated here. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings required to be used in some embodiments of the present application. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual size of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present application.

[0030] Figure 1 It is a schematic structural diagram of a chip packaging structure in some embodiments of the present application;

[0031] Figure 2 It is a schematic structural diagram of a chip packaging structure of the prior art in some embodiments of the present application;

[0032] Figure 3 It is a schematic structure of the first chip in some embodiments of the present application Figure 1 ;

[0033] Figure 4 It is a schematic structure of the first chip in some embodiments of the present application Figure 2 ;

[0034] Figure 5Structural schematic of the first chip in some embodiments of the present application Figure 3 ;

[0035] Figure 6 Structural schematic of the first chip in some embodiments of the present application Figure 4 ;

[0036] Figure 7 Structural schematic of the first chip in some embodiments of the present application Figure 5 ;

[0037] Figure 8 Flow chart of the preparation method of the semiconductor structure in some embodiments of the present application;

[0038] Figure 9 Structural schematic diagram after connecting the first chip and the substrate in some embodiments of the present application;

[0039] Figure 10 Structural schematic diagram after forming the first connection line in some embodiments of the present application;

[0040] Figure 11 Structural schematic diagram after connecting the second chip and the first chip in some embodiments of the present application;

[0041] Figure 12 Structural schematic diagram after forming the second connection line in some embodiments of the present application;

[0042] Figure 13 Block diagram of the storage system in some embodiments of the present application Figure 1 ;

[0043] Figure 14 Block diagram of the storage system in some embodiments of the present application Figure 2 .

[0044] Explanation of reference numerals: 1. Chip package structure; 2. Substrate; 3. Chip; 4. Connection line; 6. Connection contact; 7. Pad; 8. FOW adhesive film; 9. Groove; 10. First chip; 11. Second chip; 12. First groove; 13. First pad; 14. First connection line; 15. Second groove; 16. Second pad; 17. Second connection line; 18. First contact; 19. Second contact; 20. First adhesive layer; 21. Second adhesive layer. Detailed implementation manners

[0045] Next, the technical solutions in some embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments provided by the present invention, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present invention.

[0046] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present invention. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described above may be included in any one or more embodiments or examples in any appropriate manner.

[0048] Hereinafter, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content herein.

[0050] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0052] As used herein, "about", "substantially" or "approximately" includes the stated value and an average within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0053] In the context of the present invention, the meanings of "on", "above", and "over" should be construed in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something without intervening features or layers therebetween (i.e., directly on something).

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0055] Please refer to Figure 1, a chip packaging structure 1 provided by an embodiment of the present application. The chip packaging structure 1 includes a substrate 2, a plurality of chips 3, and a plurality of connecting lines 4. The plurality of chips 3 are stacked on the substrate 2. The chip 3 closest to the substrate 2 is bonded to the substrate 2, and adjacent chips 3 are bonded to each other. A connection circuit is provided inside the substrate 2. A connection contact 6 is provided on a surface of the substrate 2 close to the chip 3, and the connection contact 6 is communicated with the connection circuit inside the substrate 2. Exemplarily, the substrate 2 may include a printed circuit board (PCB), a flexible printed circuit (FPC), etc. The chip 3 may include a storage chip, that is, the chip 3 may include a NAND chip, a DRAM chip, etc. The chip 3 may include a storage layer and a device layer. The storage layer may include a plurality of transistors, and the transistors may include complementary metal oxide semiconductor (CMOS). The device layer includes a plurality of metal wirings for connecting the transistors in the storage layer. The storage layer is coupled to the device layer, and the transistors in the storage layer can be connected to the peripheral circuit through the device layer, so that the storage layer realizes the functions of storage or reading.

[0056] In the above embodiment, the chip 3 further includes a pad 7. The pad 7 is located on a side of the device layer away from the storage layer and is used to lead out the circuit in the device layer to the surface of the chip 3. The above-mentioned connecting line 4 is used to connect the chip 3 and the connection circuit inside the substrate 2 to realize the connection between the chip 3 and the chip 3, and between the chip 3 and the peripheral circuit. One end of the connecting line 4 is connected to the pad 7 on the chip 3, and the other end of the connecting line 4 is connected to the connection contact 6 on the substrate 2, thereby realizing the connection between the chip 3 and the connection circuit.

[0057] Please refer to Figure 2 , in the related art, the pad is located on one surface of the chip, and the connecting line used to connect the chip and the substrate is located on one side of the chip. For example, after the chip is bonded to the substrate, the pad on the chip is located on a side of the chip away from the substrate. After connecting the chip and the substrate through the connecting line, a part of the connecting line is farther away from the substrate than the surface of the chip away from the substrate. On this basis, if a plurality of chips are stacked, a FOW (Film on wire) adhesive film 8 needs to be provided between the plurality of chips, so that a part of the connecting line connecting the lower chip and located between two adjacent chips is located inside the FOW adhesive film 8, so that the FOW adhesive film 8 can not only fix the relative positions of the two chips, but also make a part of the connecting line located between two adjacent chips be located inside the FOW adhesive film 8, protecting the part of the connecting line located between two adjacent chips. Since the FOW adhesive film 8 needs to protect the part of the connecting line located between two adjacent chips, the thickness of the FOW adhesive film 8 is relatively large. Exemplarily, the thickness of the FOW adhesive film 8 is greater than 50 μm.

[0058] Continue to refer to Figure 1 As shown in the figure, the chip 3 in the chip packaging structure 1 provided by the embodiment of the present application further includes a groove 9. The groove 9 is provided on the side surface of the chip 3, and the gasket 7 is located in the groove 9. In an implementation manner where the chip packaging structure 1 includes multiple chips 3, the chip packaging structure 1 may include a first chip 10 and a second chip 11. The first chip 10 and the second chip 11 are stacked on the substrate 2. The first chip 10 is located between the substrate 2 and the second chip 11. The side surface of the first chip 10 has a first groove 12. In the thickness direction, the first groove 12 is located on the side of the first chip 10 away from the substrate 2. The first chip 10 further includes a first gasket 13 located in the first groove 12. The chip packaging structure 1 further includes a first connection line 14 connecting the first chip 10 and the substrate 2. One end of the first connection line 14 extends into the first groove 12 and is connected to the first gasket 13, and the other end of the first connection line 14 is connected to the substrate 2.

[0059] Please refer to Figure 1 and Figure 2 As shown in the figure, for the chip packaging structure 1 provided by the embodiment of the present application, one end of the first connection line 14 extends into the first groove 12 and is connected to the first gasket 13, and the other end of the first connection line 14 is connected to the substrate 2, so that the first connection line 14 is located between the surface of the first chip 10 away from the substrate 2 and the substrate 2 in the thickness direction of the first chip 10. Then, during the stacking process of the first chip 10 and the second chip 11, compared with the related art, there is no need for a FOW adhesive film 8 with a thickness greater than 50 μm between the first chip 10 and the second chip 11 to protect the first connection line 14, reducing the distance between the first chip 10 and the second chip 11, enabling more chips to be stacked in the thickness direction of the first chip 10 in the chip packaging structure 1, and increasing the capacity of the chip packaging structure 1.

[0060] Continue to refer to Figure 1 In the above embodiment, the groove 9 on the chip 3 extends along the thickness direction of the chip 3 to one side surface of the chip 3. According to the above description, the gasket 7 is located in the groove 9. In an implementation manner where the chip 3 includes a storage layer and a device layer, the gasket 7 may be located on the side of the device layer away from the storage layer. Therefore, the groove 9 on the chip 3 extends along the thickness direction of the chip 3 to the side surface of the chip 3 close to the device layer. Through the above setting, the process of forming the groove 9 on the chip 3 is simplified, and the groove 9 can be formed on one side surface of the chip 3 and along the edge of the chip 3. The length of the groove 9 in the thickness direction of the chip 3 is greater than the height of the connection line lifted upward after being connected to the chip 3, so that the groove 9 is sufficient to accommodate the connection line.

[0061] Please refer to Figure 3, after connecting the first chip 10 to the substrate 2, the first groove 12 extends in a direction perpendicular to the substrate 2 to the surface of the first chip 10 facing away from the substrate 2, that is, the top of the first groove 12 is open, the side wall of the first groove 12 is connected to the upper surface of the first chip 10, and the bottom wall connected to the side wall of the first groove 12 is connected to the side surface of the first chip 10. Through the above arrangement, the process of forming the first groove 12 on the first chip 10 is simplified, and the first groove 12 can be formed on one side surface of the first chip 10 and along the edge of the first chip 10. The length L1 of the first groove 12 in the thickness direction of the first chip 10 (i.e., the direction perpendicular to the substrate 2) is greater than the height L2 that the first connecting wire 14 picks up upward after being connected to the first chip 10, so that the first groove 12 is sufficient to accommodate the first connecting wire 14 and prevent the second chip 11 from damaging the first connecting wire 14 during the process of encapsulating the second chip 11 on the first chip 10.

[0062] Continue to refer to Figure 3 , in the above implementation, after the first groove 12 is formed, the first groove 12 has a surface a1 perpendicular to the thickness direction of the first chip 10 and a surface a2 parallel to the thickness direction of the first chip 10. After connecting the first chip 10 to the substrate 2, the first groove 12 has a surface parallel to the substrate 2 and a surface perpendicular to the substrate 2. The first pad 13 located in the first groove 12 may include that the first pad 13 may be located on the surface of the first groove 12 parallel to the substrate 2, or the first pad 13 is located on the surface of the first groove 12 perpendicular to the substrate 2. Through the above arrangement, in the implementation where the first pad 13 is located on the surface of the first groove 12 parallel to the substrate 2, since the first pad 13 is formed on a horizontal plane rather than a vertical plane, the difficulty of forming the first pad 13 on the first chip 10 can be reduced. In the implementation where the first pad 13 is located on the surface of the first groove 12 perpendicular to the substrate 2, since the first pad 13 is formed on a vertical plane, after the first connecting wire 14 is connected to the first pad 13, the height that the first connecting wire 14 picks up upward can be reduced, and accordingly, the length of the first groove 12 in the thickness of the first chip 10 can be reduced, and the volume of the part of the first chip 10 removed due to the formation of the first groove 12 is reduced, improving the utilization rate of the first chip 10.

[0063] Continue to refer to Figure 3 , in the above implementation, the length of the first groove 12 extending in the direction parallel to the substrate 2 is greater than the length of the first groove 12 extending in the direction perpendicular to the substrate 2, increasing the area of the surface of the first groove 12 parallel to the substrate 2. Combining the above implementation where the first pad 13 is located on the surface of the first groove 12 parallel to the substrate 2, it is convenient to form the first pad 13 on the surface of the first groove 12 parallel to the substrate 2.

[0064] Please refer toFigure 4 , in some embodiments, the groove 9 can extend around the edge of the chip 3 in the thickness direction of the chip 3. Then, during the process of forming the gasket 7 in the groove 9, the gasket 7 can be formed at any position on the edge of the chip 3, improving the flexibility of the formation position of the gasket 7. In the first chip 10, the first groove 12 can extend around the edge of the first chip 10 in a direction perpendicular to the substrate 2. Then, during the process of forming the first gasket 13 in the first groove 12, the first gasket 13 can be formed at any position on the edge of the first chip 10, improving the flexibility of the formation position of the first gasket 13.

[0065] Please refer to Figure 5 , in some other embodiments, there can be multiple grooves 9. The multiple grooves 9 are arranged at intervals on the chip 3 in the thickness direction of the chip 3, that is, the multiple grooves 9 are not connected to each other. Each groove 9 is provided with a gasket 7. In the implementation manner of connecting the connecting wire 4 to the gasket 7 in the groove 9, it is possible to avoid contact between the connecting wires 4 extending into different grooves 9 respectively, thereby avoiding leakage between the multiple connecting wires 4. In the first chip 10, the first groove 12 can be provided with multiple ones. The multiple first grooves 12 are arranged at intervals on the chip in a direction perpendicular to the substrate 2, that is, the multiple first grooves 12 are not connected to each other. Each first groove 12 is provided with a first gasket 13. In the implementation manner of connecting the first connecting wire 14 to the first gasket 13 in the first groove 12, it is possible to avoid contact between the first connecting wires 14 extending into different first grooves 12 respectively, thereby avoiding leakage between the multiple first connecting wires 14.

[0066] Please refer to Figures 5 to 7 , in the embodiment where there are multiple first grooves 12, the first chip 10 can include a first side and a second side that are oppositely arranged. The multiple first grooves 12 are respectively arranged on the first side and the second side of the first chip 10. The number of the first grooves 12 located on the first side of the first chip 10 or the number of the second grooves 15 located on the second side of the first chip 10 can be set according to the connection requirements between the first chip 10 and the substrate 2. Exemplarily, one first groove 12 can be provided on the first side of the first chip 10, and multiple first grooves 12 can be provided on the second side of the first chip 10; or, multiple first grooves 12 can be provided on the first side of the first chip 10, and one first groove 12 can be provided on the second side of the first chip 10; or, multiple first grooves 12 can be provided on the first side of the first chip 10, and multiple first grooves 12 can also be provided on the second side of the first chip 10. For example, in some implementation manners, one first groove 12 can be provided on the first side of the first chip 10, and one first groove 12 can also be provided on the second side of the first chip 10.

[0067] Continue to refer to Figure 1, in an embodiment where the chip packaging structure 1 includes a second chip 11, the side of the second chip 11 has a second groove 15. In the thickness direction, the second groove 15 is located on the side of the second chip 11 away from the substrate 2. The second chip 11 further includes a second pad 16 located in the second groove 15. The chip packaging structure 1 further includes a second connecting line 17 connecting the second chip 11 and the substrate 2. One end of the second connecting line 17 extends into the second groove 15 and is connected to the second pad 16, and the other end of the second connecting line 17 is connected to the substrate 2.

[0068] With the above arrangement, one end of the second connecting line 17 extends into the second groove 15 and is connected to the second pad 16, and the other end of the second connecting line 17 is connected to the substrate 2, so that the second connecting line 17 is located between the surface of the second chip 11 away from the substrate 2 and the substrate 2 in the thickness direction of the second chip 11, facilitating the packaging of other chips on the second chip 11 to further increase the capacity of the chip packaging structure 1.

[0069] Continue to refer to Figure 1 , in an implementation where the chip packaging structure 1 includes a first chip 10 and a second chip 11, the connection contacts 6 on the substrate 2 may include a first contact 18 and a second contact 19, and both the first contact 18 and the second contact 19 are in communication with the connection circuit in the substrate 2. Among them, both the first contact 18 and the second contact 19 are located on the side of the substrate 2 close to the first chip 10, and the first contact 18 and the second contact 19 are outside the projection of the first chip 10 on the substrate 2 (that is, after the first chip 10 is packaged on the substrate 2, the first chip 10 does not cover the first contact 18 and the second contact 19). One end of the first connecting line 14 is connected to the first pad 13, and the other end of the first connecting line 14 is connected to the first contact 18; one end of the second connecting line 17 is connected to the second pad 16, and the other end of the second connecting line 17 is connected to the second contact 19.

[0070] Continue to refer to Figure 1 , after the first chip 10 is packaged on the substrate 2, the first contact 18 is closer to the first chip 10 than the second contact 19 to avoid mutual contact between the first connecting line 14 connecting the first contact 18 and the second connecting line 17 connecting the second contact 19, thereby generating leakage.

[0071] In the above implementation, the chip packaging structure 1 may further include a third chip (not shown) on the second chip 11, a fourth chip (not shown) on the third chip, etc.; the number of stacked chips in the chip thickness direction of the chip packaging structure 1 is not limited here.

[0072] Continue to refer to Figure 1, in some embodiments, the chip packaging structure 1 further includes a first adhesive layer 20. The first adhesive layer 20 is disposed between the first chip 10 and the second chip 11. The first adhesive layer 20 is adhered to both the first chip 10 and the second chip 11 to fix the relative positions between the first chip 10 and the second chip 11, facilitating the encapsulation of the first chip 10 and the second chip 11. The first adhesive layer 20 may include DAF (Die Attach Film). DAF is an ultra-thin film adhesive used to connect semiconductor chips to substrates 2 and chips to chips in semiconductor packaging processes. The thickness of the first adhesive layer 20 may be 5μm - 10μm. Exemplarily, the thickness of the first adhesive layer 20 may be 5μm, 7μm, 10μm, etc.

[0073] Meanwhile, the chip packaging structure 1 further includes a second adhesive layer 21. The second adhesive layer 21 is disposed between the first chip 10 and the substrate 2. The first adhesive layer 20 is adhered to both the first chip 10 and the substrate 2 to fix the relative positions between the first chip 10 and the substrate 2, facilitating the encapsulation of the first chip 10 on the substrate 2. The second adhesive layer 21 may also include DAF. The thickness of the second adhesive layer 21 may also be 5μm - 10μm. Exemplarily, the thickness of the second adhesive layer 21 may be 5μm, 7μm, 10μm, etc.

[0074] In the embodiments of the present application, a method for manufacturing a chip packaging structure is also provided, which can be used to manufacture the chip packaging structure 1 in the above embodiments. Please refer to Figure 8 , the manufacturing method may include steps S100 - S300:

[0075] S100: Mount a first chip on a substrate. The side of the first chip has a first groove, and the first chip includes a first pad located in the first groove.

[0076] Please refer to Figure 9 , in step S100, mounting the first chip 10 on the substrate 2 includes: forming a second adhesive layer 21 between the first chip 10 and the substrate 2. The second adhesive layer 21 is adhered to both the first chip 10 and the substrate 2 to fix the relative positions between the first chip 10 and the substrate 2, facilitating the encapsulation of the first chip 10 on the substrate 2.

[0077] S200: Form a first connection line, connect one end of the first connection line to the first pad, and connect the other end of the first connection line to the substrate.

[0078] Please refer to Figure 10, in step S200, a first contact 18 may be provided on the substrate 2. The first contact 18 is in communication with the connection circuit within the substrate 2. One end of the first connection line 14 extends into the first groove 12 to connect with the first pad 13, and the other end of the first connection line 14 is connected to the first contact 18, enabling the first chip 10 to be connected to the substrate 2 through the first connection line 14 and realizing the connection between the first chip 10 and the peripheral circuit through the substrate 2.

[0079] S300: Stack and install a second chip on top of the first chip.

[0080] Please refer to Figure 11 , the manufacturing method provided by the embodiment of the present application further includes providing a second chip 11 before step S300. The side of the second chip 11 has a second groove 15, and the second chip 11 includes a second pad 16 located within the second groove 15.

[0081] Continue to refer to Figure 11 , in step S300, stacking and installing the second chip 11 on top of the first chip 10 includes: forming a first bonding layer 20 between the first chip 10 and the second chip 11, such that the first bonding layer 20 is spaced apart from the first connection line 14. The first bonding layer 20 is bonded to both the first chip 10 and the second chip 11 to fix the relative positions between the first chip 10 and the second chip 11, facilitating the encapsulation of the first chip 10 and the second chip 11 on the substrate 2.

[0082] Please refer to Figure 12 , the manufacturing method provided by the embodiment of the present application further includes, after step S300, forming a second connection line 17, such that one end of the second connection line 17 is connected to the second pad 16 and the other end of the second connection line 17 is connected to the substrate 2. Wherein, a second contact 19 may be provided on the substrate 2. The second contact 19 is in communication with the connection circuit within the substrate 2. One end of the second connection line 17 extends into the second groove 15 to connect with the second pad 16, and the other end of the second connection line 17 is connected to the second contact 19, enabling the second chip 11 to be connected to the substrate 2 through the second connection line 17 and realizing the connection between the second chip 11 and the peripheral circuit through the substrate 2.

[0083] In the manufacturing method provided by the embodiment of the present application, after step S300, it may further include stacking and installing a third chip on top of the second chip 11; stacking and installing a fourth chip on top of the third chip, etc.; there is no limit to the number of chips stacked in the chip thickness direction of the chip packaging structure 1 herein. Among them, the third chip and the fourth chip may both be the same as the first chip.

[0084] Please refer to Figure 13 and Figure 14, some embodiments of the present invention further provide a storage system 1000. The storage system 1000 includes a controller 22 and the above-mentioned chip package structure 1, wherein the first chip 10 and / or the second chip 11 in the chip package structure 1 are used for storing data, and the controller 22 is coupled to the chip package structure 1 to control the chip package structure 1 to store data.

[0085] Among them, the storage system 1000 can be integrated into various types of storage devices. For example, it can be included in the same package (such as a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is to say, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (such as cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic devices with a memory.

[0086] In some embodiments, referring to Figure 13 , the storage system 1000 includes a controller 22 and a chip package structure 1, and the storage system 1000 can be integrated into a memory card.

[0087] Among them, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0088] In other embodiments, referring to Figure 14 , the storage system 1000 includes a controller 22 and multiple chip package structures 1, and the storage system 1000 is integrated into a Solid State Drives (SSD).

[0089] In the storage system 1000, in some embodiments, the controller 22 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0090] In other embodiments, the controller 22 is configured to operate in a high duty cycle environment such as an SSD or an eMMC, which are used as data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0091] In some embodiments, the controller 22 may be configured to manage data stored in the chip package structure 1 and communicate with external devices (such as a host). In some embodiments, the controller 22 may also be configured to control the operation of the chip package structure 1, such as read, erase, and programming operations. In some embodiments, the controller 22 may also be configured to manage various functions regarding data stored in or to be stored in the chip package structure 1, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes for data read from or written to the chip package structure 1.

[0092] Of course, the controller 22 may also perform any other suitable functions, such as formatting the chip package structure 1; for example, the controller 22 may communicate with external devices (such as a host) through at least one of various interface protocols.

[0093] It should be noted that the interface protocols include at least one of USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0094] Some embodiments of the present invention also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0095] The electronic device may include a host and the storage system 1000 described above, wherein the host and the storage system 1000 are coupled and may further include at least one of a central processing unit (CPU) and a cache, etc.

[0096] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that, Comprising: A substrate; A first chip and a second chip stacked on the substrate, with the first chip located between the substrate and the second chip; The side of the first chip has a first groove, and the first chip includes a first pad located in the first groove; A first connecting wire, one end of the first connecting wire is connected to the first pad, and the other end of the first connecting wire is connected to the substrate.

2. The chip packaging structure according to claim 1, wherein The first groove extends around the first chip in a direction perpendicular to the substrate for one week.

3. The chip packaging structure according to claim 1, wherein There are multiple first grooves, and the multiple first grooves are spaced apart on the first chip in a direction perpendicular to the substrate.

4. The chip packaging structure according to claim 1, wherein There are multiple first grooves, and the multiple first grooves are respectively arranged on opposite sides of the first chip. The first chip includes a first side and a second side; One first groove is arranged on the first side of the first chip, and the other first grooves are spaced apart on the second side of the first chip; Or, one first groove is arranged on the second side of the first chip, and the other first grooves are spaced apart on the first side of the first chip; Or, some of the first grooves are spaced apart on the first side of the first chip, and another part of the first grooves are spaced apart on the second side of the first chip.

5. The chip packaging structure according to any one of claims 1-4, characterized in that, The first groove extends in a direction perpendicular to the substrate to the surface of the first chip facing away from the substrate.

6. The chip package structure according to any one of claims 1-4, characterized in that, The first pad is located on the surface parallel to the substrate in the first groove, or the first pad is located on the surface perpendicular to the substrate in the first groove.

7. The chip packaging structure according to any one of claims 1-4, characterized in that, The length of the first groove extending in a direction parallel to the substrate is greater than the length of the first groove extending in a direction perpendicular to the substrate.

8. The chip packaging structure according to any one of claims 1-4, characterized in that, The side of the second chip has a second groove, and the second chip includes a second pad located in the second groove; A second connecting wire, one end of the second connecting wire is connected to the second pad, and the other end of the second connecting wire is connected to the substrate.

9. The chip packaging structure according to any one of claims 1-4, characterized in that, A first bonding layer is provided between the first chip and the second chip, and the first bonding layer is bonded to both the first chip and the second chip; the thickness of the first bonding layer is 5um - 10um.

10. A chip, characterized in that, Comprising: A groove provided on the side of the chip; A pad located in the groove.

11. The chip according to claim 10, characterized in that, The groove extends around the chip in the thickness direction of the chip for one week.

12. The chip according to claim 10, wherein There are multiple grooves, and the multiple grooves are spaced apart on the chip in the thickness direction of the chip.

13. The chip according to any one of claims 10-12, characterized in that, The groove extends in the thickness direction of the chip to one side surface of the chip.

14. A method for preparing a chip packaging structure, characterized in that, Comprising: Mount a first chip on the substrate. The side of the first chip has a first groove, and the first chip includes a first pad located in the first groove; Form a first connecting wire, connect one end of the first connecting wire to the first pad, and connect the other end of the first connecting wire to the substrate; Mount a second chip stacked on the first chip.

15. The preparation method according to claim 14, characterized in that, The installation of the second chip stacked on the first chip includes: forming a first bonding layer between the first chip and the second chip, arranging the first bonding layer at an interval from the first connection line, and bonding the first bonding layer to both the first chip and the second chip.

16. The preparation method according to claim 14, wherein The installation of the first chip on the substrate includes: forming a second bonding layer between the first chip and the substrate, and bonding the second bonding layer to both the first chip and the substrate.

17. The preparation method according to claim 16, wherein The side surface of the second chip has a second groove, and the second chip includes a second pad located in the second groove; After the installation of the second chip stacked on the first chip, it includes: forming a second connection line, connecting one end of the second connection line to the second pad, and connecting the other end of the second connection line to the substrate.

18. A storage system, characterized in that, It includes: A chip packaging structure, which is the chip packaging structure according to any one of claims 1-9, and the first chip and / or the second chip are used for storing data; A controller, which is coupled to the chip packaging structure to control the chip packaging structure to store data.

19. An electronic device, characterized in that, It includes a host and a storage system according to claim 18, and the host is coupled to the chip packaging structure.

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