Decoupling capacitor and preparation method thereof, circuit module and preparation method thereof, and semiconductor device

Abstract

The invention provides a decoupling capacitor and a preparation method thereof, a circuit module and a preparation method thereof, and a semiconductor device. The preparation method of the decoupling capacitor comprises the following steps: forming a first transistor and a second transistor which are stacked; respectively forming a first source-drain metal and a second source-drain metal in a source-drain region on the first surface of the first transistor, and respectively forming a third source-drain metal and a fourth source-drain metal in a source-drain region on the second surface of the second transistor; respectively forming a first connecting structure for connecting the first source-drain metal with the second gate structure of the second transistor and a second connecting structure for connecting the third source-drain metal with the first gate structure of the first transistor in the first transistor and the second transistor; and respectively forming a first metal interconnection layer on the fourth source-drain metal and a second metal interconnection layer on the second source-drain metal through a back-end process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and particularly to a decoupling capacitor and a preparation method thereof, a circuit module and a preparation method thereof, and a semiconductor device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can further improve the transistor integration density, and become one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some solutions for manufacturing stacked transistors, the active regions of the upper and lower layers of homologous transistors are formed by etching, and the stacked transistors are fabricated on the front and back sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip transistor" solution. However, the front and back structures of the "self-aligned flip transistor" have a mirror symmetry relationship, resulting in complex internal wiring of the transistor and extremely high preparation difficulty during the process of forming a decoupling capacitor based on the "self-aligned flip transistor", and it is not conducive to the miniaturization of integrated circuits. Summary of the Invention

[0004] The present application provides a decoupling capacitor and a preparation method thereof, a circuit module and a preparation method thereof, and a semiconductor device, so as to realize the connection of the back gate structure and the front source / drain structure through the back metal direct connection structure, and the back metal direct connection structure that connects the front and back gate structures and the back source / drain structure through the front metal direct connection structure, thereby realizing the interconnection line inside the decoupling capacitor, effectively reducing the preparation difficulty, and not increasing the transistor cell size, which helps to further improve the integration degree of the circuit.

[0005] In a first aspect, the present application provides a preparation method of a decoupling capacitor. The preparation method of the decoupling capacitor includes: forming a stacked first transistor and second transistor, wherein the active structure of the first transistor is aligned with the active structure of the second transistor in a first direction; respectively forming a first source / drain metal and a second source / drain metal in the source / drain regions on the first surface of the first transistor, and respectively forming a third source / drain metal and a fourth source / drain metal in the source / drain regions on the second surface of the second transistor, wherein the first surface is the surface of the first transistor away from the second transistor, and the second surface is the surface of the second transistor away from the first transistor; respectively forming a first connection structure connecting the first source / drain metal and the second gate structure of the second transistor, and a second connection structure connecting the third source / drain metal and the first gate structure of the first transistor in the first transistor and the second transistor; through subsequent processes, respectively forming a first metal interconnection layer on the fourth source / drain metal and a second metal interconnection layer on the second source / drain metal.

[0006] In some embodiments, the first source / drain metal and the third source / drain metal are staggered in the first direction, and the second source / drain metal and the fourth source / drain metal are staggered in the first direction; in the first transistor and the second transistor, a first connection structure connecting the first source / drain metal and the second gate structure of the second transistor, and a second connection structure connecting the third source / drain metal and the first gate structure of the first transistor are formed, including: forming a back-side direct connection via structure connecting the first source / drain metal, and forming a front-side direct connection via structure connecting the third source / drain metal; forming a back-side metal direct connection structure connecting the back-side direct connection via structure and the second gate structure, and forming a front-side metal direct connection structure connecting the front-side direct connection via structure and the first gate structure; wherein, the back-side direct connection via structure and the back-side metal direct connection structure constitute the first connection structure, and the front-side direct connection via structure and the front-side metal direct connection structure constitute the second connection structure; a first metal interconnect layer is formed on the fourth source / drain metal and a second metal interconnect layer is formed on the second source / drain metal respectively, including: forming a back-side source / drain direct connection structure connecting the fourth source / drain metal and the first metal interconnect layer connecting the back-side source / drain direct connection structure, and forming a front-side source / drain direct connection structure connecting the second source / drain metal and the second metal interconnect layer connecting the front-side source / drain direct connection structure.

[0007] In some embodiments, forming the back-side metal direct connection structure connecting the back-side direct connection via structure and the second gate structure includes: depositing a dielectric material on the surface of the back-side direct connection via structure away from the first source / drain metal and the surface of the second gate structure away from the first gate structure to form a first back-side dielectric layer; etching the first back-side dielectric layer until a first part of the second gate structure and the back-side direct connection via structure are exposed to form a back-side gate / source direct connection groove; wherein, the first part of the second gate structure is a part of the second gate structure adjacent to the back-side direct connection via structure in the second direction; the second direction is the channel direction of the active structure, and the second direction is perpendicular to the first direction; depositing a metal material in the back-side gate / source direct connection groove to form the back-side metal direct connection structure.

[0008] In some embodiments, forming the back-side source / drain direct connection structure connecting the second source / drain metal and the first metal interconnect layer connecting the back-side source / drain direct connection structure includes: depositing a dielectric material on the surface of the first back-side dielectric layer away from the back-side direct connection via structure to form a second back-side dielectric layer; etching the second back-side dielectric layer and the first back-side dielectric layer in sequence until the fourth source / drain metal is exposed to form a back-side source / drain direct connection via; depositing a metal material in the back-side source / drain direct connection via to form the back-side source / drain direct connection structure; forming the first metal interconnect layer on the second back-side dielectric layer; wherein, the first metal interconnect layer has a first metal interconnect line, and the back-side source / drain direct connection structure connects the fourth source / drain metal and the first metal interconnect line.

[0009] In some embodiments, forming a front-side metal direct-connection structure that connects a front-side direct-connection via structure and a first gate structure includes: depositing a dielectric material on a surface of the front-side direct-connection via structure away from the third source / drain metal and on a surface of the first gate structure away from the second gate structure to form a first front-side dielectric layer; etching the first front-side dielectric layer until a first portion of the first gate structure and the front-side direct-connection via structure are exposed to form a front-side gate-source direct-connection groove; wherein the first portion of the first gate structure is a portion of the first gate structure that is adjacent to the front-side direct-connection via structure in a second direction; and depositing a metal material in the front-side gate-source direct-connection groove to form the front-side metal direct-connection structure.

[0010] In some embodiments, forming a front-side source / drain direct-connection structure that connects a second source / drain metal and a second metal interconnect layer that connects the front-side source / drain direct-connection structure includes: depositing a dielectric material on a surface of the first front-side dielectric layer away from the front-side direct-connection via structure to form a second front-side dielectric layer; sequentially etching the second front-side dielectric layer and the first front-side dielectric layer until the second source / drain metal is exposed to form a front-side source / drain direct-connection via; depositing a metal material in the front-side source / drain direct-connection via to form the front-side source / drain direct-connection structure; forming the second metal interconnect layer on the second front-side dielectric layer; wherein the second metal interconnect layer has a second metal interconnect line, and the front-side source / drain direct-connection structure connects the second source / drain metal and the second metal interconnect line; and the second metal interconnect line is different from the first metal interconnect line.

[0011] In some embodiments, the semiconductor structure further includes: a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer is located on both sides of the first source / drain structure in a third direction, and the second interlayer dielectric layer is located on both sides of the third source / drain structure in the third direction; the third direction is perpendicular to the first direction and the second direction; forming a back-side direct-connection via structure that connects a first source / drain metal includes: sequentially etching the second interlayer dielectric layer and the first interlayer dielectric layer until the first source / drain metal is exposed to form a first via; depositing a metal material in the first via to form the back-side direct-connection via structure; forming a front-side direct-connection via structure that connects a third source / drain metal includes: sequentially etching the first interlayer dielectric layer and the second interlayer dielectric layer until the third source / drain metal is exposed to form a second via; depositing a metal material in the second via to form the front-side direct-connection via structure.

[0012] Second aspect, the present application provides a method for manufacturing a circuit module. The circuit module includes: at least two decoupling capacitors, each of the at least two decoupling capacitors being manufactured by the method according to any one of the first aspect; at least two decoupling capacitors, including: a first decoupling capacitor and a second decoupling capacitor; the method for manufacturing the circuit module includes: forming an interconnect metal structure connecting a first source-drain metal in the first decoupling capacitor and a second source-drain metal in the second decoupling capacitor, wherein a first end of the interconnect metal structure in a second direction is connected to the first source-drain metal; a second end of the interconnect metal structure in the second direction is connected to the second source-drain metal.

[0013] In some embodiments, forming an interconnect metal structure connecting a first source-drain metal in the first decoupling capacitor and a second source-drain metal in the second decoupling capacitor includes: simultaneously etching a first front dielectric layer in the first decoupling capacitor and a first front dielectric layer in the second decoupling capacitor until the first source-drain metal and the second source-drain metal are exposed to form an interconnect metal groove; wherein the interconnect metal groove includes a first part and a second part that are connected, the first part is located in the first decoupling capacitor, and the second part is located in the second decoupling capacitor; depositing a metal material in the interconnect metal groove to form an interconnect metal structure.

[0014] Third aspect, the present application provides a decoupling capacitor. The decoupling capacitor can be manufactured by the method according to any one of the embodiments of the first aspect. The decoupling capacitor includes: forming a stacked first transistor and a second transistor, wherein the active structures of the first transistor and the second transistor are aligned in a first direction; wherein the first transistor includes: a first gate structure, a first source-drain structure and a first source-drain metal connected to the first source-drain structure, a second source-drain structure and a second source-drain metal connected to the second source-drain structure; the second transistor includes: a second gate structure, a third source-drain structure and a third source-drain metal connected to the third source-drain structure, a fourth source-drain structure and a fourth source-drain metal connected to the fourth source-drain structure; the decoupling capacitor further includes: a first connection structure connecting the first source-drain metal and the second gate structure, and a second connection structure connecting the third source-drain metal and the first gate structure; a first metal interconnect layer connecting the fourth source-drain metal and a second metal interconnect layer connecting the second source-drain metal.

[0015] In some embodiments, the first connection structure includes: a backside direct via structure and a backside metal direct connection structure; the second connection structure includes: a front side direct via structure and a front side metal direct connection structure; the first metal interconnect layer further includes: a backside source / drain direct connection structure; wherein, a first end of the backside direct via structure in a first direction is connected to a first source / drain metal, a second end of the backside direct via structure in the first direction is connected to a first end of the backside metal direct connection structure in a second direction, and a second end of the backside metal direct connection structure in the second direction is connected to a second gate structure; a first end of the backside source / drain direct connection structure in the first direction is connected to a fourth source / drain metal, and a second end of the backside source / drain direct connection structure in the first direction is connected to the first metal interconnect layer; the second direction is the channel direction of the active structure, and the second direction is perpendicular to the first direction; the second metal interconnect layer further includes: a front side source / drain direct connection structure; wherein, a first end of the front side direct via structure in the first direction is connected to a third source / drain metal, a second end of the front side direct via structure in the first direction is connected to a first end of the front side metal direct connection structure in the second direction, and a second end of the front side metal direct connection structure in the second direction is connected to a first gate structure; a first end of the front side source / drain direct connection structure in the first direction is connected to a second source / drain metal, and a second end of the front side source / drain direct connection structure in the first direction is connected to the second metal interconnect layer.

[0016] In some embodiments, the first metal interconnect layer has a first metal interconnect line, and the backside source / drain direct connection structure connects the fourth source / drain metal and the first metal interconnect line; the second metal interconnect layer has a second metal interconnect line, and the front side source / drain direct connection structure connects the second source / drain metal and the second metal interconnect line; the second metal interconnect line is different from the first metal interconnect line.

[0017] Fourthly, the present application provides a circuit module. The circuit module can be prepared and formed by using the method according to any one of the embodiments of the second aspect. The circuit module includes: at least two decoupling capacitors and an interconnect metal structure; wherein, each of the at least two decoupling capacitors is the decoupling capacitor according to any one of the embodiments of the third aspect; the at least two decoupling capacitors include: a first decoupling capacitor and a second decoupling capacitor; a first end of the interconnect metal structure in the second direction is connected to a first source / drain metal in the first decoupling capacitor; the second end of the interconnect metal structure in the second direction is connected to a second source / drain metal in the second decoupling capacitor.

[0018] Fifthly, an embodiment of the present application provides a semiconductor device, which includes: the decoupling capacitor according to any one of the embodiments of the third aspect and / or the circuit module according to any one of the embodiments of the fourth aspect.

[0019] In the embodiments of the present disclosure, by forming a backside direct connection via structure connecting the front-side source / drain structure in the self-aligned stacked transistor, and then connecting the backside gate structure and the backside direct connection via structure through the backside metal direct connection structure, the front-side source / drain structure is connected to the backside gate structure. By forming a front-side direct connection via structure connecting the backside source / drain structure in the self-aligned stacked transistor, and then connecting the front-side gate structure and the front-side direct connection via structure through the front-side metal direct connection structure, the backside source / drain structure is connected to the front-side gate structure. In this way, the interconnecting wires inside the decoupling capacitor are realized, which not only effectively reduces the manufacturing difficulty, but also does not increase the transistor cell size, contributing to further improving the integration degree of the circuit.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. Brief Description of the Drawings

[0021] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0022] Figure 1 A schematic diagram of a circuit composition of the decoupling capacitor in the embodiments of this application;

[0023] Figure 2 For Figure 1 A schematic diagram of a layout of the decoupling capacitor shown;

[0024] Figure 3 A schematic diagram of an implementation process flow of a preparation method of the decoupling capacitor in the embodiments of this application;

[0025] Figures 4 to 14 A schematic diagram of a preparation process of the decoupling capacitor in the embodiments of this application;

[0026] Figure 15 A schematic diagram of a layout of a circuit module in the embodiments of this application;

[0027] Figure 16 A schematic diagram of a cross-section of the circuit module along the second direction in the embodiments of this application.

[0028] In the above figures: 11, the first transistor; 12, the second transistor; 112, the first source / drain region structure; 113, the first interlayer dielectric layer; 114, the first gate structure; 115, the first source / drain region metal; 116, the front direct connection via structure; 117, the front metal direct connection structure; 118, the front source / drain direct connection structure; 119, the second metal interconnection layer; 122, the second source / drain region structure; 123, the second interlayer dielectric layer; 124, the second gate structure; 125, the second source / drain region metal; 126, the back direct connection via structure; 127, the back metal direct connection structure; 128, the back source / drain direct connection structure; 129, the first metal interconnection layer.

[0029] 20, fin structure; 21, the first back dielectric layer; 22, the second back dielectric layer; 23, the first front dielectric layer; 24, the second front dielectric layer. Detailed implementation manners

[0030] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present application.

[0031] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development.

[0032] By three-dimensional transistor stacking, stacked transistors can achieve the integration of two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies to continue the miniaturization of integrated circuit size.

[0033] In one embodiment, there are two schemes for the preparation process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0034] In the first solution, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this solution is better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0035] In the second solution, it is based on wafer bonding and layer-by-layer processing. Specifically, the upper layer transistors are fabricated by bonding a wafer on top of the already fabricated lower layer transistors, stacking the two transistors vertically. However, during the thermal process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and the interconnecting lines. The advantage of this solution is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matched device performance.

[0036] To solve the technical problems existing in the above two solutions, a "self-aligned flip-chip transistor" solution is proposed. The "self-aligned flip-chip transistor" solution forms the active regions of the upper and lower layer homologous transistors through etching and realizes the fabrication of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the disadvantages of the above two solutions.

[0037] For the complementary field-effect transistors (CFETs) formed by using the above "self-aligned flip-chip transistor" solution, since the power lines and signal lines are both arranged on the front side of the transistors, for relatively complex metal interconnections, such as when forming decoupling capacitors using a cross-coupled structure, there may be difficulties in wiring and processing. At the same time, for the industry-standard common-gate CFETs, there may also be a problem of increased standard cell design area. Therefore, there is an urgent need to provide a decoupling capacitor design solution that can overcome the above difficulties.

[0038] To this end, embodiments of the present application provide a decoupling capacitor and a preparation method thereof, a circuit module and a preparation method thereof, and a semiconductor device, so as to realize connecting a back gate structure and a front source-drain structure through a back metal direct connection structure in a "self-aligned flip-chip transistor", and a back metal direct connection structure connecting a front-back gate structure and a back source-drain structure, thereby realizing the interconnection line inside the decoupling capacitor, not only effectively reducing the preparation difficulty, but also not increasing the transistor unit size, which helps to further improve the integration degree of the circuit.

[0039] In some embodiments, the decoupling capacitor is a capacitor installed at the power supply end of a component in a circuit. This capacitor can provide a relatively stable power supply, and at the same time can also reduce the noise coupled by the component to the power supply end, and indirectly can reduce the influence of this component noise on other components.

[0040] In some embodiments, the decoupling capacitor can be composed of a parallel connection of an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor.

[0041] In one embodiment, the decoupling capacitor can be composed of cross-coupled PMOS transistors and NMOS transistors. Among them, the source of the PMOS transistor can be connected to the power supply VDD, and the source of the NMOS transistor can be connected to the power supply VSS.

[0042] Figure 1 It is a schematic diagram of a circuit composition of the decoupling capacitor in the embodiments of the present application. Refer to Figure 1 As shown, between the power supply VDD and the power supply VSS, a decoupling capacitor using a cross-coupling structure is provided, denoted as the first decoupling capacitor Decap1. Among them, the first decoupling capacitor Decap1 can be composed of a PMOS transistor and an NMOS transistor. The PMOS transistor and the NMOS transistor can be stacked. Among them, the source of the PMOS transistor can be connected to the power supply VDD, the gate of the PMOS transistor can be connected to the drain of the NMOS transistor, the drain of the PMOS transistor can be connected to the gate of the NMOS transistor, and the source of the NMOS transistor can be connected to the power supply VSS.

[0043] Figure 2 For Figure 1 It is a schematic diagram of a layout of the decoupling capacitor shown. Refer to Figure 1 As shown, Figure 1The first decoupling capacitor Decap1 is shown. Among them, the first decoupling capacitor Decap1 includes two transistors, and the first decoupling capacitor Decap1 can be composed of a fin structure, a gate structure, a source-drain structure, a signal line in a metal interconnect layer, and a power line in a metal interconnect layer.

[0044] Here, according to Figure 2 As can be seen from the layout shown, the first decoupling capacitor Decap1 can be composed of stacked transistors and the metal interconnect lines inside them. The stacked transistors can include a first transistor and a second transistor stacked in a first direction, and a metal interconnect line is formed between the first transistor and the second transistor. The first direction is a direction perpendicular to the plane shown in the layout.

[0045] In a first aspect, an embodiment of the present application provides a method for manufacturing a decoupling capacitor. Figure 3 For an implementation process schematic diagram of the method for manufacturing the decoupling capacitor in an embodiment of the present application, see Figure 3 As shown, the method for manufacturing a decoupling capacitor may include:

[0046] Step S301, forming a first transistor and a second transistor. It can be understood that the formed semiconductor structure includes: a first transistor and a second transistor arranged opposite to each other in a first direction, and the active structures of the first transistor and the second transistor are aligned in the first direction; wherein, the first transistor includes: a first gate structure and a first source-drain region (hereinafter all refer to including a first source-drain structure and a second source-drain structure), the first source-drain structure and the second source-drain structure are respectively located on both sides of the first gate structure in a second direction; the second transistor includes: a second gate structure and a second source-drain region (hereinafter all refer to including a third source-drain structure and a fourth source-drain structure), the third source-drain structure and the fourth source-drain structure are respectively located on both sides of the second gate structure in a second direction; the first gate structure and the second gate structure are opposite to each other in the first direction, and the first source-drain region structure and the second source-drain region structure are opposite to each other in the first direction; the second direction is perpendicular to the first direction, and the second direction may be the channel direction of the active structure;

[0047] Step S302, forming a first source-drain region metal connecting the first source-drain region structure (hereinafter all refer to including a first source-drain metal and a second source-drain metal, the first source-drain metal is connected to the first source-drain structure, and the second source-drain metal is connected to the second source-drain structure), and forming a second source-drain region metal connecting the second source-drain region structure (hereinafter all refer to including a third source-drain metal and a fourth source-drain metal, the third source-drain metal is connected to the third source-drain structure, and the fourth source-drain metal is connected to the fourth source-drain structure); wherein, the first source-drain region metal and the second source-drain region metal are arranged staggered in the first direction; the first source-drain region metal is farther away from the second source-drain region structure than the first source-drain region structure, and the second source-drain region metal is farther away from the first source-drain region structure than the second source-drain region structure;

[0048] It should be noted that for ease of description, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0049] Step S303: Form a backside direct connection via structure connected to the first source-drain region metal, and form a front-side direct connection via structure connected to the second source-drain region metal; wherein, the first end of the backside direct connection via structure in the first direction is connected to the first source-drain region metal, and the second end of the backside direct connection via structure in the first direction penetrates through the second transistor; the first end of the front-side direct connection via structure in the first direction is connected to the second source-drain region metal, and the second end of the front-side direct connection via structure in the first direction penetrates through the first transistor;

[0050] Step S304: Form a backside metal direct connection structure connecting the backside direct connection via structure and the second gate structure, and form a front-side metal direct connection structure connecting the front-side direct connection via structure and the first gate structure; wherein, the first end of the backside metal direct connection structure in the second direction is connected to the second end of the backside direct connection via structure in the first direction, and the second end of the backside metal direct connection structure in the second direction is connected to the second gate structure; the first end of the front-side metal direct connection structure in the second direction is connected to the second end of the front-side direct connection via structure in the first direction, and the second end of the front-side metal direct connection structure in the second direction is connected to the first gate structure; the backside direct connection via structure and the backside metal direct connection structure are jointly used to connect the first source-drain region metal and the first gate structure; the front-side direct connection via structure and the front-side metal direct connection structure are jointly used to connect the second source-drain region metal and the second gate structure;

[0051] Wherein, the backside direct connection via structure and the backside metal direct connection structure form a first connection structure, and the front-side direct connection via structure and the front-side metal direct connection structure form a second connection structure.

[0052] Step S305: Form a backside source-drain direct connection structure connecting the second source-drain region metal and a first metal interconnection layer connecting the backside source-drain direct connection structure, and form a front-side source-drain direct connection structure connecting the first source-drain region metal and a second metal interconnection layer connecting the front-side source-drain direct connection structure; wherein, the backside source-drain direct connection structure is connected to the second source-drain region metal not connected to the front-side direct connection via structure; the front-side source-drain direct connection structure is connected to the first source-drain region metal not connected to the backside direct connection via structure.

[0053] It can be understood that when the first source-drain metal is connected to the backside direct connection via structure, the front-side source-drain direct connection structure can be connected to the second source-drain metal; or, when the second source-drain metal is connected to the backside direct connection via structure, the front-side source-drain direct connection structure can be connected to the first source-drain metal.

[0054] It should be noted that Figure 3 the steps shown in [[ ]] are not exclusive, and other steps may also be performed before, after, or between any of the steps shown; Figure 3 the order of the steps shown in [[ ]] can be adjusted according to actual needs.

[0055] Figures 4 to 14 FIG. [[ ]] is a schematic diagram of a preparation process of a decoupling capacitor in an embodiment of the present application. For ease of understanding, Figures 4 to 14 (a) in [[ ]] shows a cross-sectional view along the direction of the dashed line A-A' in [[ ]], Figure 2 (b) in [[ ]] shows a cross-sectional view along the direction of the dashed line B-B' in [[ ]]; Figures 4 to 14 (c) in [[ ]] shows a cross-sectional view along the direction of the dashed line C-C' in [[ ]], Figure 2 (d) in [[ ]] shows a cross-sectional view along the direction of the dashed line D-D' in [[ ]]. Referring to [[ ]] shown, the preparation method of the decoupling capacitor may include: Figures 4 to 14

[0056] Figure 2 (c) in [[ ]] shows a cross-sectional view along the direction of the dashed line C-C' in [[ ]], Figures 4 to 14 (d) in [[ ]] shows a cross-sectional view along the direction of the dashed line D-D' in [[ ]], Figure 2 as shown in [[ ]], the preparation method of the decoupling capacitor may include: Figures 2 to 14 as shown in [[ ]], the preparation method of the decoupling capacitor may include:

[0056] In step S301, a semiconductor structure including a first transistor and a second transistor is formed (as shown in [[ ]]). Figure 4 as shown in [[ ]].

[0057] Here, the semiconductor structure in the embodiment of the present application includes: a first transistor 11 and a second transistor 12 disposed opposite to each other in a first direction. Among them, the first transistor 11 includes: a first gate structure 114 and a first source-drain region structure 112. The second transistor 12 includes: a second gate structure 124 and a second source-drain region structure 122.

[0058] In some embodiments, the first source-drain region structure 112 includes a first source-drain structure and a second source-drain structure. The first source-drain region structure 112 is located on both sides of the first gate structure 114 in a second direction, including: the first source-drain structure is located on one side of the first gate structure 114 in the second direction, and the second source-drain structure is located on the other side of the first gate structure in the second direction. The second source-drain region structure 122 includes a third source-drain structure and a fourth source-drain structure. The second source-drain region structure 122 is located on both sides of the second gate structure 124 in a second direction, including: the third source-drain structure is located on one side of the second gate structure 124 in the second direction, and the fourth source-drain structure is located on the other side of the second gate structure 124 in the second direction.

[0059] In some embodiments, the first gate structure 114 and the second gate structure 124 may be opposite to each other in the first direction. In some embodiments, the first source-drain region structure 112 and the second source-drain region structure 122 may be opposite to each other in the first direction. In one embodiment, the first source-drain region structure 112 and the second source-drain region structure 122 being opposite to each other in the first direction includes: the first source-drain structure being opposite to the third source-drain structure, and the second source-drain structure being opposite to the fourth source-drain structure. In one embodiment, the first source-drain region structure 112 and the second source-drain region structure 122 being opposite to each other in the first direction includes: the first source-drain structure being opposite to the fourth source-drain structure, and the second source-drain structure being opposite to the third source-drain structure.

[0060] It can be understood that the specific preparation steps and processes of the semiconductor structure in the embodiments of the present application can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0061] In some embodiments, the first transistor 11 and the second transistor 12 may be formed based on the same fin structure 20. After forming the fin structure 20, the first transistor 11 is formed based on the first part of the fin structure 20, and after flipping the wafer, the second transistor 12 is formed based on the second part of the fin structure 20, so as to obtain the semiconductor structure in the embodiments of the present application. In one embodiment, during the process of forming the first transistor 11, the first source-drain region structure 112 and the first gate structure 114 may be formed based on the first part of the fin structure 20, and during the process of forming the second transistor 12, the second source-drain region structure 122 and the second gate structure 124 may be formed based on the second part of the fin structure 20, such that the first source-drain region structure 112 and the second source-drain region structure 122 can be formed by sharing the same fin structure 20, and the first gate structure 114 and the second gate structure 124 can be formed by sharing the same fin structure 20.

[0062] In some embodiments, the fin structure 20 may be different according to the types of the first transistor 11 and the second transistor 12. For example, when the first transistor 11 is a fin field-effect transistor, the first part of the fin structure 20 may be a structure formed by a single material layer; when the first transistor 11 is a gate-all-around field-effect transistor, the first part of the fin structure 20 may be a stacked nanosheet structure formed by alternately stacking multiple material layers.

[0063] In step S302, a first source-drain region metal 115 connecting the first source-drain region structure 112 and a second source-drain region metal 125 connecting the second source-drain region structure 122 are formed (as Figure 5 shown).

[0064] It can be understood that after forming the above semiconductor structure, a first source / drain region metal 115 connected to the first source / drain region structure 112 can be formed based on the position of the first source / drain region structure 112; and a second source / drain region metal 125 connected to the second source / drain region structure 122 can be formed based on the position of the second source / drain region structure 122.

[0065] Here, in order to facilitate the formation of a straight through-hole structure extending in the first direction (including a backside through-hole structure and a front-side through-hole structure) inside the semiconductor structure in subsequent steps, the first source / drain region metal 115 and the second source / drain region metal 125 can be arranged staggered in the first direction.

[0066] In some embodiments, the first source / drain region metal 115 and the second source / drain region metal 125 are arranged staggered in the first direction, including: the first source / drain region metal 115 is located on one side of the fin structure 20 in the third direction, and the second source / drain region metal 125 is located on the other side of the fin structure 20 in the third direction. The third direction is a direction perpendicular to the first direction and the second direction. The source / drain regions and the gate regions are alternately arranged along the second direction, and the gate structure extends across the fin structure 20 in the third direction.

[0067] In some embodiments, the first source / drain region metal 115 includes a first source / drain metal and a second source / drain metal, the first source / drain metal is connected to the first source / drain structure, and the second source / drain metal is connected to the second source / drain structure. In some embodiments, the second source / drain region metal 125 includes a third source / drain metal and a fourth source / drain metal, the third source / drain metal is connected to the third source / drain structure, and the fourth source / drain metal is connected to the fourth source / drain structure.

[0068] In one embodiment, the first source / drain structure and the third source / drain metal are opposite in the first direction, and the first source / drain metal and the third source / drain metal are arranged staggered in the first direction. In one embodiment, the first source / drain structure and the fourth source / drain structure are opposite in the first direction, and the first source / drain metal and the fourth source / drain metal are arranged staggered in the first direction. In one embodiment, the second source / drain structure and the fourth source / drain structure are opposite in the first direction, and the second source / drain metal and the fourth source / drain metal are arranged staggered in the first direction. In one embodiment, the second source / drain structure and the third source / drain metal are opposite in the first direction, and the second source / drain metal and the third source / drain metal are arranged staggered in the first direction.

[0069] In some embodiments, since the first transistor 11 and the second transistor 12 are arranged back-to-back, the first source / drain region metal 115 is farther from the second source / drain region structure 122 than the first source / drain region structure 112, and the second source / drain region metal 125 is farther from the first source / drain region structure 112 than the second source / drain region structure 122.

[0070] In some embodiments, the preparation process for forming the first source / drain region metal 115 may be the same as that for forming the second source / drain region metal 125. The preparation process for forming the first source / drain region metal 115 and the preparation process for forming the second source / drain region metal 125 may also be different, and the embodiments of the present application do not limit this.

[0071] In step S303, a backside direct connection via structure connecting the first source / drain region metal 115 and a frontside direct connection via structure connecting the second source / drain region metal 125 are formed (as Figures 6 to 11 shown).

[0072] It can be understood that after forming the first source / drain region metal 115 and the second source / drain region metal 125, a backside direct connection via structure 126 connecting the first source / drain region metal 115 and a frontside direct connection via structure 116 connecting the second source / drain region metal 125 can be formed. Here, the backside direct connection via structure 126 can be connected to the first source / drain metal in the first source / drain region metal 115, or can be connected to the second source / drain metal in the first source / drain region metal 115. The frontside direct connection via structure 116 can be connected to the third source / drain metal in the second source / drain region metal 125, or can be connected to the fourth source / drain metal in the second source / drain region metal 125. The embodiments of the present application do not make specific limitations on this.

[0073] It can be understood that in order to implement a decoupling capacitor unit (formed by stacked transistors), the backside direct connection via structure 126 can be connected to the first source / drain metal in the first source / drain region metal 115, or can be connected to the second source / drain metal in the first source / drain region metal 115. The frontside direct connection via structure 116 can be connected to the third source / drain metal in the second source / drain region metal 125, or can be connected to the fourth source / drain metal in the second source / drain region metal 125. The embodiments of the present application do not make specific limitations on this.

[0074] It can be understood that the first source / drain region metal 115 and the second source / drain region metal 125 are arranged in an interleaved manner in the first direction. Therefore, the first source / drain region metal 115 and the frontside direct connection via structure 116 are arranged in an interleaved manner in the first direction, and the second source / drain region metal 125 and the backside direct connection via structure 126 are arranged in an interleaved manner in the first direction, so that the first source / drain region metal 115 is not connected to the frontside direct connection via structure 116, and the second source / drain region metal 125 is not connected to the backside direct connection via structure 126.

[0075] In some embodiments, the first source-drain metal and the second source-drain metal may be oppositely disposed in the second direction. Exemplarily, both the first source-drain metal and the second source-drain metal are located on one side of the decoupling capacitor in the third direction. At this time, the front straight through-hole structure 116 and the back straight through-hole structure 126 may be respectively located on both sides of the first gate structure 114 in the second direction, and the front straight through-hole structure 116 and the back straight through-hole structure 126 are located on both sides of the decoupling capacitor in the third direction. Alternatively, the front straight through-hole structure 116 and the back straight through-hole structure 126 may be respectively located on the same side of the first gate structure 114 in the second direction, and the front straight through-hole structure 116 and the back straight through-hole structure 126 are located on both sides of the decoupling capacitor in the third direction.

[0076] In some embodiments, the first source-drain metal and the second source-drain metal are staggered in the second direction. Exemplarily, the first source-drain metal is located on one side of the decoupling capacitor in the third direction, and the second source-drain metal is located on the other side of the decoupling capacitor in the third direction. At this time, the front straight through-hole structure 116 and the back straight through-hole structure 126 may be respectively located on both sides of the first gate structure 114 in the second direction, and the front straight through-hole structure 116 and the back straight through-hole structure 126 are located on the same side of the decoupling capacitor in the third direction. Alternatively, the front straight through-hole structure 116 and the back straight through-hole structure 126 may be respectively located on the same side of the first gate structure 114 in the second direction, and the front straight through-hole structure 116 and the back straight through-hole structure 126 are located on both sides of the decoupling capacitor in the third direction.

[0077] Similarly, the positional relationship between the third source-drain metal and the fourth source-drain metal may refer to the positional relationship between the first source-drain metal and the second source-drain metal. For the sake of brevity of the specification, it will not be elaborated here.

[0078] In some embodiments, the manufacturing process for forming the front straight through-hole structure 116 and the manufacturing process for forming the back straight through-hole structure 126 may be the same. The manufacturing process for forming the front straight through-hole structure 116 and the manufacturing process for forming the back straight through-hole structure 126 may also be different, and the embodiments of the present application do not make any limitation thereto.

[0079] In some embodiments, the front straight through-hole structure 116 is formed by depositing a metal material so that the front straight through-hole structure 116 is connected to the second source-drain region structure 122 through the second source-drain region metal 125. In some embodiments, the back straight through-hole structure 126 is formed by depositing a metal material so that the back straight through-hole structure 126 is connected to the first source-drain region structure 112 through the first source-drain region metal 115.

[0080] In some embodiments, the first transistor 11 further includes: a first interlayer dielectric layer 113, which is located on both sides of the first source / drain region structure 112 in the third direction. The second transistor 12 further includes: a second interlayer dielectric layer 123, which is located on both sides of the second source / drain region structure 122 in the third direction. The formation of the backside direct connection via structure 126 connecting the first source / drain region metal 115 in step S303 may include: sequentially etching the second interlayer dielectric layer and the first interlayer dielectric layer 113 until the first source / drain region metal 115 is exposed to form a first via; depositing a metal material in the first via to form the backside direct connection via structure 126. The formation of the frontside direct connection via structure 116 connecting the second source / drain region metal 125 in step S303 may include: sequentially etching the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 until the second source / drain region metal 125 is exposed to form a second via; depositing a metal material in the second via to form the frontside direct connection via structure 116.

[0081] It can be understood that the first interlayer dielectric layer 113 is located on both sides of the first source / drain region structure 112 in the third direction, and the second interlayer dielectric layer 123 is located on both sides of the second source / drain region structure 122 in the third direction. The first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 together are used to isolate the first source / drain region structure 112 and the second source / drain region structure 122. When forming the backside direct connection via structure 126 connecting the first source / drain region metal 115, the second interlayer dielectric layer 123 and the first interlayer dielectric layer 113 can be sequentially etched until the first source / drain region metal 115 is exposed to form a first via. Subsequently, a metal material is deposited in the first via to form the backside direct connection via structure 126. Here, the backside direct connection via structure 126 and the second source / drain region metal 125 in the second transistor 12 are electrically isolated by the second interlayer dielectric layer 123. When forming the frontside direct connection via structure 116 connecting the second source / drain region metal 125, the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 can be sequentially etched until the second source / drain region metal 125 is exposed to form a second via. Subsequently, a metal material is deposited in the second via to form the frontside direct connection via structure 116. Here, the frontside direct connection via structure 116 and the first source / drain region metal 115 in the first transistor 11 are electrically isolated by the first interlayer dielectric layer 113.

[0082] In some embodiments, the metal material for forming the frontside direct connection via structure 116 may be the same as the metal material for forming the backside direct connection via structure 126, or the metal material for forming the frontside direct connection via structure 116 may also be different from the metal material for forming the backside direct connection via structure 126. The embodiments of the present application do not limit this.

[0083] In step S304, a back metal direct connection structure 127 connecting the back direct connection via structure 126 and the second gate structure 124 is formed, and a front metal direct connection structure 117 connecting the front direct connection via structure 116 and the first gate structure 114 is formed (as Figures 7 to 12 shown).

[0084] Among them, the first end of the back metal direct connection structure 127 in the second direction is connected to the second end of the back direct connection via structure 126 in the first direction, and the second end of the back metal direct connection structure 127 in the second direction is connected to the second gate structure 124; the first end of the front metal direct connection structure 117 in the second direction is connected to the second end of the front direct connection via structure 116 in the first direction, and the second end of the front metal direct connection structure 117 in the second direction is connected to the first gate structure 114.

[0085] It can be understood that the back metal direct connection structure 127 is respectively connected to the back direct connection via structure 126 and the second gate structure 124, and the back direct connection via structure 126 is connected to the first source / drain region metal 115. Therefore, the back direct connection via structure 126 and the back metal direct connection structure 127 are jointly used to connect the first source / drain region metal 115 and the second gate structure 124. The front metal direct connection structure 117 is respectively connected to the front direct connection via structure 116 and the first gate structure 114, and the front direct connection via structure 116 is connected to the second source / drain region metal 125. Therefore, the front direct connection via structure 116 and the front metal direct connection structure 117 are jointly used to connect the second source / drain region metal 125 and the first gate structure 114.

[0086] In some embodiments, the manufacturing process for forming the back metal direct connection structure 127 and the front metal direct connection structure 117 may be a deposition process. The material used in this deposition process may be a metal material.

[0087] In some embodiments, forming the back metal direct connection structure 127 connecting the back direct connection via structure 126 and the second gate structure 124 in step S304 may include: depositing a dielectric material on the surface of the back direct connection via structure 126 away from the first transistor 11 and the surface of the second gate structure 124 away from the first transistor 11 to form a first back dielectric layer; etching the first back dielectric layer until a first portion of the back direct connection via structure 126 and the second gate structure 124 is exposed to form a back gate-source direct connection groove; depositing a metal material in the back gate-source direct connection groove to form the back metal direct connection structure 127.

[0088] It can be understood that after the formation of the back direct connection via structure 126, a dielectric material can be deposited on the surfaces of the back direct connection via structure 126 and the second gate structure 124 away from the first transistor 11 to form a first back dielectric layer 21. Subsequently, the first back dielectric layer 21 at a preset position is etched until the first part of the back direct connection via structure 126 and the second gate structure 124 is exposed to form a back gate-source direct connection groove. Here, the first part of the second gate structure 124 can be a part of the second gate structure 124 adjacent to the back direct connection via structure 126 in the second direction. After the formation of the back gate-source direct connection groove, a metal material is deposited in the back gate-source direct connection groove to obtain a back metal direct connection structure 127.

[0089] In some embodiments, forming the front metal direct connection structure 117 connecting the front direct connection via structure 116 and the first gate structure 114 in step S304 may include: depositing a dielectric material on the surface of the front direct connection via structure 116 away from the second transistor 12 and the surface of the first gate structure 114 away from the second transistor 12 to form a first front dielectric layer 23; etching the first front dielectric layer 23 until the first part of the front direct connection via structure 116 and the first gate structure 114 is exposed to form a front gate-source direct connection groove; depositing a metal material in the front gate-source direct connection groove to form the front metal direct connection structure 117.

[0090] It can be understood that after the formation of the front direct connection via structure 116, a dielectric material can be deposited on the surfaces of the front direct connection via structure 116 and the first gate structure 114 away from the second transistor 12 to form a first front dielectric layer 23. Subsequently, the first front dielectric layer 23 at a preset position is etched until the first part of the front direct connection via structure 116 and the first gate structure 114 is exposed to form a front gate-source direct connection groove. Here, the first part of the first gate structure 114 can be a part of the first gate structure 114 adjacent to the front direct connection via structure 116 in the second direction. After the formation of the front gate-source direct connection groove, a metal material is deposited in the front gate-source direct connection groove to obtain the front metal direct connection structure 117.

[0091] In step S305, a back source-drain direct connection structure 128 connecting the second source-drain region metal 125 and a first metal interconnection layer 129 connecting the back source-drain direct connection structure 128, and a front source-drain direct connection structure 118 connecting the first source-drain region metal 115 and a second metal interconnection layer 119 connecting the front source-drain direct connection structure 118 (as Figures 8 to 14 shown).

[0092] Among them, the back source-drain direct connection structure 128 is connected to the second source-drain region metal 125 of the front direct connection via-hole structure 116; the front source-drain direct connection structure 118 is connected to the first source-drain region metal 115 of the back direct connection via-hole structure 126.

[0093] It can be understood that after forming the back metal direct connection structure 127 and the back direct connection via-hole structure 126, the back metal direct connection structure 127 and the back direct connection via-hole structure 126 can connect the first source-drain region metal 115 to the second gate structure 124. Subsequently, the front source-drain direct connection structure 118 can be formed to connect the first source-drain region metal 115 to the second metal interconnection layer 119. After forming the front metal direct connection structure 117 and the front direct connection via-hole structure 116, the front metal direct connection structure 117 and the front direct connection via-hole structure 116 can connect the second source-drain region metal 125 to the first gate structure 114. Subsequently, the back source-drain direct connection structure 128 can be formed to connect the second source-drain region metal 125 to the first metal interconnection layer 129. Thus, the wiring requirements of the decoupling capacitor are met. In this way, a decoupling capacitor unit with a cross-coupled structure is formed between the first transistor 11 and the second transistor 12.

[0094] Exemplarily, the back metal direct connection structure 127 and the back direct connection via-hole structure 126 can connect the first source-drain structure in the first source-drain region metal 115 to the second gate structure 124, and the front source-drain direct connection structure 118 can connect the second source-drain structure in the first source-drain region metal 115 to the second metal interconnection layer 119. The front metal direct connection structure 117 and the front direct connection via-hole structure 116 can connect the third source-drain structure in the second source-drain region metal 125 to the first gate structure 114, and the back source-drain direct connection structure 128 can connect the fourth source-drain structure in the second source-drain region metal 125 to the first metal interconnection layer 129.

[0095] In some embodiments, forming the back source-drain direct connection structure 128 connecting the second source-drain region metal 125 and the first metal interconnection layer 129 connecting the back source-drain direct connection structure 128 in step S305 may include: depositing a dielectric material on the surface of the first back dielectric layer 21 away from the first transistor 11 to form a second back dielectric layer 22; etching the second back dielectric layer 22 and the first back dielectric layer 21 in sequence until the second source-drain region metal 125 not connected to the front direct connection via-hole structure 116 is exposed to form a back source-drain direct connection via-hole; depositing a metal material in the back source-drain direct connection via-hole to form the back source-drain direct connection structure 128; and forming the first metal interconnection layer 129 on the second back dielectric layer 22.

[0096] Among them, the first metal interconnect layer 129 has first metal interconnect lines, and the back source-drain direct connection structure 128 connects the second source-drain region metal 125 that is not connected to the front direct connection via-hole structure 116 and the first metal interconnect lines.

[0097] It can be understood that the second source-drain region metal 125 that is not connected to the front direct connection via-hole structure 116 can be connected to the first metal interconnect lines in the first metal interconnect layer 129 through the back source-drain direct connection structure 128. In this way, the subsequent interconnect lines of the second transistor 12 and the decoupling capacitor are connected, ensuring the normal use of the decoupling capacitor.

[0098] Exemplarily, when the third source-drain metal in the second source-drain region metal 125 is connected to the front direct connection via-hole structure 116, the fourth source-drain metal in the second source-drain region metal 125 can be connected to the first metal interconnect lines.

[0099] In some embodiments, the first metal interconnect lines can be the power supply lines in the first metal interconnect layer 129. For example, it is the power supply line VDD. In some embodiments, the power supply line VDD represents the power supply line connected to the voltage source. In some embodiments, the power supply line VDD represents the power supply line connected to the drain of the PMOS transistor.

[0100] In some embodiments, forming the front source-drain direct connection structure 118 connecting the first source-drain region metal 115 and the second metal interconnect layer 119 connecting the front source-drain direct connection structure 118 in step S305 may include: depositing a dielectric material on the surface of the first front dielectric layer 23 away from the second transistor 12 to form a second front dielectric layer 24; sequentially etching the second front dielectric layer 24 and the first front dielectric layer 23 until the first source-drain region metal 115 that is not connected to the back direct connection via-hole structure 126 is exposed to form a front source-drain direct connection via-hole; depositing a metal material in the front source-drain direct connection via-hole to form the front source-drain direct connection structure 118; forming the second metal interconnect layer 119 on the second front dielectric layer 24;

[0101] Among them, the second metal interconnect layer 119 has second metal interconnect lines, and the front source-drain direct connection structure 118 connects the first source-drain region metal 115 that is not connected to the back direct connection via-hole structure 126 and the second metal interconnect lines;

[0102] It can be understood that the first source-drain region metal 115 that is not connected to the back direct connection via-hole structure 126 can be connected to the second metal interconnect lines in the second metal interconnect layer 119 through the front source-drain direct connection structure 118. In this way, the subsequent interconnect lines of the first transistor 11 and the decoupling capacitor are connected, ensuring the normal use of the decoupling capacitor.

[0103] Exemplarily, when the second source / drain metal in the first source / drain region metal 115 is connected to the backside direct contact via structure 126, the first source / drain metal in the first source / drain region metal 115 can be connected to the second metal interconnect line.

[0104] In some embodiments, the second metal interconnect line is different from the first metal interconnect line.

[0105] In some embodiments, the second metal interconnect line can be a power line in the second metal interconnect layer 119. For example, it is the power line VSS. In some embodiments, the power line VSS represents a grounded power line. In some embodiments, the power line VSS represents a power line connected to the source of the NMOS transistor.

[0106] In some embodiments, the first metal interconnect line and the second metal interconnect line are opposite to each other in the first direction.

[0107] So far, the preparation of the decoupling capacitor in the embodiments of the present application is completed.

[0108] It should be noted that in the embodiments of the present application, the flip-chip process can be used multiple times to keep the same preparation direction during the preparation process of forming the decoupling capacitor. Here, the flip-chip process can be a process of flipping the structure in the first direction.

[0109] In the embodiments of the present disclosure, by forming a backside direct contact via structure connecting the front source / drain structure in the self-aligned stacked transistor, and then connecting the back gate structure and the backside direct contact via structure through the backside metal direct connection structure, the front source / drain structure is connected to the back gate structure. By forming a front direct contact via structure connecting the back source / drain structure in the self-aligned stacked transistor, and then connecting the front gate structure and the front direct contact via structure through the front metal direct connection structure, the back source / drain structure is connected to the front gate structure. In this way, the interconnect lines inside the decoupling capacitor are realized, which not only effectively reduces the preparation difficulty, but also does not increase the transistor cell size, helping to further improve the integration degree of the circuit.

[0110] In a second aspect, the embodiments of the present application provide a method for preparing a circuit module. The circuit module can include at least two decoupling capacitors. Each of the at least two decoupling capacitors can be prepared by using the preparation process described in the first aspect. Thus, the method for preparing the circuit module can include: forming an interconnect metal structure between the source / drain metals of the at least two decoupling capacitors to realize the parallel connection of multiple decoupling capacitor units.

[0111] It can be understood that the preparation method of forming the interconnect metal structure between multiple source / drain metals can also refer to the preparation method of the metal direct connection structure in the above one or more embodiments. For the sake of brevity of the specification, it will not be elaborated here.

[0112] In some embodiments, forming an interconnect metal structure between the source-drain metals of at least two decoupling capacitors may include: forming an interconnect metal structure that connects the first source-drain region metal in the first decoupling capacitor and the first source-drain region metal in the second decoupling capacitor. Wherein, a first end of the interconnect metal structure in a second direction is connected to the first source-drain region metal; a second end of the interconnect metal structure in the second direction is connected to the second source-drain region metal.

[0113] In some embodiments, forming an interconnect metal structure that connects the first source-drain region metal in the first decoupling capacitor and the first source-drain region metal in the second decoupling capacitor may include: simultaneously etching the first front dielectric layer in the first decoupling capacitor and the first front dielectric layer in the second decoupling capacitor until the first source-drain region metal in the first decoupling capacitor and the first source-drain region metal in the second decoupling capacitor are exposed to form an interconnect metal groove; wherein, the interconnect metal groove includes a first part and a second part that are connected, the first part is located in the first decoupling capacitor, and the second part is located in the second decoupling capacitor; depositing a metal material in the interconnect metal groove to form an interconnect metal structure.

[0114] It should be noted that according to actual usage requirements, the first source-drain region metal in the first decoupling capacitor and the second source-drain region metal in the second decoupling capacitor can also be connected through the interconnect metal structure, or the second source-drain region metal in the first decoupling capacitor and the first source-drain region metal in the second decoupling capacitor can be connected, etc. For the sake of simplicity of the specification, it will not be elaborated here.

[0115] Exemplarily, Figure 15 is a schematic diagram of a layout of a circuit module in an embodiment of the present application. Figure 16 is a schematic cross-sectional view of the circuit module in the embodiment of the present application along the second direction. Figures 15 to 16A first decoupling capacitor Decap1, a second decoupling capacitor Decap2, and a third decoupling capacitor Decap3 are shown. Among them, the first decoupling capacitor Decap1, the second decoupling capacitor Decap2, and the third decoupling capacitor Decap3 are arranged in parallel. Inside each of the first decoupling capacitor Decap1, the second decoupling capacitor Decap2, and the third decoupling capacitor Decap3, interleaved coupled interconnect lines can be formed through a metal direct connection structure (such as a backside metal direct connection structure). Connections are also formed between the first decoupling capacitor Decap1, the second decoupling capacitor Decap2, and the third decoupling capacitor Decap3 through a metal direct connection structure (such as an interconnect metal structure). Here, the first decoupling capacitor Decap1, the second decoupling capacitor Decap2, and the third decoupling capacitor Decap3 all have a node 1 and a node 2. After a connection is formed between the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2, node 2 can be shared between the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2. After a connection is formed between the second decoupling capacitor Decap2 and the third decoupling capacitor Decap3, node 3 can be shared between the second decoupling capacitor Decap2 and the third decoupling capacitor Decap3.

[0116] It can be seen that by using the above metal direct connection structure and combining vias with a large aspect ratio, the process manufacturing of the decoupling capacitor unit is realized under the condition of being compatible with the relevant "self-aligned flip-chip transistor" standard process. In addition, this implementation method of the decoupling capacitor unit can easily achieve the parallel connection of multiple decoupling capacitor units, such that the layout of N parallel decoupling capacitors occupies N + 1 contact pitches (CPP) in the second direction, thereby improving the integration degree of the decoupling capacitor.

[0117] In the embodiments of the present application, multiple decoupling capacitors are internally interconnected through an interconnect metal structure, thereby meeting the integration requirements of the circuit module. Since the interconnect metal structure is located between the back-end metal layer of the transistor and the active structure of the transistor, it is possible to reduce the wiring length of the upper metal in the back-end metal layer, save costs, and improve the signal transmission efficiency.

[0118] In a third aspect, the embodiments of the present application provide a decoupling capacitor, which can be prepared by using the preparation method in any one of the embodiments of the first aspect. Refer to Figure 14As shown, the decoupling capacitor may include: a first transistor 11 and a second transistor 12 disposed opposite to each other in a first direction, and the active structures of the first transistor 11 and the second transistor 12 are aligned in the first direction; wherein, the first transistor 11 includes: a first gate structure 114, a first source / drain region structure 112, and a first source / drain region metal 115 connected to the first source / drain region structure 112, and the first source / drain region structure 112 is located on both sides of the first gate structure 114 in a second direction; the second transistor 12 includes: a second gate structure 124, a second source / drain region structure 122, and a second source / drain region metal 125 connected to the second source / drain region structure 122, and the second source / drain region structure 122 is located on both sides of the second gate structure 124 in the second direction; the first gate structure 114 and the second gate structure 124 are opposite to each other in the first direction, and the first source / drain region structure 112 and the second source / drain region structure 122 are opposite to each other in the first direction; the second direction is perpendicular to the first direction; the first source / drain region metal 115 and the second source / drain region metal 125 are arranged in an interleaved manner in the first direction; the first source / drain region metal 115 is farther from the second source / drain region structure 122 than the first source / drain region structure 112, and the second source / drain region metal 125 is farther from the first source / drain region structure 112 than the second source / drain region structure 122;

[0119] a backside direct connection via structure 126, a backside metal direct connection structure 127, a backside source / drain direct connection structure 128, and a first metal interconnect layer 129; wherein, the first end of the backside direct connection via structure 126 in the first direction is connected to the first source / drain region metal 115; the first end of the backside metal direct connection structure 127 in the second direction is connected to the second end of the backside direct connection via structure 126 in the first direction, and the second end of the backside metal direct connection structure 127 in the second direction is connected to the second gate structure 124; the backside direct connection via structure 126 and the backside metal direct connection structure 127 are jointly used to connect the first source / drain region metal 115 and the first gate structure 114; the first end of the backside source / drain direct connection structure 128 in the first direction is connected to the second source / drain region metal 125 close to the backside metal direct connection structure 127, and the second end of the backside source / drain direct connection structure 128 in the first direction is connected to the first metal interconnect layer 129;

[0120] a front direct connection via structure 116, a front metal direct connection structure 117, a front source-drain direct connection structure 118, and a second metal interconnection layer 119; wherein, a first end of the front direct connection via structure 116 in a first direction is connected to a second source-drain region metal 125; the back direct connection via structure 126 and the front direct connection via structure 116 are respectively located on two sides of the first gate structure 114 in a second direction; a first end of the front metal direct connection structure 117 in the second direction is connected to a second end of the front direct connection via structure 116 in the first direction, and a second end of the front metal direct connection structure 117 in the second direction is connected to the first gate structure 114; the front direct connection via structure 116 and the front metal direct connection structure 117 are jointly configured to connect the second source-drain region metal 125 and the second gate structure 124; a first end of the front source-drain direct connection structure 118 in the first direction is connected to a first source-drain region metal 115 close to the front metal direct connection structure 117, and a second end of the front source-drain direct connection structure 118 in the first direction is connected to the second metal interconnection layer 119.

[0121] It can be understood that in the embodiments of the present application, by using a metal direct connection structure to form decoupling capacitor units arranged in a coupled and staggered manner, wherein, in Figure 14 (a), the gate structures of the upper and lower layers of transistors are respectively connected to the metal direct connection structures (including the back metal direct connection structure 127 and the front metal direct connection structure 117); in Figure 14 (b), the source-drain metal of the back PMOS is connected to the gate structure of the front NMOS through the metal direct connection structure (the front metal direct connection structure 117), corresponding to Figure 15 node 1 in the first decoupling capacitor Decap1. In Figure 14 (c), the gate structure of the back PMOS is connected to the source-drain metal of the front NMOS through the metal direct connection structure (the back metal direct connection structure 127), corresponding to Figure 15 node 2 in the first decoupling capacitor Decap1.

[0122] In some embodiments, the first metal interconnection layer 129 has a first metal interconnection line, and the back source-drain direct connection structure 128 connects the second source-drain region metal 125 that is not connected to the front direct connection via structure 116 and the first metal interconnection line; the second metal interconnection layer 119 has a second metal interconnection line, and the front source-drain direct connection structure 118 connects the first source-drain region metal 115 that is not connected to the back direct connection via structure 126 and the second metal interconnection line; the second metal interconnection line and the first metal interconnection line are different.

[0123] In some embodiments, the first source / drain region structure 112 includes a first source / drain structure and a second source / drain structure, and the first source / drain structure and the second source / drain structure are respectively located on two sides of the first gate structure 114 in the second direction; the second source / drain region structure 122 includes a third source / drain structure and a fourth source / drain structure, and the third source / drain structure and the fourth source / drain structure are respectively located on two sides of the second gate structure 124 in the second direction; the first source / drain structure and the third source / drain structure are opposite to each other in the first direction, and the second source / drain structure and the fourth source / drain structure are opposite to each other in the first direction; alternatively, the first source / drain structure and the fourth source / drain structure are opposite to each other in the first direction, and the second source / drain structure and the third source / drain structure are opposite to each other in the first direction.

[0124] In some embodiments, the first source / drain region metal 115 includes a first source / drain metal and a second source / drain metal. The first source / drain metal is connected to the first source / drain structure, and the second source / drain metal is connected to the second source / drain structure. The first source / drain metal and the second source / drain metal are staggeredly arranged in the third direction; the second source / drain region metal 125 includes a third source / drain metal and a fourth source / drain metal. The third source / drain metal is connected to the second source structure, and the fourth source / drain metal is connected to the fourth source / drain structure. The third source / drain metal and the fourth source / drain metal are staggeredly arranged in the third direction; the front direct connection via structure 116 and the back direct connection via structure 126 are respectively located on two sides of the first gate structure 114 in the second direction; the front direct connection via structure 116 and the back direct connection via structure 126 are located on the same side of the decoupling capacitor in the third direction.

[0125] Fourthly, an embodiment of the present application provides a circuit module, and the circuit module can be prepared by using the preparation method in any one of the embodiments of the second aspect. The circuit module includes at least two decoupling capacitors and an interconnecting metal structure; wherein, the structure of each decoupling capacitor in the at least two decoupling capacitors can refer to the description in any one of the embodiments of the third aspect. For the sake of brevity of the specification, it will not be described in detail here.

[0126] In some embodiments, the at least two decoupling capacitors include a first decoupling capacitor and a second decoupling capacitor; a first end of the interconnecting metal structure in the second direction is connected to the first source / drain region metal in the first decoupling capacitor; a second end of the interconnecting metal structure in the second direction is connected to the second source / drain region metal in the second decoupling capacitor.

[0127] It can be understood that in the application embodiment, after forming a self-aligned stacked transistor using a standard process, a backside direct connection via structure connecting the front source / drain structure is formed in the self-aligned stacked transistor, and then the back gate structure and the backside direct connection via structure are connected through a backside metal direct connection structure, so that the front source / drain structure is connected to the back gate structure. By forming a front direct connection via structure connecting the back source / drain structure in the self-aligned stacked transistor, and then connecting the front gate structure and the front direct connection via structure through a front metal direct connection structure, the back source / drain structure is connected to the front gate structure. In this way, the interconnection line inside the decoupling capacitor is realized, which not only effectively reduces the manufacturing difficulty, but also does not increase the transistor cell size, contributing to further improving the integration degree of the circuit.

[0128] At the same time, the self-aligned stacked transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar field-effect transistors, fin field-effect transistors, fully surrounding gate field-effect transistors, crossbar transistors, and even vertical field-effect transistors, without the need for special process development for specific device architectures, with strong flexibility and strong extensibility from the perspective of semiconductor process node iteration. The flip transistor is conceptually very advanced, has important industrial value, and has strong practicality and broad development prospects.

[0129] In a fifth aspect, an embodiment of the present application provides a semiconductor device, including: the decoupling capacitor and / or circuit module as described in the above embodiment. The specific structure of the decoupling capacitor can be referred to the above Figure 2 and Figure 14 as shown, and will not be elaborated here. The specific structure of the circuit module can be referred to the above Figures 15 to 16 as shown, and will not be elaborated here.

[0130] In a sixth aspect, an embodiment of the present application provides an electronic device, including: a circuit board and the semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned decoupling capacitor and / or circuit module. The specific structure of the decoupling capacitor can be referred to the above Figure 2 and Figure 14 as shown, and will not be elaborated here. The specific structure of the circuit module can be referred to the above Figures 15 to 16 as shown, and will not be elaborated here.

[0131] In the description of the present application, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0132] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a decoupling capacitor, characterized in that, Including: A first transistor and a second transistor are formed in a stack, wherein the active structures of the first transistor and the second transistor are aligned in a first direction; A first source / drain metal and a second source / drain metal are respectively formed in the source / drain regions on the first surface of the first transistor, and a third source / drain metal and a fourth source / drain metal are respectively formed in the source / drain regions on the second surface of the second transistor, wherein the first surface is the surface of the first transistor away from the second transistor, and the second surface is the surface of the second transistor away from the first transistor; A first connection structure connecting the first source / drain metal and the second gate structure of the second transistor and a second connection structure connecting the third source / drain metal and the first gate structure of the first transistor are respectively formed in the first transistor and the second transistor; Through a back-end process, a first metal interconnect layer is formed on the fourth source / drain metal and a second metal interconnect layer is formed on the second source / drain metal respectively.

2. The method according to claim 1, wherein The first source / drain metal and the third source / drain metal are staggered in the first direction or a second direction, and the second source / drain metal and the fourth source / drain metal are staggered in the first direction or the second direction; the second direction is the channel direction of the active structure, and the second direction is perpendicular to the first direction; The step of respectively forming in the first transistor and the second transistor a first connection structure connecting the first source / drain metal and the second gate structure of the second transistor and a second connection structure connecting the third source / drain metal and the first gate structure of the first transistor includes: Forming a back-side direct connection via structure connecting the first source / drain metal, and forming a front-side direct connection via structure connecting the third source / drain metal; Forming a back-side metal direct connection structure connecting the back-side direct connection via structure and the second gate structure, and forming a front-side metal direct connection structure connecting the front-side direct connection via structure and the first gate structure; wherein the back-side direct connection via structure and the back-side metal direct connection structure form the first connection structure, and the front-side direct connection via structure and the front-side metal direct connection structure form the second connection structure; The step of through a back-end process, forming a first metal interconnect layer on the fourth source / drain metal and a second metal interconnect layer on the second source / drain metal respectively includes: Forming a back-side source / drain direct connection structure connecting the fourth source / drain metal and a first metal interconnect layer connecting the back-side source / drain direct connection structure, and forming a front-side source / drain direct connection structure connecting the second source / drain metal and a second metal interconnect layer connecting the front-side source / drain direct connection structure.

3. The method according to claim 2, wherein The step of forming the back-side metal direct connection structure connecting the back-side direct connection via structure and the second gate structure includes: Depositing a dielectric material on the surface of the back-side direct connection via structure away from the first source / drain metal and the surface of the second gate structure away from the first gate structure to form a first back-side dielectric layer; Etch the first back dielectric layer until a first portion of the second gate structure and the back direct communication via structure are exposed to form a back gate-source direct connection groove; wherein, the first portion of the second gate structure is a portion of the second gate structure adjacent to the back direct communication via structure in the second direction; Deposit a metal material in the back gate-source direct connection groove to form the back metal direct connection structure.

4. The method according to claim 3, wherein The forming of the back source-drain direct connection structure connecting the fourth source-drain metal and the first metal interconnection layer connecting the back source-drain direct connection structure includes: Deposit a dielectric material on the surface of the first back dielectric layer away from the back direct communication via structure to form a second back dielectric layer; Etch the second back dielectric layer and the first back dielectric layer in sequence until the fourth source-drain metal is exposed to form a back source-drain direct communication via; Deposit a metal material in the back source-drain direct communication via to form the back source-drain direct connection structure; Form the first metal interconnection layer on the second back dielectric layer; wherein, the first metal interconnection layer has a first metal interconnection line, and the back source-drain direct connection structure connects the fourth source-drain metal and the first metal interconnection line.

5. The method according to claim 2, characterized in that, The forming of the front metal direct connection structure connecting the front direct communication via structure and the first gate structure includes: Deposit a dielectric material on the surface of the front direct communication via structure away from the third source-drain metal and the surface of the first gate structure away from the second gate structure to form a first front dielectric layer; Etch the first front dielectric layer until a first portion of the first gate structure and the front direct communication via structure are exposed to form a front gate-source direct connection groove; wherein, the first portion of the first gate structure is a portion of the first gate structure adjacent to the front direct communication via structure in the second direction; Deposit a metal material in the front gate-source direct connection groove to form the front metal direct connection structure.

6. The method according to claim 5, wherein The forming of the front source-drain direct connection structure connecting the second source-drain metal and the second metal interconnection layer connecting the front source-drain direct connection structure includes: Deposit a dielectric material on the surface of the first front dielectric layer away from the front direct communication via structure to form a second front dielectric layer; Etch the second front dielectric layer and the first front dielectric layer in sequence until the second source-drain metal is exposed to form a front source-drain direct communication via; Deposit a metal material in the front source-drain direct communication via to form the front source-drain direct connection structure; Form the second metal interconnection layer on the second front dielectric layer; wherein, the second metal interconnection layer has a second metal interconnection line, the front source-drain direct connection structure connects the second source-drain metal and the second metal interconnection line; the second metal interconnection line is different from the first metal interconnection line.

7. The method according to claim 1, characterized in that, The semiconductor structure further includes: a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is located on both sides of the first source / drain structure in a third direction, and the second interlayer dielectric layer is located on both sides of the third source / drain structure in the third direction; the third direction is perpendicular to the first direction and the second direction. The formation of the backside direct connection via structure connecting the first source / drain metal includes: Etching the second interlayer dielectric layer and the first interlayer dielectric layer in sequence until the first source / drain metal is exposed to form a first via hole. Depositing a metal material in the first via hole to form the backside direct connection via structure. The formation of the frontside direct connection via structure connecting the third source / drain metal includes: Etching the first interlayer dielectric layer and the second interlayer dielectric layer in sequence until the third source / drain metal is exposed to form a second via hole. Depositing a metal material in the second via hole to form the frontside direct connection via structure.

8. A method for preparing a circuit module, characterized in that, The circuit module includes: at least two decoupling capacitors, and each of the at least two decoupling capacitors is formed by using the method described in any one of claims 1 to 7; the at least two decoupling capacitors include: a first decoupling capacitor and a second decoupling capacitor. The method includes: Forming an interconnect metal structure connecting the first source / drain metal in the first decoupling capacitor and the second source / drain metal in the second decoupling capacitor, wherein a first end of the interconnect metal structure in the second direction is connected to the first source / drain metal; a second end of the interconnect metal structure in the second direction is connected to the second source / drain metal.

9. The method according to claim 8, wherein The formation of the interconnect metal structure connecting the first source / drain metal in the first decoupling capacitor and the second source / drain metal in the second decoupling capacitor includes: Simultaneously etching the first front dielectric layer in the first decoupling capacitor and the first front dielectric layer in the second decoupling capacitor until the first source / drain metal and the second source / drain metal are exposed to form an interconnect metal groove; wherein the interconnect metal groove includes a first part and a second part that are connected, the first part is located in the first decoupling capacitor, and the second part is located in the second decoupling capacitor. Depositing a metal material in the interconnect metal groove to form the interconnect metal structure.

10. A decoupling capacitor, characterized in that, Formed by using the method described in any one of claims 1 to 7, the decoupling capacitor includes: Forming a stacked first transistor and second transistor, wherein the active structures of the first transistor and the second transistor are aligned in the first direction. Wherein, the first transistor includes: a first gate structure, a first source / drain structure, a first source / drain metal connected to the first source / drain structure, a second source / drain structure, and a second source / drain metal connected to the second source / drain structure. The second transistor includes: a second gate structure, a third source / drain structure, a third source / drain metal connected to the third source / drain structure, a fourth source / drain structure, and a fourth source / drain metal connected to the fourth source / drain structure. The decoupling capacitor further includes: a first connection structure connecting the first source-drain metal and the second gate structure, and a second connection structure connecting the third source-drain metal and the first gate structure; a first metal interconnection layer connecting the fourth source-drain metal and a second metal interconnection layer connecting the second source-drain metal.

11. The decoupling capacitor according to claim 10, wherein The first connection structure includes: a backside direct via structure and a backside metal direct connection structure; the second connection structure includes: a front side direct via structure and a front side metal direct connection structure; The first metal interconnection layer further includes: a backside source-drain direct connection structure; wherein, a first end of the backside direct via structure in the first direction is connected to the first source-drain metal, a second end of the backside direct via structure in the first direction is connected to a first end of the backside metal direct connection structure in a second direction, and a second end of the backside metal direct connection structure in the second direction is connected to the second gate structure; a first end of the backside source-drain direct connection structure in the first direction is connected to the fourth source-drain metal, and a second end of the backside source-drain direct connection structure in the first direction is connected to the first metal interconnection layer; the second direction is the channel direction of the active structure, and the second direction is perpendicular to the first direction; The second metal interconnection layer further includes: a front side source-drain direct connection structure; wherein, a first end of the front side direct via structure in the first direction is connected to the third source-drain metal, a second end of the front side direct via structure in the first direction is connected to a first end of the front side metal direct connection structure in the second direction, and a second end of the front side metal direct connection structure in the second direction is connected to the first gate structure; a first end of the front side source-drain direct connection structure in the first direction is connected to the second source-drain metal, and a second end of the front side source-drain direct connection structure in the first direction is connected to the second metal interconnection layer.

12. The decoupling capacitor according to claim 11, characterized in that, The first metal interconnection layer has a first metal interconnecting line, and the backside source-drain direct connection structure connects the fourth source-drain metal and the first metal interconnecting line; The second metal interconnection layer has a second metal interconnecting line, and the front side source-drain direct connection structure connects the second source-drain metal and the second metal interconnecting line; the second metal interconnecting line is different from the first metal interconnecting line.

13. A circuit module, characterized in that, Prepared and formed by the method according to any one of claims 8 to 9, the circuit module includes: at least two decoupling capacitors and an interconnecting metal structure; Wherein, each of the at least two decoupling capacitors is the decoupling capacitor according to any one of claims 10 to 12; the at least two decoupling capacitors include: a first decoupling capacitor and a second decoupling capacitor; a first end of the interconnecting metal structure in the second direction is connected to the first source-drain metal in the first decoupling capacitor; a second end of the interconnecting metal structure in the second direction is connected to the second source-drain metal in the second decoupling capacitor.

14. A semiconductor device, characterized in that, Including: The decoupling capacitor according to any one of claims 10 to 12 and / or the circuit module according to claim 13.

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