Electronic device

Abstract

An electronic device includes a substrate, a conductive structure, an insulating layer, and a bonding structure. The conductive structure is disposed on the substrate and includes a first conductive layer, a second conductive layer, an interface metal compound, and a third conductive layer stacked in this order, where the interface metal compound includes a first opening exposing the second conductive layer. The insulating layer is disposed on the conductive structure and includes a second opening exposing the second conductive layer of the conductive structure. The bonding structure is disposed on the insulating layer, wherein the bonding structure is electrically connected to the conductive structure through the second opening of the insulating layer. A first width of the second opening of the insulating layer in the first direction is different from a second width of the interface metal compound in the first direction. The reliability of the electronic device provided by the invention can be improved.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an antenna device. Background Art

[0002] In an electronic device, a conductive structure including multiple conductive layers (such as a stacked layer of a titanium nitride layer, a copper layer, and a titanium nitride layer) is provided for use in a bonding process of a back-end-of-line (BEOL) process. However, if a relatively high-temperature process is experienced during the formation of the electronic device, titanium in the titanium nitride layer included in the conductive structure will diffuse towards the direction close to the copper layer, forming an interfacial metal compound including copper and titanium. This interfacial metal compound is difficult to remove through an etching process used during the formation of the electronic device, and will affect the electrical connection between the bonding structure and the conductive structure, resulting in a decrease in the reliability of the finally formed electronic device. Summary of the Invention

[0003] The present disclosure provides an electronic device with improved reliability.

[0004] According to some embodiments of the present disclosure, the electronic device includes a substrate, a conductive structure, an insulating layer, and a bonding structure. The conductive structure is disposed on the substrate and includes a first conductive layer, a second conductive layer, an interfacial metal compound, and a third conductive layer stacked in this order, wherein the interfacial metal compound includes a first opening exposing the second conductive layer. The insulating layer is disposed on the conductive structure and includes a second opening exposing the second conductive layer of the conductive structure. The bonding structure is disposed on the insulating layer, wherein the bonding structure is electrically connected to the conductive structure through the second opening of the insulating layer. A first width of the second opening of the insulating layer in a first direction is different from a second width of the interfacial metal compound in the first direction.

[0005] To make the above features and advantages of the present disclosure more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0006] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0007] Figure 1A A partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 1B is Figure 1A an enlarged cross-sectional schematic diagram of a first embodiment of region R in

[0009] Figure 2 is Figure 1A an enlarged cross-sectional schematic diagram of a second embodiment of region R in

[0010] Figure 3 is Figure 1A an enlarged cross-sectional schematic view of a third embodiment of region R in

[0011] Figure 4 is Figure 1A an enlarged cross-sectional schematic view of a fourth embodiment of region R in

[0012] Figure 5 is Figure 1A an enlarged cross-sectional schematic view of a fifth embodiment of region R in Detailed Description of the Invention

[0013] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that for the convenience of the reader's understanding and the simplicity of the drawings, only a part of the electronic device is shown in the multiple drawings of this disclosure, and the specific elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of this disclosure.

[0014] Throughout this specification and the appended claims, certain terms will be used to refer to particular elements. Those skilled in the art should understand that electronic device manufacturers may refer to the same element by different names. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "comprising", "including", "having" are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of this disclosure uses the terms "comprising", "including" and / or "having", it specifies the presence of the corresponding features, regions, steps, operations and / or components, but does not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0015] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions in the drawings. Therefore, the directional terms used are for illustration and not for limiting this disclosure. In the drawings, each drawing shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses and positions of each film layer, region and / or structure may be reduced or enlarged.

[0016] When a corresponding component (such as a film layer or a region) is referred to as "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as "directly on another component", there are no components between the two. Additionally, when a component is referred to as "on another component", the two have an up-and-down relationship in the top-down view direction, and this component can be above or below the other component, and this up-and-down relationship depends on the orientation of the device.

[0017] The terms "about", "substantially", or "roughly" are generally interpreted as within 10% of the given value or range, or as within 5%, 3%, 2%, 1%, or 0.5% of the given value or range.

[0018] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify elements, and they do not imply or represent that the (or those) elements have any previous ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish an element with a certain name from another element with the same name. The same terms may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

[0019] It should be noted that in the following embodiments, without departing from the spirit of the present disclosure, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments. As long as the features between the embodiments do not violate the spirit of the invention or conflict with each other, they can be arbitrarily mixed and used.

[0020] The electrical connections or couplings described in the present disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited to this.

[0021] In the present disclosure, the thickness, length, and width can be measured by using an optical microscope, and the thickness can be measured from the cross-sectional image in an electron microscope, but not limited to this. Additionally, there can be a certain error between any two values or directions used for comparison. If the first value is equal to the second value, it implies that there can be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0022] The electronic device disclosed herein may include, but is not limited to, an antenna device, a display device, a sensing device, a light-emitting device, or a splicing device. The electronic device may include a bendable or flexible electronic device. The electronic device, for example, includes a liquid crystal layer or a Light Emitting Diode (LED). The electronic device may include electronic components. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, Micro-Electro-Mechanical System (MEMS) components, liquid crystal chips, etc., but are not limited thereto. The diodes may include light-emitting diodes or photodiodes. The light-emitting diodes may, for example, include organic light-emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), quantum dot light-emitting diodes (quantum dot LEDs), fluorescence, phosphors, or other suitable materials, or combinations thereof, but are not limited thereto. The sensors may, for example, include capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, etc., but are not limited thereto.

[0023] The following exemplifies exemplary embodiments of the present disclosure, where the electronic device is taken as an antenna device for illustration, and the same reference numerals are used in the drawings and the description to represent the same or similar parts.

[0024] Figure 1A is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure, and Figure 1B is Figure 1A an enlarged cross-sectional schematic diagram of a first embodiment of the region R in

[0025] Please refer to Figure 1A and Figure 1B, the electronic device 10 of this embodiment includes a substrate SB, an insulating layer PV1, a conductive structure 100, an insulating layer PV2, a conductive layer M0, an insulating layer PV3, a semiconductor layer SE, an insulating layer PV4, a conductive layer M1, an insulating layer PV5, a conductive layer M2, an insulating layer PV6, a protective layer PL1, a conductive layer TM, an insulating layer PV7, a conductive layer M3, an insulating layer PV8, a protective layer PL2, an insulating layer PV9, and a bonding structure 200. From another perspective, the electronic device 10 of this embodiment includes a conductive structure 100, a bonding structure 200, and a driving device 300, wherein an insulating layer PV2 is disposed between the conductive structure 100 and the driving device 300, and the bonding structure 200 is electrically connected to the conductive structure 100 exposed by the opening OP2 of the insulating layer PV2. In this embodiment, the driving device 300 includes a driving element 310 and a storage capacitor 320, but the present disclosure is not limited thereto. It is worth noting that the electronic device 10 of this embodiment may, for example, include an antenna device, a display device, a sensing device, a light-emitting device, or a splicing device, but the present disclosure is not limited thereto. In this embodiment, the electronic device 10 is an antenna device. For example, the electronic device 10 may be applicable to the communication field, the radar / LIDAR field, the Reconfigurable Intelligent Surface (RIS) technology, or other suitable fields / technologies, but the present disclosure is not limited thereto. In some embodiments, the electronic device 10 may be a bendable or flexible electronic device, but the present disclosure is not limited thereto.

[0026] The material of the substrate SB may, for example, be glass, plastic, or a combination thereof. For example, the material of the substrate SB may include quartz, sapphire, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or a combination of the above materials, and the present disclosure is not limited thereto.

[0027] The insulating layer PV1 is, for example, disposed on the substrate SB. In this embodiment, the material of the insulating layer PV1 is an inorganic material. For example, the material of the insulating layer PV1 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0028] The conductive structure 100 is disposed, for example, on the insulating layer PV1. In some embodiments, the conductive structure 100 can serve as a pad portion, a ground plane, an electrostatic protection layer, an electromagnetic interference shielding layer, a heat dissipation layer, other layers with other uses, or a combination thereof in the electronic device 10. In some embodiments, the conductive structure 100 can occupy a surface area greater than 85% of the substrate SB in the top view direction Z of the substrate SB for shielding unwanted electromagnetic waves, but the present disclosure is not limited thereto. The material of the conductive structure 100 can include, for example, materials with low impedance such as copper, titanium, silver, gold, aluminum, tin, nickel, or a combination thereof. However, the material of the conductive structure 100 can also be, for example, other suitable materials or a combination of the above materials, and the present disclosure is not limited thereto.

[0029] The conductive structure 100 includes, for example, a multilayer structure. Please refer to Figure 1A and Figure 1B , in this embodiment, the conductive structure 100 includes a first conductive layer 110, a second conductive layer 120, and a third conductive layer 130 stacked in this order, wherein the material of the first conductive layer 110 is, for example, titanium nitride, the material of the second conductive layer 120 is, for example, copper, and the material of the third conductive layer 130 is, for example, titanium nitride. Since a relatively high-temperature dehydrogenation process is experienced during the formation of the active layer SE1 of the driving device 300, the titanium in the third conductive layer 130 diffuses towards the second conductive layer 120, forming an interfacial metal compound IMC. Based on this, the conductive structure 100 further includes an interfacial metal compound IMC disposed between the second conductive layer 120 and the third conductive layer 130.

[0030] The interfacial metal compound IMC includes, for example, an opening OP1 exposing the second conductive layer 120. In this embodiment, the opening OP1 exposing the second conductive layer 120 is formed before the active layer SE1 of the driving element 310 is formed. That is, the interfacial metal compound IMC has not been formed between the second conductive layer 120 and the third conductive layer 130 at this time, and the opening OP1 exposing the second conductive layer 120 can be formed by performing a simple patterning process on the third conductive layer 130. In some embodiments, the opening OP1 of the interfacial metal compound IMC has a width W1 in the direction X. In this embodiment, the width W1 is 87 micrometers, but the present disclosure is not limited thereto.

[0031] In this embodiment, the second conductive layer 120 includes a groove 120R. The groove 120R of the second conductive layer 120 overlaps at least partially with the opening OP1 of the interfacial metal compound IMC, for example, in the top view direction Z of the SB. Since the opening OP2 of the insulating layer PV2, which will be introduced later, is formed after the formation of the opening OP1 of the interfacial metal compound IMC, during the process of forming the opening OP2 of the insulating layer PV2, a part of the second conductive layer 120 exposed by the opening OP1 will also be removed, thereby forming the groove 120R of the second conductive layer 120.

[0032] The insulating layer PV2 is disposed on the conductive structure 100, for example, and includes an opening OP2 that exposes the conductive structure 100. In this embodiment, the material of the insulating layer PV2 is an inorganic material. For example, the material of the insulating layer PV2 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0033] In some embodiments, the opening OP2 of the insulating layer PV2 has a width W2 in the direction X. In this embodiment, the width W2 is 80 micrometers, but the present disclosure is not limited thereto. The width W2 of the opening OP2 of the insulating layer PV2 in the direction X is different from the width W1 of the interfacial metal compound IMC in the direction X, for example. Please refer to Figure 1B , in this embodiment, the width W2 of the opening OP2 of the insulating layer PV2 in the direction X is smaller than the width W1 of the interfacial metal compound IMC in the direction X, and the opening OP2 of the insulating layer PV2 overlaps with the opening OP1 of the interfacial metal compound IMC in the top view direction Z of the SB. Based on this, the insulating layer PV2 can contact the second conductive layer 120 exposed by the interfacial metal compound IMC. In some embodiments, the interface INF where the insulating layer PV2 contacts the second conductive layer 120 can be a copper oxide interface, which is formed by the reaction of the etching gas with copper when forming the opening OP2 of the insulating layer PV2 using an etching process, but the present disclosure is not limited thereto. In other embodiments, the interface INF where the insulating layer PV2 contacts the second conductive layer 120 can be a rough copper surface, which is formed by the corrosion of copper by the etching gas when forming the opening OP2 of the insulating layer PV2 using an etching process.

[0034] In this embodiment, since the opening OP2 of the insulating layer PV2 is formed after the opening OP1 for forming the interfacial metal compound IMC, the insulating layer PV2 includes an undercut UC1. Specifically, the opening OP2 of the insulating layer PV2 overlaps with the groove 120R of the second conductive layer 120 in the top view direction Z of the SB, and the width W2 of the opening OP2 of the insulating layer PV2 in the direction X is smaller than the width of the groove 120R of the second conductive layer 120 in the direction X. The width of the undercut UC1 of the insulating layer PV2 in the direction X can be, for example, 0.2 micrometers to 0.3 micrometers, but the present disclosure is not limited thereto.

[0035] In some embodiments, the insulating layer PV1 and the insulating layer PV2 can be selected to include materials with appropriate coefficients of thermal expansion; or materials that are opposite to the stress generated when the conductive structure 100 undergoes a heating process can be selected; or materials with good adhesion to the conductive structure 100 can be selected. Based on this, the insulating layer PV1 and the insulating layer PV2 respectively disposed below and above the conductive structure 100 can have the effect of stress regulation, which can be used to reduce the possibility of substrate warping. Specifically, since the process of forming the electronic device 10 undergoes multiple heating processes (including the process of forming the active layer SE1 of the driving element 310 described above), and the material included in the conductive structure 100 has a coefficient of thermal expansion greater than that of the material of the substrate SB, the edge of the substrate SB has a tendency to warp towards the direction facing the conductive structure 100. Based on this, the warping phenomenon generated in the substrate SB can be reduced by the setting of the insulating layer PV1 and the insulating layer PV2.

[0036] The conductive layer M0 is disposed on the insulating layer PV2, for example. In this embodiment, the conductive layer M0 includes a light-shielding layer BL and a storage electrode SC1 of the storage capacitor 320. The light-shielding layer BL is located, for example, between the substrate SB and the channel region of the active layer SE1 of the driving element 310, and at least partially overlaps with the channel region of the active layer SE1 in the top view direction Z of the substrate SB, thereby reducing the situation that the channel region of the active layer SE1 is affected and deteriorated by external ambient light irradiation. In some embodiments, the material of the conductive layer M0 can include a material with a transmittance lower than 30%, but the present disclosure is not limited thereto.

[0037] The insulating layer PV3 is disposed on the insulating layer PV2, for example. In this embodiment, the insulating layer PV3 covers the light-shielding layer BL and covers a part of the storage electrode SC1, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV3 is an inorganic material. For example, the material of the insulating layer PV3 can include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto. In this embodiment, the insulating layer PV3 is a stacked layer composed of a silicon oxide layer and a silicon nitride layer.

[0038] The semiconductor layer SE is disposed, for example, on the insulating layer PV3. In the present embodiment, the material of the semiconductor layer SE includes low temperature polysilicon (LTPS), but the present disclosure is not limited thereto. In other embodiments, the material of the semiconductor layer SE may include, but is not limited to, amorphous silicon, germanium, compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy), or a combination of the foregoing. The material of the semiconductor layer SE may also include, but is not limited to, metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO), or organic semiconductors including polycyclic aromatic compounds, or a combination of the foregoing. In the present embodiment, the semiconductor layer SE includes the active layer SE1 of the driving element 310 and the storage electrode SC2 of the storage capacitor 320. Specifically, in the present embodiment, the storage capacitor 320 is composed of the storage electrode SC1, the storage electrode SC2, and the insulating layer PV3 disposed between the storage electrode SC1 and the storage electrode SC2.

[0039] The insulating layer PV4 is disposed, for example, on the insulating layer PV3. In the present embodiment, the insulating layer PV4 covers a part of the active layer SE1 and a part of the storage electrode SC2, but the present disclosure is not limited thereto. In the present embodiment, the material of the insulating layer PV4 is an inorganic material. For example, the material of the insulating layer PV4 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials, but the present disclosure is not limited thereto. In the present embodiment, the insulating layer PV4 is a stacked layer composed of a silicon oxide layer and a silicon nitride layer.

[0040] The conductive layer M1 is disposed, for example, on the insulating layer PV4. In the present embodiment, the conductive layer M1 includes the gate G of the driving element 310 and the gate line GL. The gate G at least partially overlaps with the active layer SE1 in the top view direction Z of the substrate SB, for example. The gate line GL is electrically connected to the gate G of the driving element 310, for example, to provide a corresponding gate voltage to the driving element 310. In addition, in the present embodiment, the gate line GL may be electrically connected to the storage electrode SC1 of the storage capacitor 320 through an opening communicating in the insulating layer PV3 and the insulating layer PV4.

[0041] The insulating layer PV5 is disposed on the insulating layer PV4, for example. In this embodiment, the insulating layer PV5 covers the gate G and a part of the gate line GL, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV5 is an inorganic material. For example, the material of the insulating layer PV5 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto. In this embodiment, the insulating layer PV5 is a stacked layer composed of a silicon oxide layer and a silicon nitride layer.

[0042] The conductive layer M2 is disposed on the insulating layer PV5, for example. In this embodiment, the conductive layer M2 includes the source S and the drain D of the driving element 310 and the data line DL. The source S and the drain D are separated from each other, for example, and cover at least a part of the active layer SE1. In this embodiment, the source S and the drain D can be electrically connected to the active layer SE1 through an opening communicating in the insulating layer PV4 and the insulating layer PV5, but the present disclosure is not limited thereto. The data line DL is electrically connected to the source S of the driving element DC of the driving element 310, for example, to provide a corresponding data voltage to the driving element 310. In addition, in this embodiment, the data line DL can be electrically connected to the storage electrode SC2 of the storage capacitor 320 through another opening communicating in the insulating layer PV4 and the insulating layer PV5. In some embodiments, the conductive layer M2 further includes a conductive layer M21, which can be electrically connected to the gate line GL through an opening in the insulating layer PV5. The provision of the conductive layer M21 can increase the cross-sectional area of the gate line GL, thereby reducing the impedance value generated by the gate line GL (the impedance value is inversely proportional to the cross-sectional area of the conductive layer), and improving the signal transmission quality of the driving element 310.

[0043] In this embodiment, the driving element 310 is composed of a gate G, a source S, a drain D, and an active layer SE1. It should be noted that although this embodiment shows that the driving element 310 can be any top-gate thin film transistor well-known to those skilled in the art, the present disclosure is not limited thereto.

[0044] The insulating layer PV6 is disposed on the insulating layer PV5, for example. In this embodiment, the insulating layer PV6 covers the drain D and the conductive layer M21, and covers a part of the source S and a part of the data line DL, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV6 is an inorganic material. For example, the material of the insulating layer PV6 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0045] The conductive layer TM is disposed on the insulating layer PV6, for example. In this embodiment, the conductive layer TM may include a conductive layer TM1 and a conductive layer TM2, where the conductive layer TM1 and the conductive layer TM2 are each electrically connected to the drain D and the data line DL exposed by the insulating layer PV6, but the present disclosure is not limited thereto. The material of the conductive layer TM may be, for example, a metal oxide. For example, the material of the conductive layer TM may include indium tin oxide, but the present disclosure is not limited thereto.

[0046] The protective layer PL1 is disposed on the insulating layer PV6, for example. In this embodiment, the protective layer PL1 includes an opening exposing the conductive layer TM, but the present disclosure is not limited thereto. In this embodiment, the material of the protective layer PL1 is an organic material. For example, the material of the protective layer PL1 may include a polyimide-based resin, an epoxy-based resin, an acrylic-based resin, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0047] The insulating layer PV7 is disposed on the protective layer PL1, for example. In this embodiment, the insulating layer PV7 is disposed in the opening of the protective layer PL1 and covers a part of the conductive layer TM, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV7 is an inorganic material. For example, the material of the insulating layer PV7 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0048] The conductive layer M3 is disposed on the insulating layer PV7, for example. In this embodiment, the conductive layer M3 includes a pixel electrode PE. In this embodiment, the pixel electrode PE can be electrically connected to the drain D of the driving element 310 through the opening of the insulating layer PV7 to receive the pixel voltage from the driving element 310, but the present disclosure is not limited thereto. In some embodiments, the conductive layer M3 further includes a conductive layer M31, which can be electrically connected to the data line DL through another opening in the insulating layer PV7. The setting of the conductive layer M31 can increase the cross-sectional area of the data line DL, thereby reducing the impedance value generated by the data line DL (the impedance value is inversely proportional to the cross-sectional area of the conductive layer), and improving the signal transmission quality of the driving element 310.

[0049] The insulating layer PV8 is disposed on the insulating layer PV7, for example. In this embodiment, the insulating layer PV8 covers the conductive layer M3, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV8 is an inorganic material. For example, the material of the insulating layer PV8 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0050] The protective layer PL2 is disposed, for example, on the insulating layer PV8. In this embodiment, the protective layer PL2 covers the insulating layer PV8, but the present disclosure is not limited thereto. In this embodiment, the material of the protective layer PL2 is an organic material. For example, the material of the protective layer PL2 may include a polyimide-based resin, an epoxy-based resin, an acrylic-based resin, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0051] The insulating layer PV9 is disposed, for example, on the protective layer PL2. In this embodiment, the insulating layer PV9 covers the protective layer PL2, but the present disclosure is not limited thereto. In this embodiment, the material of the insulating layer PV9 is an inorganic material. For example, the material of the insulating layer PV9 may include silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, but the present disclosure is not limited thereto.

[0052] The bonding structure 200 is disposed, for example, on the insulating layer PV2 and is electrically connected to the conductive structure 100 through the opening OP2 of the insulating layer PV2, for example. In some embodiments, the bonding structure 200 at least partially overlaps at least one of the opening OP1 of the interfacial metal compound IMC and the opening OP2 of the insulating layer PV2 in the top view direction Z of the substrate SB. In this embodiment, the bonding structure 200 overlaps the opening OP1 of the interfacial metal compound IMC and the opening OP2 of the insulating layer PV2 in the top view direction Z of the substrate SB. The bonding structure 200 includes, for example, a conductive layer 210 and a conductive layer 220 disposed on the conductive layer 210, wherein the materials of the conductive layer 210 and the conductive layer 220 may include, for example, a metal or an alloy. In this embodiment, the bonding structure 200 is formed by performing an electroless nickel immersion gold (ENIG) process. Based on this, the material of the conductive layer 210 is nickel, and the material of the conductive layer 220 is gold, but the present disclosure is not limited thereto.

[0053] In some embodiments, a wafer (not shown) may be disposed on the bonding structure 200, but the present disclosure is not limited thereto. The wafer may include, for example, communication components. In some embodiments, the wafer may include a varactor, variable capacitor, radio frequency radiation element, variable resistor, phase shifter, amplifier, antenna, biometric sensor, graphene sensor, other suitable components, or combinations thereof, but the present disclosure is not limited thereto. For example, the wafer may be a varactor. The varactor may provide different capacitance values according to signals provided by a driving element to be introduced later, that is, by changing the voltage across the varactor, the capacitance value of the varactor can be changed. Therefore, by adjusting the capacitance value of the varactor, the operating frequency band of the electronic device 10 in this embodiment can be adjusted, but the present disclosure is not limited thereto.

[0054] Figure 2 is Figure 1A an enlarged cross-sectional schematic view of a second embodiment of the region R in Figure 2 The embodiments of Figure 1B may follow the component numbers and some content of the embodiments of

[0055] Please refer to Figure 2 This embodiment and Figure 1A The main difference between the embodiment shown in

[0056] Specifically, in this embodiment, the opening OP2 of the insulating layer PV2 formed by the patterning process is offset in the direction X and does not completely overlap with the opening OP1 of the interfacial metal compound IMC. Based on this, a part of the third conductive layer 130 is removed during the process of forming the opening OP2 of the insulating layer PV2, and the interfacial metal compound IMC can act as an etch stop layer, so that the opening OP2 of the insulating layer PV2 exposes a part of the interfacial metal compound IMC. However, the present disclosure is not limited thereto. In some other embodiments, the third conductive layer 130 can act as an etch stop layer, so that the opening OP2 of the insulating layer PV2 exposes a part of the third conductive layer 130.

[0057] The interfacial metal compound IMC exposed by the opening OP2 of the insulating layer PV2 has, for example, a width W3 in the direction X. In this embodiment, the width W3 of the exposed interfacial metal compound IMC is 0.5 micrometers, but the present disclosure is not limited thereto. Additionally, in this embodiment, the exposed interfacial metal compound IMC also includes an undercut UC2. The width of the undercut UC2 of the interfacial metal compound IMC in the direction X can be, for example, from 0.2 micrometers to 0.3 micrometers, but the present disclosure is not limited thereto.

[0058] In this embodiment, the bonding structure 200 is in contact with the interfacial metal compound IMC exposed by the opening OP2 of the insulating layer PV2. There is relatively good adhesion between the conductive layer 210 of the bonding structure 200 and the exposed interfacial metal compound IMC. Moreover, the interfacial metal compound IMC exposed by the opening OP2 of the insulating layer PV2 can have relatively good water and oxygen barrier properties. Based on this, by contacting the bonding structure 200 with the interfacial metal compound IMC, the reliability of the electrical connection between the bonding structure 200 and the conductive structure 100 can be increased.

[0059] Figure 3 For Figure 1A an enlarged cross-sectional schematic view of the third embodiment of the region R in Figure 3 The embodiments of Figure 2 can follow the reference numerals and partial content of the embodiments of

[0060] Please refer to Figure 3 This embodiment and Figure 2 The main difference between the embodiment shown in

[0061] is that the width W2 of the opening OP2 of the insulating layer PV2 in the direction X is greater than the width W1 of the opening OP1 of the interfacial metal compound IMC in the direction X.

[0062] Figure 4 For Figure 1A an enlarged cross-sectional schematic view of the fourth embodiment of the region R in Figure 4 The embodiments of Figure 3 can follow the reference numerals and partial content of the embodiments of

[0063] Please refer to Figure 4 This embodiment and Figure 3The main difference of the illustrated embodiment is that the opening OP2 of the insulating layer PV2 exposes a portion of the third conductive layer 130.

[0064] Specifically, in this embodiment, the third conductive layer 130 is used as an etching stop layer during the process of forming the opening OP2 of the insulating layer PV2. Therefore, after the opening OP2 of the insulating layer PV2 is formed, the opening OP2 of the insulating layer PV2 exposes a portion of the third conductive layer 130. In this embodiment, the bonding structure 200 contacts the third conductive layer 130 exposed by the opening OP2 of the insulating layer PV2. Similar to Figure 2 the illustrated embodiment, since there is relatively good adhesion between the conductive layer 210 of the bonding structure 200 and the exposed third conductive layer 130, it can increase the adhesion between the bonding structure 200 and the conductive structure 100, and can increase the reliability of the electrical connection between the bonding structure 200 and the conductive structure 100.

[0065] Figure 5 For Figure 1A an enlarged cross-sectional schematic diagram of the fifth embodiment of the region R in Figure 5 The embodiments of Figure 3 can follow the element numbers and partial contents of the embodiments of

[0066] Please refer to Figure 5 , the main difference between this embodiment and Figure 3 the illustrated embodiment is that one side of the opening OP2 of the insulating layer PV2 is aligned with one side of the opening OP1 of the interfacial metal compound IMC.

[0067] In this embodiment, since one side of the opening OP2 of the insulating layer PV2 is aligned with one side of the opening OP1 of the interfacial metal compound IMC, the opposite side of the opening OP2 of the insulating layer PV2 exposes more of the interfacial metal compound IMC. In some embodiments, the bonding structure 200 may expose a portion of the interfacial metal compound IMC located on the opposite side of the opening OP2 of the insulating layer PV2, but the present disclosure is not limited thereto.

[0068] In addition, in some embodiments, the third conductive layer 130 may be used as an etching stop layer during the process of forming the opening OP2 of the insulating layer PV2. Based on this, in other embodiments, after the opening OP2 of the insulating layer PV2 is formed, the opening OP2 of the insulating layer PV2 exposes a portion of the third conductive layer 130.

[0069] In summary, in the electronic devices provided by some embodiments of the present disclosure, the opening exposing the copper layer of the conductive structure is formed before the active layer of the driving element is formed. Therefore, the interfacial metal compound has not been formed between the copper layer and the titanium nitride layer at this time, and the opening exposing the copper layer can be formed by a simple patterning process. Furthermore, the subsequently formed bonding structure can have a relatively good electrical connection with the conductive layer, which can improve the reliability of the electronic devices provided by some embodiments of the present disclosure.

[0070] In the electronic devices provided by some other embodiments of the present disclosure, the opening of the insulating layer exposes a part of the interfacial metal compound. There is relatively good adhesion between the bonding structure and the exposed interfacial metal compound. Furthermore, the interfacial metal compound exposed by the opening of the insulating layer can have relatively good water and oxygen barrier properties, which can further improve the reliability of the electrical connection between the bonding structure and the conductive layer in the electronic devices provided by some embodiments of the present disclosure.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily combined and used.

Claims

1. An electronic device, characterized in that, Comprising: A substrate; A conductive structure disposed on the substrate and including a first conductive layer, a second conductive layer, an interfacial metal compound, and a third conductive layer stacked in this order, wherein the interfacial metal compound includes a first opening exposing the second conductive layer; An insulating layer disposed on the conductive structure and including a second opening exposing the second conductive layer of the conductive structure; And A bonding structure disposed on the insulating layer, wherein the bonding structure is electrically connected to the conductive structure through the second opening of the insulating layer, wherein a first width of the second opening of the insulating layer in a first direction is different from a second width of the interfacial metal compound in the first direction.

2. The electronic device according to claim 1, wherein the first width is greater than the second width.

3. The electronic device according to claim 1, wherein the first width is less than the second width.

4. The electronic device according to claim 1, wherein the second conductive layer includes a groove, and the groove at least partially overlaps with the first opening of the interfacial metal compound.

5. The electronic device according to claim 1, wherein the insulating layer has an undercut.

6. The electronic device according to claim 1, wherein the insulating layer further exposes the third conductive layer of the conductive structure, and the bonding structure contacts the third conductive layer.

7. The electronic device according to claim 1, wherein the insulating layer further exposes the interfacial metal compound of the conductive structure, and the bonding structure contacts the interfacial metal compound.

8. The electronic device according to claim 7, wherein the interfacial metal compound has an undercut.

9. The electronic device according to claim 1, wherein one side of the second opening of the insulating layer is aligned with one side of the first opening of the interfacial metal compound.

10. The electronic device according to claim 9, wherein the insulating layer further exposes the interfacial metal compound of the conductive structure, and the bonding structure contacts the interfacial metal compound.

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