All-dielectric microstructure enhanced barrier impurity band infrared detector and preparation method thereof

Abstract

The invention belongs to the technical field of very long wave infrared detectors, and particularly relates to an all-dielectric microstructure enhanced barrier impurity band infrared detector and a preparation method thereof. The device structure comprises a substrate, a bottom contact layer, a gallium-doped silicon absorption layer, a barrier layer, a top contact layer and a silicon oxide dielectric layer from bottom to top, and further comprises a positive electrode and a negative electrode which are located on the top contact layer, and an all-dielectric microstructure located between the positive electrode and the negative electrode, and the negative electrode is positioned above the top electrode contact region below the silicon oxide dielectric layer. According to the device, gallium-doped silicon is used as an absorption layer of very long wave infrared rays, and the blocking layer is used for inhibiting dark current under working bias voltage, so that high-sensitivity detection of the very long wave infrared rays is realized. Meanwhile, by introducing an all-dielectric microstructure to couple incident photons to excite transverse mode transmission, very long wave photons are localized in an absorption layer of the device, and then the silicon-based barrier impurity band infrared detector with enhanced broadband and high sensitivity is prepared.

Description

Technical Field

[0001] The present invention belongs to the technical field of very long wavelength infrared detectors, and particularly relates to a all-dielectric microstructure enhanced blocked impurity band infrared detector and a preparation method thereof. Background Art

[0002] Very long wavelength infrared detection has important application values in fields such as deep space exploration and non-destructive industrial inspection. Among them, silicon-based infrared detectors have become one of the excellent choices for infrared detectors due to advantages such as low cost, high integration, and a mature silicon process platform. However, the wavelength band of traditional silicon-based infrared detectors is limited by the intrinsic bandgap and cannot detect infrared light above 1100 nm. Currently, through doping engineering, super-bandgap detection can be achieved, and among them, silicon-based devices with blocked impurity band structures have been widely studied. However, silicon-based blocked impurity band infrared detectors operate based on impurity band transitions, and the impurity absorption coefficient is weak, resulting in limited quantum efficiency of the devices.

[0003] Currently, one-dimensional gratings or two-dimensional holey metal resonant metasurfaces are applied to silicon-based blocked impurity band infrared detectors to enhance the response of the devices at specific peak positions. The technology based on the excitation of surface plasmon polaritons on metals is only applicable to the near-field active region and is not applicable to vertical blocked impurity band devices. Moreover, due to the extremely large photon losses of metals in the very long wavelength band, the light flux distribution in the active region is reduced. At the same time, one of the advantages of silicon-based blocked impurity bands is their wide spectral response characteristics. However, using metal resonant metasurfaces to enhance narrowband responses contradicts the characteristics of wide-spectrum detectors, resulting in the inability to maximize the working advantages of silicon-based blocked impurity bands. In addition, Chinese invention patent CN115642190A also discloses a method for enhancing a planar blocked impurity band long wavelength infrared detector with phonon polaritons. Although this structure enhances the absorption efficiency near the narrow spectral band of 12 μm at a specific peak position, due to the near-field enhancement of phonon polaritons being only confined to the surface of the planar device, it is not applicable to the coupling and integration of vertical blocked impurity band devices. Therefore, it is necessary to conduct further design research to enhance blocked impurity band infrared detectors. Summary of the Invention

[0004] In order to overcome the above deficiencies of the prior art, the present invention proposes a all-dielectric microstructure coupled vertical silicon-based blocked impurity band infrared detector and a preparation method thereof, which realizes the photon residence effect and enhanced wide-spectrum response in the active region, and the all-dielectric microstructure is completely compatible with the all-silicon process, having broad application prospects.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] In the first aspect of the present invention, a blocked impurity band infrared detector integrated with a all-dielectric microstructure is provided. The blocked impurity band infrared detector includes a substrate, a bottom contact layer, a gallium-doped silicon absorption layer, a blocking layer, a top contact layer, and a silicon dioxide dielectric layer from bottom to top; it further includes a positive electrode and a negative electrode located above the top contact layer and a all-dielectric microstructure located between the positive electrode and the negative electrode; wherein, the positive electrode and the negative electrode form a good ohmic contact, the all-dielectric microstructure is a regularly arranged periodic air dielectric structure and is embedded in the gallium-doped silicon absorption layer of the device, the positive electrode is located above the recessed deep groove, and the deep groove is embedded in the bottom contact layer.

[0007] Preferably, the all-dielectric microstructure is a periodic two-dimensional regular deep hole structure, the period P of the holes is 12-18 μm, the ratio of the diameter D to the period P is 0.6-0.72, and the number of holes is greater than 1000.

[0008] Preferably, the blocked impurity band infrared detector has a photon residence effect and a wide-spectrum response enhancement effect in the wavelength range of 12-16 μm.

[0009] Preferably, both the substrate and the blocking layer are intrinsic silicon, and their thicknesses are 450-550 μm and 2-4 μm respectively.

[0010] Preferably, the doping elements of both the bottom contact layer and the top contact layer are boron, and the doping concentrations are 1-3×10 20 cm -3 and 2-4×10 19 cm -3 .

[0011] Preferably, the thickness of the gallium-doped silicon absorption layer is 4-6 μm, and the doping concentration of gallium is 1-3×10 17 cm -3 .

[0012] Preferably, the thickness of the silicon dioxide dielectric layer 6 is 150-250 nm.

[0013] Preferably, the positive electrode 7 and the negative electrode 8 are a titanium-aluminum double-layer metal, the thickness of titanium is 15-25 nm as an adhesion layer, and the thickness of aluminum is 150-250 nm.

[0014] In the second aspect of the present invention, a preparation method of the blocked impurity band infrared detector integrated with the all-dielectric microstructure described in the first aspect is provided, including the following steps:

[0015] S1. Form a bottom contact layer on the substrate through photolithography and ion implantation processes;

[0016] S2. Epitaxially grow a gallium-doped silicon absorption layer and a blocking layer on the bottom contact layer by molecular beam epitaxy;

[0017] S3. Form a top contact layer on the barrier layer through a patterning and ion implantation process, and then complete impurity activation through rapid annealing;

[0018] S4. Deposit a silicon oxide dielectric layer (6) on the wafer surface through a low-temperature plasma-enhanced chemical vapor method, and at the same time pattern and etch to form positive and negative electrode windows;

[0019] S5. Grow the positive and negative electrodes through photolithography and magnetron sputtering, and anneal to form a good ohmic contact;

[0020] S6. Form a fully dielectric microstructure through photolithography patterning and deep reactive ion etching;

[0021] S7. Deposit a silicon oxide dielectric layer through plasma-enhanced chemical vapor deposition to passivate the surface defects brought by etching and protect the device surface;

[0022] S8. Open positive and negative electrode windows through ion beam etching to expose the positive and negative electrodes.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] The present invention discloses a fully dielectric microstructure-coupled vertical silicon-based barrier impurity band infrared detector. The device structure includes a substrate, a bottom contact layer, a gallium-doped silicon absorption layer, a barrier layer, a top contact layer, and a silicon oxide dielectric layer from bottom to top. It also includes a positive electrode and a negative electrode above the top contact layer and a fully dielectric microstructure between the positive electrode and the negative electrode. The positive electrode is located above the deep groove, and the negative electrode is located above the top electrode contact area under the silicon oxide dielectric layer. The preparation method includes forming the bottom contact layer and the top contact layer by ion implantation, growing the absorption layer and the barrier layer by molecular beam epitaxy to complete the barrier impurity band structure material; then forming a back electrode groove by deep reactive ion etching of silicon material, and completing the interconnection of the metal and the top and bottom electrode contact areas by magnetron sputtering; then completing the preparation of the fully dielectric microstructure through steps such as photolithography and deep reactive ion etching; finally, realizing surface passivation and mesa protection of the device by low-temperature plasma-enhanced deposition of a silicon oxide layer. The device of the present invention uses gallium-doped silicon as the absorption layer for very long wavelength infrared, and uses a barrier layer to suppress the dark current under the working bias voltage, thereby realizing high-sensitivity detection of very long wavelength infrared. At the same time, by introducing a fully dielectric microstructure to couple the incident photons to excite transverse mode transmission, the very long wavelength photons are localized in the absorption layer of the device, and then a broadband-enhanced silicon-based barrier impurity band infrared detector is prepared. It has been found through research that the device of the present application realizes the localization of very long wavelength photons in the active region of the device, breaks through problems such as the low absorption coefficient of traditional shallow-level impurities and the weak response of very long wavelength infrared signals, improves the photoelectric conversion efficiency of the silicon-based very long wavelength infrared detector, and in the wavelength range of 12 - 19 μm, the responsivity of the device is enhanced by more than 285%. Description of the Drawings

[0025] Figure 1 It is a schematic cross-sectional view of a fully dielectric microstructure integrated silicon-based impurity band blocking infrared detector;

[0026] Figure 2 It is a top view and a partial schematic view of the fully dielectric microstructure on the device;

[0027] Figure 3 It is a distribution diagram of the quantum efficiency of the fully dielectric microstructure integrated silicon-based impurity band blocking infrared detector and the traditional silicon-based impurity band blocking device versus wavelength;

[0028] Figure 4 It is a graph of the change in the quantum efficiency of silicon-based impurity band blocking infrared detectors integrated with different fully dielectric microstructure parameters; where Figure 4 (a) shows the change in the quantum efficiency when the physical quantity period P changes. The periods P are 12μm, 14μm, 16μm, and 18μm respectively, and D / P = 0.7; Figure 4 (b) shows the change in the quantum efficiency when the physical quantity D / P changes. The period P = 12μm, and D / P are 0.6, 0.65, 0.68, 0.7, and 0.72 respectively.

[0029] Figure 5 It is a light field distribution diagram of a fully dielectric microstructure integrated silicon-based impurity band blocking infrared detector (period P = 12μm, D / P = 0.68); Note: The absorption layer source region involved in the figure refers to the specific region in the infrared detector that is responsible for absorbing infrared radiation and converting it into other detectable signals (such as electrical signals). Specific embodiments

[0030] The following further describes the specific embodiments of the present invention. It should be noted here that the description of these embodiments is for helping to understand the present invention, but does not constitute a limitation to the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] The experimental methods in the following embodiments are all conventional methods unless otherwise specified, and the test materials used in the following embodiments are all available through conventional commercial channels unless otherwise specified.

[0032] Embodiment: A fully dielectric microstructure enhanced impurity band blocking infrared detector and its preparation method

[0033] The all-dielectric microstructure enhanced barrier impurity band infrared detector includes, from bottom to top, a substrate 1, a bottom contact layer 2, a silicon gallium-doped absorption layer 3, a barrier layer 4, a top contact layer 5, and a silicon oxide dielectric layer 6. It also includes a positive electrode 7 and a negative electrode 8 above the top contact layer 5, and an all-dielectric microstructure 9 between the positive electrode 7 and the negative electrode 8. Among them, the positive electrode 7 and the negative electrode 8 form a good ohmic contact. The all-dielectric microstructure 9 is a regular periodic arrangement of air dielectric structures and is embedded in the silicon gallium-doped absorption layer 3 of the device. The positive electrode 7 is located above the sunken deep groove 10, and the deep groove 10 is embedded in the bottom contact layer 2.

[0034] Both the substrate 1 and the barrier layer 4 are intrinsic silicon. The thickness of the substrate 1 is about 500 μm, and the thickness of the barrier layer 4 is 3 μm. The doping elements of the bottom contact layer 2 and the top contact layer 5 are both boron (i.e., silicon doped with boron), and the doping concentrations are 1×10 20 cm -3 and 3×10 19 cm -3 , respectively, and the thicknesses are both 0.2 μm. The thickness of the silicon gallium-doped absorption layer 3 is 5 μm, and the doping concentration of gallium is 2×10 17 cm -3 ; The thickness of the silicon oxide dielectric layer 6 is 200 nm. The positive electrode 7 and the negative electrode 8 are both double-layer titanium-aluminum metals. The thickness of titanium is 20 nm as an adhesion layer, and the thickness of aluminum is 200 nm.

[0035] The preparation method of the above all-dielectric microstructure enhanced silicon-based barrier impurity band infrared detector includes the following steps:

[0036] (1) By ion implanting boron element on a four-inch silicon wafer substrate 1 (thickness about 500 μm, resistivity greater than 10000 Ω·cm), a 0.2-μm-thick bottom contact layer 2 is formed. The energy of ion implantation is 80 keV, and the dose is 1×10 15 cm -2 ;

[0037] (2) By molecular beam epitaxy, grow the silicon gallium-doped absorption layer 3 and the pure silicon barrier layer 4. The growth temperature of the wafer substrate is 580±10 °C, and the temperature of the crucible gallium source is 660±10 °C. Among them, the doping concentration of the silicon gallium-doped absorption layer 3 is 2×10 17 cm 3 , the barrier layer 4 is pure silicon, and the background impurity concentration is lower than 5×10 12 cm 3 , and the thicknesses are 5 μm and 3 μm, respectively;

[0038] (3) First, spin-coat photoresist on the surface. The model is AZ1518 (positive photoresist), the rotation speed is 1000 revolutions per second, and the thickness is 3 μm. Then, perform a post-exposure bake at 100 °C for 60 seconds. Next, perform ultraviolet exposure, and the exposure dose is 339 mj / cm 2 , put the exposed wafer into 100 mL of AZ300 alkaline developer and develop for 90 s. After that, pattern ion implantation of boron element is carried out, the implantation energy is 50 keV, and the dose is 3×10 14 cm -2 , and then form a top contact layer 5 on the upper surface of the barrier layer 4;

[0039] (4) Put the silicon wafer material into a rapid annealing furnace at 950 °C and anneal for 30 s to complete the activation of impurity atoms and defect repair. At this time, the material of the barrier impurity structure has been prepared;

[0040] (5) Use acetone, isopropyl alcohol, and alcohol organic solvents to ultrasonically clean the silicon wafer material for 10 minutes in sequence. The concentration of the alcohol used to clean the silicon wafer is 99.5%, the ultrasonic power is 50 W, then perform plasma cleaning. The power of the plasma cleaning equipment is set to 100 W, the gas is oxygen plasma, and the time is 5 minutes. Then, deposit a silicon oxide dielectric layer 6 by plasma-enhanced chemical vapor deposition, with a thickness of 200 nm;

[0041] (6) Spin-coat photoresist on the surface. The model is AZ1518, the rotation speed is 1000 revolutions per second, and the thickness is 3 μm. Then, perform a post-exposure bake at 100 °C for 60 seconds. Next, perform ultraviolet exposure, and the exposure dose is 339 mj / cm 2 , put the exposed wafer into 100 mL of AZ300 alkaline developer and develop for 90 s;

[0042] (7) First, selectively etch the surface silicon oxide dielectric layer 6 by ion beam to complete the bottom electrode layer window, and the etching depth is 200 nm. Then, etch the silicon material by deep reactive ion etching to a depth of 8.2 μm to form a recessed deep groove 10. The deep groove 10 is embedded in the bottom contact layer 2 (the ion beam etched 0.2 μm, and the deep silicon etching etched 8.2 μm, and the actual total etching is 8.4 μm);

[0043] (8) Put the silicon wafer sample into an acetone solution, heat it to 60 °C, and ultrasonically clean it for 10 minutes. The ultrasonic power is 60 W. Then, perform plasma cleaning for 10 minutes, and the power is 200 W to remove the residual photoresist;

[0044] (9) Spin-coat photoresist (negative photoresist) on the surface. The model is nr9-1000py, and the thickness is 1.5 μm. Then, perform ultraviolet exposure, and the exposure dose is 65 mj / cm 2; Then place the wafer on a hot plate for post-baking at a temperature of 100 °C for 2 minutes; then place the post-baked wafer in RD6 developer, with the volume ratio of developer to water being 1:3 and the development time being 150 s,

[0045] (10) Place the silicon wafer sample in a magnetron sputtering device, deposit 20 nm of metal titanium and 200 nm of metal aluminum, and then place it in an acetone solution for stripping to form the positive electrode 7 and the negative electrode 8;

[0046] (11) Place the silicon wafer sample in an annealing furnace, set the temperature to 450 °C and the time to 5 min to complete alloying annealing;

[0047] (12) Spin-coat photoresist (positive photoresist) AZ1518 on the surface with a thickness of 3 μm, and then perform ultraviolet exposure with an exposure dose of 339 mj / cm 2 , place the exposed wafer in 100 mL of AZ300 alkaline developer for 90 s of development;

[0048] (13) Place the silicon wafer sample in a deep reactive ion etching device (manufactured by Samco of Japan, device model RIE-400iPB), set the period P to 12 μm, the diameter D to 8.2 μm, the etching depth to 5 μm, the number of holes to 1089, and embed it at the silicon gallium-doped absorption layer 3 of the device to form a all-dielectric microstructure 9 between the positive electrode 7 and the negative electrode 8, as Figure 2 shown;

[0049] (14) First, place the silicon wafer sample in an acetone solution, heat it to 60 °C, and use a plasma device to remove the residual photoresist with a power setting of 100 W, the gas being oxygen plasma and the time being 5 minutes; then deposit a silicon oxide dielectric layer 6 with a thickness of 100 nm by plasma-enhanced chemical vapor deposition, and the temperature of the etching device is 350 °C. This step is to passivate the surface defects caused by etching and protect the device surface;

[0050] (15) Spin-coat photoresist on the surface, with the model being AZ1518, the rotation speed being 1000 revolutions per second, and the thickness being 3 μm; then perform hard baking at 100 °C for 60 seconds; then perform ultraviolet exposure with an exposure dose of 339 mj / cm 2 , place the exposed wafer in 100 mL of AZ300 alkaline developer for 90 s of development;

[0051] (16) Ion beam selectively etch the silicon oxide dielectric layer 6 on the surface of the metal electrode with an etching depth of 100 nm to expose the positive and negative electrodes; after depositing the thin film, the device electrodes are blocked, so this step exposes the electrodes by etching.

[0052] (17) Dicing, wire bonding and device testing;

[0053] So far, the device fabrication has been completed through the above 16-step process. Among them, Figure 1 shows a schematic diagram of a fully dielectric microstructured contact silicon-based impurity band infrared detector fabricated through the above process. Figure 2 shows a top view and a partial schematic diagram of the fully dielectric microstructure on the device, used to illustrate the distribution of the fully dielectric microstructure on the device. The device size ranges from 400×400 μm 2 .

[0054] Figure 3 shows the quantum efficiency distributions of a fully dielectric microstructured silicon-gallium-doped impurity band infrared detector and a traditional silicon-based impurity band (without a fully dielectric microstructure 9) device. This quantum efficiency spectrum is obtained through standard Fourier transform infrared spectroscopy and blackbody response testing. First, the relative photocurrent spectrum as a function of wavelength is measured by a Fourier spectrometer, and from this, the distribution of the intensity-weighting factor as a function of wavelength is obtained. Then, the responsivity of the device under total incident light at a fixed bias is obtained through calibrated blackbody response testing, and the peak quantum efficiency at each wavelength is obtained by the total responsivity and the relative spectral distribution. Figure 3 Among them, the fully dielectric microstructure is a fully dielectric microstructure integrated device with a period P = 12 μm and D / P = 0.68. In the wavelength range of 12 - 19 μm, the quantum efficiency of the device is enhanced by more than 285%, and the highest quantum efficiency reaches 15%, while the quantum efficiency of the traditional device is only 5%. This shows that the response performance of the microstructured integrated device of the present invention is significantly improved compared to the traditional device.

[0055] In addition, further studying the influence of different structural parameters on the device performance, it is found that not all structural parameters can significantly improve the device performance. The specific study is as follows: Different-parameter fully dielectric microstructures are fabricated on a 400×400 μm 2 area. When the physical quantity period P is 12 μm, 14 μm, 16 μm, 18 μm respectively and D / P = 0.7, the quantum efficiency spectrum of the device is as shown in Figure 4 (a). The results show that when the period P is 12 μm, the performance of the microstructured integrated device is most significantly improved, and the quantum efficiency in the wavelength range of 12 - 16 μm is above 10% (the quantum efficiency of the traditional device is below 5%). However, when the period P deviates from 12 μm, the quantum efficiency in the corresponding wavelength section decreases significantly. In addition, when the physical quantity period P = 12 μm and D / P is 0.6, 0.65, 0.68, 0.7, and 0.72 respectively, the quantum efficiency spectrum of the device is as shown in Figure 4 (b). The results show that when D / P = 0.68, the performance of the microstructured integrated device is most significantly improved, and when deviating from this parameter, the performance will significantly decline. Based on the above research results, it can be seen that when the period P = 12 μm and D / P = 0.68, the performance of the fully dielectric microstructure integrated device reaches the optimum.

[0056] Figure 5 It shows the optical field distribution of a all-dielectric microstructured integrated silicon-based impurity band blocking infrared detector with a period P = 12 μm and D / P = 0.68. This figure obtains the electric field distribution at an incident wavelength of 14 μm through finite element analysis. It can be seen from the figure that the areas with strong optical fields are distributed in the absorption layer source region, demonstrating the local coupling effect of the microstructure on very long wavelength photons, and further illustrating that the all-dielectric microstructured integrated silicon-based impurity band blocking infrared detector constructed by the present invention realizes the photon residence effect in the active region and enhanced broadband response, thereby improving the photoelectric conversion efficiency of the silicon-based very long wavelength infrared detector.

[0057] The above has described the embodiments of the present invention in detail, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions, and variations made to these embodiments still fall within the protection scope of the present invention.

Claims

1. A all-dielectric microstructured coupled vertical silicon-based impurity band blocking infrared detector, characterized in that, The vertical silicon-based impurity band blocking infrared detector includes, from bottom to top, a substrate (1), a bottom contact layer (2), a gallium-doped silicon absorption layer (3), a blocking layer (4), a top contact layer (5), and a silicon oxide dielectric layer (6); it also includes a positive electrode (7) and a negative electrode (8) located above the top contact layer (5) and a all-dielectric microstructure (9) located between the positive electrode (7) and the negative electrode (8); wherein, the positive electrode (7) and the negative electrode (8) form a good ohmic contact, the all-dielectric microstructure (9) is a regularly periodically arranged air dielectric structure and is embedded at the gallium-doped silicon absorption layer (3) of the device, the positive electrode (7) is located above a sunken deep groove (10), and the deep groove (10) is embedded at the bottom contact layer (2).

2. The all-dielectric microstructured coupled vertical silicon-based impurity band blocking infrared detector according to claim 1, characterized in that, The all-dielectric microstructure (9) is a periodically two-dimensional regular deep hole structure, the period P of the holes is 12 - 18 μm, the ratio of the diameter D to the period P is 0.6 - 0.72, and the number of holes is greater than 1000.

3. A all-dielectric microstructured coupled vertical silicon-based blocked impurity band infrared detector according to claim 1, characterized in that, The vertical silicon-based impurity band blocking infrared detector has a photon residence effect and a wide-spectrum response enhancement effect in the wavelength range of 12 - 16 μm.

4. A all-dielectric microstructured coupled vertical silicon-based blocked-impurity-band infrared detector according to claim 1, characterized in that, Both the substrate (1) and the blocking layer (4) are intrinsic silicon, and their thicknesses are 450 - 550 μm and 2 - 4 μm respectively.

5. A all-dielectric microstructured coupled vertical silicon-based blocked-impurity-band infrared detector according to claim 1, wherein The doping elements of the bottom contact layer (2) and the top contact layer (5) are both boron, and the doping concentrations are 1-3×10 20 cm -3 and 2-4×10 19 cm -3 .

6. The all-dielectric microstructured coupled vertical silicon-based blocked impurity band infrared detector according to claim 1, wherein The thickness of the gallium-doped silicon absorption layer (3) is 4-6 μm, and the doping concentration of gallium is 1-3×10 17 cm -3 .

7. A all-dielectric microstructured coupled vertical silicon-based blocked impurity band infrared detector according to claim 1, characterized in that, The thickness of the silicon oxide dielectric layer (6) is 150 - 250 nm.

8. A all-dielectric microstructured coupled vertical silicon-based blocked impurity band infrared detector according to claim 1, wherein, The positive electrode (7) and the negative electrode (8) are a titanium-aluminum double-layer metal, the thickness of titanium is 15 - 25 nm as an adhesion layer, and the thickness of aluminum is 150 - 250 nm.

9. The preparation method of the all-dielectric microstructured coupled vertical silicon-based impurity band blocking infrared detector according to any one of claims 1-8, characterized in that, Including the following steps: S1. Form the bottom contact layer (2) on the substrate (1) through photolithography and ion implantation processes. S2. Epitaxially grow the gallium-doped silicon absorption layer (3) and the blocking layer (4) on the bottom contact layer (2) by molecular beam epitaxy. S3. Form the top contact layer (5) on the blocking layer (4) through patterning and ion implantation processes, and then complete impurity activation through rapid annealing. S4. Deposit the silicon oxide dielectric layer (6) on the wafer surface by low-temperature plasma enhanced chemical vapor deposition method, and at the same time pattern and etch to form positive and negative electrode windows. S5. Grow the positive electrode (7) and the negative electrode (8) through photolithography and magnetron sputtering, and anneal to form a good ohmic contact. S6. Form the all-dielectric microstructure (9) through photolithography patterning and deep reactive ion etching. S7. Deposit the silicon oxide dielectric layer (6) by plasma enhanced chemical vapor deposition to passivate surface defects caused by etching and protect the device surface. S8. Open positive and negative electrode windows through ion beam etching to expose the positive and negative electrodes.

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