Capacitor array, memory cell array and method for forming capacitor array

Abstract

A method of forming an array of capacitors includes forming horizontally spaced openings into a sacrificial material and passing them through an insulating material between a top and a bottom of the sacrificial material, the insulating material including at least predominantly at least one of SiN, SiBN, and SiCN, the insulating material through which horizontally spaced openings pass comprises an insulating level lattice; depositing an insulating liner within the opening and directly over the sacrificial material, the liner including at least mainly at least one of SiO and SiON; during the deposition, intermittently exposing the liner to a nitrogen-containing plasma; laterally forming first capacitor electrodes individually located within individual ones of the openings over the liner located in the openings; removing the sacrificial material and forming a capacitor insulator over the first capacitor electrode and the lattice; and forming a second capacitor electrode material over the capacitor insulator.

Description

Technical Field

[0001] The embodiments disclosed herein relate to capacitor arrays, memory cell arrays, and methods for forming capacitor arrays. Background Art

[0002] A memory is a type of integrated circuit system and is used in a computer system to store data. The memory can be fabricated as one or more arrays of individual memory cells. Digital lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines) can be used to write to or read from the memory cells. The digital lines can conductively interconnect the memory cells along the columns of the array, and the access lines can conductively interconnect the memory cells along the rows of the array. Each memory cell is uniquely addressed by a combination of a digital line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for an extended period without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is thus refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. In any case, the memory cells are configured to hold or store memory in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells can be configured to store information of more than two levels or states.

[0004] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored electrostatically in this material. Depending on the composition of the insulator material, the stored field will be volatile or non-volatile. For example, a capacitor insulator material that consists only of SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor that has a ferroelectric material as at least part of the insulating material. A ferroelectric material is characterized by having two stable polarization states and can thereby include programmable material for a capacitor and / or a memory cell. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and remains (at least for some time) after the programming voltage is removed. Each polarization state has a charge storage capacitance that is different from each other, and it can ideally be used for writing (i.e., storing) and reading a memory state without reversing the polarization state until it is needed to be reversed. Less desirably, in some memories with ferroelectric capacitors, the act of reading the memory state can reverse the polarization. Therefore, when determining the polarization state, the memory cell is rewritten to place the memory cell in a pre-read state immediately after its determination. In any case, due to the bistable characteristics of the ferroelectric material that forms part of the capacitor, a memory cell incorporating a ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as the capacitor insulator to make the capacitor non-volatile.

[0005] A field-effect transistor is a type of electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions that have a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. A field-effect transistor can also include additional structures, such as a reversibly programmable charge storage region as part of the gate structure between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, for example, ferroelectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a DRAM memory array and peripheral circuitry according to the prior art and according to an embodiment of the present invention.

[0007] Figure 2 is Figure 1 an enlarged view of a part of

[0008] Figure 3 is a schematic perspective view of a part of a substrate being processed according to an embodiment of the present invention.

[0009] Figures 4 to 15In the process according to some embodiments of the present invention Figure 1 schematic diagram of and Figure 3 the structure of or a part thereof or a partial hybrid schematic diagram or a partial schematic diagram and / or a diagrammatic sequential cross-section, expansion, magnification, perspective and / or partial view of an alternative embodiment. Detailed Description

[0010] Embodiments of the present invention include methods for forming capacitor arrays, such as those that can be used in memory or other integrated circuit systems. Embodiments of the present invention also cover methods for forming memory cell arrays, which, for example, include multiple capacitors located above multiple transistors. Embodiments of the present invention also cover capacitor arrays and memory cell arrays independent of the manufacturing method. Refer to Figures 1 to 15 Described is an exemplary embodiment of a method for forming a memory cell array.

[0011] In Figure 1 and 2 is shown a schematic diagram of an exemplary prior art DRAM circuit system according to an embodiment of the present invention. Figure 2 Shown is an exemplary memory cell MC individually including a transistor T and a capacitor C. The transistor T includes a pair of source / drain regions. The capacitor C includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator therebetween. One electrode of the capacitor C is directly electrically coupled to a suitable potential (e.g., ground), and the other capacitor electrode is in contact with or includes one of the source / drain regions of the transistor T. The other source / drain region of the transistor T is electrically coupled (e.g., directly) to a digital line 130 or 131 (also individually designated as DL). The gate of the transistor T is directly electrically coupled to the word line WL (e.g., includes a part of the word line WL). Figure 1 Shown are digital lines 130 and 131 extending from one of the opposite sides 100 and 200 of the memory array region 10 to the peripheral circuit system region 113 beside the memory array region 10. The digital lines 130 and 131 are individually directly electrically coupled to sense amplifiers SA on the opposite sides 100 and 200 of the array region 10 within the peripheral circuit system region 113. Thus, and in one embodiment, the transistors T are arranged in rows 85 and columns 90, and the gate lines (e.g., WL) interconnect multiple transistors T along individual ones of the rows. The digital lines DL interconnect multiple transistors T along individual ones of the columns.

[0012] Refer to Figures 3 to 5 , which shows a part of a structure 8 including an array or an array region 10 in which a capacitor array will be fabricated. The structure 8 includes a substrate 11 having any one or more of conductive / conductor / conduction, semiconductive / semiconductor / semiconduction, and insulating / insulator / insulation (i.e., electrically insulating herein) materials. The materials can be inFigures 3 to 5 Next to, vertically inside, or vertically outside the depicted material. By way of example, other portions of the integrated circuit system or fully fabricated components may be disposed somewhere above, around, or inside a substrate (not shown). Control and / or other peripheral circuitry for operating components within the memory array may also be fabricated and may or may not be fully or partially within the memory array or subarray. Additionally, multiple subarrays may be fabricated and operated independently, in concert, or otherwise relative to each other. As used in this document, a "subarray" may also be considered an array.

[0013] The transistor T (e.g., an access device) is Figure 3 shown schematically in and may be formed as part of the substrate 11. By way of example only, this may include a field effect transistor for controlling access to an individual capacitor, such as in a DRAM circuitry where the transistor T and capacitor C (not yet formed) comprise components of a single memory cell (e.g., a single transistor single capacitor [1T / 1C] memory cell). However, other memory and non-memory circuitries may be considered, whether existing or not yet developed. The exemplary substrate 11 is shown as including an insulating material 16 (e.g., doped and / or undoped silicon dioxide), the insulating material 16 having a conductive via 17 extending therethrough to the transistor T. One of the source / drain regions of the pair of source / drain regions of an individual transistor T is electrically coupled (e.g., directly) to an individual digit line DL. The other of the source / drain regions of the pair of source / drain regions of an individual transistor T is electrically coupled (e.g., directly) to one of the capacitor electrodes (e.g., the first capacitor electrode herein; e.g., through an individual conductive via 17).

[0014] A stack 18 has been formed directly above the substrate 11 and includes a sacrificial material 20 and an insulating material 22 (e.g., at least initially as a continuous layer thereof), the insulating material 22 being located between the top 24 and the bottom 26 of the sacrificial material 20. In one embodiment, the insulating material 22 at least predominantly (i.e., more than 50% by volume up to and including 100%) includes at least one of silicon nitride, silicon boron nitride, and silicon carbon nitride (i.e., regardless of stoichiometry). By way of example only, only one layer 25 of the insulating material 22 is shown between the top 24 and the bottom 26, and one or more additional such layers 25 of the insulating material 22 may be provided therebetween (not shown). A layer 25 of the insulating material 22 may also be below the sacrificial material 20, as shown. It may have the same or different thickness as the insulating material 22 above it. The sacrificial material 20 and the insulating material 22 desirably have compositions that are etchably different relative to each other. The exemplary sacrificial material 20 includes doped and undoped silicon dioxide and doped and undoped polysilicon. As shown, a hard mask material 28 (e.g., silicon dioxide) may be on top of the stack 18.

[0015] Horizontally spaced openings 30 have been formed, for example, by anisotropic etching into the sacrificial material 20 and through the insulating material 22 located between the top 24 and the bottom 26. The openings 30 are also formed through the hard mask material 28 (when present) and through the layer 25 to the conductive vias 17 (when present). The insulating material 22 located between the top 24 and the bottom 26 and through which the openings 30 pass includes an insulating horizontal lattice 32. If one or more layers of the insulating material 22 are between the top 24 and the bottom 26, more such lattices (not shown) can be formed. In one embodiment, the insulating horizontal lattice 32 and its insulating material 22 at least mainly include at least two of silicon nitride, boron nitride silicon, and carbon nitride silicon. In one embodiment, the insulating horizontal lattice 32 and its insulating material 22 at least mainly include silicon nitride, include boron nitride boron in one embodiment, and include carbon nitride silicon in one embodiment. In one such subsequent embodiment, the carbon content in the carbon nitride silicon is from 0.1 atomic percent to 30.0 atomic percent, and in one such embodiment, it is from 5.0 atomic percent to 7.0 atomic percent. The openings 30 can taper inwards and / or outwards, thus moving deeper into the stack 18 (desirably or as a natural result of manufacturing). The example opening 30 is shown as being widest at its top and tapering inwards only over a portion of the height of such an opening (e.g., as an undesired natural result of manufacturing).

[0016] Reference Figures 6 to 8 , an insulating liner 34 has been deposited within the horizontally spaced openings 30 and directly above the sacrificial material 20. The insulating liner 34 at least mainly includes at least one of silicon oxide and silicon oxynitride (i.e., regardless of stoichiometry; for example, SiO2 is a type of silicon oxide). In one embodiment, the insulating liner 34 at least mainly includes silicon oxide, and in one embodiment at least mainly includes silicon oxynitride. In one embodiment, the insulating liner 34 is not deposited next to the insulating horizontal lattice 32 (as shown), while in another embodiment, the insulating liner 34 is deposited next to the insulating horizontal lattice 32 (not shown). In any case, during deposition, the insulating liner 34 is intermittently exposed to a nitrogen-containing plasma, as indicated, for example, by the downward-pointing arrow 35. Desirably, and in one embodiment, the intermittent exposure results in less of the insulating liner 34 being deposited directly above the sacrificial material 20 compared to the case where there is no intermittent exposure under the same deposition conditions. Example ways of depositing the insulating liner 34 include chemical vapor deposition and atomic layer deposition, with or without plasma. Example nitrogen-containing plasmas can be sourced from N2, NH3, NF3, NO xone or more of (e.g., in combination with a non-nitrogen containing inert gas such as Ar). Example conditions during the intermittent exposure include a substrate temperature of 0°C to 1,000°C and a chamber pressure of 1 millitorr to 1 torr.

[0017] Reference Figures 9 to 11 , a first capacitor electrode 40 has been formed and the first capacitor electrode 40 is individually located within an individual one of the horizontally spaced apart openings 30, laterally above an insulating liner 34 within the opening 30. The insulating liner 34 and a hard mask material 28 (not shown) located directly above the sacrificial material 20 may be removed in the process, as shown.

[0018] Reference Figure 12 and 13 , and in one embodiment, all of the insulating liners 34 (not shown) have been removed (e.g., leaving a void space 71). This can occur, for example, by selectively isotropically etching relative to the first capacitor electrode 40. For example, in the case where the insulating liner 34 comprises undoped silicon dioxide and the sacrificial material 20 comprises boron and / or phosphorus doped silicon dioxide, an example isotropic etch chemistry mainly comprises HF and H2O and etches the insulating liner 34 faster than the sacrificial material 20 using this. Thereafter, and in one embodiment, an upper insulating lattice 42 (e.g., comprising an insulating material 22) has been formed on top of the sacrificial material 20. This may have the same or a different thickness as the thickness of the insulating horizontal lattice 32 and / or layer 25.

[0019] Reference Figure 14 and 15 , the sacrificial material 20 (not shown) has been removed (e.g., by selectively isotropically etching relative to the insulating material 22 and the first capacitor electrode 40). In the presence of the upper insulating lattice 42, example openings 44 may be formed through the upper insulating lattice 42 (see Figure 12), to provide access to the sacrificial material 20 therebelow for the etch fluid. Such openings may also be formed through the insulating horizontal lattice 32 (not shown / invisible in the example figures). Thereafter, the capacitor insulator 46 is formed over the first capacitor electrode 40 and the insulating horizontal lattice 32 (e.g., directly above and below it; e.g., and over the upper insulating lattice 42 and layer 25 (when present)). Thereafter, a second capacitor electrode material 48 is formed over the capacitor insulator 46, thereby forming a second capacitor electrode 50 and individual capacitors C (only a few are so designated) including one of the first capacitor electrode 40, the capacitor insulator 46, and the second capacitor electrode 50. The example second capacitor electrode 50 is shown to be common to all the capacitors C in the array 10. Alternatively, the second capacitor electrode material 48 may be isolated (e.g., by masked anisotropic etching) to isolate the individual second capacitor electrodes 50 from the individual first capacitor electrodes 40 or from multiple first capacitor electrodes 40 in the array 10, where the multiple first capacitor electrodes are fewer than all the first capacitor electrodes in the array 10 (none are shown). In any case, and in one embodiment, a memory array 10 has been formed that includes memory cells MC (only a few are so designated) each individually including a capacitor C and a transistor T. In one embodiment and as shown, all the insulating liners 34 are removed (e.g., by isotropic etching) before forming the capacitor insulator 46 (e.g., as Figure 12 and 13 shown).

[0020] In one embodiment, the insulating horizontal lattice 32 includes carbon (e.g., carbon-doped insulating material, silicon carbonitride, etc. [i.e., regardless of stoichiometry / whether stoichiometric or not]). This insulating horizontal lattice 32 has less carbon (if any) adjacent laterally to an individual one of the first capacitor electrodes 40 than away from said individual one (i.e., there is no insulating material 22 of the insulating horizontal lattice 32 between the first capacitor electrode 40 and the first capacitor electrode 40 adjacent laterally thereto). For example, and by way of example only, the insulating horizontal lattice 32 is shown to include individual regions 60 that are laterally adjacent to individual ones of the first capacitor electrodes 40 and regions 65 that are laterally away from the first capacitor electrodes 40 (i.e., compared to the individual regions 60). By way of example only, this may be caused by the regions 60 being exposed to a nitrogen-containing plasma 35 during the deposition of the insulating liner 34. This may also occur with respect to layer 25 (if it includes carbon and is not shown). The example regions 60 each individually include a ring, and the diameter expansion thereof will depend on the number of intermittent exposures, the intensity, and / or the time. If the regions 60 are formed in layer 25 or other insulating lattices 32 that are present and include carbon (not shown), the diameter expansion may be less when moving deeper into the stack.

[0021] In one embodiment, the insulating horizontal lattice 32 that is laterally adjacent to an individual first capacitor electrode 40 is carbon-free (here, "carbon-free" means from 0 atoms / cm 3 to up to and including 1 x 10 12 atoms / cm 3 ). In one embodiment, the insulating horizontal lattice 32 that is laterally adjacent to an individual first capacitor electrode 40 includes more than 1 x 10 12 atoms / cm 3 of carbon. In one embodiment, the insulating horizontal lattice 32 that is laterally adjacent to an individual first capacitor electrode 40 contains 10.0 atomic percent to 90.0 atomic percent less carbon (40.0 atomic percent to 70.0 atomic percent in one such embodiment) compared to the atomic percentage of carbon in the insulating horizontal lattice 32 that is laterally remote from the individual first capacitor electrode 40.

[0022] Any other property or aspect shown and / or described herein relative to other embodiments may be used in the shown embodiments and described with reference to the above embodiments.

[0023] Intermittently exposing the insulating liner 34 to a nitrogen-containing plasma during its deposition can sufficiently inhibit this deposition to reduce the risk or extent to which an individual opening 30 is pinched off (significantly narrowed) at its top. This can provide an increase in margin and an improved capacitor critical dimension.

[0024] Alternative embodiment configurations may be derived from the method embodiments described above or other embodiments. In any case, embodiments of the present invention encompass memory arrays independent of the manufacturing method. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the above method embodiments may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0025] In one embodiment, an array (e.g., 10) of capacitors (e.g., C) includes a plurality of capacitors (e.g., C), the plurality of capacitors individually including a first capacitor electrode (e.g., 40), a second capacitor electrode (e.g., 50), and a capacitor insulator (e.g., 46) between the first capacitor electrode and the second capacitor electrode. An insulating horizontal lattice (e.g., 32) is located between the top (e.g., 67) and the bottom (e.g., 68) of an individual one of the capacitors among the plurality of capacitors. The capacitor insulator is directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors. The insulating horizontal lattice includes carbon. The insulating horizontal lattice has less carbon (if any) that is laterally adjacent to an individual one of the first capacitor electrodes than that which is laterally remote from the individual one. Any other property or aspect shown and / or described herein relative to other embodiments may be used.

[0026] In one embodiment, an array (e.g., 10) of memory cells (e.g., MC) each including a capacitor (e.g., C) over a transistor (e.g., T) includes rows (e.g., 85) and columns (e.g., 90) of transistors (e.g., T). Gate lines (e.g., WL) interconnect multiple transistors along individual ones of the rows. Digital lines (e.g., 130 or 131) interconnect multiple transistors along individual ones of the columns. Each transistor includes a pair of source / drain regions (e.g., 70 and 72). One of the pair of source / drain regions (e.g., 70) is (e.g., directly) electrically coupled to an individual one of the digital lines. The other of the pair of source / drain regions (e.g., 72) is (e.g., directly) electrically coupled to a first capacitor electrode (e.g., 40) of one of the multiple capacitors (e.g., C) over the transistor. Each of the multiple capacitors includes a first capacitor electrode, a second capacitor electrode (e.g., 50), and a capacitor insulator (e.g., 46) between the first capacitor electrode and the second capacitor electrode. An insulating horizontal lattice (e.g., 32) is located between the top (e.g., 67) and the bottom (e.g., 68) of individual ones of the capacitors among the multiple capacitors. The capacitor insulator is directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors. The insulating horizontal lattice includes carbon. The insulating horizontal lattice has less carbon (if any) horizontally adjacent to individual ones of the first capacitor electrodes than horizontally remote from the individual ones. Any other property or aspect(s) shown and / or described herein with respect to other embodiments may be used.

[0027] The above processing or construction may be considered with respect to an array of components formed as a single stack or single layer of such components over or as part of a underlying substrate or formed within the single stack or single layer (although the single stack / layer may have multiple tiers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction and, in some embodiments, may be under the array (e.g., array-under-CMOS). In any case, one or more additional such stack(s) / layer(s) may be provided or fabricated above and / or below the stack / layer shown in the figures or described above. Additionally, the arrays of components may be the same or different relative to each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses relative to each other. Intermediary structures (e.g., additional circuitry and / or dielectric layers) may be provided between vertically adjacent stacks / layers. Further, the different stacks / layers may be electrically coupled to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0028] The assemblies and structures discussed above can be used in integrated circuits / circuit systems and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and specialized modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting devices, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0029] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "below", "beneath", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to a direction generally along the main substrate surface (i.e., within 10 degrees) and can be relative to the direction in which the substrate is processed during fabrication, and vertical is a direction generally orthogonal to horizontal. A reference to "perfectly horizontal" is a direction along the main substrate surface (i.e., at no angle to the main substrate surface) and can be relative to the direction in which the substrate is processed during fabrication. Additionally, as used herein, "vertical" and "horizontal" are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "extending in the vertical direction" refer to a direction at least 45° from perfectly horizontal. Additionally, with respect to a field effect transistor, "extending in the vertical direction", "vertically extending", "extending horizontally", "horizontally extending", and the like are with reference to the orientation of the channel length of the transistor, along which current flows between the source / drain regions in operation. For a bipolar junction transistor, "extending in the vertical direction", "vertically extending", "extending horizontally", "horizontally extending", and the like are with reference to the orientation of the base length, along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends in the vertical direction extends vertically or within 10° of the vertical direction.

[0030] In addition, "directly above", "directly below", and "directly beneath" require that the two stated regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Further, use of "above" without the prefix "directly" only requires that a portion of the stated region / material / component that is above another region / material / component be vertically external to the stated other region / material / component (i.e., regardless of whether there is any lateral overlap between the two stated regions / materials / components). Similarly, use of "below" and "beneath" without the prefix "directly" only requires that a portion of the stated region / material / component that is below / beneath another region / material / component be vertically internal to the stated other region / material / component (i.e., regardless of whether there is any lateral overlap between the two stated regions / materials / components).

[0031] Any of the materials, regions, and structures described herein can be homogeneous or non - homogeneous and can be continuous or discontinuous above any material over which it is disposed. In cases where one or more example compositions of any material are provided, the material can include such one or more compositions, consist essentially of such one or more compositions, or consist of such one or more compositions. Additionally, unless otherwise stated, any suitable existing or future - developed techniques can be used to form each material, examples being atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0032] In addition, "thickness" by itself (without a directional adjective in front) is defined as the average straight - line distance perpendicular to the closest surface of the adjacent material or adjacent region of a different composition through a given material or region. Additionally, the various materials or regions described herein can have a substantially constant thickness or a variable thickness. If it has a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and due to the thickness being variable, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, for example, if two stated materials or regions are not homogeneous, then "different compositions" only requires that those portions of such materials or regions that can be directly adjacent to each other be chemically and / or physically different. In cases where two stated materials or regions are not directly adjacent to each other, if such materials or regions are not homogeneous, then "different compositions" only requires that those portions of the two stated materials or regions that are closest to each other be chemically and / or physically different. In this document, the stated materials, regions, or structures "directly abut" another material, region, or structure when there is at least some physical contact by touching between them. In contrast, "above", "on", "adjacent to", "along", and "abut" without the prefix "directly" encompass "directly abut" as well as configurations where intervening materials, regions, or structures result in the stated materials, regions, or structures not having physical contact by touching relative to each other.

[0033] In this document, if in normal operation, current can flow continuously from one region-material-component to another region-material-component, and flows mainly through the movement of subatomic positive charges and / or negative charges (when subatomic positive charges and / or negative charges are sufficiently generated), then the region-material-components are "electrically coupled" to each other. Another electronic component can be between the region-material-components and be electrically coupled to the region-material-components. In contrast, when the region-material-components are said to be "directly electrically coupled", there is no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled region-material-components.

[0034] Any use of "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and components have been or can be formed along the "rows" and "columns". "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. In any case, the rows can be straight and / or curved and / or parallel and / or non-parallel to each other, and the columns can be the same. Additionally, the rows and columns can intersect each other at 90° or at one or more other angles (i.e., other than a right angle).

[0035] The composition of any of the conductive / conductor / conduction materials in this document can be a conductive metal material and / or a conductive doped semi-conductive / semiconductor / semi-conduction material. "Metal material" is an elemental metal, any mixture or alloy of two or more elemental metals, and any one or combination of any one or more metal compounds.

[0036] In this document, any use of "selective" with respect to etching (etch / etching), removing (removing / removal), depositing, forming (forming), and / or formation is such an action that a stated material acts on another stated material(s) at a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is for depositing, growing, or forming a material at a ratio of at least 2:1 by volume for a deposition, growth, or formation of at least the first 75 angstroms with respect to another stated material(s).

[0037] Unless otherwise indicated, the use of "or" in this document covers either and both.

[0038] Conclusion

[0039] In some embodiments, a method for forming a capacitor array includes forming horizontally spaced openings into a sacrificial material and passing them through an insulating material between a top and a bottom of the sacrificial material. The insulating material at least mainly includes at least one of silicon nitride, silicon boron nitride, and silicon carbon nitride. The insulating material through which the horizontally spaced openings pass includes an insulating horizontal lattice. An insulating layer is deposited within the horizontally spaced openings and directly above the sacrificial material. The insulating layer at least mainly includes at least one of silicon oxide and silicon oxynitride. During deposition, the insulating layer is intermittently exposed to a nitrogen-containing plasma. First capacitor electrodes are individually formed laterally within respective ones of the horizontally spaced openings above the insulating layer located within the horizontally spaced openings. The sacrificial material is removed, and a capacitor insulator is formed above the first capacitor electrodes and the insulating horizontal lattice. Second capacitor electrode material is formed above the capacitor insulator.

[0040] In some embodiments, a capacitor array includes a plurality of capacitors, each of the plurality of capacitors individually including a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode. An insulating horizontal lattice is located between a top and a bottom of an individual capacitor among the plurality of capacitors. The capacitor insulator is directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors. The insulating horizontal lattice includes carbon. The insulating horizontal lattice has less carbon (if any) laterally adjacent to an individual one of the first capacitor electrodes than laterally remote from the individual one.

[0041] In some embodiments, a memory cell array individually including a capacitor above a transistor includes rows and columns of transistors. Gate lines interconnect a plurality of transistors along respective ones of the rows. Digital lines interconnect a plurality of transistors along respective ones of the columns. Each transistor individually includes a pair of source / drain regions. One of the pair of source / drain regions is electrically coupled to an individual one of the digital lines. The other of the pair of source / drain regions is electrically coupled to a first capacitor electrode of one of the plurality of capacitors located above the transistor. Each of the plurality of capacitors individually includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode. An insulating horizontal lattice is located between a top and a bottom of an individual capacitor among the plurality of capacitors. The capacitor insulator is directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors. The insulating horizontal lattice includes carbon. The insulating horizontal lattice has less carbon (if any) laterally adjacent to an individual one of the first capacitor electrodes than laterally remote from the individual one.

Claims

1. A method for forming a capacitor array, comprising: forming horizontally spaced openings into a sacrificial material and passing them through an insulating material located between the top and bottom of the sacrificial material; the insulating material at least mainly comprises at least one of silicon nitride, silicon boron nitride, and silicon carbonitride; the insulating material through which the horizontally spaced openings pass comprises an insulating horizontal lattice; depositing an insulating liner within the horizontally spaced openings and directly above the sacrificial material, the insulating liner at least mainly comprises at least one of silicon oxide and silicon oxynitride; during the deposition, intermittently exposing the insulating liner to a nitrogen-containing plasma; laterally forming a first capacitor electrode individually within each of the horizontally spaced openings above the insulating liner located within the horizontally spaced openings; removing the sacrificial material and forming a capacitor insulator above the first capacitor electrode and the insulating horizontal lattice; and forming a second capacitor electrode material above the capacitor insulator.

2. The method according to claim 1, wherein the intermittent exposure results in less of the insulating liner being deposited directly above the sacrificial material compared to the same deposition conditions but without the intermittent exposure.

3. The method according to claim 1, wherein the nitrogen-containing plasma is derived from at least one of N2, NH3, NF3, and NO x among others.

4. The method according to claim 1, wherein the insulating material and the insulating horizontal lattice at least mainly comprise the silicon nitride.

5. The method according to claim 1, wherein the insulating material and the insulating horizontal lattice at least mainly comprise the silicon boron nitride.

6. The method according to claim 1, wherein the insulating material and the insulating horizontal lattice at least mainly comprise the silicon carbonitride.

7. The method according to claim 6, wherein the carbon content in the silicon carbonitride is from 0.1 atomic percent to 30.0 atomic percent.

8. The method according to claim 7, wherein the carbon content in the silicon carbonitride is from 5.0 atomic percent to 7.0 atomic percent.

9. The method according to claim 1, wherein the insulating material and the insulating horizontal lattice at least mainly comprise at least two of the silicon nitride, the silicon boron nitride, and the silicon carbonitride.

10. The method according to claim 1, wherein the insulating liner at least mainly comprises the silicon oxide.

11. The method according to claim 1, wherein the insulating liner at least mainly comprises the silicon boron nitride.

12. The method according to claim 1, wherein the insulating liner is not deposited next to the insulating horizontal lattice.

13. The method according to claim 1, wherein the insulating liner is deposited next to the insulating horizontal lattice.

14. The method according to claim 1, which comprises removing all of the insulating liner before forming the capacitor insulator.

15. The method according to claim 1, wherein the insulating horizontal lattice comprises carbon; the insulating horizontal lattice has less carbon (if any) adjacent to an individual one of the first capacitor electrodes laterally than laterally away from the individual one.

16. A capacitor array, comprising: a plurality of capacitors, each individually including a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; an insulating horizontal lattice located between the top and bottom of each of the capacitors among the plurality of capacitors, the capacitor insulator being directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors; and the insulating horizontal lattice includes carbon; the insulating horizontal lattice has less carbon (if any) horizontally adjacent to each of the first capacitor electrodes than horizontally remote from each of the first capacitor electrodes.

17. The array according to claim 16, wherein the insulating horizontal lattice horizontally adjacent to each of the individual first capacitor electrodes is carbon-free.

18. The array according to claim 16, wherein the insulating horizontal lattice immediately adjacent to the respective first capacitor electrodes includes carbon in an amount greater than 1x10 12 atoms / cm 3 .

19. The array according to claim 18, wherein the insulating horizontal lattice horizontally adjacent to each of the individual first capacitor electrodes contains 10.0 atomic percent to 90.0 atomic percent less carbon than the percentage of carbon atoms in the insulating horizontal lattice horizontally remote from each of the individual first capacitor electrodes.

20. A memory cell array, each individually including a capacitor over a transistor, the memory cell array comprising: rows and columns of transistors, gate lines interconnecting a plurality of the transistors along each of the rows, digit lines interconnecting a plurality of the transistors along each of the columns, each of the transistors individually including a pair of source / drain regions, one of the pair of source / drain regions being electrically coupled to an individual one of the digit lines, and the other of the pair of source / drain regions being electrically coupled to a first capacitor electrode of one of a plurality of capacitors located over the transistor; the plurality of capacitors each individually including the first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; an insulating horizontal lattice located between the top and bottom of each of the capacitors among the plurality of capacitors, the capacitor insulator being directly above and directly below the insulating horizontal lattice between horizontally adjacent ones of the capacitors; and the insulating horizontal lattice includes carbon; the insulating horizontal lattice has less carbon (if any) horizontally adjacent to each of the first capacitor electrodes than horizontally remote from each of the first capacitor electrodes.

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