Memory device with hierarchy of 2-transistor memory cells

Abstract

Some embodiments include devices and methods of using the devices. One of the devices includes: first, second, and third conductive structures each having a length in a first direction; first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction; a first conductive region; and a second conductive region. Each of the first and second memory cells includes a first semiconductor portion positioned on a first level of the device and coupled to the third conductive structure and one of the first and second conductive structures; a second semiconductor portion is positioned on a second level of the device and coupled to one of the first and second conductive structures. The first conductive region is opposite the respective first and second semiconductor portions of the first memory cell. A second conductive region is opposite the respective first and second semiconductor portions of the second memory cell.

Description

[0001] Priority Application

[0002] This application claims the priority benefit of U.S. Provisional Application No. 63 / 429,784, filed on Dec. 2, 2022, which is incorporated herein by reference in its entirety. Background Art

[0003] Memory devices are widely used to store information in computers and many other electronic products. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Memory devices typically have numerous memory cells for storing information. In a volatile memory device, the information stored in the memory cells is lost when power supply is disconnected from the memory device. In a non-volatile memory device, the information stored in the memory cells remains retained even when power supply is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of charge in a capacitor structure included in a memory cell. As the requirement for device storage density increases, many conventional techniques provide ways to reduce the size of the memory cells in order to increase the device storage density for a given device area. However, if the memory cell size is reduced to a certain dimension, physical limitations and manufacturing constraints pose challenges to such conventional techniques. Brief Description of the Drawings

[0005] Figure 1 A block diagram of an apparatus in the form of a memory device including volatile memory cells, according to some embodiments described herein.

[0006] Figure 2 A schematic diagram of a portion of a memory device including a memory array of 2-transistor (2T) memory cells, according to some embodiments described herein.

[0007] Figure 3 A memory device including example voltages used during a read operation of the memory device, according to some embodiments described herein. Figure 2 of the memory device.

[0008] Figure 4 A memory device including example voltages used during a write operation of the memory device, according to some embodiments described herein. Figure 2 of the memory device.

[0009] Figure 5 A memory device including a separate driver coupled to an access line associated with a memory cell, according to some embodiments described herein. Figure 2 of the memory device.

[0010] Figures 6A to 7C Showing different views of the structure of a memory device Figures 2 to 5 including memory cells of multiple levels according to some embodiments described herein. Detailed Description

[0011] The memory device described herein includes volatile memory cells, where each of the memory cells may include two transistors (2T). One of the two transistors has a charge storage structure, which may form the memory element of the memory cell to store information.

[0012] The described memory device includes levels stacked one above the other on a substrate (e.g., a semiconductor substrate) of the memory device. Each level has memory cells and associated access lines (e.g., word lines).

[0013] The access lines may be configured to include separate conductive regions (e.g., conductive strips) having a length extending horizontally across the memory cells in the respective levels. The access lines in a level are used to control the transistors of the memory cells in that level. The conductive regions of the access lines may be configured such that the two transistors in a memory cell can be controlled by the same signal provided through the access line or alternatively by separate signals (e.g., two different signals from two different drivers).

[0014] The described memory device includes data lines (e.g., bit lines), which may include conductive structures extending through the levels (e.g., vertically). Memory cells of different levels may share the conductive structures of the data lines (e.g., vertical data lines). Some of the data lines may be coupled to each other.

[0015] In addition to the conductive structures of the data lines, the described memory device further includes common conductive structures. The common conductive structures may also extend through the levels (e.g., vertically). The common conductive structures may be part of the ground connection (e.g., a ground plane) of the memory device.

[0016] The improvements and benefits of the described memory device include improved device area efficiency, reduced capacitive coupling between adjacent data lines, and reduced total capacitance associated with the data lines. In addition, the hierarchical structure of the described memory device may also improve (e.g., reduce) the cost per bit of the memory device. Other improvements and benefits of the described memory device and its variants are discussed below with reference to Figures 1 to 7C are discussed.

[0017] Figure 1FIG. 0 is a block diagram showing an apparatus in the form of a memory device 100 including volatile memory cells according to some embodiments described herein. The memory device 100 includes a memory array 101 that may contain memory cells 102. The memory device 100 may include a volatile memory device such that the memory cells 102 may be volatile memory cells. Examples of the memory device 100 include dynamic random access memory (DRAM) devices. Information stored in the memory cells 102 of the memory device 100 is lost (e.g., invalidated) when power supply (e.g., supply voltage Vcc) is disconnected from the memory device 100. Hereinafter, the supply voltage Vcc is referred to as representing some voltage levels; however, they are not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator (not shown in Figure 1 that generates an internal voltage based on the supply voltage Vcc, then this internal voltage may be used instead of the supply voltage Vcc.

[0018] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different levels (e.g., stacked on different layers) above a substrate (e.g., semiconductor substrate) of the memory device 100. The memory device 100 may also include multiple levels (e.g., multiple tiers) of memory cells, where the memory cells of one level (e.g., one tier) may be formed (e.g., stacked) above additional memory cells of another level (e.g., another tier). The structure of the memory array 101 including the memory cells 102 may include the structure of the memory array and memory cells described below with reference to Figures 2 to 7C FIG.

[0019] As shown in Figure 1 FIG., the memory device 100 may include access lines 104 (e.g., "word lines") and data lines (e.g., bit lines) 105. The memory device 100 may use signals on the access lines 104 (e.g., word line signals) to access the memory cells 102 and use the data lines 105 to provide information (e.g., data) stored in (e.g., written to) or read from (e.g., sensed from) the memory cells 102.

[0020] The memory device 100 may include an address register 106 for receiving address information ADDR (such as row address signals and column address signals) on a line 107 (such as an address line). The memory device 100 may include a row access circuit system 108 (such as an X decoder) and a column address circuit system 109 (such as a Y decoder) operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 will be accessed during a memory operation. The memory device 100 may perform a write operation to store information in the memory cells 102 and a read operation to read (such as sense) the information (such as previously stored information) in the memory cells 102. The memory device 100 may also perform an operation (such as a refresh operation) to refresh the information value stored in the memory cells 102 (such as to keep the information value valid). Each of the memory cells 102 may be configured to store information that can represent at most one bit (such as a single bit having binary 0 (“0”) or binary 1 (“1”)) or more than one bit (such as multiple bits having a combination of at least two binary bits).

[0021] The memory device 100 may receive supply voltages, including a supply voltage Vcc and a supply voltage Vss on lines 130 and 132, respectively. The supply voltage Vss may operate at a ground potential (such as having a value of about 0 volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source such as a battery or an alternating current / direct current (AC-DC) converter circuit system.

[0022] As Figure 1 shown, the memory device 100 may include a memory control unit 118 that includes circuitry (such as hardware components) for controlling the memory operations (such as read and write operations) of the memory device 100 based on control signals on a line (such as a control line) 120. Examples of signals on the line 120 include a row access strobe signal RAS*, a column access strobe signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals may be part of the signals provided to a DRAM device.

[0023] As Figure 1 shown, the memory device 100 may include a line (such as a global data line) 112 that can carry signals DQ0 to DQN. During a read operation, the value (such as “0” or “1”) of the information provided to the line 112 (read from the memory cells 102) (in the form of signals DQ0 to DQN) may be based on the value of the signals on the data line 105. During a write operation, the value (such as “0” or “1”) of the information provided to the data line 105 (for storage in the memory cells 102) may be based on the values of the signals DQ0 to DQN on the line 112.

[0024] Memory device 100 may include a sensing circuit system 103, a selection circuit system 115, and an input / output (I / O) circuit system 116. The column access circuit system 109 may selectively activate signals on lines (such as select lines) based on an address signal ADDR. The selection circuit system 115 may respond to signals on line 114 to select signals on the data line 105. The signals on the data line 105 may represent information values stored in the memory cells 102 (such as during a write operation) or information values read (such as sensed) from the memory cells 102 (such as during a read operation).

[0025] The I / O circuit system 116 may be operable to provide information read from the memory cells 102 to line 112 (such as during a read operation) and to provide information from line 112 (such as provided by an external device) to the data line 105 for storage in the memory cells 102 (such as during a write operation). Line 112 may include a node within the memory device 100 or a pin (or solder ball) on a package in which the memory device 100 may reside. Other devices external to the memory device 100 (such as a hardware memory controller or a hardware processor) may communicate with the memory device 100 via lines 107, 112, and 120.

[0026] The memory device 100 may include other components, which are not shown Figure 1 herein so as not to obscure the example embodiments described herein. At least a portion of the memory device 100 (such as a portion of the memory array 101) may include a structure and operation similar to or the same as any of the memory devices described below with reference to Figures 2 to 2 8C.

[0027] Figure 2 A schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 the memory device 100. For example, the memory array 201 may form Figure 1 a portion of the memory array 101. As Figure 2 shown, the memory device 200 may include memory cells 210 to 215, which are volatile memory cells (such as DRAM cells). For simplicity, similar or identical elements between the memory cells 210 to 215 are given the same reference numerals.

[0028] Each of memory cells 210 to 215 may include two transistors T1 and T2. Thus, each of memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., 2T gain cell). Each of transistors T1 and T2 may include a field effect transistor (FET). As an example, transistor T1 may be a p-channel FET (PFET), and transistor T2 may be an n-channel FET (NFET). A portion of transistor T1 may include the structure of a p-channel metal oxide semiconductor (PMOS) transistor. Thus, transistor T1 may include operations similar to those of a PMOS transistor. A portion of transistor T2 may include an n-channel metal oxide semiconductor (NMOS). Thus, transistor T2 may include operations similar to those of an NMOS transistor.

[0029] Transistor T1 of memory device 200 may include a charge storage-based structure (e.g., based on a floating gate). As Figure 2 shown, each of memory cells 210 to 215 may include a charge storage structure 202, which may include the floating gate of transistor T1. The charge storage structure 202 may form the memory element of the corresponding memory cell in memory cells 210 to 215. The charge storage structure 202 may store charge. The information value (e.g., "0" or "1") stored in a particular memory cell among memory cells 210 to 215 may be based on the amount of charge in the charge storage structure 202 of this particular memory cell. For example, the information value stored in a particular memory cell among memory cells 210 to 215 may be "0" or "1" (if each memory cell is configured as a single-bit memory cell) or "00", "01", "10", or "11" (or other multi-bit values) (if each memory cell is configured as a multi-bit memory cell).

[0030] As Figure 2 shown, transistor T2 (e.g., the channel region of transistor T2) of a particular memory cell among memory cells 210 to 215 may be electrically coupled to (e.g., directly coupled to (in contact with)) the charge storage structure 202 of this particular memory cell. Thus, a circuit path (e.g., a current path) may be directly formed between transistor T2 of a particular memory cell and the charge storage structure 202 of this particular memory cell during the operation (e.g., a write operation) of memory device 200. During the write operation of memory device 200, a circuit path (e.g., a current path) may be formed between the corresponding data line (e.g., data line 221 or 222) and the charge storage structure 202 of a particular memory cell through transistor T2 of the particular memory cell (e.g., through the channel region of transistor T2).

[0031] Memory cells 210 to 215 may be arranged into memory cell groups 2010 and 2011.Figure 2 Two memory cell groups, such as 2010 and 2011, are shown as examples. However, the memory device 200 may include more than two memory cell groups. The memory cell groups 2010 and 2011 may include the same number of memory cells. For example, the memory cell group 2010 may include memory cells 210, 212, and 214, and the memory cell group 2011 may include memory cells 211, 213, and 215. Figure 2 Three memory cells of each of the memory cell groups 2010 and 2011 are shown as examples. The number of memory cells in the memory cell groups 2010 and 2011 may be different from 3.

[0032] The memory device 200 may perform a write operation to store information in the memory cells 210 to 215 and perform a read operation to read (e.g., sense) information from the memory cells 210 to 215. The memory device 200 may be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure of a container such as a capacitor, the memory device 200 may store information in the form of charge in a charge storage structure 202, which may be a floating gate structure. As mentioned above, the charge storage structure 202 may be the floating gate of the transistor T1. During the operation (e.g., read or write operation) of the memory device 200, an access line (e.g., a single access line) and a data line (e.g., a single data line) may be used to access a selected memory cell (e.g., a target memory cell).

[0033] As Figure 2 shown, the memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that can carry corresponding signals (e.g., word line signals) WL1, WL2, and WLN. The access lines 241, 242, and 243 may be used to access both the memory cell groups 2010 and 2011. In the physical structure of the memory device 200, each of the access lines 241, 242, and 243 may be constructed as at least one conductive wire (one conductive wire or multiple conductive wires, where the multiple conductive wires may be electrically coupled to each other (e.g., shorted)) (formed by the at least one conductive wire).

[0034] The access lines 241, 242, and 243 may be selectively activated (e.g., one at a time) during the operation (e.g., read or write operation) of the memory device 200 to access one selected memory cell (or several selected memory cells) among the memory cells 210 to 215. The selected memory cell may be referred to as a target memory cell. In a read operation, information may be read from one selected memory cell (or several selected memory cells). In a write operation, information may be stored in one selected memory cell (or several selected memory cells).

[0035] As Figure 2 shown, transistors T1 and T2 may have gates 251 and 252, respectively. The gate of each of transistors T1 and T2 (e.g., gate 251 or 252) may be part of a corresponding access line (e.g., a corresponding word line). As Figure 2 shown, the gate of each of transistors T1 and T2 of memory cell 210 (e.g., gate 251 or 252) may be part of access line 241. The gate of each of transistors T1 and T2 of memory cell 211 (e.g., gate 251 or 252) may be part of access line 241. For example, in the physical structure of memory device 200, four different portions of the conductive material forming access line 241 (e.g., four different portions of a continuous metal or polysilicon sheet) may form four gates, which include gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 210 and gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 211.

[0036] The gate of each of transistors T1 and T2 of memory cell 212 (e.g., gate 251 or 252) may be part of access line 242. The gate of each of transistors T1 and T2 of memory cell 213 (e.g., gate 251 or 252) may be part of access line 242. For example, in the physical structure of memory device 200, four different portions of the conductive material forming access line 242 (e.g., four different portions of a continuous metal or polysilicon sheet) may form four gates, which include gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 212 and gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 213.

[0037] The gate of each of transistors T1 and T2 of memory cell 214 (e.g., gate 251 or 252) may be part of access line 243. The gate of each of transistors T1 and T2 of memory cell 215 (e.g., gate 251 or 252) may be part of access line 243. For example, in the physical structure of memory device 200, four different portions of the conductive material forming access line 243 (e.g., four different portions of a continuous metal or polysilicon sheet) may form four gates, which include gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 214 and gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 215.

[0038] In this description, a material may include a single material or a combination of multiple materials. A conductive material may include a single conductive material or a combination of multiple conductive materials.

[0039] The memory device 200 may include data lines (e.g., bit lines) 221 and 222 that can carry corresponding signals (e.g., bit line signals) BL1 and BL2. During a read operation, the memory device 200 may use data line 221 to obtain information read (e.g., sensed) from a selected memory cell of the memory cell group 2010 and use data line 222 to read information from a selected memory cell of the memory cell group 2011. During a write operation, the memory device 200 may use data line 221 to provide information to be stored in a selected memory cell of the memory cell group 2010 and use data line 222 to provide information to be stored in a selected memory cell of the memory cell group 2011.

[0040] The memory device 200 may include a ground connection (e.g., a ground plate) 297 coupled to each of the memory cells 210 to 215. The ground connection 297 may be constructed of a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of the memory device 200.

[0041] As Figure 2 shown, a transistor T1 (e.g., a channel region of the transistor T1) of a particular memory cell among the memory cells 210 to 215 may be electrically coupled to (e.g., directly coupled to) the ground connection 297 and electrically coupled to (e.g., directly coupled to) a corresponding data line (e.g., data line 221 or 222). Thus, a circuit path (e.g., a current path) may be formed between the corresponding data line (e.g., data line 221 or 222) and the ground connection 297 through the transistor T1 of the selected memory cell during an operation (e.g., a read operation) performed on the selected memory cell.

[0042] The memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained through the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a specific memory cell (e.g., memory cell 210, 212, or 214) may include a current path (e.g., a read current path) through the channel region of transistor T1 of this specific memory cell, data line 221, and ground connection 297. In the memory cell group 2011, the read path of a specific memory cell (e.g., memory cell 211, 213, or 215) may include a current path (e.g., a read current path) through the channel region of transistor T1 of this specific memory cell, data line 222, and ground connection 297. In an example where transistor T1 is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) may include hole conduction (e.g., hole conduction in the direction from data line 221 through the channel region (e.g., a p-channel region) of transistor T1 to ground connection 297). Since transistor T1 may be used in the read path to read information from the corresponding memory cell during a read operation, transistor T1 may be referred to as a read transistor and the channel region of transistor T1 may be referred to as a read channel region.

[0043] The memory device 200 may include a write path (e.g., a circuit path). Information stored in a selected memory cell during a write operation may be provided to the selected memory cell through the write path coupled to the selected memory cell. In the memory cell group 2010, the write path of a specific memory cell may include transistor T2 of this specific memory cell (e.g., may include a write current path through the channel region of transistor T2) and data line 221. In the memory cell group 2011, the write path of a specific memory cell (e.g., memory cell 211, 213, or 215) may include transistor T2 of this specific memory cell (e.g., may include a write current path through the channel region of transistor T2) and data line 222. In an example where transistor T2 is an NFET (e.g., an NMOS), the current in the write path (e.g., during a write operation) may include electron conduction through the channel region (e.g., an n-channel region) of transistor T2 (e.g., electron conduction in the direction from data line 221 to charge storage structure 202). Since transistor T2 may be used in the write path to store information in the corresponding memory cell during a write operation, transistor T2 may be referred to as a write transistor and the channel region of transistor T2 may be referred to as a write channel region.

[0044] Each of transistors T1 and T2 may have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of the threshold voltages Vt1 and Vt2 may be different (unequal values). For example, the value of the threshold voltage Vt2 may be greater than the value of the threshold voltage Vt1. The difference between the values of the threshold voltages Vt1 and Vt2 allows information stored in the charge storage structure 202 in transistor T1 on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) transistor T2 on the write path (e.g., the path through transistor T2). This can prevent charge from leaking from the charge storage structure 202 through transistor T2 on the write path (e.g., during a read operation).

[0045] In the structure of memory device 200, transistors T1 and T2 may be formed (e.g., designed) such that the threshold voltage Vt1 of transistor T1 may be less than 0 volts (e.g., Vt1 < 0V), regardless of the value of the information stored in the charge storage structure 202 of transistor T1 (e.g., "0" or "1"), and Vt1 < Vt2. When information having a "0" value is stored in the charge storage structure 202, the charge storage structure 202 may be in state "0". When information having a "1" value is stored in the charge storage structure 202, the charge storage structure 202 may be in state "1". Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 can be expressed as follows: Vt1 of state "0" < Vt1 of state "1" < 0V, and Vt2 = 0V (or alternatively, Vt2 > 0V).

[0046] In an alternative structure of memory device 200, transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 of state "0" < Vt1 of state "1", where Vt1 of state "0" < 0V (or alternatively, Vt1 of state "0" = 0V), Vt1 of state "1" > 0V, and Vt1 < Vt2.

[0047] In another alternative structure, transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 of state "0" < Vt1 of state "1", where Vt1 of state "0" = 0V (or alternatively, Vt1 of state "0" > 0V), and Vt1 < Vt2.

[0048] During a read operation of the memory device 200, only one memory cell of the same memory cell group may be selected one at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of the memory cell group 2010 may be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of the memory cell group 2011 may be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0049] During a read operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) may be selected concurrently (or alternatively may be selected sequentially). For example, memory cells 210 and 211 may be selected concurrently during a read operation to read (e.g., concurrently read) information from memory cells 210 and 211. Memory cells 212 and 213 may be selected concurrently during a read operation to read (e.g., concurrently read) information from memory cells 212 and 213. Memory cells 214 and 215 may be selected concurrently during a read operation to read (e.g., concurrently read) information from memory cells 214 and 215.

[0050] The information value read from the selected memory cell of the memory cell group 2010 during a read operation may be determined based on the value of the current detected (e.g., sensed) from the read path (described above) including the data line 221, the transistor T1 of the selected memory cell (e.g., memory cells 210, 212, or 214), and the ground connection 297. The information value read from the selected memory cell of the memory cell group 2011 during a read operation may be determined based on the value of the current detected (e.g., sensed) from the read path including the data line 222, the transistor T1 of the selected memory cell (e.g., memory cells 211, 213, or 215), and the ground connection 297.

[0051] Memory device 200 may include detection circuitry (not shown) that may operate during a read operation to detect (e.g., sense) a current (e.g., current I1 (not shown)) on a read path including data line 221 and to detect a current (e.g., current I2 (not shown)) on a read path including data line 222. The value of the detected current may be based on the information value stored in the selected memory cell. For example, depending on the information value stored in the selected memory cell of memory cell group 2010, the value of the current detected on data line 221 (e.g., the value of current I1) may be 0 or greater than 0. Similarly, depending on the information value stored in the selected memory cell of memory cell group 2011, the value of the current detected on data line 222 (e.g., the value of current I2) may be 0 or greater than 0. Memory device 200 may include circuitry (not shown) for translating the value of the detected current into the information value (e.g., "0", "1", or a combination of multi-bit values) stored in the selected memory cell.

[0052] During a write operation of memory device 200, only one memory cell of the same memory cell group may be selected at a time to store information in the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 may be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0053] During a write operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) may be selected concurrently. For example, memory cells 210 and 211 may be selected concurrently during a write operation to store information (e.g., concurrently store) in memory cells 210 and 211. Memory cells 212 and 213 may be selected concurrently during a write operation to store information (e.g., concurrently store) in memory cells 212 and 213. Memory cells 214 and 215 may be selected concurrently during a write operation to store information (e.g., concurrently store) in memory cells 214 and 215.

[0054] During a write operation, the information stored in the selected memory cells of memory cell group 2010 can be provided through the write path (described above) including data line 221 and transistor T2 of the selected memory cells (such as memory cells 210, 212, or 214). During a write operation, the information stored in the selected memory cells of memory cell group 2011 can be provided through the write path (described above) including data line 222 and transistor T2 of the selected memory cells (such as memory cells 211, 213, or 215). As described above, the information value (such as a binary value) stored in a specific memory cell among memory cells 210 to 215 can be based on the amount of charge in charge storage structure 202 of this specific memory cell.

[0055] During a write operation, the amount of charge in charge storage structure 202 of the selected memory cell can be changed (to reflect the information value stored in the selected memory cell) by applying a voltage to the write path including transistor T2 of this specific memory cell and the data line coupled to this specific memory cell (such as data line 221 or 222). For example, if the information in the selected memory cells stored in memory cells 210, 212, and 214 has a value (such as "0"), then a voltage having a value (such as 0V) can be applied to data line 221 (such as providing 0V to signal BL1). In another example, if the information in the selected memory cells stored in memory cells 210, 212, and 214 has another value (such as "1"), then a voltage having another value (such as a positive voltage) can be applied to data line 221 (such as providing a positive voltage to signal BL1). Thus, information can be stored (such as directly stored) in charge storage structure 202 of this specific memory cell by providing the information (such as in the form of a voltage) to the write path of the specific memory cell which includes transistor T2.

[0056] Figure 3 Showing a memory device 200 including example voltages V1, V2, and V3 used during a read operation of the memory device 200 according to some embodiments described herein Figure 2 of the memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are the selected memory cells (such as target memory cells) during a read operation to read (such as sense) the information stored (such as previously stored) in memory cells 210 and 211. Memory cells 212 to 215 are considered unselected memory cells. This means that: during Figure 3In the example, memory cells 212 to 215 are not accessed and the information stored in memory cells 212 to 215 is not read. Instead, information is read from memory cells 210 and 211. In this example, access line 241 may be referred to as a selected access line (e.g., a selected word line), which is an access line associated (e.g., coupled) with selected memory cells (e.g., memory cells 210 and 211 in this example). In this example, access lines 242 and 243 may be referred to as unselected access lines (e.g., unselected word lines), which are access lines associated (e.g., coupled) with unselected memory cells (e.g., memory cells 212, 213, 214, and 215 in this example).

[0057] In Figure 3 , voltages V1, V2, and V3 may represent different voltages applied to respective access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of memory device 200. Voltage V1 may be applied to the selected access line (e.g., access line 241). In a read operation, voltage V2 may be applied to the unselected access lines (e.g., access lines 242 and 243).

[0058] Voltages V1, V2, and V3 may have different values. As an example, voltages V1, V2, and V3 may have values of -1V, 0V, and 0.5V, respectively. The specific values of the voltages used for this description are only example values. Different values may be used. For example, voltage V1 may have a negative value range (e.g., the value of voltage V1 may be from -3V to -1V).

[0059] In Figure 3 the read operation shown, voltage V1 may have a value (e.g., a voltage value) to turn on transistors T1 of each of memory cells 210 and 211 (selected memory cells in this example) and turn off (or avoid) transistors T2 of each of memory cells 210 and 211. This allows information to be read from memory cells 210 and 211. Voltage V2 may have a value such that transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., avoided). Voltage V3 may have a value such that a current (e.g., a read current) can be formed on the read paths including data line 221 and transistor T1 of memory cell 210 and on the read path including data line 222 and transistor T1 of memory cell 212 (separate read paths). This allows the currents coupled to the read paths of memory cells 210 and 211 (e.g., on respective data lines 221 and 222) to be detected. The detection circuitry (not shown) of memory device 200 may be operable to translate the value of the detected current (during reading information from the selected memory cells) into the value of the information read from the selected memory cells (e.g., "0", "1", or a combination of multiple-bit values). In Figure 3In the example, the values of the currents detected on data lines 221 and 222 can be translated into the information values read from memory cells 210 and 211, respectively.

[0060] In Figure 3 the read operation shown, the voltages applied to the respective access lines 241, 242, and 243 can cause the transistors T1 and T2 in each of memory cells 212 to 215 (except for the transistor T1 in each of memory cells 210 and 211 (selected memory cells)) to turn off (or remain off). The transistor T1 of memory cell 210 (selected memory cell) may or may not be turned on, depending on the value of the threshold voltage Vt1 of the transistor T1 of memory cell 210. The transistor T1 of memory cell 211 (selected memory cell) may or may not be turned on, depending on the value of the threshold voltage Vt1 of the transistor T1 of memory cell 211. For example, if the transistor T1 in each of the memory cells (such as 210 to 215) of memory device 200 is configured (such as constructed) such that the threshold voltage of the transistor T1 is less than 0 (e.g., Vt1 < -1V) (regardless of the information value (such as state) stored in the corresponding memory cell 210), then in this example, the transistor T1 of memory cell 210 can be turned on and conduct current on data line 221 (through the transistor T1 of memory cell 210). In this example, the transistor T1 of memory cell 211 can also be turned on and conduct current on data line 222 (through the transistor T1 of memory cell 211). Memory device 200 can determine the information values stored in memory cells 210 and 211 based on the values of the currents on data lines 221 and 222, respectively. As described above, memory device 200 can include detection circuitry for measuring the current values on data lines 221 and 222 during a read operation.

[0061] Figure 4 Memory device 200 showing example voltages V4, V5, V6, and V7 used during a write operation of memory device 200 according to some embodiments described herein Figure 2 of. Figure 4 The example of assumes that memory cells 210 and 211 are the selected memory cells (such as target memory cells) during a write operation to store information in memory cells 210 and 211. Memory cells 212 to 215 are considered unselected memory cells. This means that: in Figure 4 the example, memory cells 212 to 215 are not accessed and information is not stored in memory cells 212 to 215, but rather information is stored in memory cells 210 and 211.

[0062] In Figure 4Among them, voltages V4, V5, V6, and V7 can represent different voltages applied to corresponding access lines 241, 242, and 243 and data lines 221 and 222 during a write operation of memory device 200. During the write operation, voltage V4 can be applied to a selected access line (such as access line 241). Voltage V5 can be applied to unselected access lines (such as access lines 242 and 243).

[0063] Voltages V4, V5, V6, and V7 can have different values. As an example, voltages V4 and V5 can have values of 3V and 0V respectively. These values are example values. Different values can be used.

[0064] The values of voltages V6 and V7 can be the same or different, depending on the information values (such as "0" or "1") stored in memory cells 210 and 211. For example, if memory cells 210 and 211 will store information with the same value, then the values of voltages V6 and V7 can be the same (such as V6 = V7). As an example, if the information stored in each of memory cells 210 and 211 is "0", then V6 = V7 = 0V. In another example, if the information stored in each of memory cells 210 and 211 is "1", then V6 = V7 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)).

[0065] In another example, if memory cells 210 and 211 will store information with different values, then the values of voltages V6 and V7 can be different (such as V6 ≠ V7). As an example, if "0" will be stored in memory cell 210, then V6 = 0V, and if "1" will be stored in memory cell 211, then V7 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)). As another example, if "1" will be stored in memory cell 210, then V6 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)), and if "0" will be stored in memory cell 211, then V7 = 0V.

[0066] Here, a voltage range of 1V to 3V is used as an example. Different voltage ranges can be used. In addition, instead of applying 0V (such as V6 = 0V or V7 = 0V) to a specific write data line (such as data line 221 or 222) to store information with the value "0" into a memory cell (such as memory cell 210 or 211) coupled to this specific write data line, a positive voltage (such as V6 > 0V or V7 > 0V) can be applied to this specific data line.

[0067] In Figure 4In the write operation of the memory device 200, the voltage V5 may have a value (e.g., V5 = 0V or V5 < 0V) such that the transistors T1 and T2 of each of the memory cells 212 to 215 (the unselected memory cells in this example) are turned off (e.g., avoided). The voltage V4 may have a value (e.g., V4 > 0V) to turn on the transistor T2 of each of the memory cells 210 and 211 (the selected memory cells in this example) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221 and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222. A current (e.g., a write current) may be formed between the charge storage structure 202 of the memory cell 210 (the selected memory cell) and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect the information value stored in the memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 (the selected memory cell) and the data line 222. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the information value stored in the memory cell 211.

[0068] In Figure 4 an example write operation, the value of the voltage V6 may cause the charge storage structure 202 of the memory cell 210 to discharge or charge such that the resulting charge on the charge storage structure 202 of the memory cell 210 (e.g., the charge remaining after the discharge or charge operation) may reflect the information value stored in the memory cell 210. Similarly, in this example, the value of the voltage V7 may cause the charge storage structure 202 of the memory cell 211 to discharge or charge such that the resulting charge on the charge storage structure 202 of the memory cell 211 (e.g., the charge remaining after the discharge or charge operation) may reflect the information value stored in the memory cell 211.

[0069] Figure 5 shows a memory device 200 having separate access lines (e.g., separate word lines) for the transistors T1 and T2 of each memory cell according to some embodiments described herein Figure 2 of. Figure 5 The memory device 200 of Figure 2 may be a variant of the memory device 200 of. As Figure 5As shown, the memory device 200 may include access lines (e.g., word lines) 241, 241', 242, 242', 243, and 243' that can carry corresponding signals (e.g., word line signals) WL1, WL1', WL2, WL2', WL3, and WL3'. The access lines 241, 241', 242, 242', 243, and 243' may be electrically separated from each other. Each memory cell may be associated with two access lines (e.g., a read access line and a write access line).

[0070] The access lines 241, 242, and 243 may be read access lines. The access lines 241, 242, and 243 may be used to selectively turn on the corresponding transistors T1 (e.g., read transistors) of a selected memory cell (or selected memory cells) during a read operation to read information from the selected memory cell (or selected memory cells). The access lines 241, 242, and 243 may also be used to turn off the corresponding transistors T1 of a selected memory cell (or selected memory cells) during a write operation performed on a selected memory cell (or selected memory cells).

[0071] The access lines 241', 242', and 243' may be referred to as write access lines. The access lines 241', 242', and 243' may be used to selectively turn on the corresponding transistors T2 (e.g., write transistors) of a selected memory cell (or selected memory cells) during a write operation to store information in the selected memory cell (or selected memory cells). The access lines 241', 242', and 243' may also be used to turn off the corresponding transistors T2 of a selected memory cell (or selected memory cells) during a read operation performed on a selected memory cell (or selected memory cells).

[0072] As Figure 5 shown, each of the gates 251 and 252 of the corresponding transistors T1 and T2 may be electrically coupled to the corresponding access line. In the structure of the memory device 200 (see Figures 6A to 7C ), each of the gates 251 and 252 may be formed by a portion (e.g., a portion of the material) of the corresponding access line among the access lines 241, 241', 242', 242, 243, and 243'. As described above, the access lines (e.g., access lines 241 and 241') associated with a memory cell (e.g., memory cell 210) may be electrically separated from each other. Thus, the gate 251 of the transistor T1 and the gate 252 of the transistor T2 of the memory cell (e.g., memory cell 210) are also electrically separated from each other.

[0073] In Figure 2In the memory device 200, the gates 251 of different transistors T1 of memory cells associated with the same access line (e.g., a read access line) can be formed by different portions of the conductive material forming this access line. The gates 252 of different transistors T2 of memory cells associated with the same access line (e.g., a write access line) can be formed by different portions of the conductive material forming this access line.

[0074] For example, as Figure 2 shown, the gates 251 of the corresponding transistors T1 of memory cells 210 and 211 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 241. The gates 252 of the corresponding transistors T2 of memory cells 210 and 211 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 241'.

[0075] The gates 251 of the corresponding transistors T1 of memory cells 212 and 213 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 242. The gates 252 of the corresponding transistors T2 of memory cells 212 and 213 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 242'.

[0076] The gates 251 of the corresponding transistors T1 of memory cells 214 and 215 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 243. The gates 252 of the corresponding transistors T2 of memory cells 214 and 215 can be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 243'.

[0077] The access lines 241, 241', 242, 242', 243, and 243' can be used to access both memory cell groups 2010 and 2011. Each of the access lines 241, 241', 242, 242', 243, and 243' can be configured as a conductive line, which can be driven (e.g., activated) by a separate driver (described below).

[0078] The memory device 200 can include drivers 231, 231', 232', 232, 233, and 233' respectively coupled to the access lines 241, 241', 242, 242', 243, and 243'. The drivers 231, 232, and 233 can be referred to as read drivers and can be used to selectively drive (e.g., activate) the access lines 241, 242, and 243 respectively during a read operation. The drivers 231', 232', and 233' can be referred to as write drivers and can be used to selectively drive (e.g., activate) the access lines 241', 242', and 243' respectively during a write operation.

[0079] Drivers 231, 231', 232', 232, 233' and 233' can be respectively coupled to access lines 241, 241', 242, 242', 243 and 243'. The drivers can be complementary metal-oxide-semiconductor (CMOS) drivers or other types of drivers operable to provide (e.g., drive) signals WL1, WL1', WL2, WL2', WL3' and WL3' respectively associated with access lines 241, 241', 242, 242', 243 and 243'. The signals WL1, WL1', WL2, WL2', WL3' and WL3' can be provided (e.g., biased) with different voltages depending on which operation (e.g., read or write operation) the memory device 200 performs.

[0080] Drivers 231, 231', 232', 232, 233' and 233' can be configured to respectively drive access lines 241, 241', 242, 242', 243 and 243' one at a time during an operation (e.g., read or write operation) of the memory device 200 to access one selected memory cell (or a plurality of selected memory cells) among memory cells 210 to 215. The selected cell(s) can be referred to as the target cell(s). In a read operation, information can be read from one selected memory cell (or a plurality of selected memory cells). In a write operation, information can be stored in one selected memory cell (or a plurality of selected memory cells).

[0081] During an operation (such as a read or write performed on a selected memory cell), a driver coupled to an access line (selected access line) associated with the selected memory cell may apply different voltages to the selected access line (the conductive region of the selected access line). For example, during an operation to read information from memory cell 210 (such as a read operation), driver 231 may apply a voltage to line 241 to turn on transistor T1 of memory cell 210, and driver 231' may apply another voltage to line 241' to turn off transistor T2 of memory cell 210. In another example, during an operation to store information in memory cell 210 (such as a write operation), driver 231 may apply a voltage to line 241 to turn off transistor T1 of memory cell 210, and driver 231' may apply another voltage to line 241' to turn on transistor T2 of memory cell 210. Separate drivers (such as drivers 231 and 231') that include access lines (such as access lines 241 and 241') associated with a memory cell (such as memory cell 210) may improve the operation of memory device 200. For example, the separate drivers may allow transistors T1 or T2 of a selected memory cell to be turned off (such as completely turned off) during a particular operation (such as a read or write operation) to improve control of the current (such as a read current or a write current) associated with the selected memory cell.

[0082] The structure of memory device 200 described above with reference to Figures 2 to 5 is described below with reference to Figures 6A to 7C description.

[0083] For simplicity, a detailed description of the same elements of memory device 200 is not repeated in Figures 6A to 7C description. Figures 6A to 7C Some of the memory cells and associated data lines and access lines of memory device 200 schematically shown in Figure 2 are not shown. Figures 6A to 7C Some of the memory cells and associated data lines and access lines of memory device 200 that are not schematically shown in Figure 2 are also shown. For simplicity and ease of viewing, cross-sectional lines (such as hatching) are omitted from most of the elements shown in Figures 6A to 7C and other figures described herein. Some elements of memory device 200 may be omitted from a particular figure among the figures to avoid obscuring the description of one element (or several elements) described in this particular figure. The dimensions (such as physical structure) of the elements shown in the figures described herein are not drawn to scale.

[0084] Figure 6AShows the structure of a memory device 200 including a substrate 699 and levels 601 and 602 positioned one above the other (e.g., stacked) on the substrate 699, according to some embodiments described herein. Figure 6A Shows two levels 601 and 602 of the memory device 200 as an example. However, the memory device 200 includes a large number of levels (e.g., up to 100 levels or more than 100 levels).

[0085] Figure 6A The X, Y, and Z directions shown in may represent directions corresponding to a three-dimensional (3D) structure of the memory device 200. For simplicity, Figure 6A only a portion of the memory device 200 with respect to the X-Z direction is shown. The Z direction (e.g., the vertical direction) is the direction perpendicular to the substrate 699 (e.g., outward from the substrate 699). The Z direction is also perpendicular to the X direction and the Y direction (e.g., extending vertically from the X direction and the Y direction). The X direction and the Y direction are perpendicular to each other. Figure 6B Shows a top view (e.g., an X-Y plan view) of the memory device 200 in the X-Y direction along line 6B-6B. Figure 6A A portion labeled " Figure 7A " is shown in detail in Figure 7A .

[0086] In Figure 6A , the substrate 699 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrates. As Figure 6A shown in, each of the levels 601 and 602 may itself have memory cells (labeled "memory cells"). Thus, the levels 601 and 602 may be referred to as memory cell levels 601 and 602.

[0087] Each of the levels 601 and 602 may itself include access lines associated with the memory cells in the same level. Figure 6A Shows access lines (also referred to as "access lines") associated with signals WL0, WL1, WLi, WLj, and WL. Memory cells in different levels (e.g., levels 601 and 602) may not share access lines. For example, the memory cells in level 601 may not share access lines with the memory cells in level 602. As Figure 6A shown in, each memory cell may be between and adjacent (e.g., associated) with two corresponding portions of the access line (e.g., top and bottom access lines). For example, the memory cell 210 may be associated with two corresponding portions of the access line associated with the signal WL1. In another example, the memory cell 299 may be associated with two corresponding portions of the access line associated with the signal WLi. Figure 2 The memory cell 299 is not schematically shown in.

[0088] AsFigure 6A As shown in, the memory device 200 may include data lines (also referred to as "data lines" or data lines BLA, BLB, BLC, BL1, BLD, and BLE) associated with signals BLA, BLB, BLC, BL1, BLD, and BLE. The data line associated with signal BL1 may correspond to Figure 2 data line 221 (associated signal BL1). Each of the data lines may include a conductive structure. For simplicity, Figure 6A only the conductive structures 760, 761, 762, and 763 of the data lines associated with signals BLC, BL1, BLD, and BLE are labeled in. As Figure 6A shown in, each of the data lines may have a length extending in the Z direction through the levels (through levels 601 and 602), where the Z direction is perpendicular to the substrate 699. As Figure 6A shown in, the Z direction is also the direction from one level to another (e.g., from one horizontal level to another). Thus, each of the data lines (and their corresponding conductive structures) of the memory device 200 may have a length in the direction from one level to another (e.g., from one horizontal level to another).

[0089] The memory device 200 may include dielectric portions (which include dielectric material) 795 between adjacent data lines (e.g., adjacent data lines BLC and BL1 and adjacent data lines BLD and BLE). Figure 6A Six data lines BLA, BLB, BLC, BL1, BLD, and BLE are shown as an example. The number of data lines of the memory device 200 may vary.

[0090] As Figure 6A shown in, the memory device 200 may also include conductive lines (e.g., common conductive lines) associated with signals PLT0 and PLT1. Each of these conductive lines may include a corresponding conductive structure, such as conductive structures 796 and 797. Each of the conductive structures 796 and 979 may include a conductive material (e.g., conductive doped polysilicon, metal, or other conductive material). Each of the conductive structures 796 and 797 may be a common conductive structure between adjacent memory cells in the Z direction ( Figure 6A ) for different levels (e.g., levels 601 and 602) and between adjacent memory cells in the X direction ( Figure 6B ) for the same level (e.g., level 602). Each of the conductive structures 796 and 797 of the corresponding conductive lines (e.g., the conductive lines associated with signal PLT0 or PLT1) may be coupled to the ground connection (e.g., ground connection 297) of the memory device 200 (or may be part of the ground connection). During operation of the memory device, signals PLT0 and PLT1 may be provided with 0V (e.g., ground potential). AsFigure 6A As shown, like data lines BLA, BLB, BLC, BL1, BLD, and BLE, the conductive structure 797 of each of the conductive lines (associated with signals PLT0 and PLT1) can have a length extending in the Z direction through the layers (through layers 601 and 602).

[0091] Figure 6B Shows a top view (e.g., cross-section) of the structure of memory device 200 along Figure 6A line 6B-6B, which includes Figure 6A a portion of layer 602. For simplicity, Figure 6B only some of the memory cells in layer 602 and some of the other data lines of memory device 200 (e.g., data lines associated with signals BLF, BLG, BLH, BLI, BLJ, BLK, and BLL) are shown in Figure 6B Also shown Figure 6A is a top view of some memory cells of memory device 200 not shown in Figure 6B Also shown is a top view of other conductive lines (e.g., common conductive lines) associated with signals PLT2 and PLT3. Figure 6A (described above) shows a side view of memory device 200 along line 6A-6A. Figure 6A A portion marked as “ Figure 7B ” in Figure 7B is shown in detail in

[0092] In Figure 6B , the access lines associated with signals WL0, WL1, WLi, and WLj are shown in a partially cut-away top view to show some portions of the underlying memory cells underlying these access lines. As Figure 6B shown, each of the access lines associated with signals WL0, WL1, WLi, and WLj can be a separate strip (e.g., a strip of conductive material) having a length in the Y direction, where the Y direction is perpendicular to the direction (e.g., the X direction) from one memory to the next memory in the same layer (e.g., layer 602) in the X direction. The access lines associated with signals WL0, WL1, WLi, and WLj can be separated (electrically separated) from each other in the X direction. As Figure 6B shown, the memory cells of the same layer (e.g., layer 602) can be arranged in the X direction (spaced apart from each other) and in the Y direction (spaced apart from each other). Memory cells in the X direction (e.g., adjacent memory cells) may not share an access line (e.g., may not share a word line). For example, Figure 6BThe memory cell 210 therein (which is adjacent to (e.g., neighboring) the memory cell 299 and positioned at a distance from the memory cell 299 in the X direction) may not share the access line associated with the signal WL1 with the memory cell 299 in the X direction.

[0093] As Figure 6C shown, each memory cell may be adjacent to two conductive regions (e.g., top and bottom conductive regions) of the access line and between the two conductive regions. For example, the access line associated with the signal WL1 may include a conductive region (e.g., top conductive region) 741T and a conductive region (e.g., bottom conductive region) 741B. The conductive regions 741T and 741B may be part of the access line 241 ( Figure 2 ) of the memory device 200. The conductive regions 741T and 741B are opposite to each other in the Z direction. Relative to the top view (relative to the Figure 6A Z direction shown), the conductive region 741T may be located above (e.g., on top of) the memory cell 210. Relative to the top view (relative to the Figure 6A Z direction shown), the conductive region 741B may be located below (e.g., beneath) the memory cell 210. As Figure 6B shown, each of the conductive regions 741T and 741B may be configured as a strip of conductive material electrically separated from adjacent conductive regions of other access lines (e.g., access lines associated with the signals WL0, WLi, and WLj).

[0094] In another example, as Figure 6B shown, the access line associated with the signal WLi may include a conductive region (e.g., top conductive region) 749T and a conductive region (e.g., bottom conductive region) 749B. The conductive regions 749T and 749B may be part of the access line associated with the memory cell 299. As Figure 6B shown, each of the conductive regions 749T and 749B may be configured as a strip of conductive material electrically separated from adjacent conductive regions of other access lines (e.g., access lines associated with the signals WL1, WLi, and WLj). The conductive regions 749T and 749B are opposite to each other in the Z direction. Relative to the top view (relative to the Figure 6A Z direction shown), the conductive region 749T may be located above (e.g., on top of) the memory cell 299. Relative to the top view (relative to the Figure 6A Z direction shown), the conductive region 749B may be located below (e.g., beneath) the memory cell 299.

[0095] In Figure 6B the example, the conductive regions 741T and 741B may be electrically coupled to each other through a connection 740. The connection 740 may include a conductive connection (which may include a conductive material (e.g., metal)). As Figure 6BAs shown, each of the other access lines (e.g., the access lines associated with signals WL0, WLi, and WLj) may also include top and bottom conductive regions, where the top and bottom conductive regions may also be electrically coupled to each other through corresponding connections 740.

[0096] Figure 6C Shown Figure 6B is an example of a variant of the memory device 200, where the conductive regions 741T and 741B are electrically separated from each other. The conductive regions 741T and 741B in FIG. C may be parts of the access lines 241 and 241' respectively. As Figure 5 shown in Figure 6C the conductive regions 741T and 741B of the access lines associated with signals WL1 and WL' may be coupled to different drivers 231 and 231' respectively. The drivers 231 and 231' are the same as the drivers Figure 2 shown in Figure 6C As shown in

[0097] Figure 6D Shown Figure 6B is an example of a variant of the memory device 200, where the conductive regions of the corresponding data lines may be electrically coupled to each other. For example, as Figure 6D shown in Figure 6D the conductive structures 761 and 762 of the corresponding data lines (associated with signals BL1 and BLD) may be electrically coupled to each other through a connection 723. The conduction 723 may include a conductive connection (which may include a conductive material such as metal).

[0098] Figure 6E Shown Figure 6C is an example of a variant of the memory device 200, where the conductive regions of the corresponding data lines may be electrically coupled to each other. Figure 6E The memory device 200 of Figure 6Cis the same as the memory device 200 in, except that Figure 6E the memory device 200 in may include a connection 723. Similar to Figure 6D the memory device 200 in, Figure 6E two or more of the data lines of the memory device 200 in may be electrically coupled to each other.

[0099] Figure 7A Shows Figure 6A a side view (e.g., cross-section) of the portion of the memory device 200 in labeled " Figure 7A ". Figure 7B Shows a portion of the memory device 200 along Figure 7A line 7B - 7B and Figure 6B a top view of the portion in labeled " Figure 7B ". Figure 7C Shows a top view of a portion of the memory device 200 along Figure 7A line 7C - 7C.

[0100] In Figure 7A , Figure 7B and Figure 7C the same elements of the memory cells 210 and 299 and other elements of the memory device 200 are given the same labels. Thus, for simplicity, the following description of the elements of the memory cells 210 and 299 and Figure 7A other elements in also refers to Figure 7B and Figure 7C the same elements shown in. Therefore, some of the elements in Figure 7B and Figure 7C are not described separately.

[0101] Figure 7A Shows details of the cross-section of levels 601 and 602 of the memory device 200. As Figure 7A shown, each of levels 601 and 602 may have different tiers (physical tiers) that are positioned one above the other (e.g., stacked) in the Z direction on top of the substrate 699. For example, level 602 may include tiers 771 to 777. For simplicity, the tiers in level 601 are not labeled.

[0102] Each of the data lines (associated with signals BLC, BL1, BLD, and BLE) may be formed of a conductive structure (e.g., may include a conductive structure). Figure 7A Shows conductive structures 760, 761, 762, and 763 of the data lines associated with signals BLC, BL1, BLD, and BLE respectively. Each of the conductive structures 760, 761, 762, and 763 may include a conductive material (e.g., conductive doped polysilicon, metal, or other conductive material). As Figure 7AAs shown, each of the conductive structures 760, 761, 762, and 763 may have a length extending in the Z direction through the tiers (through tiers 601 and 602), where the Z direction is perpendicular to the substrate 699.

[0103] The conductive structures 760, 761, 762, and 763 may be electrically coupled to some of the elements (e.g., the read and write channel regions of the respective transistors T1 and T2, described below) of the corresponding memory cells (e.g., memory cells 210 and 299) in the memory cell of tier 602. Each of the conductive structures 760, 761, 762, and 763 is electrically separated from the access lines (e.g., the access lines associated with signals WL1, WLi, and WL) of the memory device 200 by respective dielectric portions (e.g., dielectric portions 725, 735, 745, and 755). Each of the dielectric portions 725, 735, 745, and 755 may comprise a dielectric material (e.g., silicon dioxide or other dielectric material).

[0104] For simplicity, Figure 7A the description describes the elements of tier 602. Tier 601 may have elements similar to those of the memory cell 210 (which have similar or identical markings). As Figure 7A shown, the conductive regions 741T and 741B may be respectively located on the levels 777 and 771. The conductive regions 741T and 741B may collectively be part of the access line 241 ( Figure 2 ) (e.g., the top and bottom conductive regions (or parts)). Alternatively, the conductive regions 741T and 741B may be respectively part of Figure 5 the access lines 241 and 241' of

[0105] Each of the conductive regions 741T and 741B may comprise a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). The conductive region 741T may be electrically separated from the conductive structure 761 of the data line associated with the signal BL1 and the conductive structure 797 of the conductive line (e.g., the common conductive line) associated with the signal PLT1 by the respective dielectric portion 725. The conductive region 741B is electrically separated from the conductive structures 761 and 797 by the respective dielectric portion 735.

[0106] As Figure 7A shown, the memory cell 299 adjacent to the memory cell 210 in the X direction also includes conductive portions 749T and 749B (as part of the access line associated with the signal WLi) respectively located on the levels 777 and 771, similar to the conductive regions 741T and 741B respectively.

[0107] In memory device 200, adjacent memory cells in the X direction may not share one access line (e.g., word line) or a plurality of access lines. For example, memory cells 210 and 299 may not share one or more access lines. Accordingly, conductive regions 741T and 749T, which are located on the same tier 777, may be electrically separated from each other. For example, conductive regions 741T and 749T are not formed of the same piece of conductive material (e.g., are not included in the same piece of conductive material). Similarly, conductive regions 741B and 749B, which are located on the same tier 771, may be electrically separated from each other. For example, conductive regions 741B and 749B are not formed of the same piece of conductive material (e.g., are not included in the same piece of conductive material).

[0108] As Figure 7A shown, memory device 200 may include different dielectric portions located on different tiers in the Z direction to electrically separate components within the same level (in the Z direction) and to electrically separate the levels from each other. For example, as Figure 7A shown, memory device 200 may include dielectric portions 717, 718, and 719 located on tiers 772, 774, and 776, respectively. Dielectric portions 717, 718, and 719 may electrically separate components within level 602 (in the Z direction). Memory device 200 may include dielectric portion 765 that may electrically separate the levels from each other (in the Z direction).

[0109] Dielectric portions 717, 718, 719, and 765 may have the same dielectric material or different dielectric materials. Example materials for dielectric portions 717, 718, 719, and 765 include silicon oxide, silicon nitride, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials (e.g., other high-k dielectric materials).

[0110] Memory device 200 may include charge storage structure 702 and material 720 located on tier 775. Material 720 may also be referred to as portion 720. Material 720 is adjacent to (e.g., in contact with) charge storage structure 702 and is electrically coupled to charge storage structure 702. Material 720 may also be electrically coupled to a corresponding conductive structure (e.g., conductive structure 761 or 762) of a corresponding data line (e.g., a data line associated with signal BL1 or BLD). As Figure 7A shown, each of memory cells 210 and 299 of memory device 200 (and two other memory cells located below memory cells 210 and 299) may include transistor T2. Material 720 may form a portion of the channel region (e.g., write channel region) of transistor T2 of a corresponding memory cell (e.g., memory cell 210 or 299).

[0111] The material 720 (also referred to as portion 720) of a particular memory cell (e.g., memory cell 210) can form the source (e.g., source terminal), drain (e.g., drain terminal), or channel region (e.g., write channel region) between the source and drain of transistor T2 of this particular memory cell (e.g., memory cell 210). For example, as Figure 7A shown in, the source, channel region, and drain of transistor T2 of memory cell 210 can be formed of a monolithic same material (or alternatively, a combination of monolithic same materials), such as material 720. Thus, the source, drain, and channel region of transistor T2 of memory cell 210 can be formed of the same material (e.g., material 720) of the same conduction type (e.g., n-type or p-type).

[0112] The material 720 (e.g., the write channel region of transistor T2) of a particular memory cell (e.g., memory cell 210) of memory device 200 can be part of the write path of this particular memory cell. For example, the material 720 of memory cell 210 can be part of the write path of memory cell 210 that can carry current (e.g., write current) during a write operation for storing information in memory cell 210. For example, during a write operation, in order to store information in Figure 7A memory cell 210, the material 720 of memory cell 210 can conduct current (e.g., write current) between the conductive structure 761 and the charge storage structure 702 of memory cell 210. The direction of the write current can be from the conductive structure 761 of memory device 200 to the charge storage structure 702. In an example where transistor T2 is an NFET (e.g., NMOS), the current (e.g., write current) can include electron conduction of memory cell 210 (e.g., electron conduction in the direction from the conductive structure 761 through the material 720 (channel region of transistor T2) to the charge storage structure 702).

[0113] The material 720 can include a structure of semiconductor material (e.g., a piece (e.g., a layer)). In an example where transistor T2 is an NFET (as described above), the material 720 can include an n-type semiconductor material (e.g., n-type silicon).

[0114] In another example, the semiconductor material forming the material 720 can include a piece of oxide material. Examples of oxide materials for the material 720 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0115] As an example, the material 720 can include at least one of the following: tin zinc oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x, indium oxide (In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

[0116] Using the foregoing materials in the memory device 200 provides improvements and benefits to the memory device 200. For example, during a read operation, in order to read information from a selected memory cell (e.g., memory cell 210), charge from the charge storage structure 702 of the selected memory cell may leak into the transistor T2 of the selected memory cell. Using the foregoing materials for the channel region of the transistor T2 (e.g., material 720) may reduce or prevent such leakage. This improves the accuracy of the information read from the selected memory cell and improves the retention of the information stored in the memory cells of the memory devices (e.g., memory device 200) described herein.

[0117] The foregoing materials are examples of material 720. However, other materials different from the foregoing materials (e.g., relatively high bandgap materials) may be used.

[0118] As Figure 7A shown, the charge storage structure 702 is adjacent to (e.g., in contact with) the material 720 and is electrically coupled to the material 720. The charge storage structure 702 may correspond to Figure 2 the charge storage structure 202 of the memory device 200 schematically shown in Figure 7A shown, the charge storage structure 702 is electrically separated from the conductive structure 797 of the corresponding conductive line (e.g., the conductive line associated with the signal PLT1) by the dielectric portion 715. The charge storage structure 702 may comprise a charge storage material (or combination of materials), which may comprise a sheet (e.g., a layer) of semiconductor material (e.g., polysilicon), a sheet (e.g., a layer) of metal, or a sheet of material (or materials) capable of trapping charge. The materials of the charge storage structure 702 and the conductive regions 741T, 741B, 749T, and 749B may be the same or different.

[0119] The memory device 200 may comprise a portion 710 on the tier 773. The portion 710 is adjacent to one side (e.g., the bottom side) of the dielectric portion 718 and is separated from the portion 720 and the charge storage structure 702 by the dielectric portion 718. The portion 720 and the charge storage structure 702 are adjacent to the other side (e.g., the top side) of the dielectric portion 718 and are separated from the portion 710 by the dielectric portion 718. The portion 710 may be electrically coupled to the conductive structure 797. The portion 710 may also be electrically coupled to one of the conductive structures 761 and 762 of the corresponding data line (the data line associated with the signal BL1 or BLD). As Figure 7A shown, each of the memory cells 210 and 299 (and two other memory cells located below the memory cells 210 and 299) may comprise a transistor T1. The portion 710 may form a portion of the channel region (e.g., the read channel region) of the transistor T1 of the corresponding memory cell (e.g., memory cell 210 or 299).

[0120] A portion 710 of a particular memory cell (e.g., memory cell 210) may form a source (e.g., source terminal), a drain (e.g., drain terminal), or a channel region (e.g., write channel region) between the source and the drain of a transistor T1 of this particular memory cell (e.g., memory cell 210). For example, as Figure 7A shown, the source, channel region, and drain of transistor T1 of memory cell 210 may be formed of a monolithic same material (or alternatively, a combination of monolithic same materials), such as material 710. Thus, the source, drain, and channel region of transistor T1 of memory cell 210 may be formed of the same material (e.g., the material of portion 710) of the same conduction type (e.g., n-type or p-type).

[0121] Portion 710 may comprise a semiconductor material. Example materials for portion 710 include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials, and semi-conductive oxide materials (oxide semiconductors, such as SnO or other oxide semiconductors). The semiconductor material of portion 710 and the semiconductor material of portion 720 (material 720) may have different conduction types (e.g., n-type conductivity and p-type conductivity). Alternatively, the semiconductor material of portion 710 and the semiconductor material of portion 720 (material 720) may have the same conduction type (e.g., n-type conductivity or p-type conductivity).

[0122] A portion 710 (e.g., the read channel region of transistor T1) of a particular memory cell (e.g., memory cell 210) of memory device 200 may be part of the read path of this particular memory cell. For example, portion 710 of memory cell 210 may be part of the read path of memory cell 210 that may carry a current (e.g., read current) during a read operation to read information from memory cell 210. For example, during a read operation, in order to read information from Figure 7A memory cell 210 in, portion 710 of memory cell 210 may conduct a current (e.g., read current) between conductive structure 761 and conductive structure 797 (e.g., a portion of a ground connection). The direction of the read current may be from conductive structure 761 through portion 710 to conductive structure 797. In an example where transistor T1 is a PFET (e.g., PMOS), the current (e.g., read current) may comprise hole conduction of memory cell 210 (e.g., hole conduction in the direction from conductive structure 761 through portion 710 (the channel region of transistor T1) to conductive structure 797).

[0123] In an example where transistor T1 is a PFET and transistor T2 is an NFET, the material forming portion 710 may have a different conductivity type from that of material 720. For example, portion 710 may include a region of p-type semiconductor material (such as p-type silicon), and material 720 may include a region of n-type semiconductor material (such as n-type gallium phosphide (GaP)).

[0124] As Figure 7A shown in Figure 6B , conductive region 741B may be opposite (in the Z direction) to portion 710 of transistor T1 of memory cell 210 and may form the gate of transistor T1 of memory cell 210. Conductive region 741T may be opposite (in the Z direction) to portion 720 of memory cell 210 and charge storage structure 702 and may form the gate of transistor T2 of memory cell 210. Thus, the same signal (such as WL1) may be used to control (such as turn on or off) transistors T1 and T2 of memory cell 210 in a structure (such as Figure 6B ) where conductive regions 741T and 741B may be electrically coupled to each other (such as shorted) (such as through Figure 6C the corresponding connection 740 in

[0125] As Figure 7A shown in Figure 6B , conductive region 749B may be opposite (in the Z direction) to portion 710 of transistor T1 of memory cell 299 and may form the gate of transistor T1 of memory cell 299. Conductive region 749T may be opposite (in the Z direction) to portion 720 of memory cell 299 and charge storage structure 702 and may form the gate of transistor T1 of memory cell 299. Thus, the same signal (such as WLi) may be used to control (such as turn on or off) transistors T1 and T2 of memory cell 299 in a structure (such as Figure 6B ) where conductive regions 749T and 749B may be electrically coupled to each other (such as shorted) (such as through Figure 6C the corresponding connection 740 in

[0126] As Figure 7AAs shown, the memory cells of the memory device 200 (e.g., memory cells 210, 299, and two memory cells (not labeled) located below memory cells 210 and 299) have similar or identical structures. Thus, for simplicity, the detailed description of memory cell 299 and other memory cells is omitted.

[0127] The description above with reference to Figures 6A to 7C shows that elements (e.g., memory cells and access lines) can be arranged (e.g., formed) in different levels in the memory device 200. This can allow multiple levels (e.g., levels 601 and 602 and similar levels) of the memory device 200 to be formed together. Thus, the cost of forming the memory device 200 (e.g., cost per bit) can be reduced. Additionally, the length of the conductive structure of the data lines can be based on the number of levels. The memory device 200 (as Figure 7A shown) can have a relatively compact size for the level structure and memory cell structure of its memory cells (e.g., each memory cell includes a relatively small (e.g., thin) size in the Z direction). This can improve (e.g., increase) the area efficiency of the memory device compared to some similar memory devices. The compact size (e.g., relatively small memory cell size in the Z direction) can also improve (e.g., shorten) the length of the data lines of the memory device 200 (e.g., the vertical length in the Z direction). This can reduce the coupling capacitance between the data lines of the memory device 200 and the total capacitance of the data lines. The reduction of these capacitances can lead to improved operation of the memory device 200.

[0128] The description of the devices (e.g., memory devices 100 and 200) and methods (e.g., the operations of memory devices 100 and 200) is intended to provide a general understanding of the structures of the various embodiments and is not intended to provide a complete description of all elements and features of the devices that can use the structures described herein. The devices herein refer to, for example, an apparatus (e.g., any of memory devices 100 and 200) or a system (e.g., an electronic product that can include any of memory devices 100 and 200).

[0129] The description above with reference to Figures 1 to 7CAny of the described components can be implemented in numerous ways, including via software simulation. Thus, a device (such as memory devices 100 and 200) or portions of each of these memory devices may herein be characterized generally as "a number of modules" (or "modules"). Such modules may include, depending on the expectations and / or requirements of the particular implementation of each embodiment, hardware circuitry, single and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware and combinations thereof. For example, such modules may be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / heat dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various possible embodiments.

[0130] The memory devices described herein (such as memory devices 100 and 200) may be included in a device (such as an electronic circuitry), such as a high-speed computer, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message switches, and specialized modules including multi-layer multi-chip modules. Such devices may further be included as sub-components within a variety of other devices (such as electronic systems), such as televisions, mobile phones, personal computers (such as laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (such as MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (such as heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0131] The foregoing reference Figures 1 to 7C The described embodiments include devices and methods of operating the devices. One of the devices includes: first, second, and third conductive structures, each having a length in a first direction; first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction; a first conductive region; and a second conductive region. Each of the first and second memory cells includes: a first semiconductor portion positioned on a first tier of the device and coupled to the third conductive structure and one of the first and second conductive structures; a second semiconductor portion positioned on a second tier of the device and coupled to one of the first and second conductive structures. The first conductive region is opposite the respective first and second semiconductor portions of the first memory cell. The second conductive region is opposite the respective first and second semiconductor portions of the second memory cell. Other embodiments including additional devices and methods are described.

[0132] In the detailed description and claims, the term "on", as used with respect to two or more elements (e.g., materials), where one is "on" another means that there is at least some contact between the elements (e.g., between the materials). The term "above" means that the element (e.g., material) is in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "above" implies any directionality as used herein, unless so stated.

[0133] In the detailed description and claims, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0134] In the detailed description and claims, a list of items joined by the term "at least one of..." can mean any combination of the listed items. For example, if the items A and B are listed, then the phrase "at least one of A and B" means only A, only B, or A and B. In another example, if the items A, B, and C are listed, then the phrase "at least one of A, B, and C" means only A, only B, only C, A and B (excluding C), A and C (excluding B), B and C (excluding A), or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0135] In the detailed description and claims, a list of items joined by the term "one of..." can mean only one of the listed items. For example, if the items A and B are listed, then the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if the items A, B, and C are listed, then the phrase "one of A, B, and C" means only A, only B, or only C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0136] The foregoing description and drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other variations. The examples represent possible variations. Portions and features of some embodiments may be included in portions and features of other embodiments or may replace portions and features of other embodiments. Many other embodiments will be apparent to those skilled in the art after reading and understanding the foregoing description.

Claims

1. An apparatus, comprising: a first conductive structure, a second conductive structure, and a third conductive structure, each of the first, second, and third conductive structures having a length in a first direction; a first memory cell and a second memory cell, the second memory cell positioned at a distance from the first memory cell in a second direction perpendicular to the first direction, each of the first and second memory cells comprising: a first semiconductor portion positioned on a first tier of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures; and a second semiconductor portion positioned on a second tier of the apparatus and coupled to one of the first and second conductive structures; a first conductive region positioned on a third tier of the apparatus and opposite the first semiconductor portion of the first memory cell; a first additional conductive region positioned on a fourth tier of the apparatus and opposite the second semiconductor portion of the first memory cell; a second conductive region positioned on the third tier and opposite the first semiconductor portion of the second memory cell, the second conductive region being electrically separated from the first conductive region; and a second additional conductive region positioned on the fourth tier and opposite the second semiconductor portion of the second memory cell, the second additional conductive region being electrically separated from the first additional conductive region.

2. The apparatus according to claim 1, wherein each of the first conductive region, the first additional conductive region, the second conductive region, and the second additional conductive region has a length in a third direction perpendicular to a direction from the first memory cell to the second memory cell.

3. The apparatus according to claim 1, wherein: the first conductive region and the first additional conductive region are electrically coupled to each other; and the second conductive region and the second additional conductive region are electrically coupled to each other.

4. The apparatus according to claim 1, wherein: the first conductive structure is part of a first data line of the apparatus; and the second conductive structure is part of a second data line of the apparatus.

5. The apparatus according to claim 1, wherein the third conductive structure is part of a ground connection of the apparatus.

6. The apparatus according to claim 1, wherein: the first conductive region is part of a first word line of the apparatus; and the second conductive region is part of a second word line of the apparatus.

7. The apparatus according to claim 1, wherein: the first additional conductive region is part of a first word line of the apparatus; and the second additional conductive region is part of a second word line of the apparatus.

8. The apparatus according to claim 1, wherein the first and second semiconductor portions have different conductivity types.

9. The apparatus according to claim 1, wherein the first and second semiconductor portions have the same conductivity type.

10. The apparatus according to claim 1, wherein the second semiconductor portion comprises a semiconductive oxide material.

11. An apparatus, comprising: a first conductive structure; A second conductive structure, each of the first and second conductive structures having a length in a first direction; A memory cell, comprising: A first channel region, located on a first tier of the device and coupled to the first and second conductive structures; And A second channel region, located on a second tier of the device and coupled to the first conductive structure; A first conductive region, located on a third tier of the device and opposite to the first channel region; And A first additional conductive region, located on a fourth tier of the device and opposite to the second channel region, wherein the first additional conductive portion is electrically separated from the first conductive region, and each of the first conductive region and the first additional conductive region has a length in a second direction.

12. The device according to claim 11, wherein the first conductive structure is part of a data line of the device, and the second conductive structure is part of a ground plane of the device.

13. The device according to claim 11, wherein the first channel region comprises a first semiconductor material having a first conductivity type, and the second channel region comprises a second semiconductor material having a second conductivity type.

14. The device according to claim 11, wherein the first channel region comprises a first semiconductor material having p-type conductivity, and the second channel region comprises a second semiconductor material having n-type conductivity.

15. The device according to claim 11, wherein the second channel region comprises at least one of the following: tin zinc oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ) Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

16. The device according to claim 11, further comprising: A first driver, coupled to the first additional conductive region; And A second driver, coupled to a second additional conductive region.

17. The device according to claim 11, further comprising: A first driver for applying a first voltage to the First additional conductive region during an operation performed on the memory cell; And A second driver for applying a second voltage to the Second additional conductive region during the operation performed on the memory cell.

18. A device, comprising: A first data line, a second data line coupled to the first data line, and a conductive line between the first and second data lines; A first memory cell, comprising: A first channel region, located on a first tier of the device and coupled to the first data line and the conductive line; And A second channel region, located on a second tier of the device and coupled to the first data line; A second memory cell, adjacent to the first memory cell in a direction perpendicular to the length direction of the conductive line, the second memory cell comprising: A third channel region, located on the first tier and coupled to the second data line and the conductive line; and A fourth channel region, located on the second tier and coupled to the second data line.

19. The device according to claim 18, further comprising: A first conductive region, located on a third tier of the device and opposite to the first channel region of the first memory cell; A first additional conductive region, located on a fourth tier of the device and opposite to the second channel region of the first memory cell; A second conductive region, which is located on the third step and is opposite to the third channel region of the second memory cell, and the second conductive region is electrically separated from the first conductive region; and A second additional conductive region, which is located on the fourth step and is opposite to the fourth channel region of the second memory cell, and the second additional conductive region is electrically separated from the first additional conductive region.

20. The device according to claim 19, wherein each of the first conductive region, the first additional conductive region, the second conductive region, and the second additional conductive region has a length in a direction perpendicular to the direction from the first memory cell to the second memory cell.

21. The device according to claim 19, wherein: the first additional conductive region is electrically coupled to the first conductive region; and the second additional conductive region is electrically coupled to the second conductive region.

22. A device, comprising: layers, which are located one above the other, and each of the layers includes memory cells; a first data line, a second data line, and a conductive wire, and each of the conductive wire and the first and second data lines includes a conductive structure that extends through the layers; a first memory cell and a second memory cell, which are included in the memory cells of one of the layers, and the first memory cell is positioned at a certain distance from the second memory cell in a direction perpendicular to the direction from one layer to another layer, and each of the first and second memory cells includes: a first transistor, which is coupled to the conductive wire and one of the first and second data lines; and a second transistor, which is coupled to one of the first and second data lines; a first conductive region, which is opposite to a part of the first transistor of the first memory cell; a first additional conductive region, which is opposite to a part of the second transistor of the first memory cell; a second conductive region, which is opposite to a part of the first transistor of the second memory cell and is electrically separated from the first conductive region; and a second additional conductive region, which is opposite to a part of the second transistor of the second memory cell and is electrically separated from the first additional conductive region, wherein each of the first conductive region, the first additional conductive region, the second conductive region, and the second additional conductive region has a length in a direction perpendicular to the direction from the first memory cell to the second memory cell.

23. The device according to claim 22, wherein: the part of the first transistor of the first memory cell includes the channel region of the first transistor of the first memory cell; the part of the second transistor of the first memory cell includes the channel region of the second transistor of the first memory cell; the part of the first transistor of the second memory cell includes the channel region of the first transistor of the second memory cell; and the part of the second transistor of the second memory cell includes the channel region of the second transistor of the second memory cell.

24. The device according to claim 22, wherein: the portion of the first transistor of the first memory cell includes a charge storage structure of the first memory cell; and the portion of the first transistor of the second memory cell includes a charge storage structure of the second memory cell.

25. The device according to claim 22, wherein the first conductive region is electrically coupled to the first additional conductive region, and the second conductive region is electrically coupled to the second additional conductive region.

26. The device according to claim 22, wherein the first conductive region is electrically separated from the first additional conductive region, and the second conductive region is electrically separated from the second additional conductive region.

27. The device according to claim 22, wherein the first data line is coupled to the second data line.

28. The device according to claim 22, wherein the conductive wire is part of a ground connection of the device.

29. The device according to claim 22, further comprising: a first driver for turning on the first transistor of the first memory cell during an operation of reading information from the first memory cell; and a second driver for turning off the second transistor of the first memory cell during the operation of reading information from the first memory cell.

30. The device according to claim 22, further comprising: a first driver for turning off the first transistor of the first memory cell during an operation of storing information in the first memory cell; and a second driver for turning on the second transistor of the first memory cell during the operation of storing information in the first memory cell.

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