Three-dimensional memory devices including composite word lines including

Abstract

A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory openings, the memory opening fill structure comprising: a respective vertical stack of memory elements; and a corresponding vertical semiconductor channel; forming a lateral isolation trench through the alternating stack; forming lateral recesses by selectively removing the sacrificial material layers relative to the insulating layers and the memory opening fill structures; depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant; and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of the entire contents of U.S. Non - provisional application Ser. No. 18 / 360,474, filed on Jul. 27, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE WORD LINES INCLUDING A RESPECTIVE FLUORINE - FREE CAPPING SUBLAYER AND METHODS OF FORMING THE SAME", which claims the priority of U.S. Provisional Application No. 63 / 488,818, filed on Mar. 7, 2023, and is hereby incorporated by reference in its entirety for all purposes. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including composite word lines including respective fluorine - free capping sublayers and methods of forming the same. Background art

[0004] Three - dimensional vertical NAND strings with one bit per cell are disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", IEDM Proc. (2001) 33 - 36. Summary of the invention

[0005] According to one aspect of the present disclosure, a method of forming a memory device includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, the memory opening fill structures including: respective vertical stacks of memory elements; and respective vertical semiconductor channels; forming lateral isolation trenches through the alternating stack; forming lateral grooves by selectively removing the sacrificial material layers relative to the insulating layer and the memory opening fill structures; depositing a first tungsten layer in the lateral grooves using a first tungsten deposition process, in which a fluorine - containing tungsten precursor gas is used as a reactant; and depositing a second tungsten layer on the first tungsten layer in the lateral grooves using a second tungsten deposition process, in which a fluorine - free tungsten precursor gas is used as a reactant.

[0006] According to another aspect of the present disclosure, a memory device includes: an alternating stack of insulating layers and conductive layers, wherein each of the conductive layers includes: an outer first tungsten layer containing fluorine at a first average fluorine atom concentration; and an inner second tungsten layer embedded in the first tungsten layer and containing fluorine at a second average fluorine atom concentration that is less than 50% of the first average fluorine atom concentration; a memory opening extending vertically through the alternating stack; and a memory opening fill structure located in the memory opening and including: a corresponding vertical stack of memory elements; and a corresponding vertical semiconductor channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming an optional semiconductor device, an optional lower-level metal interconnect structure, a semiconductor material layer, and an alternating stack of insulating layers and sacrificial material layers, according to an embodiment of the present disclosure.

[0008] Figure 2 is a schematic vertical cross-sectional view of an exemplary structure after forming a stepped platform, according to an embodiment of the present disclosure.

[0009] Figure 3 is a schematic vertical cross-sectional view of an exemplary structure after forming a retro-stepped dielectric material portion, according to an embodiment of the present disclosure.

[0010] Figure 4A is a schematic vertical cross-sectional view of an exemplary structure after forming a memory opening and a support opening, according to an embodiment of the present disclosure.

[0011] Figure 4B is Figure 4A a top-down view of an exemplary structure. The vertical plane A-A' is Figure 4A the plane of the cross-section of

[0012] Figures 5A to 5F is a sequential schematic vertical cross-sectional view of a memory opening within an exemplary structure during formation of a memory opening fill structure, according to an embodiment of the present disclosure.

[0013] Figure 6 is a schematic vertical cross-sectional view of an exemplary structure after forming a memory opening fill structure and a support pillar structure, according to an embodiment of the present disclosure.

[0014] Figure 7A is a schematic vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer, a lateral isolation trench, and a source region, according to an embodiment of the present disclosure.

[0015] Figure 7B is Figure 7A a partial perspective top-down view of an exemplary structure of Figure 7A The vertical plane A-A' is the plane of the schematic vertical cross-section of

[0016] Figure 8 is a schematic vertical cross-section of an exemplary structure after forming a lateral groove according to an embodiment of the present disclosure.

[0017] Figures 9A to 9F and Figure 9H are sequential vertical cross-sections of regions of an exemplary structure around a memory opening filling structure during the formation of a conductive layer according to an embodiment of the present disclosure.

[0018] Figure 9G is along Figure 9F the horizontal plane G-G' of an exemplary structure.

[0019] Figure 10 is Figure 9H the distribution of atomic concentrations of an example embodiment of

[0020] Figure 11 is the distribution of atomic concentrations of fluorine of a comparative example.

[0021] Figure 12 is a schematic vertical cross-section of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0022] Figure 13A is a schematic vertical cross-section of an exemplary structure after forming a lateral isolation trench filling structure according to an embodiment of the present disclosure.

[0023] Figure 13B is Figure 13A a top-down view of an exemplary structure of Figure 13A The vertical plane A-A' is the plane of the schematic vertical cross-section of

[0024] Figure 14A is a schematic vertical cross-section of an exemplary structure after forming an additional contact via structure according to an embodiment of the present disclosure.

[0025] Figure 14B is Figure 14A a top-down view of an exemplary structure of Figure 14A The vertical plane A-A' is the plane of the schematic vertical cross-section of

[0026] Figure 14C is Figure 14A and Figure 14B an enlarged vertical cross-section of regions of an exemplary structure. Detailed Implementation Modes

[0027] As discussed above, embodiments of the present disclosure relate to three-dimensional memory devices including composite word lines including corresponding fluorine-free capping sub-layers and methods of forming the same. Various aspects of the three-dimensional memory devices are described below.

[0028] The accompanying drawings are not drawn to scale. In the case of showing a single instance of an element, multiple instances of the element may be replicated, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0029] Like reference numerals denote the same or similar elements. Unless otherwise indicated, elements having the same reference numerals are considered to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or between each other, the two elements are "separated" from each other or "separated" between each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0030] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a smaller extent than the extent of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure or between pairs of any horizontal planes thereat. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0031] As used herein, "semiconductor material" refers to an electrical conductivity in 1.0x 10 -6 S / cm to 1.0x10 5Materials in the range of S / cm. As used herein, "semiconductor material" refers to a material that has a conductivity in the range of 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm in the absence of electrical dopants, and that can produce a doped material having a conductivity in the range of 1.0 S / cm to 1.0 x 10 5 S / cm when appropriately doped with electrical dopants. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0 x 10 5 S / cm. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0 x 10 -6 S / cm.

[0032] As used herein, "heavily doped semiconductor material" refers to a semiconductor material that is doped with electrical dopants at a high enough atomic concentration to become a conductive material when formed as a crystalline material or when converted to a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., having a conductivity greater than 1.0 x 10 5 S / cm. A "doped semiconductor material" can be a heavily doped semiconductor material, or can be a semiconductor material that includes electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration that provides a conductivity in the range of 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semi-conductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are made under standard conditions.

[0033] Generally speaking, a semiconductor die or semiconductor package can include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). The same, concurrent operations can occur on each plane, but with some limitations. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest units that can be programmed, i.e., the smallest units on which a read operation can be performed.

[0034] Reference Figure 1 FIG. , shows an exemplary structure in accordance with an embodiment of the present disclosure. The exemplary structure includes a substrate 8, which can be a semiconductor substrate, an insulating substrate, a conductive substrate, or a combination thereof. The substrate 8 includes a substrate material layer 9, which may or may not be a semiconductor material layer. In one embodiment, the substrate 8 may include a semiconductor substrate substantially composed of a single crystal semiconductor material or a polycrystalline semiconductor material. In one embodiment, the substrate 8 can be a commercially available silicon wafer, on which a plurality of semiconductor die, such as a two-dimensional array of semiconductor die, can be subsequently formed. In this case, the substrate material layer 9 may include doped wells in the silicon wafer or an epitaxial silicon layer located on the silicon wafer. In the case where the substrate 8 includes a semiconductor substrate, the semiconductor device 620 may optionally be formed on top of the substrate 8. Generally speaking, the semiconductor device 620 may include any type of semiconductor device known in the art. In one embodiment, the semiconductor device 620 may include complementary metal oxide semiconductor (CMOS) field effect transistors of a peripheral circuit for controlling the operation of a three-dimensional memory device subsequently formed above it.

[0035] Optionally, a metal interconnect structure 680 embedded within a dielectric material layer 660 may be formed above the substrate 8. The metal interconnect structure 680 is also referred to as a lower level metal interconnect structure 680, and the dielectric material layer 660 is also referred to as a lower level dielectric material layer 660. In the presence of the semiconductor device 620, the lower level metal interconnect structure 680 may provide an electrical connection to the semiconductor device 620. In one embodiment, the metal interconnect structure 680 may include a metal pad 682, which can be used as a contact pad for a subsequently formed connection via structure. Alternatively, the formation of the semiconductor device 620, the metal interconnect structure 680, and the dielectric material layer 660 above the substrate 8 may be omitted. Instead, the semiconductor device 620 may be formed on a separate substrate and then bonded to the three-dimensional memory device.

[0036] In the presence of a lower-level dielectric material layer 660, a semiconductor material layer (e.g., a polysilicon layer) 10 may be formed over the lower-level dielectric material layer 660. The semiconductor material layer 10 may include a single semiconductor material layer or may include a vertical stack of multiple semiconductor material sub-layers. In one embodiment, the semiconductor material layer 10 may be doped with a first conductivity type, which may be p-type or n-type. In one embodiment, a source-level material layer in process may be formed in place of the semiconductor material layer 10. In such a case, the source-level material layer in process may include a vertical stack including a lower source semiconductor layer, a source-level sacrificial layer subsequently replaced with a source contact layer, and an upper source semiconductor layer. In the absence of the lower-level dielectric material layer 660, the semiconductor material layer 10 may be omitted. Although embodiments in which the semiconductor material layer 10 is employed are described, embodiments in which the semiconductor material layer is replaced with a source-level material layer in process or omitted are expressly contemplated herein.

[0037] An alternating stack of an insulating layer 32 and a spacer material layer may be formed over the semiconductor material layer 10. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In such a case, an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed over the semiconductor material layer 10. The insulating layer 32 includes an insulating material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride. The alternating stack (32, 42) may include multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in the range of 8 to 1,024 such as 32 to 256, but fewer and greater numbers of repetitions may also be employed. The topmost insulating layer in the insulating layer 32 is hereinafter referred to as the topmost insulating layer 32T. The bottommost insulating layer in the insulating layer 32 is hereinafter referred to as the bottommost insulating layer 32B.

[0038] Each insulating layer in the insulating layer 32 other than the topmost insulating layer 32 may have a thickness in the range of 20 nm to 100 nm such as 30 nm to 60 nm, but smaller and greater thicknesses may also be employed. Each sacrificial material layer in the sacrificial material layer 42 may have a thickness in the range of 20 nm to 100 nm such as 30 nm to 60 nm, but smaller and greater thicknesses may also be employed. In one embodiment, the topmost insulating layer 32 may have a thickness approximately half of the thickness of the other insulating layers 32.

[0039] The exemplary structure may include a memory array region 100 where a memory stack structure will be subsequently formed, and a contact region 300 where a stepped surface and a contact via structure will be subsequently formed.

[0040] Reference Figure 2 , a stepped surface is optionally formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within a volume, and portions of the alternating stacks (32, 42) are removed from the stepped cavity by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0041] The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes gradually according to the vertical distance from the top surface of the semiconductor material layer 10. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process. The first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the region vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including alternating multiple layers is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0042] Each sacrificial material layer 42 within the alternating stacks (32, 42) except for the topmost sacrificial material layer 42 extends laterally farther than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the platform region. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0043] Reference Figure 3, a reverse stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed, for example, by chemical mechanical planarization (CMP), from above the top surface of the topmost insulating layer 32T. The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the reverse stepped dielectric material portion 65. As used herein, a "reverse stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the top surface on which the element exists on the substrate. If silicon oxide is used for the reverse stepped dielectric material portion 65, the silicon oxide of the reverse stepped dielectric material portion 65 can be doped or undoped with dopants such as B, P, and / or F.

[0044] Optionally, the drain select level isolation structure 72 can be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 at the drain select level. For example, the drain select level isolation structure 72 can be formed by forming a drain select level lateral isolation trench and filling the drain select level lateral isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material can be removed from above the top surface of the topmost insulating layer 32T.

[0045] Reference Figure 4A and Figure 4B , a lithography material stack (not shown) including at least a photoresist layer can be formed over the topmost insulating layer 32T and the reverse stepped dielectric material portion 65 and can be lithographically patterned to form openings therein. These openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the contact region 300. The pattern in the lithography material stack can be transferred by at least one anisotropic etch using the patterned lithography material stack as an etch mask through the topmost insulating layer 32T or the reverse stepped dielectric material portion 65 and through the alternating stack (32, 42). The portion of the alternating stack (32, 42) underlying the openings in the patterned lithography material stack is etched to form memory openings 49 and support openings 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, a "support opening" refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings 49 are formed through the topmost insulating layer 32T and the entire alternating stack (32, 42) in the memory array region 100. The support openings 19 are formed through the reverse stepped dielectric material portion 65 and the portion of the alternating stack (32, 42) underlying the stepped surface in the contact region 300.

[0046] The memory opening 49 extends through the entire alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process for etching through the materials of the alternating stack (32, 42) can be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etches. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical or can be tapered. Subsequently, the patterned photoresist material stack can be removed, for example, by ashing.

[0047] The memory opening 49 and the support opening 19 can extend from the top surface of the alternating stack (32, 42) at least to a horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, an over-etch into the semiconductor material layer 10 can be optionally performed. In one embodiment, the recessed surface of the semiconductor material layer 10 can be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth can be, for example, in the range of 0 nm to 30 nm, but smaller and larger recess depths can also be employed. The over-etch is optional and can be omitted. If the over-etch is not performed, the bottom surfaces of the memory opening 49 and the support opening 19 can be coplanar with the topmost surface of the semiconductor material layer 10.

[0048] Each of the memory opening 49 and the support opening 19 can include sidewalls (or a sidewall) that extend substantially perpendicular to the topmost surface of the substrate 8. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the contact region 300.

[0049] Figure 5A To FIGS. 5H show a structural variation in the memory opening 49, which is Figure 4A and Figure 4B one memory opening among the memory openings 49 in the exemplary structure of. The same structural variation occurs simultaneously in each memory opening and each support opening 19 in the other memory openings 49.

[0050] Reference Figure 5A shows Figure 4A and Figure 4BMemory opening 49 in the exemplary device structure. The memory opening 49 extends through the alternating stack (32, 42) and optionally into the upper portion of the semiconductor material layer 10. In this processing step, each support opening 19 may extend through the reverse stepped dielectric material portion 65, a subset of the layers in the alternating stack (32, 42), and optionally into the upper portion of the semiconductor material layer 10. The recess depth of the bottom surface of each memory opening relative to the top surface of the semiconductor material layer 10 may be in the range of 0 nm to 30 nm, although larger recess depths may also be employed. Optionally, lateral grooves (not shown) may be formed by partially laterally recessing the sacrificial material layer 42, for example, by isotropic etching.

[0051] An optional pedestal channel portion 11 (which may be an epitaxial pedestal) may be formed, for example, by a selective semiconductor deposition process at the bottom portion of each memory opening 49 and each support opening 19. In one embodiment, the pedestal channel portion 11 may be doped with an electrical dopant of the same first conductivity type as the semiconductor material layer 10. In one embodiment, the top surface of each pedestal channel portion 11 may be formed below the horizontal plane including the top surface of the bottommost insulating layer 32B. The pedestal channel portion 11 may be part of a transistor channel. A memory cavity 49' exists in the unfilled portion of the memory opening 49 above the pedestal channel portion 11. If the semiconductor material layer 10 includes single-crystal semiconductor material, the pedestal channel portion 11 may include single-crystal semiconductor material epitaxially aligned with the single-crystal semiconductor material of the semiconductor material layer 10. In one embodiment, the pedestal channel portion 11 may include single-crystalline silicon.

[0052] Reference Figure 5B , a stack of layers including a barrier dielectric layer 52, a memory material layer 54, and a dielectric liner layer 56 may be deposited in each memory opening 49. The stack of layers is referred to herein as the memory film 50.

[0053] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than that of silicon nitride. Alternatively or additionally, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. In such a case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method such as low-pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be employed.

[0054] The memory material layer 54 may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of the presence or absence of charge, the direction of ferroelectric polarization, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or a patterned discrete portion of a charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the memory material layer 54 may include a continuous layer or a patterned discrete portion of a conductive material (such as doped polysilicon or a metal material), which is patterned into a plurality of electrically isolated portions (e.g., floating gates) by forming, for example, into a sacrificial material layer 42 within a lateral groove. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer. Generally speaking, the memory material layer 54 may include a vertical stack of memory elements at the level of the sacrificial material layer 42. For example, the vertical stack of memory elements may be embodied as an annular portion of the memory material layer 54 at the level of the sacrificial material layer 42.

[0055] Optional dielectric liner 56 (if present) includes a dielectric liner material. In one embodiment, dielectric liner 56 may include a tunneling dielectric layer through which charge tunneling may be performed under suitable electrical biasing conditions. Charge tunneling may be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. Dielectric liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, dielectric liner 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, dielectric liner 56 may include a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of dielectric liner 56 may be in the range of 2 nm to 20 nm, although smaller or larger thicknesses may also be employed. Optionally, a sacrificial capping material layer 601 may be formed over memory film 50.

[0056] Reference Figure 5C , at least one anisotropic etching process is employed to anisotropically etch, in sequence, optional sacrificial capping material layer 601, dielectric liner 56, memory material layer 54, and barrier dielectric layer 52. Sacrificial capping material layer 601, dielectric liner 56, memory material layer 54, and the portions of barrier dielectric layer 52 located above the top surface of topmost insulating layer 32T may be removed by at least one anisotropic etching process. Additionally, the horizontal portions of sacrificial capping material layer 601, dielectric liner 56, memory material layer 54, and barrier dielectric layer 52 located at the bottom of each memory cavity 49' may be removed to form openings in their remaining portions. Each of sacrificial capping material layer, dielectric liner 56, memory material layer 54, and barrier dielectric layer 52 may be etched by a corresponding anisotropic etching process employing a corresponding etching chemical, which corresponding etching chemical may be the same or different for the various material layers.

[0057] Each remaining portion of the sacrificial capping material layer may have a tubular configuration. The surface of the base channel portion 11 (or the surface of the semiconductor material layer 10 in the case where the base channel portion 11 is not employed) may be physically exposed under the opening through the sacrificial capping material layer 601, the dielectric liner 56, the memory material layer 54, and the dielectric metal oxide barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' may be vertically recessed such that the recessed semiconductor surface under the memory cavity 49' is vertically offset by a recess distance from the topmost surface of the base channel portion 11 (or from the semiconductor material layer 10 in the case where the base channel portion 11 is not employed). In one embodiment, the sacrificial capping material layer, the dielectric liner 56, the memory material layer 54, and the barrier dielectric layer 52 may have vertically coincident sidewalls. The sacrificial capping material layer may then be selectively removed relative to the material of the dielectric liner 56. In the case where the sacrificial capping material layer comprises amorphous silicon, a wet etching process employing hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to remove the sacrificial capping material layer. Alternatively, if the sacrificial capping material layer comprises a semiconductor material, the sacrificial capping material layer may remain in the final device.

[0058] Reference Figure 5D , the semiconductor channel layer 60L may be directly deposited on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 10 if the base channel portion 11 is omitted, and directly on the memory film 50. The semiconductor channel layer 60L comprises a semiconductor material such as at least one elemental semiconductor material, at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may have a doping of a first conductivity type that is the same as the conductivity type of the semiconductor material layer 10 and the base channel portion 11. The semiconductor channel layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be employed. The semiconductor channel layer 60L may partially fill the memory cavity 49' in each memory opening, or may completely fill the cavity in each memory opening.

[0059] Reference Figure 5E, an inter-core dielectric layer may be deposited to fill any remaining portion of the memory cavity 49' within each memory opening 49. The inter-core dielectric layer includes a dielectric material, such as silicon oxide or organosilicate glass. The inter-core dielectric layer may be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating.

[0060] The horizontal portions of the inter-core dielectric layer may be removed, for example, by a recess etching process such that each remaining portion of the inter-core dielectric layer is located within a corresponding memory opening 49 and has a corresponding top surface below the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the inter-core dielectric layer constitutes an inter-core dielectric 62.

[0061] Reference Figure 5F , a doped semiconductor material having a second conductivity type may be deposited over each recessed area above the inter-core dielectric 62. The deposited semiconductor material may be doped with a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be in the range of 5.0x10 18 / cm 3 to 2.0x 10 21 / cm 3 , but smaller or larger dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0062] The excess portions of the deposited doped semiconductor material having a second conductivity type and the horizontal portions of the semiconductor channel layer 60L may be removed from above the horizontal plane of the top surface including the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etching process. Each remaining portion of the doped semiconductor material having a second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (which is doped with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0063] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel 60, a tunneling dielectric layer, a plurality of memory elements including a portion of the memory material layer 54, and optionally a barrier dielectric layer 52. Each combination of the pedestal channel portion 11 (if present), the memory stack structure 55 within the memory opening 49, the inter-core dielectric 62, and the drain region 63 is referred to herein as a memory opening fill structure 58. Each combination of the pedestal channel portion 11 (if present), the memory film 50 within each support opening 19, the vertical semiconductor channel 60, the inter-core dielectric 62, and the drain region 63 fills a corresponding support opening 19 and constitutes a support pillar structure.

[0064] Reference Figure 6 shows an exemplary structure after forming a memory opening fill structure 58 and a support pillar structure 20 in a memory opening 49 and a support opening 19, respectively. Examples of the memory opening fill structure 58 can be formed in each memory opening 49 of the structure of Figure 4A and Figure 4B Each support opening 19 of the structure of the support pillar structure 20 can be formed in Figure 4A and Figure 4B .

[0065] Although the described embodiments employ a configuration of Figure 5F and Figure 6 for the memory stack structure 55, an alternative memory stack structure including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channels 60 can be used instead.

[0066] Reference Figure 7A and Figure 7B , a contact level dielectric layer 80 can be formed over the alternating stack (32, 42) and over the memory opening fill structure 58 and the support pillar structure 20. The contact level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact level dielectric layer 80 can include silicon oxide. The contact level dielectric layer 80 can have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be employed.

[0067] A photoresist layer (not shown) can be applied over the contact level dielectric layer 80 and patterned lithographically to form openings in the regions between the clusters of the memory stack structure 55. Anisotropic etching can be employed to transfer the pattern in the photoresist layer through the contact level dielectric layer 80, the alternating stack (32, 42), and / or the reverse stepped dielectric material portion 65 to form a lateral isolation trench 79 that extends at least vertically from the top surface of the contact level dielectric layer 80 to the top surface of the semiconductor material layer 10 and extends laterally across the memory array region 100 and the contact region 300.

[0068] In one embodiment, the lateral isolation trenches 79 may extend laterally along a first horizontal direction (e.g., word line direction) hd1 and may be laterally spaced from each other along a second horizontal direction (e.g., bit line direction) hd2 perpendicular to the first horizontal direction hd1. The memory opening fill structures 58 may be arranged in rows extending along the first horizontal direction hd1. The drain select level isolation structures 72 may extend laterally along the first horizontal direction hd1. Each lateral isolation trench 79 may have a uniform width that remains constant along the length direction (i.e., along the first horizontal direction hd1). The various drain select level isolation structures 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, and this vertical cross-sectional profile remains unchanged with translation along the first horizontal direction hd1. Multiple rows of memory opening fill structures may be located between adjacent pairs of lateral isolation trenches 79 and the drain select level isolation structures 72, or between adjacent pairs of drain select level isolation structures 72. In one embodiment, the lateral isolation trenches 79 may include source contact openings in which source contact via structures may be subsequently formed. For example, the photoresist layer may be removed by ashing. Generally speaking, the lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the contact level dielectric layer 80 and the alternating stack (32, 42). The alternating stack (32, 42) is divided into a plurality of alternating stacks (32, 42) that are laterally spaced from each other along the second horizontal direction hd2 by the lateral isolation trenches 79. A layer stack (32, 42, 80) is formed, and each layer stack in this layer stack includes corresponding patterned portions of the contact level dielectric layer 80 and corresponding patterned portions of the alternating stack (32, 42) that are formed in the processing steps as in Figure 1 and are laterally spaced from each other by the lateral isolation trenches 79.

[0069] Optionally, dopants of a second conductivity type may be implanted into the physically exposed surface portion of the semiconductor material layer 10 at the bottom of the lateral isolation trenches 79 through an ion implantation process. Optional source regions 61 may be formed at the surface portion of the semiconductor material layer 10 below each lateral isolation trench 79. Due to the spread of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during the subsequent activation annealing process, each source region 61 may have a lateral extent larger than the lateral extent of the overlying lateral isolation trench 79. Alternatively, the source regions 61 in the semiconductor material layer 10 may be replaced by horizontal source lines (e.g., direct strip contacts) that contact the sidewalls of the vertical semiconductor channels 60, or by source layers (e.g., top source contacts) formed on the bottom tips of the vertical semiconductor channels 60 after removing the substrate 8 and any layers between the substrate and the vertical semiconductor channels 60.

[0070] The upper portion of the semiconductor material layer 10 extending between the source region 61 and the plurality of pedestal channel portions 11 constitutes an optional horizontal semiconductor channel 59 for the plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to the plurality of vertical semiconductor channels 60 through the respective pedestal channel portions 11. Each horizontal semiconductor channel 59 contacts the source region 61 and the plurality of pedestal channel portions 11.

[0071] Reference Figure 8 and Figure 9A , an etchant that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 can be introduced into the lateral isolation trench 79. A lateral groove 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 can be selective with respect to the first material of the insulating layer 32, the material of the reverse stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost layer material of the memory film 50. In one embodiment, the sacrificial material layer 42 can include silicon nitride, and the materials of the insulating layer 32 and the reverse stepped dielectric material portion 65 can be silicon oxide.

[0072] The etching process for selectively removing the second material relative to the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a gas phase (dry) etching process in which the etchant is introduced into the lateral isolation trench 79 in a gas phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath including phosphoric acid, and the wet etching process selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. When the lateral groove 43 is present in the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the reverse stepped dielectric material portion 65, and the memory stack structure 55 provide structural support.

[0073] Each lateral groove 43 can be a laterally extending cavity having a lateral dimension larger than the vertical extent of the cavity. In other words, the lateral dimension of each lateral groove 43 can be greater than the height of the lateral groove 43. A plurality of lateral grooves 43 can be formed in the volume from which the second material of the sacrificial material layer 42 is removed. Compared with the lateral groove 43, the memory opening 49 in which the memory stack structure 55 is formed is referred to herein as a front side opening or a front side cavity. In one embodiment, the memory array region 100 includes an array of three-dimensional NAND strings having a plurality of device levels located above the semiconductor material layer 10. In this case, each lateral groove 43 can define a space for receiving a corresponding word line or select gate line of the array of three-dimensional NAND strings.

[0074] Each of the plurality of lateral grooves 43 may extend substantially parallel to the top surface of the semiconductor material layer 10. The lateral grooves 43 may be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral groove 43 may always have a consistent height. Generally, the lateral grooves 43 may be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32.

[0075] Reference Figure 9B , an external blocking dielectric layer 44 may optionally be formed. The external blocking dielectric layer 44 (if present) includes a dielectric material that serves as a control gate electrolyte for a control gate (i.e., a portion of a word line) to be subsequently formed in the lateral groove 43. The external blocking dielectric layer 44 is optional in the case where the blocking dielectric layer 52 is present within each memory opening 49. In the case where the blocking dielectric layer 52 is omitted, the external blocking dielectric layer 44 may be present.

[0076] The external blocking dielectric layer 44 may be formed in the lateral grooves 43 and on the sidewalls of the lateral isolation trenches 79. The external blocking dielectric layer 44 may be formed directly on the horizontal surface of the insulating layer 32 and on the sidewalls of the memory stack structure 55 within the lateral grooves 43. In one embodiment, the external blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition (ALD). The external blocking dielectric layer 44 may consist essentially of aluminum oxide. The thickness of the external blocking dielectric layer 44 may be in the range of 1 nm to 15 nm, such as 2 nm to 6 nm, although smaller and larger thicknesses may also be employed.

[0077] The dielectric material of the external blocking dielectric layer 44 may be a dielectric metal oxide, such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, an oxide of aluminum, at least one transition metal element, and / or a combination of at least one lanthanide element. Alternatively or additionally, the external blocking dielectric layer 44 may include a layer of silicon oxide. A lateral isolation cavity 79' exists within the portion of each lateral isolation trench 79 that is not filled with the external blocking dielectric layer 44.

[0078] Reference Figure 9C, Optionally, a conductive metal barrier liner 46A can be deposited in the first volume of the lateral groove 43. The conductive metal barrier liner 46A includes a conductive metal material that can act as a diffusion barrier layer and / or an adhesion promoting layer for the tungsten fill material to be subsequently deposited. The conductive metal barrier liner 46A can include a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof; a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof; or a conductive metal carbonitride material, such as WCN, TiCN, TaCN, or a stack thereof. In one embodiment, the conductive metal barrier liner 46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the conductive metal barrier liner 46A can be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller or larger thicknesses can also be employed. In one embodiment, the conductive metal barrier liner 46A can consist essentially of a conductive metal nitride such as TiN. The conductive metal barrier liner 46A is in direct contact with the external barrier dielectric layer 44 (if present) or the internal barrier dielectric layer 52 (if the external barrier dielectric layer 44 is omitted).

[0079] Reference Figure 9D , A non-metallic nucleation layer 46N can be formed on the physically exposed surface of the conductive metal barrier liner 46A by performing an immersion process that induces the adsorption of non-metallic atoms that can subsequently be used to induce the nucleation of tungsten. For example, an exemplary structure can be placed in a vacuum chamber and immersed in a low-pressure environment that includes a silicon or borohydride gas such as silane (SiH4) or diborane (B2H6) as the main component gas. Silicon atoms or boron atoms can be adsorbed onto the physically exposed surface of the conductive metal barrier liner 46A to form the non-metallic nucleation layer 46N. The non-metallic nucleation layer 46N includes a monolayer or sub-monolayer of silicon atoms or boron atoms. The surface coverage of the atoms within the non-metallic nucleation layer 46N with respect to the surface of the conductive metal barrier liner 46A can be in the range of 1% to 100%, such as 3% to 30%, but lower surface coverages can also be employed. The surface coverage refers to the percentage of the area covered by the atoms of the overlying layer relative to the area of the underlying layer. Alternatively, the non-metallic nucleation layer 46N can be omitted.

[0080] Reference Figure 9E , A first tungsten layer 461 can be deposited on the conductive metal barrier liner 46A in the second volume of the lateral groove 43 using a first tungsten deposition process. According to one aspect of the present disclosure, a fluorine-containing tungsten precursor gas is employed as a reactant in the first tungsten deposition process (such as a CVD or ALD process). For example, tungsten hexafluoride (WF6) is employed as a reactant in the first tungsten deposition process. The thickness of the first tungsten layer 461 is in the range of 10 nm to 20 nm.

[0081] In one embodiment, a surface portion of the first tungsten layer 461 proximate to the interface with the conductive metal barrier liner 46A (if present) or the barrier electrolyte (e.g., the external barrier electrolyte 44 (if present) or alternatively the internal barrier electrolyte 52 if the barrier liner 46 is omitted) includes boron or silicon at a peak atomic concentration in the range of 1 ppm to 10,000 ppm. Accordingly, the non-metallic nucleation layer 46N is incorporated into the first tungsten layer 461. After the formation of the first tungsten layer 461, there is an unfilled volume within each of the lateral grooves 43.

[0082] Although a deposition process using a fluorine-free precursor gas can provide a tungsten layer free of fluorine, it has been observed that such a tungsten layer has an average grain size (about 1 nm to 2 nm) smaller than the average grain size (about 3 nm to 10 nm) in a tungsten layer formed using a fluorine-containing precursor gas such as tungsten hexafluoride. Accordingly, the first tungsten layer 461 can provide a lower resistivity than a tungsten layer of the same thickness formed using a fluorine-free tungsten precursor gas.

[0083] Since a fluorine-containing precursor gas such as tungsten hexafluoride is used during the deposition process for forming the first tungsten layer 461, the first tungsten layer 461 includes fluorine atoms at an average atomic concentration in the range of 1 x 10 21 / cm 3 to 5 x 10 21 / cm 3 .

[0084] In one embodiment, an air-break process may optionally be performed to physically expose the outer surface of the first tungsten layer 461 to an environment having a total pressure of about 1 atmosphere. The environment may include air or another oxygen-containing environment. The air-break process oxidizes the exposed surface of the first tungsten layer 461 to form tungsten oxide and / or tungsten oxyfluoride (e.g., WO2F2, etc.). An inert environment annealing process may optionally be performed to remove tungsten oxide and / or tungsten oxyfluoride from the surface of the first tungsten layer 461 and / or to remove fluorine from the third volume of the groove 43 via the lateral isolation trench 79. For example, the exemplary structure may be placed in an argon-containing environment or another inert environment and annealed to remove fluorine atoms in gaseous form or in the form of fluorine-containing volatile compounds such as WO2F2. The elevated temperature of the argon annealing process may be in the range of 350 degrees Celsius to 500 degrees Celsius.

[0085] Reference Figure 9F and Figure 9G , a second tungsten deposition process may be employed to deposit a second tungsten layer 462 on the first tungsten layer 461 within the third volume of the lateral groove 43. The thickness of the second tungsten layer 462 is in the range of 5 nm to 10 nm.

[0086] According to one aspect of the present disclosure, a fluorine-free tungsten precursor gas is used as a reactant during a second tungsten deposition process. For example, tungsten pentachloride (WCl5), ditungsten dioxide (WO2Cl2) (also known as tungsten trichloride acid), or tungsten(VI) oxychloride (WOCl4) can be used as reactants during the second tungsten deposition process. In one embodiment, the second tungsten deposition process includes an ALD process that includes multiple repetitions of a unit process sequence. The unit process sequence includes: (1) a reactant soak step in which a fluorine-free tungsten precursor gas (such as WCl5, WO2Cl2, or WOCl4) and a purge gas (such as nitrogen gas) are concurrently supplied to the lateral groove 43; (2) a first purge step; (3) a reduction step in which hydrogen is supplied to the lateral groove 43; and (4) a second purge step. In one embodiment, a purge gas (such as nitrogen gas) can flow into the processing chamber during the four steps of the entire unit process sequence, and the first and second purge steps include nitrogen purge steps. Thus, the purge gas can be the only gas flowing into the processing chamber during the first and second purge steps. In one embodiment, during the reduction step, hydrogen and the purge gas can flow into the processing chamber concurrently. The second tungsten deposition process can be carried out at a temperature of 375 degrees Celsius to 500 degrees Celsius.

[0087] The duration of the second tungsten deposition process can be selected such that the second tungsten layer 462 encapsulates a plurality of encapsulated cavities (i.e., air gaps) 469 that do not contain any solid-phase material within the volume of a subset of the lateral grooves 43 located away from the respective lateral isolation trenches 79 (e.g., in the middle portion of the space between adjacent pairs of the respective lateral isolation trenches 79). Generally, the second tungsten layer 462 can be used to fill the gap between adjacent pairs of memory opening fill structures 58 located adjacent to the lateral isolation trenches 79 to form a seam 46S between two growth surfaces of the second tungsten layer 462. The unfilled remaining volume of the lateral groove 46 laterally surrounded by a corresponding set of adjacent memory opening fill structures 58 located away from the respective lateral isolation trenches 79 constitutes the encapsulated cavity 469. Each of the plurality of encapsulated cavities 469 can be laterally surrounded by a corresponding subset of the memory opening fill structures 58.

[0088] Generally, when forming the encapsulated cavity 469, each seam 46S where two surfaces of the second tungsten layer 462 contact each other can be connected to at least one encapsulated cavity 469. Each of the encapsulated cavities 469 can be encapsulated by the second tungsten layer 462 and can be free of any solid-phase material. Each of the encapsulated cavities 469 can be laterally surrounded by a corresponding subset of the memory opening fill structures 58, and the corresponding subset can be a set of two adjacent memory opening fill structures 58. In one embodiment, all surfaces of each seam 46S can be surfaces of the second tungsten layer 462.

[0089] In one embodiment, the second tungsten layer 462 is free of silicon atoms or includes residual silicon atoms at an average atomic concentration of less than 1 ppm, such as less than 0.1 ppm and / or less than 0.01 ppm (due to diffusion through the first tungsten layer 461). In one embodiment, the second tungsten layer 462 is free of boron atoms or includes residual boron atoms at an average atomic concentration of less than 1 ppm, such as less than 0.1 ppm and / or less than 0.01 ppm (due to diffusion through the first tungsten layer 461).

[0090] Since a fluorine-free precursor gas (such as tungsten hexafluoride) is used during the deposition process for forming the second tungsten layer 462, the second tungsten layer 462 includes fluorine atoms at an average atomic concentration lower than the average fluorine atom concentration in the first tungsten layer 461. In such a case, all fluorine atoms present in the second tungsten layer 462 can be attributed to the diffusion of fluorine atoms from the first tungsten layer 461 into the second tungsten layer 462. In one embodiment, the second tungsten layer 462 may include fluorine atoms at an average atomic concentration in the range of less than 2 x 10 21 / cm 3 , at 1 x 10 19 / cm 3 to 1 x 10 21 / cm 3 such as 5 x 10 19 / cm 3 to 5 x 10 20 / cm 3 of the second tungsten layer 462 is mainly determined by the average grain size of the underlying tungsten layer (i.e., the average grain size of the first tungsten layer 461). Thus, although a fluorine-free precursor gas is used during the second tungsten deposition process, the average grain size of the second tungsten layer 462 can still be relatively large. In other words, using a fluorine-free tungsten precursor gas during the second tungsten deposition process does not result in a significant reduction in the average grain size of the second tungsten layer 462. Therefore, the average grain size of the second tungsten layer 462 can be maintained at approximately the same value as the average grain size of the first tungsten layer 461 (e.g., within 10%), while reducing the average fluorine atom concentration in the second tungsten layer 462.

[0091] The average grain size

[0092] Reference Figure 9H, an etch-back process may be performed to remove portions of the second tungsten layer 462, the first tungsten layer 461, and the conductive metal barrier liner 46A that are located in the lateral isolation trench 79 or above the contact-level dielectric layer 80. The etch-back process may include an isotropic etching process and / or an anisotropic etching process, and removes portions of the second tungsten layer 462, the first tungsten layer 461, and the conductive metal barrier liner 46A that are outside the volume of the lateral recess 43. The etch-back process may be selective with respect to the external barrier dielectric layer 44. Each remaining portion of the second tungsten layer 462, the first tungsten layer 461, and the conductive metal barrier liner 46A that fills the lateral recess 43 constitutes a conductive layer 46. The outer sidewalls of each conductive layer 46 may be vertically aligned with the sidewalls of the external barrier dielectric layer 44. Alternatively, in the case of removing the vertical extension of the external barrier dielectric layer 44 around the lateral isolation trench 79 or completely omitting the layer 44, the outer sidewalls of each conductive layer 46 may be vertically aligned with the sidewalls of the lateral isolation trench 79.

[0093] An alternating stack (32, 46) of insulating layers 32 and conductive layers 46 may be formed. Each conductive layer in the conductive layer 46 may include a conductive metal barrier liner 46A; a first tungsten layer 461 that contacts the conductive metal barrier liner 46A and contains fluorine at a first average fluorine atom concentration; and a second tungsten layer 462 that contacts the first tungsten layer 461 and contains fluorine at a second average fluorine atom concentration that is less than 50% of the first average fluorine atom concentration. In one embodiment, the two horizontal surfaces of the second tungsten layer 462 may contact each other at the horizontally extending seam section (i.e., the horizontally extending portion of the seam 46S) of the corresponding conductive layer 46.

[0094] Figure 10 is the distribution of the atomic concentration of fluorine along the Figure 9H vertical line V of the embodiment. The region having a first average fluorine atom concentration aac1 of about 1 x 10 21 / cm 3 to 3 x 10 21 / cm 3 corresponds to the region of the upper and lower boundaries of the first tungsten layer 461 having a conductive metal barrier liner 46A (if present) or a barrier dielectric layer (44 or 52) (if the liner 46A is absent). The region having a second average fluorine atom concentration aac2 of about 4 x 10 20 / cm 3 to 8 x 10 20 / cm 3 corresponds to the region of the second tungsten layer 462. For a thickness between 10 nm and 20 nm, the conductive layer 46 including the TiN liner 46A and the composite tungsten layer (461, 462) may have a resistivity of less than 40 microohm-cm, such as between 30 microohm-cm and 39 microohm-cm.

[0095] Figure 11 is the distribution of the atomic concentration of fluorine along the vertical line V in a comparative example in which the second tungsten layer 462 is omitted and the entire tungsten portion of the conductive layer 46 consists of a first tungsten layer 461 deposited using tungsten hexafluoride. Having about 1x10 21 / cm 3 to 4x10 21 / cm 3 The region of the first average fluorine atomic concentration aac1 corresponds to the upper and lower boundaries of the first tungsten layer 461 having a conductive metal barrier liner 46A (if present) or a barrier dielectric layer (44 or 52) (if the liner 46A is absent). The third average fluorine atomic concentration aac3 is 8x10 20 / cm 3 to 1x10 21 / cm 3 The region around corresponds to the central portion of the first tungsten layer 461 when viewed from the vertical direction. The high fluorine atomic concentration acc3 of about 8x10 20 / cm 3 to 1x10 21 / cm 3 at the middle part of the first tungsten layer 461 is considered to be caused by the accumulation of fluorine in the encapsulation cavity 469. Having about 4x10 20 / cm 3 to 8x10 20 / cm 3 The region of the second average fluorine atomic concentration aac2 corresponds to the portion of the first tungsten layer 461 between the middle portion of the first tungsten layer and the upper and lower boundary portions of the first tungsten layer. Therefore, compared with the Figure 10 example embodiment of Figure 11 the comparative example includes a higher fluorine concentration in the middle of the conductive layer 46. Generally speaking, compared with the comparative example, the example embodiment provides at least a 50% reduction in the concentration of fluorine and / or fluorine compounds in the memory device. For a thickness between 10 nm and 25 nm, the conductive layer 46 including the TiN liner 46A and the fluorine-containing tungsten layer 461 may also have a resistivity of less than 40 microohm-centimeters, such as between 20 microohm-centimeters and 39 microohm-centimeters. Therefore, the resistivity of the conductive layer of the example embodiment is similar to that of the comparative example.

[0096] Referring to Figure 12 shows a first exemplary structure after forming the conductive layer 46 at the processing step of Figure 9H For clarity, the external barrier dielectric layer 44 is not explicitly shown.

[0097] Referring to Figure 13A andFigure 13B , an insulating material layer can be formed in the lateral isolation trenches 79 and on the contact level dielectric layer 80 through a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes insulating materials such as silicon oxide, silicon nitride, dielectric metal oxides, organosilicate glass, or combinations thereof. In one embodiment, the insulating material layer may include silicon oxide. For example, the insulating material layer can be formed by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range of 1.5 nm to 60 nm, but smaller or larger thicknesses can also be employed.

[0098] Anisotropic etching is performed to remove the horizontal portions of the insulating material layer from above the contact level dielectric layer 80 and from the bottoms of each of the lateral isolation trenches 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A lateral isolation cavity exists within the volume surrounded by each insulating spacer 74.

[0099] The top surface of the source region 61 can be physically exposed at the bottom of each of the lateral isolation trenches 79. Each source region 61 is formed in the upper portion of the semiconductor material layer 10. The semiconductor channels (59, 11, 60) extend between each source region 61 and a corresponding set of drain regions 63. The semiconductor channels (59, 11, 60) include the vertical semiconductor channel 60 of the memory stack structure 55.

[0100] A source contact via structure 76 can be formed within each lateral isolation cavity. Each contact via structure 76 can fill the corresponding lateral isolation cavity. The source contact via structure 76 can be formed by depositing at least one conductive material in the remaining unfilled volume of the lateral isolation trench 79 (i.e., the lateral isolation cavity). For example, the at least one conductive material can include a conductive liner (not explicitly shown) and a conductive fill material portion (not explicitly shown). The conductive liner can include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive liner can be in the range of 3 nm to 30 nm, but smaller or larger thicknesses can also be employed. The conductive fill material portion can include a metal or a metal alloy. For example, the conductive fill material portion can include W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks.

[0101] The contact-level dielectric layer 80 overlying the alternating stack (32, 46) can be used as a stop layer to planarize at least one conductive material. If a chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 80 can be used as a CMP stop layer. Each remaining continuous portion of at least one conductive material in the lateral isolation trench 79 constitutes a source contact via structure 76. Each source contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of a corresponding source region 61. Generally, the source contact via structures 76 can be formed within each of the lateral isolation trenches 79 by depositing and planarizing at least one conductive material in the volume of the lateral isolation trench 79 not filled with the insulating spacer 74 after the insulating spacers 74 are formed. Each continuous combination of the insulating spacer 74 and the source contact via structure 76 fills a corresponding lateral isolation trench 79 and is herein referred to as a lateral isolation trench fill structure (74, 76).

[0102] Alternatively, the insulating material layer described above can be formed in the lateral isolation trenches 79 to completely fill the entire volume of the lateral isolation trenches 79 and can consist essentially of at least one dielectric material. In this alternative embodiment, the source regions 61 and the lateral isolation trench via structures 76 can be omitted, and each lateral isolation trench fill structure can consist of at least one insulating material portion.

[0103] Generally, each lateral isolation trench fill structure (74, 76) extends vertically from the bottommost layer of the alternating stack (32, 46) to the topmost layer of the alternating stack (32, 46) and includes a dielectric sidewall surface adjacent to a horizontally extending seam section of a seam 46S of the conductive layer 46. In one embodiment, the dielectric sidewall surfaces of the lateral isolation trench fill structures (74, 76) contact each conductive layer 46 within the alternating stack (32, 46).

[0104] Reference Figures 14A to 14C , additional contact via structures (88, 86, 386) can be formed through the contact-level dielectric layer 80 and optionally through the reverse stepped dielectric material portion 65.

[0105] For example, the drain contact via structure 88 may be formed through the contact level dielectric layer 80 over each drain region 63. The layer contact via structure 86 may be formed through the contact level dielectric layer 80 and through the reverse stepped dielectric material portion 65 over the conductive layer 46. The optional through-memory-level connection via structure 386 may be formed directly over the respective metal pad 682 through the reverse stepped dielectric material portion 65 and through the semiconductor material layer 10. The insulating spacer 384 may be formed around each through-memory-level connection via structure 386 to electrically isolate the through-memory-level connection via structure 386 from the semiconductor material layer 10. Then, a bit line (not shown) is formed in electrical contact with the drain contact via structure 88.

[0106] Referring to all the figures and in accordance with various embodiments of the present disclosure, a memory device includes an alternating stack of an insulating layer 32 and a conductive layer 46, wherein each conductive layer in the conductive layer 46 includes: an outer first tungsten layer 461 that contains fluorine at a first average fluorine atom concentration; and an inner second tungsten layer 462 that is embedded in the first tungsten layer and contains fluorine at a second average fluorine atom concentration that is less than 50% of the first average fluorine atom concentration; a memory opening 49 that vertically extends through the alternating stack (32, 46); and a memory opening fill structure 58 that is located in the memory opening 49 and includes: a respective vertical stack of memory elements (e.g., portions of the memory film 50); and respective vertical semiconductor channels 60.

[0107] In one embodiment, each conductive layer in the conductive layer 46 further includes a conductive metal barrier liner 46A, and the first tungsten layer 461 is in contact with the conductive metal barrier liner 46A. In one embodiment, a surface portion of the first tungsten layer 461 proximate to the interface with the conductive metal barrier liner 46A includes an element selected from boron and silicon at a peak atomic concentration in the range of 1 ppm to 10,000 ppm; and the second tungsten layer 462 does not contain boron and silicon atoms or includes boron atoms or silicon atoms at an average atomic concentration of less than 1 ppm.

[0108] In one embodiment, the first tungsten layer 461 contains a peak fluorine concentration of at least 1x10 21 cm -3 in an outer portion proximate to the interface with the conductive metal barrier liner 46A, and contains a steady fluorine concentration of less than 1x10 21 cm -3 in an inner portion proximate to the interface with the second tungsten layer 462; and the second tungsten layer has a steady fluorine concentration of less than 1x10 21 cm -3

[0109] In one embodiment, the second tungsten layer 462 includes a horizontally extending seam 46S. In one embodiment, the lateral isolation trench fill structures (74, 76) extend vertically from the bottommost layer of the alternating stack to the topmost layer of the alternating stack and include dielectric sidewall surfaces adjacent to the horizontally extending seam 46S. In one embodiment, the dielectric sidewall surfaces of the lateral isolation trench fill structures contact each conductive layer 46 within the alternating stack (32, 46). In one embodiment, the second tungsten layer 462 encapsulates an encapsulation cavity 469 that contains no solid phase material and is laterally surrounded by a subset of the memory opening fill structures 58.

[0110] In one embodiment, the first average fluorine concentration is at least 1x10 21 cm -3 ; and the second average fluorine concentration is less than 1x10 21 cm -3 . For example, the first average fluorine concentration ranges from 1x10 21 cm -3 to 5x10 21 cm -3 ; and the second average fluorine concentration ranges from 4x10 20 cm -3 to 8x10 20 cm -3 .

[0111] Various embodiments of the present disclosure provide a composite tungsten layer having a large average grain size comparable to the average grain size of a comparative exemplary tungsten layer formed using only a fluorine-containing tungsten precursor gas, while providing a reduced average atomic fluorine concentration in the tungsten layer as compared to the comparative exemplary tungsten layer. Thus, various embodiments of the present disclosure provide a tungsten layer that contains less fluorine than a tungsten layer formed entirely using tungsten hexafluoride while having comparable resistivity (e.g., within 25% of each other). Additionally, due to the higher cost of the fluorine-free tungsten precursors and the lower grain size obtained by depositing tungsten layers using such precursors, various embodiments of the present disclosure provide a composite tungsten layer having a lower resistivity (e.g., at least 30% lower) than a tungsten layer formed entirely using a fluorine-free tungsten precursor.

[0112] Although the foregoing relates to specific preferred embodiments, it is to be understood that the disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the word "comprising" or "including" encompasses all embodiments in which the word "consisting essentially of" or the word "consisting of" replaces the word "comprising" or "including". Where embodiments employing a specific structure and / or configuration are shown in the disclosure, it is to be understood that the disclosure can be practiced using any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A method of forming a memory device, the method comprising: Forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; Forming a memory opening through the alternating stack; Forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure comprises: a corresponding vertical stack of memory elements; and a corresponding vertical semiconductor channel; Forming a lateral isolation trench through the alternating stack; Forming a lateral groove by selectively removing the sacrificial material layer relative to the insulating layer and the memory opening fill structure; Depositing a first tungsten layer in the lateral groove using a first tungsten deposition process, in which a tungsten precursor gas containing fluorine is used as a reactant; and Depositing a second tungsten layer on the first tungsten layer in the lateral groove using a second tungsten deposition process, in which a tungsten precursor gas without fluorine is used as a reactant.

2. The method according to claim 1 further comprises: Before depositing the first tungsten layer in the lateral groove, depositing a conductive metal barrier liner in the lateral groove, wherein the first tungsten layer is deposited on the conductive metal barrier liner located in the lateral groove.

3. The method according to claim 1, wherein the first tungsten deposition process comprises tungsten deposition using tungsten hexafluoride as the reactant.

4. The method according to claim 1, wherein: The second tungsten deposition process comprises multiple repetitions of a unit process sequence; And The unit process sequence comprises: a reactant soak step in which the tungsten precursor gas without fluorine is provided into the lateral groove; a first purge step; a reduction step in which a reducing gas is provided into the lateral groove; and a second purge step.

5. The method according to claim 4, wherein: The tungsten precursor gas without fluorine comprises WCl5, WO2Cl2 or WOCl4; and The reducing gas comprises hydrogen.

6. The method according to claim 5, wherein a nitrogen purge gas is provided into the lateral groove during the first purge step and the second purge step.

7. The method according to claim 1, further comprising: Before depositing the second tungsten layer, exposing an outer surface of the first tungsten layer to an oxygen-containing environment to oxidize the outer surface of the first tungsten layer, and then annealing the first tungsten layer in an inert environment to remove at least one of tungsten oxide or tungsten oxyfluoride from the outer surface of the first tungsten layer.

8. The method according to claim 1, wherein the second tungsten layer encapsulates a packaging cavity that does not contain any solid-phase material and is laterally surrounded by a subset of the memory opening fill structures.

9. The method according to claim 1, wherein the second tungsten layer contains at least 50% less fluorine than the first tungsten layer.

10. The method according to claim 1, wherein a surface portion of the first tungsten layer comprises boron or silicon at a peak atomic concentration in the range of 1 ppm to 10,000 ppm, and the second tungsten layer does not contain silicon atoms and boron atoms or comprises silicon atoms or boron atoms at an average atomic concentration of less than 1 ppm.

11. A memory device, the memory device comprising: An alternating stack of insulating layers and conductive layers, wherein each conductive layer in the conductive layers comprises: an external first tungsten layer containing fluorine at a first average fluorine atom concentration; and an internal second tungsten layer embedded in the first tungsten layer and containing fluorine at a second average fluorine atom concentration less than 50% of the first average fluorine atom concentration; A memory opening extending vertically through the alternating stack; and A memory opening filling structure located in the memory opening and comprising: a corresponding vertical stack of memory elements; and a corresponding vertical semiconductor channel.

12. The memory device according to claim 11, wherein each conductive layer in the conductive layers further comprises a conductive metal barrier liner, and the first tungsten layer contacts the conductive metal barrier liner.

13. The memory device according to claim 12, wherein: A surface portion of the first tungsten layer proximate to the interface with the conductive metal barrier liner comprises elements selected from boron and silicon at a peak atomic concentration in the range of 1 ppm to 10,000 ppm; and The second tungsten layer does not contain boron atoms and silicon atoms or comprises boron atoms or silicon atoms at an average atomic concentration less than 1 ppm.

14. The memory device according to claim 12, wherein: The first tungsten layer contains a peak fluorine concentration of at least 1x10 21 cm -3 in an outer portion positioned near the interface with the conductive metal barrier liner, and contains a steady fluorine concentration of less than 1x10 21 cm -3 in an inner portion positioned near the interface with the second tungsten layer; and The second tungsten layer has a steady fluorine concentration lower than 1x10 21 cm -3 .

15. The memory device according to claim 11, wherein the second tungsten layer comprises a horizontally extending seam.

16. The memory device according to claim 15, further comprising: A lateral isolation trench filling structure extending vertically from the bottommost layer of the alternating stack to the topmost layer of the alternating stack and comprising a dielectric sidewall surface adjacent to the horizontally extending seam.

17. The memory device according to claim 16, wherein the dielectric sidewall surface of the lateral isolation trench filling structure contacts each conductive layer within the alternating stack.

18. The memory device according to claim 11, wherein the second tungsten layer encapsulates an encapsulation cavity that does not contain any solid-phase material and is laterally surrounded by a subset of the memory opening filling structure.

19. The memory device according to claim 11, wherein: The first average fluorine concentration is at least 1x10 21 cm -3 ; and The second average fluorine concentration is lower than 1x10 21 cm -3 .

20. The memory device according to claim 11, wherein: The first average fluorine concentration is between 1x10 21 cm -3 and 5x10 21 cm -3 ; and The second average fluorine concentration is between 4x10 20 cm -3 and 8x10 20 cm -3 .

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