Three-dimensional memory device with cylindrical trench bridge structure and method of forming same

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and conductive layers extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction by lateral isolation trenches; an array of memory openings, the array of memory openings extending vertically through the alternating stack; an array of memory opening fill structures within the array of memory openings and including a respective vertical stack of memory elements and a vertical semiconductor channel; and a composite lateral isolation trench filling structure, wherein the composite lateral isolation trench filling structure is located between a corresponding pair of adjacent alternating stacks. Each of the composite lateral isolation trench fill structures includes a dielectric pillar structure extending vertically from at least a first horizontal plane including a bottom of the alternating stack to a second horizontal plane including a top of the alternating stack.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of the entire content of U.S. Non - provisional Application No. 18 / 459,938, filed on September 1, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE WITH PILLAR SHAPED TRENCH BRIDGE STRUCTURES AND METHODS OF FORMING THE SAME", and is hereby incorporated by reference in its entirety for all purposes. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including pillar - shaped trench bridge structures and methods of forming the same. Background art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" by T. Endoh et al., pages 33 - 36 (2001). Summary of the invention

[0005] According to an embodiment of the present disclosure, a three - dimensional memory device includes: an alternating stack of insulating layers and conductive layers, wherein each alternating stack in the alternating stack extends laterally along a first horizontal direction, and the alternating stacks are laterally spaced apart from each other by lateral isolation trenches along a second horizontal direction; an array of memory openings, wherein each memory opening in the array of memory openings extends vertically through a corresponding alternating stack in the alternating stack; an array of memory opening filling structures located within the array of memory openings, wherein each memory opening filling structure in the array of memory opening filling structures includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; and a composite lateral isolation trench filling structure located between a corresponding pair of adjacent alternating stacks, wherein each composite lateral isolation trench filling structure in the composite lateral isolation trench filling structure includes a dielectric pillar structure that extends vertically at least from a first horizontal plane including the bottom of the alternating stack to a second horizontal plane including the top of the alternating stack.

[0006] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer; forming elongated dielectric pillar structures through the vertical alternating sequence, the elongated dielectric pillar structures extending laterally along a first horizontal direction and being laterally spaced apart along a second horizontal direction; forming memory openings through the vertical alternating sequence; forming memory opening fill structures in the memory openings, wherein each memory opening fill structure in the memory opening fill structures includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; forming laterally extending trenches through the vertical alternating stack, wherein the continuous combination of the elongated dielectric pillar structures and the laterally extending trenches divides the vertical alternating sequence into an alternating stack of insulating layers and sacrificial material layers; and replacing the sacrificial material layer with a conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view of an exemplary semiconductor die according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming an optional semiconductor device, an optional dielectric material layer embedding an optional underlying metal interconnect structure, a semiconductor material layer, and a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer according to an embodiment of the present disclosure. Figure 2 The region illustrated in Figure 1 corresponds to region M1 in

[0009] Figure 3A is a top-down view of an exemplary structure after forming a plurality of sets of stepped surfaces according to an embodiment of the present disclosure. Figure 3A The region illustrated in Figure 1 corresponds to region M1 in

[0010] Figure 3B is a vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of Figure 3A

[0011] Figure 3C is a vertical cross-sectional view of an exemplary structure along the vertical plane C-C' of Figure 3A

[0012] Figure 4A is a top-down view of an exemplary structure after forming a stepped dielectric material portion according to an embodiment of the present disclosure. Figure 4A The region illustrated in Figure 1 corresponds to region M1 in

[0013] Figure 4B is a vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of Figure 4A ​​​

[0014] Figure 4C is an exemplary structure along the Figure 4A vertical cross-sectional view of the vertical plane C-C'.

[0015] Figure 5A is a vertical cross-sectional view of the region R of the exemplary structure according to an embodiment of the present disclosure Figure 4A in

[0016] Figure 5B is Figure 5A a top-down view of the region of the exemplary structure. The vertical plane A-A' is Figure 5A the cutting plane of the vertical cross-sectional view.

[0017] Figure 5C is an exemplary structure along the Figure 5B vertical cross-sectional view of the region of the vertical plane C-C'.

[0018] Figure 6A is a vertical cross-sectional view of the region of the exemplary structure after forming an elongated column cavity, a support opening, and a stepped region isolation opening according to an embodiment of the present disclosure.

[0019] Figure 6B is Figure 6A a top-down view of the region of the exemplary structure. The vertical plane A-A' is Figure 6A the cutting plane of the vertical cross-sectional view.

[0020] Figure 6C is an exemplary structure along the Figure 6B vertical cross-sectional view of the region of the vertical plane C-C'.

[0021] Figure 7A is a vertical cross-sectional view of the region of the exemplary structure after forming an elongated sacrificial column structure, a sacrificial support opening filling structure, and a sacrificial isolation opening filling material portion according to an embodiment of the present disclosure.

[0022] Figure 7B is Figure 7A a top-down view of the region of the exemplary structure. The vertical plane A-A' is Figure 7A the cutting plane of the vertical cross-sectional view.

[0023] Figure 7C is an exemplary structure along the Figure 7B vertical cross-sectional view of the region of the vertical plane C-C'.

[0024] Figure 8A is a vertical cross-sectional view of the region of the exemplary structure after forming an etching mask layer according to an embodiment of the present disclosure.

[0025] Figure 8B Yes Figure 8A Partial perspective top - down view of the region of the exemplary structure. The vertical plane A - A’ is Figure 8A The cutting plane of the vertical cross - sectional view of

[0026] Figure 8C along Figure 8B Vertical cross - sectional view of the region of the exemplary structure along the vertical plane C - C’ of

[0027] Figure 9A Vertical cross - sectional view of the region of the exemplary structure after removing the sacrificial isolation opening filling material portion according to an embodiment of the present disclosure.

[0028] Figure 9B Yes Figure 9A Partial perspective top - down view of the region of the exemplary structure. The vertical plane A - A’ is Figure 9A The cutting plane of the vertical cross - sectional view of

[0029] Figure 9C along Figure 9B Vertical cross - sectional view of the region of the exemplary structure along the vertical plane C - C’ of

[0030] Figure 10A Vertical cross - sectional view of the region of the exemplary structure after removing the etching mask layer according to an embodiment of the present disclosure.

[0031] Figure 10B Yes Figure 10A Top - down view of the region of the exemplary structure. The vertical plane A - A’ is Figure 10A The cutting plane of the vertical cross - sectional view of

[0032] Figure 10C along Figure 10B Vertical cross - sectional view of the region of the exemplary structure along the vertical plane C - C’ of

[0033] Figure 11A Vertical cross - sectional view of the region of the exemplary structure after forming the sacrificial staircase region isolation opening filling structure and removing the elongated sacrificial pillar structure and the sacrificial support opening filling structure according to an embodiment of the present disclosure.

[0034] Figure 11B Yes Figure 11A Top - down view of the region of the exemplary structure. The vertical plane A - A’ is Figure 11A The cutting plane of the vertical cross - sectional view of

[0035] Figure 11C along Figure 11BVertical cross-sectional view of a region of an exemplary structure of vertical plane C-C'.

[0036] Figure 12A Is a vertical cross-sectional view of a region of an exemplary structure after forming an elongated dielectric pillar structure and a dielectric support pillar structure according to an embodiment of the present disclosure.

[0037] Figure 12B Is Figure 12A Partial perspective top-down view of a region of an exemplary structure. Vertical plane A-A' is Figure 12A The cutting plane of the vertical cross-sectional view.

[0038] Figure 12C Is along Figure 12B Vertical cross-sectional view of a region of an exemplary structure of vertical plane C-C'.

[0039] Figure 13A Is a vertical cross-sectional view of a region of an exemplary structure after forming an insulating capping layer, a memory opening, multiple row through-stack isolation openings, a semiconductor pillar structure, and a base channel portion according to an embodiment of the present disclosure.

[0040] Figure 13B Is Figure 13A Partial perspective top-down view of a region of an exemplary structure. Vertical plane A-A' is Figure 13A The cutting plane of the vertical cross-sectional view.

[0041] Figure 13C Is along Figure 13B Vertical cross-sectional view of a region of an exemplary structure of vertical plane C-C'.

[0042] Figure 14A Is a vertical cross-sectional view of a region of an exemplary structure after forming a sacrificial memory opening fill structure, a sacrificial through-stack isolation opening fill structure, and a first hard mask layer according to an embodiment of the present disclosure.

[0043] Figure 14B Is Figure 14A Partial perspective top-down view of a region of an exemplary structure. Vertical plane A-A' is Figure 14A The cutting plane of the vertical cross-sectional view.

[0044] Figure 14C Is along Figure 14B Vertical cross-sectional view of a region of an exemplary structure of vertical plane C-C'.

[0045] Figure 15A Is a vertical cross-sectional view of a region of an exemplary structure after patterning the first hard mask layer and removing the sacrificial memory opening fill structure according to an embodiment of the present disclosure.

[0046] Figure 15B is Figure 15A a top-down view of a region of an exemplary structure. The vertical plane A-A' is Figure 15A the cutting plane of a vertical cross-sectional view of

[0047] Figure 15C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 15B vertical plane C-C' of

[0048] Figures 16A to 16F a sequential vertical cross-sectional view of a memory opening during the formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0049] Figure 17A is a vertical cross-sectional view of a region of an exemplary structure after forming a memory opening fill structure and removing a first hard mask layer according to an embodiment of the present disclosure.

[0050] Figure 17B is Figure 17A a top-down view of a region of an exemplary structure. The vertical plane A-A' is Figure 17A the cutting plane of a vertical cross-sectional view of

[0051] Figure 17C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 17B vertical plane C-C' of

[0052] Figure 18A a vertical cross-sectional view of a region of an exemplary structure after forming a second hard mask layer according to an embodiment of the present disclosure.

[0053] Figure 18B is Figure 18A a partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A' is Figure 18A the cutting plane of a vertical cross-sectional view of

[0054] Figure 18C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 18B vertical plane C-C' of

[0055] Figure 19A a vertical cross-sectional view of a region of an exemplary structure after removing a sacrificial through-stack isolation opening fill structure according to an embodiment of the present disclosure.

[0056] Figure 19B is Figure 19A a partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A' is Figure 19AThe cutting plane of the vertical cross-sectional view.

[0057] Figure 19C is along Figure 19B The vertical cross-sectional view of the region of the exemplary structure along the vertical plane C-C' of

[0058] Figure 20A The vertical cross-sectional view of the region of the exemplary structure after forming the first laterally extending trench and dividing the vertical alternating sequence into alternating stacks according to an embodiment of the present disclosure.

[0059] Figure 20B is Figure 20A The partial perspective top-down view of the region of the exemplary structure of . The vertical plane A-A' is Figure 20A The cutting plane of the vertical cross-sectional view of

[0060] Figure 20C is along Figure 20B The vertical cross-sectional view of the region of the exemplary structure along the vertical plane C-C' of

[0061] Figure 21A The vertical cross-sectional view of the region of the exemplary structure after forming the third hard mask layer, patterning the third hard mask layer and the second hard mask layer, and removing the sacrificial staircase region isolation opening filling structure according to an embodiment of the present disclosure.

[0062] Figure 21B is Figure 21A The partial perspective top-down view of the region of the exemplary structure of . The vertical plane A-A' is Figure 21A The cutting plane of the vertical cross-sectional view of

[0063] Figure 21C is along Figure 21B The vertical cross-sectional view of the region of the exemplary structure along the vertical plane C-C' of

[0064] Figure 22A The vertical cross-sectional view of the region of the exemplary structure after forming the second laterally extending trench according to an embodiment of the present disclosure.

[0065] Figure 22B is Figure 22A The partial perspective top-down view of the region of the exemplary structure of . The vertical plane A-A' is Figure 22A The cutting plane of the vertical cross-sectional view of

[0066] Figure 22C is along Figure 22B The vertical cross-sectional view of the region of the exemplary structure along the vertical plane C-C' of

[0067] Figure 23AIs a vertical cross-sectional view of a region of an exemplary structure after removing a second hard mask layer and a third hard mask layer according to an embodiment of the present disclosure.

[0068] Figure 23B Is Figure 23A A partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A’ is Figure 23A The cutting plane of the vertical cross-sectional view.

[0069] Figure 23C Is along Figure 23B A vertical cross-sectional view of a region of an exemplary structure along the vertical plane C-C’.

[0070] Figure 24A Is a vertical cross-sectional view of a region of an exemplary structure after replacing a sacrificial material layer with a conductive layer according to an embodiment of the present disclosure.

[0071] Figure 24B Is Figure 24A A partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A’ is Figure 24A The cutting plane of the vertical cross-sectional view.

[0072] Figure 24C Is along Figure 24B A vertical cross-sectional view of a region of an exemplary structure along the vertical plane C-C’.

[0073] Figure 25A Is a vertical cross-sectional view of a region of an exemplary structure after forming a composite lateral isolation trench fill structure according to an embodiment of the present disclosure.

[0074] Figure 25B Is Figure 25A A partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A’ is Figure 25A The cutting plane of the vertical cross-sectional view.

[0075] Figure 25C Is along Figure 25B A vertical cross-sectional view of a region of an exemplary structure along the vertical plane C-C’.

[0076] Figure 26A Is a vertical cross-sectional view of a region of an exemplary structure after forming a layer contact via structure according to an embodiment of the present disclosure.

[0077] Figure 26B Is Figure 26A A partial perspective top-down view of a region of an exemplary structure. The vertical plane A-A’ is Figure 26A The cutting plane of the vertical cross-sectional view.

[0078] Figure 26C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 26B vertical plane C-C' of DETAILED DESCRIPTION

[0079] As discussed above, embodiments of the present disclosure relate to three-dimensional memory devices including columnar trench bridge structures that reduce or prevent tilting of the word line layer stack and methods of forming the same. Various aspects of the three-dimensional memory device are now described in detail.

[0080] The drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of a single instance of the illustrated element, unless otherwise explicitly described or clearly indicated as absent of replication of the element. Ordinal numbers such as "first," "second," and "third" are used only to identify similar elements and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0081] Like reference numerals denote like or similar elements. Unless otherwise specified, elements having the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or are "separated" from each other. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is "directly" located "on" a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is an electrical path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure whose shape or composition of at least one of its components is subsequently modified.

[0082] As used herein, a "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than the extent of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of a first continuous structure. For example, a layer may be located between the top surface and the bottom surface of a first continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0083] As used herein, if a second surface overlies or underlies a first surface and there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface, the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that linearly extends along a direction that deviates from the vertical direction by an angle less than 5 degrees. The vertical plane or the substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include a curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0084] As used herein, a "memory level" or a "memory array level" refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the top surface of an array of memory elements and a second horizontal plane that includes the bottom surface of the array of memory elements. As used herein, a "through-stack" element is an element that vertically extends through the memory level.

[0085] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of an electrical dopant, and is capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulating material" or a "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" is a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0×10 5 S / m. A "doped semiconductor material" may be a heavily doped semiconductor material or may be a semiconductor material that includes an electrical dopant (i.e., a p-type dopant and / or an n-type dopant), and the concentration of these electrical dopants provides a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7Conductivity within the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that contains at least one metallic element. All conductivity measurements are performed under standard conditions.

[0086] Generally speaking, a semiconductor package (or "package") refers to a single semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include a semiconductor chip (or "chip") or multiple semiconductor chips that are fully bonded, for example, through flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operations can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0087] Reference Figure 1 , a semiconductor die 1000 including multiple three-dimensional memory array regions and inter-array regions is illustrated in various views. The semiconductor die 1000 can include multiple planes, and each of these planes includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a corresponding inter-array region 200. Generally speaking, the semiconductor die 1000 can include a single plane or multiple planes. The total number of planes in the semiconductor die 1000 can be selected based on the performance requirements of the semiconductor die 1000. A pair of memory array regions 100 in a plane can be laterally spaced apart along a first horizontal direction hd1 (which can be the word line direction). A second horizontal direction hd2 (which can be the bit line direction) can be perpendicular to the first horizontal direction hd1.

[0088] Reference Figure 2 , an exemplary structure according to an embodiment of the present disclosure is illustrated. Figure 2The regions illustrated in correspond to Figure 1 region M1 in. This exemplary structure includes a substrate 8, which includes a substrate material layer 9. The substrate material layer 9 may include a semiconductor material layer, a dielectric material layer, or a combination thereof. In one embodiment, the substrate 8 may include a commercially available semiconductor substrate, such as a single crystal silicon wafer, and the substrate material layer 9 may include a doped well in the top surface of the silicon wafer or an epitaxial silicon layer on the silicon wafer. Thus, in one embodiment, the substrate material layer 9 includes a single crystal silicon layer. In this case, semiconductor devices 720, such as complementary metal oxide semiconductor (CMOS) devices (e.g., peripheral or driver circuit devices overlying a memory device), may be formed in or above the substrate material layer 9. Alternatively, the peripheral or driver circuit devices may be formed on a separate substrate and then bonded to the memory device formed above the substrate 8.

[0089] A metal interconnect structure embedded in a dielectric material layer may be formed above the substrate material layer 9. The metal interconnect structure is referred to herein as the lower metal interconnect structure 780, and the dielectric material layer is referred to herein as the lower dielectric material layer 760. The lower metal interconnect structure 760 may be electrically connected to the corresponding semiconductor devices in the semiconductor devices 720 on the substrate material layer 9.

[0090] At least one semiconductor material layer 110 may be formed above the lower dielectric material layer 760. The at least one semiconductor material layer 110 may be used as a horizontal semiconductor channel, and a source region may be formed in or on the horizontal semiconductor channel subsequently. Alternatively, the at least one semiconductor material layer 110 may include a source semiconductor layer that serves as a common source region for a vertical semiconductor channel to be formed subsequently. Additionally or alternatively, the at least one semiconductor material layer 110 may include a source-level continuous sacrificial material layer that is subsequently replaced with a source contact layer that contacts the bottom end of a vertical semiconductor channel to be formed subsequently and serves as part of the common source region of the vertical semiconductor channel.

[0091] A vertical alternating sequence of a continuous insulating layer 32L and a continuous sacrificial material layer 42L may be formed above the at least one semiconductor material layer 110. As used herein, "vertical alternating sequence" or "alternating stack" refers to a sequence of a plurality of instances of a first element and a plurality of instances of a second element that are arranged such that instances of the second element are located between each pair of vertically adjacent instances of the first element, and instances of the first element are located between each pair of vertically adjacent instances of the second element.

[0092] The continuous insulating layer 32L may be composed of a first material, and the continuous sacrificial material layer 42L may be composed of a second material, which is different from the first material. The first material of the continuous insulating layer 32L may be at least one insulating material. Insulating materials that can be used for the continuous insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides generally referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the continuous insulating layer 32L may be silicon oxide.

[0093] The second material of the continuous sacrificial material layer 42L is a sacrificial material that can be selectively removed relative to the first material of the continuous insulating layer 32L. As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, the removal of the material is "selective" relative to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0094] The continuous sacrificial material layer 42L may include an insulating material, a semiconductor material, or a conductive material. The second material of the continuous sacrificial material layer 42L may subsequently be replaced with conductive electrodes, for example, these conductive electrodes can be used as control gate electrodes of a vertical NAND device. In one embodiment, the continuous sacrificial material layer 42L may be a material layer including silicon nitride.

[0095] Reference Figures 3A to 3C , a staircase may be formed through the vertical alternating sequence of the continuous insulating layer 32L and the continuous sacrificial material layer 42L. A stepped surface may be formed within the area of the staircase. A hard mask layer (not shown), such as a metal or dielectric mask material layer, may be formed over the vertical alternating sequence and may be patterned to form a plurality of rectangular openings. The area of the openings in the hard mask layer corresponds to the staircase well (i.e., the area where the staircase including the stepped surface is to be formed subsequently). The periphery of the opening OP (i.e., the staircase well) may or may not be rectangular. Each opening through the hard mask layer may be rectangular and may have a pair of sides parallel to the horizontal direction hd1 and a pair of sides parallel to the second horizontal direction hd2.

[0096] The region within the periphery of the opening OP in the hard mask layer that is part of the vertically alternating sequence (32L, 42L) can be etched by performing multiple iterations of a combination of a corresponding lithographic patterning process and a corresponding anisotropic etching process. A stepped cavity 69 having a stepped bottom surface is formed within each region surrounded by the respective periphery of the opening OP in the topmost continuous insulating layer 32L in the inter-array region 200. The inter-array region 200 is located between a first memory array region 100A and a second memory array region 100B that are laterally spaced apart from each other along a first horizontal direction hd1.

[0097] Generally speaking, the sidewalls 41 of the stairwells of the vertically alternating sequence (32L, 42L) can be physically exposed to the stairs. The sidewalls 41 of the vertically alternating sequence (32L, 42L) can be formed with a taper angle such that the portion of each stepped cavity 69 in the stairwell having a greater depth has a smaller lateral extent. Although, for simplicity of illustration, Figure 3B an embodiment is illustrated in which the depth of each stepped cavity 69 in the stairs varies monotonically as a function of the lateral distance along the first horizontal direction hd1, the depth of each stepped cavity 69 in the respective stairwells including the respective stairs can generally increase or decrease along the first horizontal direction hd1, where the depth of a local region varies in the opposite manner. In other words, except in local regions where the depth generally decreases along the first horizontal direction hd1, the stepped cavities 69 in the stairwells can have a depth that generally increases along the first horizontal direction hd1. Alternatively, except in local regions where the depth generally increases along the first horizontal direction hd1, the stepped cavities 69 in the stairwells can have a depth that generally decreases along the first horizontal direction hd1. Such variations in the vertical cross-sectional profile of the stairs along the first horizontal direction hd1 are expressly contemplated herein.

[0098] Reference Figures 4A to 4C and Figures 5A to 5C , a dielectric fill material (such as silicon oxide) can be deposited in the stepped cavities 69. Figure 5A is Figure 4A a vertical cross-sectional view of the region R of the exemplary structure in

[0099] Reference Figures 6A to 6C, a photoresist layer (not shown) can be applied over the exemplary structure and can be lithographically patterned to form openings. An anisotropic etching process can be performed to transfer the pattern of the openings through the vertical alternating sequence (32L, 42L) and the stepped dielectric material portion 65. A cavity can be formed that extends vertically from a horizontal plane of the top surface of the stepped dielectric material portion 65 to the top surface of the semiconductor material layer 110 (or another layer underlying the vertical alternating sequence (32L, 42L)). The cavity can include an elongated column cavity 219, a support opening 19, and a stepped region isolation opening 119.

[0100] The elongated column cavity 219 extends laterally along a first horizontal direction (e.g., the word line direction) hd1. Each elongated column cavity 219 includes a central portion having a uniform width along a second horizontal direction (e.g., the bit line direction) hd2. In one embodiment, a first subset of the elongated column cavities 219 can be laterally offset from the stepped dielectric material portion 65, and a second subset of the elongated column cavities 219 can extend vertically through a portion of the corresponding stepped dielectric material portion in the stepped dielectric material portion 65. In some embodiments, a two-dimensional array of the elongated column cavities 219 can be formed. In this case, multiple rows of the elongated column cavities 219 can be laterally spaced apart from each other along the second horizontal direction hd2. Each row of the elongated column cavities 219 can include a plurality of the elongated column cavities 219 arranged along the first horizontal direction hd1. The thickness of each elongated column cavity 219 can be in the range of 40 nm to 300 nm (such as 60 nm to 200 nm), but smaller and larger thicknesses can also be employed. The aspect ratio of each elongated column cavity 219 can be in the range of 2 to 30 (such as 3 to 20 and / or 4 to 15), but smaller and larger aspect ratios can also be employed.

[0101] The support opening 19 can be formed through the underlying stepped surface of the vertical alternating sequence (32L, 42L) and the stepped dielectric material portion 65. The support openings 19 can be laterally spaced apart from each other and can have corresponding circular or elliptical horizontal cross-sectional shapes. The lateral dimension (such as the diameter) of each support opening 19 can be in the range of 30 nm to 200 nm (such as 50 nm to 120 nm), but smaller and larger lateral dimensions can also be employed.

[0102] The stepped region isolation opening 119 is formed through corresponding sets of stepped surfaces of the vertical alternating sequence (32L, 42L) and through corresponding stepped dielectric material portions 65. The stepped region isolation openings 119 can be formed as multiple rows of stepped region isolation openings 119 arranged along a first horizontal direction hd1 and aligned with corresponding ones of the elongated column cavities 219 in the elongated column cavities 219 along the first horizontal direction hd1. In one embodiment, the combination of the elongated column cavities 219 and a row of stepped region isolation openings 119 can be arranged along the first horizontal direction hd1 and pass through the stepped dielectric material portion 65 (i.e., through the staircase region) along a second horizontal direction hd2 midway.

[0103] In one embodiment, a thermal conversion process such as a thermal oxidation process and / or a thermal nitridation process can be performed to convert a physically exposed surface portion of the semiconductor material layer 110 (or the semiconductor substrate 8 if layer 110 is omitted) into a dielectric liner 212 that includes a dielectric oxide or a dielectric nitride of the semiconductor material of the semiconductor material layer 110 (or the semiconductor substrate 8 if layer 110 is omitted). If the semiconductor material is silicon, the dielectric liner 212 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0104] Reference Figures 7A to 7C , a first sacrificial fill material can be deposited in the elongated column cavities 219, the support openings 19, and the stepped region isolation openings 119. The first sacrificial fill material includes a material that can subsequently be selectively removed relative to the materials of the vertical alternating sequence (32L, 42L), the dielectric liner 212, and the stepped dielectric material portion 65. For example, the first sacrificial fill material can include a carbon-based material (such as amorphous carbon or diamond-like carbon) or can include a silicon-based material (such as amorphous silicon, polysilicon, or silicon-germanium). The excess portion of the first sacrificial fill material can be removed from above the vertical alternating sequence by a planarization process that can include a chemical mechanical polishing (CMP) process or a recess etching process. Each remaining portion of the first sacrificial fill material that fills the elongated column cavities 219 constitutes an elongated sacrificial column structure 271. Each remaining portion of the first sacrificial fill material that fills the support openings 19 constitutes a sacrificial support opening fill structure 21. Each remaining portion of the first sacrificial fill material that fills the stepped region isolation openings 119 constitutes a sacrificial isolation opening fill material portion 121.

[0105] Reference Figures 8A to 8C , an etch mask layer 33 can be formed over the vertical alternating sequence (32L, 42L) and the stepped dielectric material portion 65. The etch mask layer 33 includes a hard mask material that can subsequently be selectively removed relative to the topmost layer 32L of the vertical alternating sequence (32L, 42L); or can include a patterned photoresist layer. In one embodiment, the etch mask layer 33 includes silicon nitride.

[0106] ReferenceFigures 9A to 9C , the patterning etch mask layer 33 can be etched to form openings above each row of sacrificial isolation opening filling material portions 121. For example, elongated openings 331 extending along the first horizontal direction hd1 can be formed through the etch mask layer 33 above each row of sacrificial isolation opening filling material portions 121. A selective material removal process (such as an ashing process or a wet etching process) can be performed to remove the first sacrificial filling material of the sacrificial isolation opening filling material portion 121 from the stepped region isolation opening 119 and reopen the stepped region isolation opening 119.

[0107] Reference Figures 10A to 10C , the etch mask layer 33 can be removed by selective anisotropic etching that is selective to the top insulating layer 32L of the vertical alternating sequence (32L, 42L), the stepped dielectric material portion 65, the elongated sacrificial pillar structure 271, the sacrificial support opening filling structure 21, and the dielectric pad 212.

[0108] Reference Figures 11A to 11C , a second sacrificial filling material different from the first sacrificial filling material can be deposited in the volume of the stepped region isolation opening 119. For example, the second sacrificial filling material can include semiconductor materials (such as amorphous silicon, polysilicon, or silicon-germanium), carbon-based materials (such as amorphous carbon or diamond-like carbon), polymer materials, or high-etch-rate silicate glass materials (such as organosilicate glass or borosilicate glass), etc. In an exemplary example, the first sacrificial filling material can include a carbon-based material, and the second sacrificial filling material can include a semiconductor material, such as amorphous silicon. The excess portion of the second sacrificial filling material can be removed from above the vertical alternating sequence (32L, 42L) by a planarization process such as a chemical mechanical polishing process or a recess etching process. Each remaining portion of the second sacrificial filling material that fills the volume of the stepped region isolation opening 119 constitutes a sacrificial staircase region isolation opening filling structure 115, which is a sacrificial isolation opening filling structure located in the staircase region (i.e., the region where there is a set of stepped surfaces).

[0109] Subsequently, a selective removal process can be performed to selectively remove the first sacrificial filling material relative to the second sacrificial filling material and the materials of the vertical alternating sequence (32L, 42L) and the stepped dielectric material portion 65. Thus, the elongated sacrificial pillar structure 271 is removed from the elongated pillar cavity 219, and the sacrificial support opening filling structure 21 is removed from the support opening 19 to reopen the elongated pillar cavity 219 and the support opening 19. For example, if the first sacrificial filling material includes a carbon material, an ashing process can be used to selectively remove the first sacrificial filling material.

[0110] Reference Figures 12A to 12C, A dielectric filling material, such as undoped silicate glass (i.e., silica) or doped silicate glass, can be conformally deposited in the volumes of the elongated column cavities 219 and the support openings 19 and above the vertical alternating sequence (32L, 42L). The excess portion of the dielectric filling material can be removed from above the vertical alternating sequence (32L, 42L) by performing a planarization process, which can include a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the dielectric filling material that fills the elongated column cavity 219 constitutes an elongated dielectric column structure 220. Each remaining portion of the dielectric filling material that fills the support opening 19 constitutes a dielectric support column structure 20. Each of the elongated dielectric column structure 220 and the dielectric support column structure 20 can extend vertically at least from a horizontal plane including the top surface of the vertical alternating sequence (32L, 42L) to a horizontal plane including the bottom surface of the vertical alternating sequence (32L, 42L).

[0111] The elongated dielectric column structure 220 is formed through the vertical alternating sequence (32L, 42L), laterally extends along a first horizontal direction hd1, and can be laterally spaced apart along a second horizontal direction hd2. In one embodiment, a first subset of the elongated dielectric column structures 220 is formed through corresponding stepped dielectric material portions in the stepped dielectric material portion 65, and a second subset of the elongated dielectric column structures 220 is laterally spaced apart from the stepped dielectric material portion 65 along the second horizontal direction hd2. The first subset of the elongated dielectric column structures 220 can be in direct contact with the vertical alternating sequence (32L, 42L) and the corresponding stepped dielectric material portion 65. In one embodiment, the dielectric support column structure 20 can vertically extend through the corresponding stepped dielectric material portions in the stepped dielectric material portion 65 and the stair region of the vertical alternating sequence (32L, 42L). The dielectric support column structure 20 and the elongated dielectric column structure 220 can include the same dielectric filling material, such as undoped silicate glass or doped silicate glass.

[0112] Reference Figures 13A to 13C , An insulating capping layer 70 can be formed above the vertical alternating sequence (32L, 42L) and the stepped dielectric material portion 65. The insulating capping layer 70 includes an insulating material, such as undoped silicate glass or doped silicate glass, and can have a thickness in the range of 30 nm to 300 nm (such as 60 nm to 150 nm), but smaller and larger thicknesses can also be employed.

[0113] A photoresist layer (not shown) can be applied above the insulating capping layer 70 and can be lithographically patterned to form openings therein. An anisotropic etching process can be performed to transfer the pattern of the openings through the insulating capping layer 70, the vertical alternating sequence (32L, 42L), and the stepped dielectric material portion 65. An array of memory openings 49 is formed in each memory array region (such as Figure 1within the memory array region 100 illustrated in the example, where each layer within the vertical alternating sequence (32L, 42L) exists. A plurality of multi-row through-stack isolation openings 179 can be formed between each pair of adjacent memory opening arrays 49 spaced apart along the second horizontal direction hd2 (e.g., between adjacent memory blocks) within the vertical alternating sequence (32L, 42L) and between each pair of adjacent stepped dielectric material portions 65 laterally spaced apart along the second horizontal direction hd2. Each of the memory openings 49 and the through-stack isolation openings 179 can be formed through each layer within the vertical alternating sequence (32L, 42L).

[0114] In one embodiment, a subset of the through-stack isolation openings 179 can be formed by etching the peripheral portions of the respective elongated dielectric column structures within the elongated dielectric column structure 220. In one embodiment, each elongated dielectric column structure within the elongated dielectric column structure 220 can include at least one peripheral portion removed during the formation of the respective through-stack isolation opening 179. In one embodiment, a subset of the elongated dielectric column structure 220 can include a respective pair of peripheral portions removed during the formation of the respective pair of through-stack isolation openings 179. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0115] A selective semiconductor deposition process (such as a selective semiconductor epitaxy process) can be performed to grow semiconductor material portions from the physically exposed surface of the semiconductor material layer 110. In this case, a pedestal channel portion 11 can be formed at the bottom of each memory opening 49. A semiconductor pedestal 13 can be formed at the bottom of each through-stack isolation opening 179. The semiconductor pedestal 13 and the pedestal channel portion 11 can include the same semiconductor material, such as silicon.

[0116] Reference Figures 14A to 14C Referring to, a third sacrificial fill material can be deposited in the memory openings 49 and the through-stack isolation openings 179. The third sacrificial fill material can include any material that can be used for the first sacrificial fill material. The excess portion of the third sacrificial fill material can be removed from above the horizontal plane of the top surface including the insulating capping layer 70 by performing a planarization process, which can include a recess etching process or a chemical mechanical polishing process. Each remaining portion of the third sacrificial fill material filling the memory openings 49 constitutes a sacrificial memory opening fill structure 45. Each remaining portion of the third sacrificial fill material filling the through-stack isolation openings 179 constitutes a sacrificial through-stack isolation opening fill structure 175.

[0117] The first hard mask layer 37 may be formed over the insulating capping layer 70, the sacrificial memory opening fill structure 45, and the sacrificial through-stack isolation opening fill structure 175. The first hard mask layer 37 includes a first hard mask material which may be, for example, silicon oxide. The thickness of the first hard mask layer 37 may be in the range of 30 nm to 300 nm (such as 60 nm to 150 nm), although smaller and larger thicknesses may also be employed.

[0118] Reference Figures 15A to 15C , the first hard mask layer 37 may be patterned to form openings over each array of the sacrificial memory opening fill structures 45. For example, a photoresist layer (not shown) may be applied over the first hard mask layer 37 and lithographically patterned to form openings in the regions overlying the sacrificial memory opening fill structures 45. An etching process may be performed to remove the unmasked portions of the first hard mask layer 37. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0119] Subsequently, the sacrificial memory opening fill structure 45 may be selectively removed from the memory opening 49 relative to the materials of the vertical alternating sequence (32L, 42L), the first hard mask layer 37, and the base channel portion 11. The memory opening 49 is reopened while the through-stack isolation opening 179 remains filled with the sacrificial through-stack isolation opening fill structure 175.

[0120] Figures 16A to 16F is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening fill structure in accordance with an embodiment of the present disclosure.

[0121] Reference Figure 16A , illustrates the region around the memory opening 49 after removal of the sacrificial memory opening fill structure 45 (i.e., after the processing steps described in reference Figures 15A to 15C ).

[0122] Reference Figure 16B, a stack of layers including a blocking dielectric layer 52, a memory material layer 54, and a dielectric material liner 56 can be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metal element and oxygen, or can consist essentially of at least one metal element, oxygen, and at least one non-metal element (such as nitrogen). In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller or larger thicknesses can also be used. The dielectric metal oxide layer is then used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes alumina. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0123] Subsequently, a memory material layer 54 can be formed. Generally speaking, the memory material layer can include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of the presence or absence of charge, the direction of ferroelectric polarization, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the memory material layer 54 can include a continuous layer or a patterned discrete portion of a conductive material such as doped polysilicon or a metal material, which is patterned into a plurality of electrically isolated portions (e.g., floating gates) by forming, for example, into a continuous sacrificial material layer 42L within a lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the continuous sacrificial material layer 42L and the continuous insulating layer 32L can have vertically coincident sidewalls, and the memory material layer 54 can be formed as a single continuous layer.

[0124] In another embodiment, the continuous sacrificial material layer 42L may be laterally recessed relative to the sidewalls of the continuous insulating layer 32L, and a combination of a deposition process and an anisotropic etching process may be employed to form the memory material layer 54 as a plurality of vertically spaced memory material portions. Although embodiments in which the memory material layer 54 is a single continuous layer are used to describe the present disclosure, embodiments in which the memory material layer 54 is replaced by a plurality of vertically spaced memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions) are clearly contemplated herein. The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, although smaller and larger thicknesses may also be employed.

[0125] The dielectric material liner 56 is an optional material layer that may or may not be employed. In cases where the memory material layer 54 includes a charge storage layer, the dielectric material liner 56 may include a tunneling dielectric layer that includes a dielectric material through which charge tunneling may be performed under suitable electrical biasing conditions. Depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling may be performed by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. The dielectric material liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the dielectric material liner 56 may include a stack of a silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly referred to as an ONO stack. In one embodiment, the dielectric material liner 56 may include a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the dielectric material liner 56 may be in the range of 2 nm to 20 nm, although smaller and larger thicknesses may also be used.

[0126] Reference Figure 16C, an anisotropic etching process can be performed to remove the dielectric material liner 56, the memory material layer 54, and the horizontal extension portions of the barrier dielectric layer 52 from above the vertical alternating sequence (32, 42) and from the bottom portions of each memory opening in the memory opening 49. Optionally, a sacrificial material layer (not shown) can be deposited above the memory film 50 prior to the anisotropic etching process and can be removed after the anisotropic etching process to protect the vertical extension portions of the memory film 50. The top surface of the pedestal channel portion 11 can be physically exposed at the bottom of each memory opening 49. Each successive combination of the remaining portions of the barrier dielectric layer 52, the remaining portions of the memory material layer 54, and the remaining portions of the dielectric material liner 56 located in the memory opening 49 constitutes the memory film 50.

[0127] Reference Figure 16D , a semiconductor channel material layer 60L can be conformally deposited in the memory opening 49. The semiconductor channel material layer 60L can include an undoped semiconductor material or a doped semiconductor material. The semiconductor channel material layer 60L includes at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L can have a uniform doping. In one embodiment, the semiconductor channel material layer 60L includes a dopant of a first conduction type having an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 (such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 ). The thickness of the semiconductor channel material layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. A cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).

[0128] Reference Figure 16E, in the case where the memory opening 49 is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the unfilled volume of the memory opening 49. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer that overlies the top surface of the vertical alternating sequence (32, 42) can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the topmost continuous insulating layer 32L. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0129] Reference Figure 16F , a doped semiconductor material of a second conductivity type can be deposited in the cavity that overlies the dielectric core 62. The second conductivity type is opposite to this conductivity type. For example, if this conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material, the semiconductor channel material layer 60L, the dielectric material liner 56, the memory material layer 54, and the overlying portions of the barrier dielectric layer 52 that are in a horizontal plane overlying the top surface including the insulating capping layer 70 and the first hard mask layer 37 can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0130] Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain region 63 can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0131] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, and when the vertical NAND device including the vertical semiconductor channel 60 is turned on, current can flow through the vertical semiconductor channel. The dielectric material liner 56 is surrounded by the memory material layer 54 and laterally surrounds the vertical semiconductor channel 60. Each adjacent set of the barrier dielectric layer 52, the memory material layer 54, and the dielectric material liner 56 together constitutes a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, at this step, the barrier dielectric layer 52 may not be present in the memory film 50, and the barrier dielectric layer can be formed later after forming the backside recess. As used herein, the macroscopic retention time refers to the retention time suitable for the memory device to operate as a permanent memory device, such as a retention time exceeding 24 hours.

[0132] Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a dielectric material liner 56, a vertical stack of memory elements including portions of a memory material layer 54, and optionally a blocking dielectric layer 52. In one embodiment, the vertical stack of memory elements includes portions of corresponding memory material layers 54 at levels of successive sacrificial material layers 42L. The memory stack structure 55 may be formed through a second vertical alternating sequence of a memory array region 100 in which all layers of the second vertical alternating sequence are present. Each combination of the memory stack structure 55, a dielectric core 62, and a drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Generally, the memory opening fill structures 58 are formed within the memory openings 49. Each memory opening fill structure in the memory opening fill structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60. The pedestal channel portion 11 may include a lower portion of the memory opening fill structure 58. The combination of the memory film 50, the vertical semiconductor channel 60, optionally the dielectric core 62, and the drain region 63 constitutes an upper memory opening fill portion 57 of the memory opening fill structure 58.

[0133] Reference Figures 17A to 17C , an exemplary structure after forming the memory opening fill structure 58 is illustrated. In one embodiment, each memory opening fill structure in the memory opening fill structures 58 includes a corresponding pedestal channel portion 11 having the same material composition as the semiconductor pedestal 13.

[0134] Reference Figures 18A to 18C , a second hard mask layer 39 may be deposited over the insulating capping layer 70. The second hard mask layer 39 includes a second hard mask material which may be, for example, boron-doped amorphous silicon. The thickness of the second hard mask layer 39 may be in the range of 30 nm to 300 nm (such as 60 nm to 150 nm), although smaller and larger thicknesses may also be employed.

[0135] Reference Figures 19A to 19C , the second hard mask layer 39 may be patterned to form openings in regions overlying the sacrificial through-stack isolation opening fill structure 175. For example, a photoresist layer (not shown) may be applied over the second hard mask layer 39 and lithographically patterned with openings having the same pattern as the sacrificial through-stack isolation opening fill structure 175. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the second hard mask layer 39.

[0136] An optional removal process (such as an ashing process or an isotropic etching process) can be performed to selectively remove the third sacrificial fill material of the sacrificial through-stack isolation fill structure 175 from the through-stack isolation opening 179 relative to the materials of the vertical alternating sequence (32L, 42L), the stepped dielectric material portion 65, the insulating capping layer 70, the second hard mask layer 39, and the semiconductor substrate 13. The through-stack isolation opening 179 is reopened.

[0137] Reference Figures 20A to 20C , a first isotropic etching process can be performed to isotropically laterally recess the physically exposed sidewalls of the vertical alternating sequence (32L, 42L) surrounding each through-stack isolation opening in the through-stack isolation opening 179. The first laterally extending trench 79A can be formed in the continuous void formed by merging adjacent through-stack isolation openings 179. The first isotropic etching process can include an isotropic etching step of isotropically etching the material of the continuous insulating layer 32L and another isotropic etching step of isotropically etching the material of the continuous sacrificial material layer 42L. In one embodiment, the first isotropic etching process can include sequentially etching the silicon nitride continuous sacrificial material layer 42L using hot phosphoric acid and separately etching the silicon oxide continuous insulating layer 32L using hydrofluoric acid before or after etching the silicon nitride continuous sacrificial material layer 42L. The duration of the isotropic etching step can be selected to merge the corresponding rows of through-stack isolation openings 179 into the corresponding first laterally extending trenches 79A.

[0138] In summary, multiple rows of isolation openings (such as multiple rows of through-stack isolation openings 179) can be formed through the vertical alternating sequence (32L, 42L), and the volume of the isolation openings can be laterally expanded by isotropically laterally recessing the portions of the vertical alternating sequence (32L, 42L) surrounding the multiple rows of isolation openings to form the first laterally extending trenches 79A. The first laterally extending trenches 79A are the first subset of the laterally extending trenches 79 that will exist after the exemplary structure is completed. Each first laterally extending trench in the first laterally extending trenches 79A generally extends along a first horizontal direction hd1 and has a lateral width variation along a second horizontal direction hd2 that varies with the lateral distance along the first horizontal direction hd1.

[0139] Each successive volume including at least one elongated dielectric pillar structure 220 and at least two first laterally extending trenches 79A constitutes a lateral isolation trench. The lateral isolation trenches (79A, 220) divide a vertical alternating sequence (32L, 42L) into a plurality of alternating stacks of corresponding insulating layers 32 and corresponding sacrificial material layers 42. Each insulating layer 32 is a patterned portion of a continuous insulating layer 32L. Each sacrificial material layer 42 is a patterned portion of a continuous sacrificial material layer 42L. Thus, the successive combination of the elongated dielectric pillar structure 220 and the first laterally extending trenches 79A divides the vertical alternating sequence (32L, 42L) into an alternating stack (32, 46) of insulating layers 32 and sacrificial material layers 42. The elongated dielectric pillar structure 220 serves as a bridge structure to prevent or reduce tilting or collapse of the alternating stack (32, 46) into the first laterally extending trenches 79A.

[0140] Reference Figures 21A to 21C , a third hard mask layer 41 can be formed over the second hard mask layer 39 by performing an anisotropic deposition process. For example, a non-conformal chemical vapor deposition process (such as a plasma-enhanced chemical deposition process or a physical vapor deposition process) can be employed to deposit the third hard mask layer 41. The third hard mask layer 41 can include a dielectric material different from the material of the second hard mask layer 39. In one embodiment, the second hard mask layer 39 includes amorphous silicon, and the third hard mask layer 41 includes silicon nitride. The thickness of the third hard mask layer 41 can be selected such that the third hard mask layer 41 covers the openings in the second hard mask layer 39. The thickness of the third hard mask layer 41 over the horizontally extending portion of the second hard mask layer 39 can be in the range of 100 nm to 400 nm, although smaller and larger thicknesses can also be employed.

[0141] The third hard mask layer 41 can be patterned to form openings in the regions of the sacrificial staircase region isolation opening filling structures 115. For example, a photoresist layer (not shown) can be applied over the third hard mask layer 41 and lithographically patterned to form openings having the same pattern as the sacrificial staircase region isolation opening filling structures 115. An anisotropic etching process can be performed to remove the unmasked portions of the third hard mask layer 41. Subsequently, the second sacrificial filling material of the sacrificial staircase region isolation opening filling structures 115 can be selectively removed from the staircase region isolation openings 119 with respect to the materials of the alternating stack (32, 42), the stepped dielectric material portion 65, the insulating capping layer 70, the second hard mask layer 39, and the third hard mask layer 41 to reopen the staircase region isolation openings 119. The photoresist layer can be removed before, during, or after removing the sacrificial staircase region isolation opening filling structures 115.

[0142] Reference Figures 22A to 22C, a second isotropic etching process may be performed to isotropically and laterally recess portions of each of the step region isolation openings 119 in the alternating stack (32, 42), the stepped dielectric material portion 65, and the elongated dielectric column structure 220 surrounding the step regions. The second laterally extending trench 79B may be formed in the continuous void formed by merging adjacent step region isolation openings 119. The second isotropic etching process may include an isotropic etching step of isotropically etching the material of the insulating layer 32 and another isotropic etching step of isotropically etching the material of the sacrificial material layer 42. In one embodiment, the first isotropic etching process may include sequentially etching the silicon nitride sacrificial material layer 42 using hot phosphoric acid and separately etching the silicon oxide insulating layer 32 using hydrofluoric acid before or after etching the silicon nitride sacrificial material layer 42. The duration of the isotropic etching step may be selected to form the corresponding rows of step region isolation openings 119. The second laterally extending trench 79B may be a subset of the laterally extending trench 79. Additionally, the dielectric liner 212 may be removed from the step region isolation openings 119 to form a recess 119R in the layer underlying the step region isolation openings 119 (e.g., the semiconductor material layer 110 or the substrate 8).

[0143] In summary, multiple rows of isolation openings (such as multiple rows of step region isolation openings 119) may be formed through the vertical alternating sequence (32L, 42L), and the volume of the isolation openings may be laterally expanded by isotropically and laterally recessing portions of the alternating stack (32, 42) surrounding the multiple rows of isolation openings to form laterally extending trenches (such as the second laterally extending trench 79B). Each of the laterally extending trenches in the laterally extending trench 79 extends generally along a first horizontal direction hd1 and has a lateral width variation along a second horizontal direction hd2 that varies with the lateral distance along the first horizontal direction hd1.

[0144] In one embodiment, a subset of the laterally extending trenches 79, such as the second laterally extending trench 79B, may be formed through a respective one of the stepped dielectric material portion 65 and the staircase region, and may divide the respective stepped dielectric material portion in the stepped dielectric material portion 65 into a respective pair of patterned stepped dielectric material portions 65 and a pair of staircase regions. When forming the second laterally extending trench 79B, each of the alternating stacks (32, 42) in the alternating stack may have a respective stepped surface in the staircase region that underlies and contacts the respective stepped dielectric material portion 65. Each of the alternating stacks (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may extend laterally along a first horizontal direction hd1. The alternating stacks (32, 42) may be laterally spaced apart from each other by the lateral isolation trenches (219, 79) along a second horizontal direction hd2. Generally, each of the lateral isolation trenches (219, 79) may include at least one elongated pillar cavity 219 and a volume of at least two laterally extending trenches 79.

[0145] Reference Figures 23A to 23C , an anisotropic etching process may be performed to remove the third hard mask layer 41 and the second hard mask layer 39.

[0146] Reference Figures 24A to 24C , the sacrificial material layer 42 may be selectively removed relative to the insulating layer 32, the stepped dielectric material portion 65, the insulating capping layer 70, the outermost layer of the memory film 50, and the semiconductor substrate 13. For example, an etchant that selectively etches the material of the sacrificial material layer 42 relative to the materials of the insulating layer 32, the stepped dielectric material portion 65, the insulating capping layer 70, the outermost layer of the memory film 50, and the semiconductor substrate 13 may be introduced into the laterally extending trench 79, for example, using an isotropic etching process.

[0147] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which the etchant is introduced into the laterally extending trench 79 in a gas phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art.

[0148] A dorsal recess is formed in the volume from which the sacrificial material layer 42 is removed. Each dorsal recess among the dorsal recesses can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each dorsal recess among the dorsal recesses can be greater than the height of the corresponding dorsal recess. Each dorsal recess among the dorsal recesses can extend substantially parallel to the top surface of the substrate 8. The dorsal recess can be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each dorsal recess among the dorsal recesses can always have a uniform height.

[0149] Optionally, an optional dorsal barrier dielectric layer (not shown) can be deposited in the dorsal recesses and the laterally extending trenches 79 and above the insulating capping layer 70. The dorsal barrier dielectric layer includes a dielectric material such as a dielectric metal oxide (e.g., alumina), silicon oxide, or a combination thereof.

[0150] At least one conductive material can be deposited in the plurality of dorsal recesses, on the sidewalls of the laterally extending trenches 79, and above the insulating capping layer 70. The at least one conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material can include elemental metals, intermetallic alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal semiconductor alloys (such as metal silicides), their alloys, and combinations or stacks thereof.

[0151] In one embodiment, the at least one conductive material can include at least one metallic material, i.e., a conductive material including at least one metallic element. Non-limiting exemplary metallic materials that can be deposited in the dorsal recesses include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and / or ruthenium. For example, the at least one conductive material can include a conductive metal nitride liner including a conductive metal nitride material (such as TiN, TaN, MoN, WN, or a combination thereof) and a conductive filling material (such as W, Co, Ru, Mo, Cu, or a combination thereof). In one embodiment, the at least one conductive material for filling the dorsal recesses can be a combination of a titanium nitride layer and a tungsten filling material.

[0152] The conductive layer 46 can be formed in the backside recess by depositing at least one conductive material. A continuous metal material layer (not shown) can be formed on the sidewalls of each of the laterally extending trenches 79 and above the insulating capping layer 70. Each conductive layer in the conductive layer can include a corresponding conductive metal nitride liner and a corresponding conductive fill material. Thus, the sacrificial material layer 42 can be replaced by the conductive layer 46. Specifically, each sacrificial material layer 42 can be replaced by an optional portion of the backside barrier dielectric layer and the conductive layer 46. A backside cavity exists in the portion of each laterally extending trench 79 that is not filled with the continuous metal material layer.

[0153] The continuous metal material layer can be removed from inside the laterally extending trenches 79. Specifically, the continuous metal material layer can be etchback from the sidewalls of each laterally extending trench 79 and from above the insulating capping layer 70, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the backside recess constitutes the conductive layer 46. The sidewalls of the conductive layer 46 can be physically exposed to the corresponding laterally extending trench 79.

[0154] Each conductive layer 46 can be a conductive sheet including openings therein. A subset of the openings through each conductive layer 46 can be filled with a memory opening fill structure 58. A second subset of the openings through each conductive layer 46 can be filled with a dielectric support pillar structure 20. A subset of the conductive layers 46 can include word lines of the memory elements.

[0155] Reference Figures 25A to 25C, a laterally extending trench fill structure {(74, 76) or (274, 276)} may be formed in each laterally extending trench 79. In one embodiment, the laterally elongated tubular insulating spacer (74, 274) may be formed at the periphery of each laterally extending trench 79 by conformally depositing a layer of insulating material and anisotropically etching the insulating material layer. The laterally elongated tubular insulating spacer (74, 274) may include a first laterally elongated tubular insulating spacer 74 formed in the first laterally extending trench 79A and a second laterally elongated tubular insulating spacer 274 formed in the second laterally extending trench 79B. At least one conductive material may optionally be deposited in the remaining unfilled volume of the laterally extending trench 79, and the excess of at least one conductive fill material may be removed from above the horizontal plane of the top surface including the insulating capping layer 70. Each remaining portion of at least one conductive material constitutes a source contact via structure (76, 276). The source contact via structure (76, 276) may include a first source contact via structure 76 formed in the first laterally isolated trench 79A and a second source contact via structure 276 formed in the second laterally extending trench 79B. In this case, each consecutive combination of the source contact via structure (76, 276) and the laterally elongated tubular insulating spacer (74, 274) constitutes a laterally extending trench fill structure {(74, 76) or (274, 276)}. In one embodiment, the source contact via structure (76, 276) may be formed within the laterally extending trench 79 and may be electrically connected to the semiconductor material layer 110 or the semiconductor substrate 8 underlying the alternating stack (32, 46).

[0156] Each consecutive combination of the material portions filling the respective laterally isolated trenches (219, 79) constitutes a composite laterally isolated trench fill structure (220, 74, 76, 274, 276). Thus, each composite laterally isolated trench fill structure (220, 74, 76, 274, 276) includes at least one elongated dielectric pillar structure 220 and at least two laterally extending trench fill structures {(74, 76) and / or (274, 276)}. The width of the first type of laterally extending trench fill structure {(74, 76)} located in the first laterally extending trench 79A along the second horizontal direction hd2 may be narrower than the width of the second type of laterally extending trench fill structure {(274, 276)} located in the second laterally extending trench 79B.

[0157] Each alternating stack (32, 46) having a memory opening fill structure 58 extending vertically therethrough includes a memory block. In the interarray region 200 is located as Figure 1In an embodiment between two memory array regions (100A, 100B) in the same memory block as shown, the conductive layer 46 can continuously extend from the first memory array region 100A to the second memory array region 100B through the connection portion 202 in the inter-array region 200. The connection portion 202 is located in the region between the stepped dielectric material portion 65 covering the staircase region and the laterally extending trench fill structure {(74, 76)}.

[0158] Reference Figures 26A to 26C , the contact via cavity can be formed through the insulating capping layer 70 and the stepped dielectric material portion 65 to the top surface of the corresponding conductive layer 46. At least one conductive material (such as at least one metal material) can be deposited in the contact via cavity to form a layer contact via structure 86. Additionally, a drain contact via structure 88 can be formed through the insulating capping layer 70 on the top surface of the corresponding drain region in the drain region 63.

[0159] Referring to all the figures and according to various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46, wherein each alternating stack in the alternating stack (32, 46) extends laterally along a first horizontal direction hd1, and the alternating stacks (32, 46) are laterally spaced apart from each other along a second horizontal direction hd2 by lateral isolation trenches (219, 79); an array of memory openings 49, wherein each array of memory openings 49 extends vertically through a corresponding alternating stack in the alternating stack (32, 46); an array of memory opening fill structures 58 located within the array of memory openings 49, wherein each memory opening fill structure 58 in the memory opening fill structures 58 includes a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50) and a vertical semiconductor channel 60; and composite lateral isolation trench fill structures (220, 74, 76, 274, 276) located between a corresponding pair of adjacent alternating stacks (32, 46). Each composite lateral isolation trench fill structure (220, 74, 76, 274, 276) in the composite lateral isolation trench fill structures (220, 74, 76, 274, 276) includes a dielectric column structure 220 that extends vertically at least from a first horizontal plane HP1 including the bottom of the alternating stack (32, 46) to a second horizontal plane HP2 including the top of the alternating stack (32, 46), as Figure 26A and Figure 26C shown.

[0160] In Figure 26BIn one embodiment shown, the dielectric pillar structure 220 includes an elongated dielectric pillar structure 220 that includes an intermediate portion 220M that extends laterally along a first horizontal direction hd1 and has a uniform width along a second horizontal direction hd2; and also includes a pair of end portions 220E that have respective vertically straight and laterally recessed sidewalls.

[0161] In one embodiment, each composite lateral isolation trench fill structure (220, 74, 76, 274, 276) includes at least one source contact via structure (76, 276) that has a pair of longitudinal sidewalls that generally extend along a first horizontal direction hd1 and has a lateral undulating width along a second horizontal direction hd2 that undulates along the first horizontal direction hd1. In one embodiment, each source contact via structure (76, 276) of the at least one source contact via structure is laterally surrounded by a laterally elongated tubular insulating spacer (74, 274) that has a laterally undulating extent along the second horizontal direction hd2 that varies with a lateral distance along the first horizontal direction hd1.

[0162] In one embodiment, each source contact via structure (76, 276) of the at least one source contact via structure includes a respective bottom surface that contacts a corresponding row of the semiconductor base 13 (which may overlie the semiconductor material layer 110 or the semiconductor substrate 8). In one embodiment, each memory opening fill structure 58 includes a respective base channel portion 11 that has the same material composition as the semiconductor base 13.

[0163] In one embodiment, each elongated dielectric pillar structure 220 of the elongated dielectric pillar structures contacts a respective pair of laterally elongated tubular insulating spacers (74, 274), each of which has a laterally undulating extent along the second horizontal direction hd2 that varies with a lateral distance along the first horizontal direction hd1.

[0164] In one embodiment, each of the alternating stacks (32, 46) in the alternating stack has a corresponding stepped surface that underlies and contacts the corresponding stepped dielectric material portion 65. In one embodiment, the composite lateral isolation trench fill structure (220, 74, 76, 274, 276) includes: a first composite lateral isolation trench fill structure (220, 74, 76) that does not directly contact any of the stepped dielectric material portions in the stepped dielectric material portion 65; and a second composite lateral isolation trench fill structure (220, 74, 76, 274, 276) that contacts the corresponding stepped dielectric material portion in the stepped dielectric material portion 65. In one embodiment, each of the first composite lateral isolation trench fill structures (220, 74, 76) includes a corresponding pair of first source contact via structures 76 having a first maximum lateral width along the second horizontal direction hd2; and each of the second composite lateral isolation trench fill structures (220, 74, 76, 274, 276) includes a corresponding additional first source contact via structure 76 and a second source contact via structure 276, the corresponding additional first source contact via structure having a first maximum lateral width along the second horizontal direction hd2, and the second source contact via structure having a second maximum lateral width greater than the first maximum lateral width along the second horizontal direction hd2.

[0165] In one embodiment, the continuous set of stepped surfaces extends continuously at least from the bottommost conductive layer 46 within the corresponding alternating stack in the alternating stack (32, 46) to the topmost conductive layer 46 within the corresponding alternating stack in the alternating stack (32, 46).

[0166] In one embodiment, the three-dimensional memory device includes layer contact via structures 86 that extend vertically through the corresponding stepped dielectric material portions in the stepped dielectric material portion 65 and contact the corresponding conductive layers 46 within the alternating stack (32, 46).

[0167] In one embodiment, the three-dimensional memory device includes dielectric support pillar structures 20 that extend vertically through the corresponding stepped dielectric material portions in the stepped dielectric material portion 65, wherein the dielectric support pillar structures 20 and the dielectric pillar structures 220 include the same dielectric filling material.

[0168] In one embodiment, a subset of the dielectric pillar structures 220 directly contacts the corresponding pair of alternating stacks (32, 46) in the alternating stack (32, 46) and the corresponding pair of stepped dielectric material portions in the dielectric material portion.

[0169] Various embodiments of the present disclosure can be used to prevent pattern collapse (i.e., the insulating layer 32 collapses into the backside recess) during replacement of the sacrificial material layer 42 with the conductive layer 46. This reduces or eliminates the vertical deflection of the conductive layer 46, thereby reducing or eliminating short circuits between vertically adjacent conductive layers 46. During the formation of the laterally extending trench 79, during the formation of the backside recess, during the formation of the conductive layer 46, and during the formation of the laterally extending trench fill structure {(74,76),(274,276)}, the elongated dielectric column structure 220 fills the corresponding elongated column cavities 219 of the lateral isolation trenches (219,79). Thus, the elongated dielectric column structure 220 also serves as a trench bridge structure that reduces or prevents the alternating stack from tilting into the laterally extending trench 79 before the formation of the laterally extending trench fill structure {(74,76),(274,276)}.

[0170] Although the foregoing relates to specific embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision various modifications to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not mutually alternative. Unless otherwise expressly stated, the word "comprising" or "including" contemplates all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Where embodiments using a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: An alternating stack of insulating layers and conductive layers, wherein each alternating stack in the alternating stack extends laterally along a first horizontal direction, and the alternating stacks are laterally spaced apart from each other by lateral isolation trenches along a second horizontal direction; An array of memory openings, wherein each array of memory openings extends vertically through a corresponding alternating stack in the alternating stack; An array of memory opening filling structures, the array of memory opening filling structures being located within the array of memory openings, wherein each memory opening filling structure in the array of memory opening filling structures includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; And A composite lateral isolation trench filling structure, the composite lateral isolation trench filling structure being located between a corresponding pair of adjacent alternating stacks, wherein each composite lateral isolation trench filling structure in the composite lateral isolation trench filling structure includes a dielectric column structure, the dielectric column structure extending vertically at least from a first horizontal plane including the bottom of the alternating stack to a second horizontal plane including the top of the alternating stack.

2. The three-dimensional memory device according to claim 1, wherein the dielectric column structure includes an elongated dielectric column structure, the elongated dielectric column structure including: A middle portion, the middle portion extending laterally along the first horizontal direction and having a uniform width along the second horizontal direction; And A pair of ends, the pair of ends having corresponding vertically straight and laterally recessed sidewalls.

3. The three-dimensional memory device according to claim 2, wherein each composite lateral isolation trench filling structure in the composite lateral isolation trench filling structure further includes at least one source contact via structure, the at least one source contact via structure having a pair of longitudinal sidewalls extending generally along the first horizontal direction and having a lateral undulating width along the second horizontal direction that undulates along the first horizontal direction.

4. The three-dimensional memory device according to claim 3, wherein each source contact via structure in the at least one source contact via structure is laterally surrounded by a laterally elongated tubular insulating spacer, the laterally elongated tubular insulating spacer having an undulating lateral extent along the second horizontal direction that varies with a lateral distance along the first horizontal direction.

5. The three-dimensional memory device according to claim 3, wherein: Each source contact via structure in the at least one source contact via structure includes a corresponding bottom surface in contact with a semiconductor base of a corresponding row; and Each memory opening filling structure in the array of memory opening filling structures further includes a corresponding base channel portion having the same material composition as the semiconductor base.

6. The three-dimensional memory device according to claim 2, wherein each elongated dielectric column structure in the elongated dielectric column structure is in contact with a corresponding pair of laterally elongated tubular insulating spacers, each laterally elongated tubular insulating spacer having an undulating lateral extent along the second horizontal direction that varies with a lateral distance along the first horizontal direction.

7. The three-dimensional memory device according to claim 1, wherein each of the alternating stacks in the alternating stack has a corresponding stepped surface underlying and contacting a corresponding stepped dielectric material portion.

8. The three-dimensional memory device according to claim 7, wherein the composite lateral isolation trench fill structure comprises: a first composite lateral isolation trench fill structure that does not directly contact any of the stepped dielectric material portions in the stepped dielectric material portions; and a second composite lateral isolation trench fill structure that contacts a corresponding stepped dielectric material portion in the stepped dielectric material portions.

9. The three-dimensional memory device according to claim 8, wherein: each of the first composite lateral isolation trench fill structures in the first composite lateral isolation trench fill structure comprises a corresponding pair of first source contact via structures having a first maximum lateral width along the second horizontal direction; and each of the second composite lateral isolation trench fill structures in the second composite lateral isolation trench fill structure comprises a corresponding additional first source contact via structure and a second source contact via structure, the corresponding additional first source contact via structure having the first maximum lateral width along the second horizontal direction, and the second source contact via structure having a second maximum lateral width greater than the first maximum lateral width along the second horizontal direction.

10. The three-dimensional memory device according to claim 7, wherein the continuous set of stepped surfaces extends continuously at least from the bottommost conductive layer within one of the alternating stacks in the alternating stack to the topmost conductive layer within the one of the alternating stacks in the alternating stack.

11. The three-dimensional memory device according to claim 7, the three-dimensional memory device further comprising a layer contact via structure that vertically extends through a corresponding stepped dielectric material portion in the stepped dielectric material portions and contacts a corresponding conductive layer within the alternating stack.

12. The three-dimensional memory device according to claim 7, the three-dimensional memory device further comprising a dielectric support pillar structure that vertically extends through a corresponding stepped dielectric material portion in the stepped dielectric material portions, wherein the dielectric support pillar structure and the dielectric pillar structure comprise the same dielectric fill material.

13. The three-dimensional memory device according to claim 7, wherein a subset of the dielectric pillar structures directly contacts a corresponding pair of the alternating stacks and a corresponding pair of the stepped dielectric material portions.

14. A method of forming a memory device, the method comprising: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer; forming elongated dielectric pillar structures through the vertical alternating sequence, the elongated dielectric pillar structures extending laterally along a first horizontal direction and being laterally spaced apart along a second horizontal direction; forming memory openings through the vertical alternating sequence; A memory opening fill structure is formed in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; A laterally extending trench is formed through the vertically alternating stack, wherein the continuous combination of the elongated dielectric pillar structure and the laterally extending trench divides the vertically alternating sequence into an alternating stack of insulating layers and sacrificial material layers; And The sacrificial material layer is replaced with a conductive layer.

15. The method according to claim 14, wherein forming the laterally extending trench comprises: Forming a plurality of rows of isolation openings through the vertically alternating sequence; And Isotropically expanding the volume of the isolation openings by isotropically laterally recessing portions of the vertically alternating sequence surrounding the plurality of rows of isolation openings to form the laterally extending trench.

16. The method according to claim 15, wherein each laterally extending trench in the laterally extending trench extends generally along the first horizontal direction and has a lateral width undulation along the second horizontal direction that varies with the lateral distance along the first horizontal direction.

17. The method according to claim 15, wherein a subset of the isolation openings is formed by etching peripheral portions of corresponding elongated dielectric pillar structures in the elongated dielectric pillar structure.

18. The method according to claim 14, the method further comprising: Forming a plurality of sets of stepped surfaces by patterning the vertically alternating sequence; And Forming a stepped dielectric material portion over the plurality of sets of stepped surfaces, wherein: A first subset of the elongated dielectric pillar structures is formed through corresponding stepped dielectric material portions in the stepped dielectric material portion; and A second subset of the elongated dielectric pillar structures is laterally spaced from the stepped dielectric material portion.

19. The method according to claim 18, wherein a subset of the laterally extending trenches is formed through corresponding stepped dielectric material portions in the stepped dielectric material portion and divides the corresponding stepped dielectric material portions in the stepped dielectric material portion into corresponding pairs of patterned stepped dielectric material portions.

20. The method according to claim 14, the method further comprising forming a source contact via structure in the laterally extending trench.

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