Optical chip and preparation method and application thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to an optical chip and a preparation method and application thereof. The preparation method comprises the following steps: (1) sequentially depositing a first hard mask, a second hard mask, an anti-reflection layer and photoresist on the surface of a silicon substrate; the material of the second hard mask comprises amorphous silicon; (2) sequentially etching at least part of the photoresist, the anti-reflection layer, the second hard mask and the first hard mask according to the structure of the optical chip; and (3) removing the photoresist and cleaning to obtain a silicon substrate containing at least part of the second hard mask and the first hard mask, etching the silicon substrate, and removing the second hard mask and the first hard mask to obtain the optical chip. According to the preparation method provided by the invention, the optical chip with small line width size and high aspect ratio, especially the metasurface optical chip, can be prepared; moreover, the preparation method is compatible with a CMOS process, is suitable for a conventional CMOS production line, and can realize large-scale mass production.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to an optical chip, a preparation method thereof, and an application thereof. Background Art

[0002] The hard mask process is a common process for fabricating optical chips. The principle of the hard mask process: In the etching process, in order to etch a specific shape, an etching barrier layer needs to be set on the target material. The target material protected by the etching barrier layer is not etched, and the target material without the protection of the etching barrier layer is etched. Photoresist is a traditional etching barrier layer material. However, when the line width gradually decreases, a thinner photoresist is required. Because of too high thickness, it is very easy to have the problem of photoresist collapse, and the lithography resolution will be greatly reduced. However, due to the limited etching selectivity between the photoresist and the target material, the too thin photoresist is not enough to block the long-term plasma bombardment during the dry etching process.

[0003] For optical chips with small line width dimensions and high aspect ratios, especially metasurface optical chips, the difficulty of solving the above problems will be further increased.

[0004] Therefore, it is crucial to develop a preparation method for optical chips with small line width dimensions and high aspect ratios, especially metasurface optical chips with small line width dimensions and high aspect ratios. Summary of the Invention

[0005] In view of the above problems, the present application provides an optical chip, a preparation method thereof, and an application thereof. The preparation method can fabricate optical chips with small line width dimensions and high aspect ratios, especially metasurface optical chips. Moreover, the preparation method is compatible with the CMOS process, applicable to a conventional CMOS production line, and can be mass-produced.

[0006] In a first aspect, the present application provides a preparation method for an optical chip, and the preparation method includes the following steps:

[0007] (1) Deposit a first hard mask, a second hard mask, an antireflection layer, and a photoresist on the surface of a silicon substrate in sequence;

[0008] The material of the second hard mask includes amorphous silicon;

[0009] (2) Etch at least part of the photoresist, the antireflection layer, the second hard mask, and the first hard mask in sequence according to the structure of the optical chip;

[0010] (3) Remove the glue and clean it to obtain a silicon substrate containing at least part of the second hard mask and the first hard mask, and etch the silicon substrate to remove the second hard mask and the first hard mask to obtain the optical chip.

[0011] In the technical solution of the embodiment of the present application, a photoresist pattern is transferred to a silicon substrate by using a two-layer hard mask process; first, the photoresist pattern is transferred to a second hard mask, and the material of the second hard mask, amorphous silicon, has the advantages of high flatness, good chemical stability, high hardness, high melting point, and high etching selectivity; then, the pattern is transferred to a first hard mask by using the second hard mask, and finally, the pattern is transferred to the silicon substrate by using the first hard mask, and finally, the preparation of the pattern on the silicon substrate is completed to obtain the optical chip; the preparation method can obtain a metasurface optical chip with a small line width size and a high aspect ratio; in addition, the preparation method of the present application is compatible with the CMOS process (complementary metal oxide semiconductor, a mainstream technology in modern integrated circuit manufacturing), is applicable to a conventional CMOS production line, and can be mass-produced.

[0012] In the present application, a metasurface is an array structure formed by arranging sub-wavelength artificial microstructure units in a certain sequence. By reasonably designing the unit structure of the metasurface, precise regulation of electromagnetic waves can be achieved, including regulation of amplitude, polarization, phase, etc.

[0013] In the present application, the amorphous silicon refers to α-silicon, which is a form of elemental silicon.

[0014] In some embodiments, the material of the first hard mask includes silicon dioxide.

[0015] In some embodiments, the thickness ratio of the first hard mask to the second hard mask is (1-6):1, and further preferably (1.5-3.5):1, where 1-6 can be 2, 3, 4, 5, etc.

[0016] In the technical solution of the embodiment of the present application, the thickness ratio of the first hard mask to the second hard mask is within the above range. If the thickness ratio is too high, when etching the first hard mask (such as silicon dioxide) with the second hard mask (amorphous silicon) as the mask, a higher selectivity requirement between amorphous silicon and silicon dioxide is required. When the selectivity is insufficient, the amorphous silicon is etched away but the silicon dioxide is not completely etched; if the thickness ratio is too low, the thickness of the amorphous silicon increases, and a higher selectivity requirement between the photoresist and the amorphous silicon is proposed. When the amorphous silicon is too thick, the photoresist needs to be thicker, thus affecting the lithography resolution.

[0017] Preferably, the etching depth of the silicon substrate and the thickness ratio of the second hard mask are (1-12):1, and further preferably (5-10):1, where 1-12 can be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0018] In the technical solution of the embodiment of the present application, the ratio of the etching depth of the silicon substrate to the thickness of the second hard mask is within the above range. If the ratio of their thicknesses is too high, it will lead to an increased requirement for the selectivity between the second hard mask and the first hard mask, and at the same time, an increased requirement for the selectivity between the first hard mask and the silicon substrate. When the selectivity is insufficient, the second hard mask cannot block during the process of etching silicon dioxide or the first hard mask cannot block during the process of etching the silicon substrate, ultimately resulting in abnormal patterns. If the ratio of their thicknesses is too low, it will lead to an increase in the thickness of the first hard mask, thus posing challenges to the thicknesses of the second hard mask and the photoresist.

[0019] In this way, the requirement for the selectivity between the second hard mask and the first hard mask increases, and at the same time, the requirement for the selectivity between the first hard mask and the silicon substrate increases. When the selectivity is insufficient, the second hard mask or the first hard mask cannot block during the process of etching silicon, resulting in abnormal patterns.

[0020] In the present application, the first hard mask and the second hard mask serve for the etching of the target material, and the basic idea of their thickness design is as follows: Taking the etching of the silicon substrate as an example, the commonly used etching depth h in the CMOS process line is usually within 5 μm. After the etching depth is determined, the selectivity between the silicon substrate and the first hard mask is n, which means that etching n depths of the silicon substrate will consume 1 depth of silicon dioxide, and the minimum thickness of the silicon dioxide is h / n. Similarly, the selectivity between the amorphous silicon of the second hard mask and the first hard mask is m, and the minimum thickness of the first hard mask is h / n, then the minimum thickness of the second hard mask is h / mn. Usually, the thickness setting is not so critical, and it is more reasonable to increase by 40%-60% (such as 50% etc.) on the basis of the minimum thickness. On this basis, combining the above thickness design principle, the ratio of the thicknesses of the first hard mask and the second hard mask and the ratio of the thicknesses of the silicon substrate and the second hard mask are obtained comprehensively.

[0021] In some embodiments, the etching depth of the silicon substrate is 300 - 1500 nm, such as 320 nm, 440 nm, 580 nm, 620 nm, 780 nm, 900 nm, 1000 nm, etc., and the thickness of the first hard mask is 200 - 300 nm, such as 220 nm, 240 nm, 260 nm, 280 nm, etc.

[0022] In the technical solution of the embodiment of the present application, the thickness of the first hard mask can be adjusted as needed.

[0023] In some embodiments, the etching depth of the silicon substrate is 300 - 1500 nm, such as 320 nm, 440 nm, 580 nm, 620 nm, 780 nm, 900 nm, 1000 nm, etc., and the thickness of the second hard mask is 50 - 150 nm, such as 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, etc.

[0024] In the technical solution of the embodiment of the present application, the thickness of the second hard mask can be adjusted as needed.

[0025] In some embodiments, in step (1), the deposition method of the first hard mask includes low-pressure chemical vapor deposition (LPCVD) and / or plasma-enhanced chemical vapor deposition (PECVD).

[0026] In some embodiments, in step (1), the deposition method of the second hard mask includes thermal oxidation, low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0027] As an example, in step (1), the deposition method of the anti-reflection coating (BARC) includes spin coating or chemical vapor deposition.

[0028] As an example, the material of the anti-reflection coating includes a high molecular polymer composed of carbon, hydrogen and oxygen. For example, the composition of the material of the anti-reflection coating includes by mass percentage: 75%-85% propylene glycol monomethyl ether, 10%-20% propylene glycol monoethyl ether, 0.1%-1.0% amide methyl ether cross-linking agent, 1.0%-10.0% acrylic polymer, <1.0% 2-methoxy-1-propanol and <1.0% surfactant.

[0029] As an example, in step (1), the deposition method of the photoresist includes spin coating.

[0030] As an example, in step (2), the etching methods of at least part of the photoresist, anti-reflection coating, second hard mask and first hard mask include reactive ion etching (RIE), inductively coupled plasma etching (ICP), electron cyclotron resonance plasma etching (ECR), plasma etching or ion beam etching (IBE), etc.

[0031] In some embodiments, in step (3), the etching temperature of the silicon substrate is 5-20°C, such as 12°C, 14°C, 16°C, 18°C, etc.

[0032] As an example, the etching time of the silicon substrate is 10-120 s, such as 20 s, 40 s, 60 s, 80 s, 100 s, etc.

[0033] In some embodiments, in step (3), the etching gas of the silicon substrate includes sulfur hexafluoride (SF6) and oxygen.

[0034] As an example, the gas flow rate of sulfur hexafluoride is 25 - 45 sccm, preferably 30 sccm, such as 30 sccm, 35 sccm, 40 sccm, etc.;

[0035] The gas flow rate of oxygen is 10 - 30 sccm, preferably 25 sccm, such as 15 sccm, 20 sccm, 25 sccm, etc.

[0036] As an example, the pressure for etching the silicon substrate is 20 - 60 mt, such as 30 mt, 40 mt, 50 mt, etc.

[0037] As an example, the upper radio frequency power for etching the silicon substrate is 300 - 800 W, preferably 500 W, such as 400 W, 500 W, 600 W, 700 W, etc.

[0038] The lower radio frequency voltage for etching the silicon substrate is 150 - 200 V, preferably 165 V, such as 160 V, 170 V, 180 V, 190 V, etc.

[0039] In step (3) of the present application, while etching the silicon substrate, the second hard mask can be removed simultaneously.

[0040] As an example, in step (3), the method for removing the first hard mask includes dry etching and / or wet etching, and wet etching is further preferred. This method causes less damage to the silicon substrate. Common wet etching solutions for removing silicon dioxide include: hydrofluoric acid (HF) and / or buffered oxide etchant (BOE).

[0041] In some embodiments, the minimum pattern resolution of the optical chip is 100 - 250 nm, such as 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, etc.

[0042] Preferably, the optical chip includes a metasurface optical chip.

[0043] In some embodiments, the preparation method includes the following steps:

[0044] (1) Deposit a first hard mask, a second hard mask, an antireflection layer, and a photoresist on the surface of the silicon substrate in sequence;

[0045] The material of the first hard mask includes silicon dioxide, and the material of the second hard mask includes amorphous silicon;

[0046] The thickness ratio of the first hard mask to the second hard mask is (1 - 6):1;

[0047] (2)Etch at least part of the photoresist, antireflection layer, second hard mask, and first hard mask successively according to the structure of the optical chip;

[0048] (3)Remove the glue and clean it to obtain a silicon substrate containing at least part of the second hard mask and the first hard mask. Etch the silicon substrate in an atmosphere of sulfur hexafluoride and oxygen at a temperature of 5-20 °C to remove the second hard mask and the first hard mask, and obtain the optical chip.

[0049] In a second aspect, the present application provides an optical chip obtained by the preparation method described in the first aspect.

[0050] Compared with the prior art, the technical solution of the present application has at least the following advantages:

[0051] (1) The preparation method described in the present application can prepare optical chips with small linewidth dimensions and high aspect ratios, especially metasurface optical chips.

[0052] (2) The preparation method described in the present application is compatible with the CMOS process, applicable to a conventional CMOS production line, and can be mass-produced.

[0053] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the following specifically illustrates the specific implementation manners of the present application. Description of the Drawings

[0054] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0055] Figure 1 It is a schematic diagram of depositing the first hard mask in the preparation method of some embodiments of the present application;

[0056] Figure 2 It is a schematic diagram of depositing the second hard mask in the preparation method of some embodiments of the present application;

[0057] Figure 3 It is a schematic diagram of coating the photoresist and the antireflection layer in the preparation method of some embodiments of the present application;

[0058] Figure 4 It is a schematic diagram of photolithography in the preparation method of some embodiments of the present application;

[0059] Figure 5 It is a schematic diagram of etching the antireflection layer in the preparation method of some embodiments of the present application;

[0060] Figure 6 Schematic diagram of etching the second hard mask in the preparation method of some embodiments of the present application;

[0061] Figure 7 Schematic diagram of etching the first hard mask in the preparation method of some embodiments of the present application;

[0062] Figure 8 Schematic diagram of resist stripping and cleaning in the preparation method of some embodiments of the present application;

[0063] Figure 9 Schematic diagram of etching the silicon substrate in the preparation method of some embodiments of the present application;

[0064] Figure 10 Schematic diagram of removing the second hard mask in the preparation method of some embodiments of the present application;

[0065] Figure 11 Schematic diagram of removing the first hard mask in the preparation method of some embodiments of the present application;

[0066] Wherein, 1 - silicon substrate; 2 - first hard mask; 3 - second hard mask; 4 - anti-reflection layer; 5 - photoresist.

[0067] Figure 12 Scanning electron microscope image of the optical chip obtained by the preparation method of some embodiments of the present application;

[0068] Figure 13 Magnified scanning electron microscope image of the optical chip obtained by the preparation method of some embodiments of the present application. Detailed implementation manners

[0069] Hereinafter, embodiments of the technical solutions of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and thus are only examples and should not be used to limit the protection scope of the present application.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above accompanying drawing descriptions are intended to cover non-exclusive inclusion.

[0071] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality" is more than two, unless otherwise specifically defined.

[0072] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0073] The "range" disclosed in the present application is defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of the specific range. The range defined in this way can include the end values or not include the end values, and can be combined arbitrarily, that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, ranges of 60-110 and 80-120 are also contemplated. In addition, if the minimum range values 1 and 2 are listed, and if the maximum range values 3, 4, and 5 are listed, then the following ranges are all contemplated: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In the present application, unless otherwise specified, the numerical range "a-b" represents an abbreviated representation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "2-10" means that all real numbers between "2-10" are fully listed herein, and "2-10" is only an abbreviated representation of these numerical combinations. Additionally, when stating that a certain parameter is an integer ≥2, it is equivalent to disclosing that the parameter is, for example, the integers 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0074] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " in this document generally represents an "or" relationship between the associated objects before and after.

[0075] Embodiment 1

[0076] This embodiment provides a method for preparing a metasurface optical chip. The schematic diagram is as Figure 1-11 shown, and the preparation method includes the following steps:

[0077] As shown Figure 1 in FIG. 1, a first hard mask 2 is deposited on the surface of the silicon substrate 1 by thermal oxidation; specifically, the material of the first hard mask is silicon dioxide and the thickness is 250 nm.

[0078] As shown Figure 2 in FIG. 2, a second hard mask 3 is deposited on the surface of the first hard mask 2 by LPCVD, and the silicon substrate 1, the first hard mask 2, and the second hard mask 3 are stacked in sequence; specifically, the material of the second hard mask is amorphous silicon and the thickness is 100 nm; the etching depth of the silicon substrate, and the thickness ratio of the first hard mask and the second hard mask is 10:2.5:1. Figure 2 In FIG. 3, the irregularity of the lower bottom surface of the silicon substrate represents that the silicon substrate is relatively thick and is not completely drawn in the figure, which does not mean uneven thickness.

[0079] As shown Figure 3 in FIG. 4, an anti-reflection layer 4 and a photoresist 5 are sequentially deposited on the surface of the second hard mask, and the silicon substrate 1, the first hard mask 2, the second hard mask 3, the anti-reflection layer 4 (the material includes 15% propylene glycol monoethyl ether, 0.5% amide methyl ether cross-linking agent, 5% acrylic polymer, 0.5% 2-methoxy-1-propanol, 0.5% surfactant sodium dodecylsulfonate, up to 100% propylene glycol monomethyl ether) and the photoresist 5 are stacked in sequence.

[0080] As shown Figure 4 in FIG. 5, lithography is performed according to the structure of the optical chip, and the silicon substrate 1, the first hard mask 2, the second hard mask 3, the anti-reflection layer 4, and the photoresist 5 are stacked in sequence, and part of the photoresist 5 is removed.

[0081] As shown Figure 5 in FIG. 6, lithography is performed, and the silicon substrate 1, the first hard mask 2, the second hard mask 3, the anti-reflection layer 4, and the photoresist 5 are stacked in sequence, and part of the anti-reflection layer 4 is removed.

[0082] As shown Figure 6 in FIG. 7, the second hard mask is etched, and the silicon substrate 1, the first hard mask 2, the second hard mask 3, the anti-reflection layer 4, and the photoresist 5 are stacked in sequence, and part of the second hard mask 3 is removed.

[0083] As shown Figure 7 in FIG. 8, the first hard mask is etched, and the silicon substrate 1, the first hard mask 2, the second hard mask 3, the anti-reflection layer 4, and the photoresist 5 are stacked in sequence, and part of the first hard mask 2 is removed.

[0084] As shown Figure 8 in FIG. 9, the photoresist is removed and the substrate is cleaned, and the silicon substrate 1, the first hard mask 2, and the second hard mask 3 are stacked in sequence, and the remaining photoresist and anti-reflection layer are removed.

[0085] As shown Figure 9As shown, the silicon substrate is etched. The silicon substrate 1, the first hard mask 2, and the second hard mask 3 are stacked in sequence. According to the patterning design, a part of the silicon substrate 1 is removed.

[0086] As Figure 10 shown, while etching the silicon substrate, the remaining second hard mask can be removed to obtain the shown structure, where the silicon substrate 1 and the first hard mask 2 are stacked; specifically, the etching parameters are as follows: pressure: 40 mt; upper radio frequency power: 500 W; lower radio frequency voltage: 165 V; etching gas: SF 6: 35 sccm and O 2: 20 sccm; time: 65 s; temperature 15 °C.

[0087] As Figure 11 shown, the remaining first hard mask is removed, and the remaining patterned silicon substrate 1 is obtained to obtain the optical chip.

[0088] Taking Example 1 as an example, the surface topography of the metasurface optical chip obtained by the preparation method is tested, and the results are as Figure 12 and Figure 13 shown. The present application can realize the preparation of a silicon-based metasurface optical chip with a small line width size of 200 nm and a high aspect ratio.

[0089] Example 2

[0090] The present embodiment provides a method for preparing an optical chip, and the preparation method includes the following steps:

[0091] Deposit the first hard mask on the surface of the silicon substrate by thermal oxidation; specifically, the material of the first hard mask is silicon dioxide, and the thickness is 200 nm.

[0092] Deposit the second hard mask on the surface of the first hard mask, and the silicon substrate, the first hard mask, and the second hard mask are stacked in sequence; specifically, the material of the second hard mask is amorphous silicon, and the thickness is 120 nm; the etching depth of the silicon substrate, and the thickness ratio of the first hard mask and the second hard mask is 3:1.67:1.

[0093] Deposit an anti-reflection layer and a photoresist on the surface of the second hard mask in sequence, and the silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are stacked in sequence.

[0094] According to the structure of the optical chip, perform photolithography. The silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are stacked in sequence, and a part of the photoresist is removed.

[0095] Perform photolithography. The silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are stacked in sequence, and a part of the anti-reflection layer is removed.

[0096] Etch the second hard mask. The silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are sequentially stacked, and part of the second hard mask is removed.

[0097] Etch the first hard mask. The silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are sequentially stacked, and part of the first hard mask is removed.

[0098] Strip the photoresist and clean. The silicon substrate, the first hard mask, and the second hard mask are sequentially stacked, and the remaining photoresist and anti-reflection layer are removed.

[0099] Etch the silicon substrate. The silicon substrate, the first hard mask, and the second hard mask are sequentially stacked, and part of the silicon substrate is removed according to the patterning design.

[0100] While etching the silicon substrate, the remaining second hard mask can be removed to obtain the shown structure. The silicon substrate and the first hard mask are stacked; specifically, the etching parameters are as follows: pressure: 40 mt; upper RF power: 500 W; lower RF voltage: 165 V; etching gas: SF 6: 45 sccm and O 2: 30 sccm; time: 40 s; temperature 5 °C.

[0101] Remove the remaining first hard mask, and the remaining patterned silicon substrate to obtain the optical chip.

[0102] This embodiment can achieve the preparation of a silicon-based metasurface optical chip with a small line width size of 200 nm and a high aspect ratio.

[0103] Example 3

[0104] This embodiment provides a method for preparing an optical chip, and the preparation method includes the following steps:

[0105] Deposit the first hard mask on the surface of the silicon substrate by thermal oxidation; specifically, the material of the first hard mask is silicon dioxide, and the thickness is 300 nm.

[0106] Deposit the second hard mask on the surface of the first hard mask by LPCVD. The silicon substrate, the first hard mask, and the second hard mask are sequentially stacked; specifically, the material of the second hard mask is amorphous silicon, and the thickness is 50 nm; the etching depth of the silicon substrate, and the thickness ratio of the first hard mask and the second hard mask is 12:6:1.

[0107] Deposit the anti-reflection layer and the photoresist on the surface of the second hard mask in sequence. The silicon substrate, the first hard mask, the second hard mask, the anti-reflection layer, and the photoresist are sequentially stacked.

[0108] According to the structure of the optical chip, photolithography is performed, and a silicon substrate, a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist are sequentially stacked, and a part of the photoresist is removed.

[0109] Photolithography is performed, and a silicon substrate, a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist are sequentially stacked, and a part of the anti-reflection layer is removed.

[0110] The second hard mask is etched. A silicon substrate, a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist are sequentially stacked, and a part of the second hard mask is removed.

[0111] The first hard mask is etched. A silicon substrate, a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist are sequentially stacked, and a part of the first hard mask is removed.

[0112] The photoresist is removed and the substrate is cleaned. A silicon substrate, a first hard mask, and a second hard mask are sequentially stacked, and the remaining photoresist and anti-reflection layer are removed.

[0113] The silicon substrate is etched. A silicon substrate, a first hard mask, and a second hard mask are sequentially stacked, and a part of the silicon substrate is removed according to the patterning design.

[0114] While etching the silicon substrate, the remaining second hard mask can be removed to obtain the shown structure, where the silicon substrate and the first hard mask are stacked; specifically, the etching parameters are as follows: pressure: 40 mt; upper radio frequency power: 500 W; lower radio frequency voltage: 165 V; etching gas: SF6: 25 sccm and O 2: 10 sccm; time: 100 s; temperature 20 °C.

[0115] The remaining first hard mask is removed, and the remaining patterned silicon substrate is obtained to obtain the optical chip.

[0116] This embodiment can achieve the preparation of a silicon-based metasurface optical chip with a small line width size of 200 nm and a high aspect ratio.

[0117] Example 4-5

[0118] The difference between Example 4-5 and Example 1 is that the thickness of the first hard mask remains unchanged, and the thickness ratio of the first hard mask to the second hard mask is adjusted. The thickness ratios are 0.5:1 (Example 4) and 6.5:1 (Example 5), and the rest are the same as Example 1.

[0119] Analysis of Examples 4-5 and Example 1 shows that the performance of Examples 4-5 is inferior to that of Example 1. Specifically, in Example 4, the thickness ratio of the first hard mask to the second hard mask is on the low side, the thickness of the amorphous silicon increases, which poses higher requirements for the selectivity between the photoresist and the amorphous silicon. When the amorphous silicon thickens, the photoresist needs to be thicker, thus affecting the lithography resolution. In Example 5, when etching the first hard mask (such as silicon dioxide) using the second hard mask (amorphous silicon) as the mask, the thickness ratio of the first hard mask to the second hard mask is on the high side, increasing the requirements for the selectivity between the amorphous silicon and the silicon dioxide. When the selectivity is insufficient, the amorphous silicon is etched completely but the silicon dioxide is not fully opened, resulting in the incomplete transfer of the amorphous silicon pattern to the silicon dioxide layer and ultimately causing pattern distortion. It is proved that adjusting the thickness ratio of the first hard mask to the second hard mask within the range of (1-6):1 is more conducive to obtaining a metasurface optical chip with small linewidth dimensions and high aspect ratios.

[0120] Examples 6-7

[0121] The differences between Examples 6-7 and Example 1 lie in keeping the etching depth of the silicon substrate unchanged and adjusting the thickness ratio of the etching depth of the silicon substrate to the second hard mask. The thickness ratios of the two are 0.5:1 (Example 6) and 13:1 (Example 7), respectively, and the rest are the same as those in Example 1.

[0122] Analysis of Examples 6-7 and Example 1 shows that the performance of Examples 6-7 is inferior to that of Example 1. Specifically, in Example 6, the thickness ratio of the etching depth of the silicon substrate to the second hard mask is on the low side, resulting in an increase in the thickness of the first hard mask. Therefore, when etching the second hard mask, the thickness of the photoresist needs to be increased, leading to an increase in the lithography difficulty and a decrease in the lithography resolution. In Example 7, the thickness ratio of the two is on the high side, which increases the requirements for the selectivity between the second hard mask and the first hard mask, and at the same time increases the requirements for the selectivity between the first hard mask and the silicon substrate. When the selectivity is insufficient, the second hard mask cannot block during the etching of the silicon dioxide or the first hard mask cannot block during the etching of the silicon substrate, ultimately resulting in abnormal patterns. It is proved that adjusting the thickness ratio of the etching depth of the silicon substrate to the second hard mask within the range of (1-12):1 is more conducive to obtaining a metasurface optical chip with small linewidth dimensions and high aspect ratios.

[0123] Comparative Example 1

[0124] The difference between this comparative example and Example 1 is that the material of the second hard mask is replaced from amorphous silicon to silicon nitride, and the rest are the same as those in Example 1.

[0125] The comparative example 1 is inferior to the example 1, specifically manifested in that a higher selectivity can be obtained between amorphous silicon and silicon dioxide, far higher than the selectivity between silicon nitride and silicon dioxide. With a higher selectivity, a thinner hard mask can be used to obtain higher resolution and conformality; it is proved that the preparation method described in this application is more conducive to obtaining a metasurface optical chip with a small line width size and a high aspect ratio.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be covered by the scope of the claims and the specification of the present application. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for preparing an optical chip, characterized in that, The preparation method includes the following steps: (1) Deposit a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist on the surface of the silicon substrate in sequence; The material of the second hard mask includes amorphous silicon; (2) Etch at least part of the photoresist, anti-reflection layer, second hard mask, and first hard mask in sequence according to the structure of the optical chip; (3) Remove the photoresist and clean it to obtain a silicon substrate containing at least part of the second hard mask and the first hard mask, etch the silicon substrate, and remove the second hard mask and the first hard mask to obtain the optical chip.

2. The preparation method according to claim 1, wherein The material of the first hard mask includes silicon dioxide.

3. The preparation method according to claim 1 or 2, characterized in that, The thickness ratio of the first hard mask to the second hard mask is (1-6):1, and further preferably (1.5-3.5):1; Preferably, the etching depth ratio of the silicon substrate to the thickness of the second hard mask is (1-12):1, and further preferably (5-10):

1.

4. The preparation method according to any one of claims 1-3, characterized in that, The etching depth of the silicon substrate is 300-1500 nm, and the thickness of the first hard mask is 200-300 nm.

5. The preparation method according to any one of claims 1-4, characterized in that, The etching depth of the silicon substrate is 300-1500 nm, and the thickness of the second hard mask is 50-150 nm.

6. The preparation method according to any one of claims 1-5, characterized in that, In step (1), the deposition method of the first hard mask includes low-pressure chemical vapor deposition and / or plasma-enhanced chemical vapor deposition; Preferably, in step (1), the deposition method of the second hard mask includes thermal oxidation, low-pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

7. The preparation method according to any one of claims 1-6, characterized in that, In step (3), the etching temperature of the silicon substrate is 5-20 °C; Preferably, in step (3), the etching gas of the silicon substrate includes sulfur hexafluoride and oxygen.

8. The preparation method according to any one of claims 1-7, characterized in that, The minimum pattern resolution of the optical chip is 100-250 nm; Preferably, the optical chip includes a metasurface optical chip.

9. The preparation method according to any one of claims 1-8, characterized in that, The preparation method includes the following steps: (1) Deposit a first hard mask, a second hard mask, an anti-reflection layer, and a photoresist on the surface of the silicon substrate in sequence; The material of the first hard mask includes silicon dioxide, and the material of the second hard mask includes amorphous silicon; The thickness ratio of the first hard mask to the second hard mask is (1-6):1; (2) Etch at least part of the photoresist, anti-reflection layer, second hard mask, and first hard mask in sequence according to the structure of the optical chip; (3) Remove the photoresist and clean it to obtain a silicon substrate containing at least part of the second hard mask and the first hard mask, and etch the silicon substrate in an atmosphere of sulfur hexafluoride and oxygen at a temperature of 5-20 °C to remove the second hard mask and the first hard mask to obtain the optical chip.

10. An optical chip, characterized in that, The optical chip is obtained by the preparation method according to any one of claims 1-9.

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