Counting system with zero cumulative error and driving method thereof
By setting the counting frequency and counting string at the transmitter end of the counter, combined with the Gray code encoding and bit compensation module, the cumulative error and clock domain crossover problems in the counting system are solved, and a counting system with zero cumulative error and low power consumption is realized.
Patent Information
- Application Number
- CN202510074681.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-17
- Filing Date
- 2025-01-17
- Publication Date
- 2025-07-18
AI Technical Summary
The operation of counters in different clock domains in the prior art may introduce quantization errors and timeline offsets, resulting in accumulated errors, increasing hardware space and power consumption, and the clock domain crossover problem has not been effectively solved.
By setting the counting frequency at the transmitting end of the counter, setting the first time counting string is greater than the original time counting string, setting the second time counting string is less than the original time counting string, and accumulating these two counting strings in multiple cycles to generate the transmitting end time counting string, and using the Gray code encoding and bit compensation module to achieve zero accumulation error.
It realizes zero cumulative errors of counting systems in different clock domains, solves the clock domain crossover problem, and reduces hardware space and power consumption.
Smart Images
Figure CN120335551A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a counting system and its driving method, particularly to a counting system with zero cumulative error and its driving method. Background Art
[0002] With the rapid development of technology, various operating systems are adopted in computer applications according to their standards. For example, the operating frequency of the Advanced RISC Machine (ARM) architecture is specified as 1 GHz. To align with the Central Processing Unit (CPU) timeline, some subsystems rely on the same system counter to perform their synchronization. Generally, the system counter and other processors operate in different clock domains. Therefore, digital encoded bits can be used to achieve communication between the system counter and other processors.
[0003] However, if the operating frequency is lower than 1 GHz and not a factor of 1 GHz, quantization errors and timeline offsets may be introduced. Since these errors accumulate over time, serious counter biases may occur. In addition, the clock domain crossing (CDC) problem still exists. Currently, additional hardware may be needed to mitigate the cumulative errors and CDC problems. As a result, additional hardware space and high power consumption are inevitably increased. Therefore, developing a zero cumulative error counting system applicable to different clock domains is an important issue. Summary of the Invention
[0004] In an embodiment of the present invention, a driving method for a counting system with zero cumulative error is provided. The method includes setting a counting frequency of a counter transmitter, setting an original time counting string according to the counting frequency, setting a first time counting string of the counter to be greater than the original time counting string, setting a second time counting string of the counter to be less than the original time counting string, and accumulating at least one of the first time counting string and at least one of the second time counting string in N periods to generate a transmitter time counting string. Wherein N is greater than 2, and the real-time string generated by the original time counting string in the N periods is equal to the transmitter time counting string.
[0005] In another embodiment of the present invention, a counting system with zero cumulative error is provided. The counting system includes a counter transmitting end and a counter receiving end. The counter transmitting end includes a counting module and a bit truncation module connected to the counting module. The counter receiving end includes a digital decoder connected to the digital encoder of the counter transmitting end and a bit compensation module connected to the digital decoder. The counter transmitting end sets a counting frequency. The counter transmitting end sets an original time counting string according to the counting frequency. The counter transmitting end sets a first time counting string of the counter greater than the original time counting string. The counter transmitting end sets a second time counting string of the counter less than the original time counting string. The counting module accumulates at least one of the first time counting strings and at least one of the second time counting strings in N periods to generate a transmitting end time counting string. Where N is greater than 2. The real-time string generated by the original time counting string in the N periods is equal to the transmitting end time counting string.
[0006] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments depicted in the various figures and charts. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings:
[0008] Figure 1 is a block diagram of a counting system with zero cumulative error according to an embodiment of the present invention;
[0009] Figure 2 is Figure 1 a data flow diagram of the counter transmitting end of the counting system in
[0010] Figure 3 is Figure 1 a data flow diagram of the counter receiving end of the counting system in
[0011] Figure 4 is a flowchart of the method for driving the counting system in Figure 1 DETAILED DESCRIPTION OF THE EMBODIMENTS
[0012] Figure 1 FIG. 0 is a block diagram of a counting system 100 with zero cumulative error according to an embodiment of the present invention. The counting system 100 includes a counter transmitter 10 and a counter receiver 11. The counter transmitter 10 includes a counting module 10a, a bit truncation module 10b, and a digital encoder 10c. The counting module 10a includes an adder 10a1 and a counter 10a2. The adder 10a1 is connected to the counter 10a2 in a closed-loop feedback manner. The bit truncation module 10b is connected to the counting module 10a. The digital encoder 10c is connected to the bit truncation module 10b. The counter receiver 11 includes a digital decoder 11a and a bit compensation module 11b. The digital decoder 11a is connected to the digital encoder 10c of the counter transmitter 10. The bit compensation module 11b is connected to the digital decoder 11a. In this counting system 100, the counter transmitter 10 sets a counting frequency. The counter transmitter 10 sets an original time count string according to the counting frequency. The counter transmitter 10 sets a first time count string of a counter to be greater than the original time count string. The counter transmitter 10 sets a second time count string of the counter to be less than the original time count string. The counting module 10a accumulates at least one first time count string and at least one second time count string in N cycles to generate a transmitter time count string. Here, N is greater than 2. The real-time string generated from the original time count string in N cycles is equal to the transmitter time count string. Since the real-time string is equal to the transmitter time count string in N cycles, no cumulative error is introduced into the counting system 100. The details of driving the counting system 100 are described below.
[0013] Figure 2 FIG. 4 is a data flow diagram of the counter transmitter 10 in the counting system 100. As described above, the counter transmitter 10 sets the counting frequency. For example, the operating frequency of the advanced RISC machine (ARM) architecture is specified as 1 GHz. The counting frequency can be set to 13 MHz (hertz). Then, the counter transmitter 10 can set the original time count string according to the counting frequency. For example, an original time count string corresponding to 1000 / 13 = 76.92 ns (nanoseconds) can be set. Here, the original time count string is a floating-point value. Then, the counter transmitter 10 sets a first time count string of the counter to be greater than the original time count string. The counter transmitter 10 sets a second time count string of the counter to be less than the original time count string. For example, the first time count string can be the ceiling function output of the original time count string. As a result, the first time count string can be set to 77 (in decimal representation). The second time count string can be the floor function output of the original time count string. As a result, the second time count string can be set to 76 (in decimal representation). In Figure 2In [the system], the input data D1 includes at least one first time count string and at least one second time count string in N cycles. By using the adder 10a1 and the counter 10a2, at least one first time count string and at least one second time count string can be accumulated to generate the transmitter end time count string D2 over time. For example, at least one first time count string and at least one second time count string can be accumulated to generate a 64-bit transmitter end time count string D2. Here, 64 bits can be used to ensure that the maximum time count can be represented as the transmitter end time count string D2 (i.e., less than 64 bits).
[0014] In the counting system 100, since the first time count string (77) and the second time count string (76) can be regarded as two binary string values close to 76.92, at least one first time count string (77) and at least one second time count string (76) can be accumulated to approximate the real-time string generated by the original time count string (i.e., 76.92) in N cycles, such as 76.92×N. The N cycles, the transmitter end time count string D2, the input data D1, the real-time string, and the timing error can be represented in Table 1.
[0015] Table 1
[0016]
[0017] In Table 1, the real-time string is equal to the transmitter end time count string D2 in 13 cycles. Specifically, the timing error of the counter transmitter end 10 of the counting module 10a in each cycle is a positive timing error or a negative timing error. For example, the timing error in the 6th cycle is 0.46153846. The timing error in the 7th cycle is -0.4615385. In Table 1, the cumulative error of the counter transmitter end 10 of the counting module 10a in 13 cycles is zero.
[0018] In Figure 2 [the system], the digital encoder 10c is a Gray code encoder. Therefore, in order to meet the Gray code requirements, the bit truncation module 10b can be introduced into the counter transmitter end 10. The bit truncation module 10b can truncate the Q least significant bits (LSBs) of the transmitter end time count string D2 to generate the truncated transmitter end time count string D3. 2 Q is greater than the decimal value of the first time count string. For example, the decimal value of the first time count string is equal to 77. Q can be set to 7 to meet 2 7= 128 > 77. Then, when the transmitter time count string D2 has 64 bits, the bit truncation module 10b can truncate 7 LSB bits of the transmitter time count string D2 to generate a truncated transmitter time count string D3 with 57 bits. Then, the digital encoder 10c can encode the truncated transmitter time count string D3 to generate an encoded transmitter time count string D4. In particular, since the digital encoder 10c is a Gray code encoder and the coding rate of the Gray code encoder is one. Therefore, the encoded transmitter time count string D4 has 57 bits.
[0019] In the counting system 100, since 2 Q is greater than the decimal value of the first time count string (i.e., 77), after the transmitter time count string D2 is truncated by Q LSB bits, the Hamming distance between two consecutive encoded transmitter time count strings D4 in two consecutive periods is less than or equal to 1. Therefore, the codeword set of the encoded transmitter time count string D4 satisfies the conditions of the Gray code. As a result, the counting system 100 of the counter transmitter 10 can implement the Gray code encoding mechanism.
[0020] Figure 3 is the data flow diagram of the counter receiver 11 in the counting system 100. As described above, the encoded transmitter time count string D4 is a Gray code word. Therefore, a digital decoder 11a of the counter receiver 11 can be introduced. The digital decoder 11a can decode the encoded transmitter time count string D4 to generate a decoded receiver time count string D5. The digital decoder 11a is a Gray code decoder. For example, the encoded transmitter time count string D4 with 57 bits can be decoded by the digital decoder 11a to generate a decoded receiver time count string D5 with 57 bits. Then, the bit compensation module 11b can fill Q zero bits into the decoded receiver time count string D5 to generate a receiver time count compensation string D6. For example, the bit compensation module 11b can fill 7 zero bits into the decoded receiver time count string D5 with 57 bits to generate a receiver time count compensation string D6 with 64 bits. As a result, the bit length of the receiver time count compensation string D6 is equal to that of the transmitter time count string D4 (i.e., 64 bits).
[0021] In the counting system 100, although the encoded transmitter time count string D4 slightly sacrifices the accuracy of aligning the time lines in each period, the clock domain crossing (CDC) problem can be solved by implementing the Gray code mechanism because the conditions of the Gray code can be satisfied. In addition, the cumulative error of the counter receiver in M periods is still zero. M is greater than 2. For simplicity, M periods, the encoded transmitter time count string D4, the decoded receiver time count string D5, the real-time string, and the timing error can be represented in Table 2.
[0022] Table 2
[0023]
[0024]
[0025] In Table 2, the real-time string is equal to the decoded receiver time count string D5 in 208 cycles. The decimal value (time line) of the receiver time count compensation string D6 is equal to the decimal value (time line) of the decoded receiver time count string D5 because the receiver time count compensation string D6 is generated by filling Q zero bits at the Q LSB addresses of the decoded receiver time count string D5. Specifically, the timing error of the counter receiver 11 in each cycle is a positive timing error or a negative timing error. In Table 2, the cumulative error of the counter receiver 11 in 208 cycles is zero. In addition, since the encoded transmitter time count string D4 has 57 bits, this means that 7 truncated bits may cause information loss. As a result, the maximum absolute timing error of the counter receiver 11 in each cycle is less than 2 Q (nanoseconds), for example 2 7 = 128 (nanoseconds). However, the counter transmitter 10 and the counter receiver 11 of the counting system 100 do not introduce cumulative errors.
[0026] Figure 4 is a flowchart of a method for driving the counting system 100. The method for driving the counting system 100 includes steps S401 to step S405. Any technical or hardware modifications fall within the scope of the present invention. Steps S401 to S405 are as follows.
[0027] Step S401: Set the counting frequency of the counter transmitter 10;
[0028] Step S402: Set the original count string according to the counting frequency;
[0029] Step S403: Set the first time count string of the counter to be greater than the original time count string;
[0030] Step S404: Set the second time count string of the counter to be less than the original time count string;
[0031] Step S405: Accumulate at least one of the first time count strings and at least one of the second time count strings in N cycles to generate a transmitter time count string.
[0032] The details of steps S401 to S405 have been described above. Therefore, they are omitted here. In the counting system 100, since at least one first time counting string and at least one second time counting string are introduced. The timing error in each cycle is a positive timing error or a negative timing error. As a result, after accumulating at least one first time counting string and at least one second time counting string in N cycles, the cumulative error of the counting system 100 can be completely eliminated. Therefore, when the counting system 100 operates over time, no error accumulation is introduced.
[0033] In summary, the present invention discloses a counting system with zero cumulative error. The counting system uses at least two different values to eliminate the cumulative timing error in several cycles. Although a positive timing error or a negative timing error may be introduced in each cycle, they cancel each other out over time. As a result, when the counting system operates over time, no error accumulation is introduced. In addition, the Hamming distance between two encoded transmitter time counting strings in two consecutive cycles satisfies the conditions of the Gray code. The counting system can implement the Gray code encoding mechanism. Therefore, by using the counting system of the present invention, the clock domain crossing problem can be solved.
[0034] Those skilled in the art will readily observe that many modifications and changes can be made to the devices and methods while retaining the teaching of the invention. Therefore, the above disclosure should be limited only to the scope of the appended claims.
Claims
1. A driving method for a counting system with zero cumulative error, characterized in that, Comprising: Setting a counting frequency of a counter transmitter; Setting an original time counting string according to the counting frequency; Setting a first time counting string of the counter to be greater than the original time counting string; Setting a second time counting string of the counter to be less than the original time counting string; And Accumulating at least one of the first time counting strings and at least one of the second time counting strings in N cycles to generate a transmitter time counting string; Where N is greater than 2, and the real-time string generated by the original time counting string in the N cycles is equal to the transmitter time counting string.
2. The method according to claim 1, wherein The first time counting string is the output of the ceiling function of the original time counting string, the second time counting string is the output of the floor function of the original time counting string, and the original time counting string is a floating-point value.
3. The method according to claim 1, characterized in that, The transmission-end time count string is generated in the form of P binary digits, and 2 P is greater than the transmission-end time count string.
4. The method according to claim 1, wherein The timing error of the counter transmitter in each cycle is a positive timing error or a negative timing error, and the cumulative error of the counter transmitter in the N cycles is zero.
5. The method according to claim 1, characterized in that, Further comprising: Truncating Q least significant bits of the transmitter time counting string to generate a truncated transmitter time counting string; And Encoding the truncated transmitter time counting string through a digital encoder of the counter transmitter to generate an encoded transmitter time counting string; Among which 2 Q is greater than the decimal value of the first time counting string.
6. The method according to claim 5, wherein The Hamming distance between two encoded transmitter time counting strings in two consecutive cycles is less than or equal to 1.
7. The method according to claim 5, wherein Further comprising: Decoding the encoded transmitter time counting string through a digital decoder of the counter receiver to generate a decoded receiver time counting string; Where the decoding frequency of the counter receiver is equal to the counting frequency of the counter transmitter.
8. The method according to claim 5, wherein Further comprising: Padding Q zero bits to the decoded receiver time counting string to generate a receiver time counting compensation string; Where the bit length of the receiver time counting compensation string is equal to the transmitter time counting string.
9. The method according to claim 7, wherein The timing error of the counter receiving end in each cycle is a positive timing error or a negative timing error, and the maximum absolute timing error of the counter receiving end in each cycle is less than 2 Q , the cumulative error of the counter receiving end in M cycles is zero, and M is greater than 2.
10. The method according to claim 7, wherein The digital encoder is a Gray code encoder, and the digital decoder is a Gray code decoder.
11. A counting system with zero cumulative error, characterized in that, Comprising: A counter transmitter, comprising: A counting module; A bit truncation module connected to the counting module; and A digital encoder connected to the bit truncation module; and A counter receiver, comprising: A digital decoder connected to the digital encoder of the counter transmitter; and A bit compensation module connected to the digital decoder; Where the counter transmitter sets a counting frequency, the counter transmitter sets an original time counting string according to the counting frequency, the counter transmitter sets a first time counting string of the counter to be greater than the original time counting string, the counter transmitter sets a second time counting string of the counter to be less than the original time counting string, the counting module accumulates at least one of the first time counting strings and at least one of the second time counting strings in N cycles to generate a transmitter time counting string, N is greater than 2, and the real-time string generated by the original time counting string in the N cycles is equal to the transmitter time counting string.
12. The system according to claim 11, wherein, The first time count string is the ceiling function output of the original time count string, the second time count string is the floor function output of the original time count string, and the original time count string is a floating-point value.
13. The system according to claim 11, wherein The transmission-end time count string is generated in the form of P binary digits, and 2 P is greater than the transmission-end time count string.
14. The system according to claim 11, wherein The timing error of the counter transmitting end of the counting module in each cycle is a positive timing error or a negative timing error, and the cumulative error of the counter transmitting end of the counting module in the N cycles is zero.
15. The system according to claim 11, wherein The bit truncation module truncates the Q least significant bits of the transmitter time count string to generate a truncated transmitter time count string, and the digital encoder encodes the truncated transmitter time count string to generate an encoded transmitter time count string, and 2 Q is greater than the decimal value of the first time count string.
16. The system according to claim 15, characterized in that, The Hamming distance between two encoded transmitting end time count strings in two consecutive cycles is less than or equal to 1.
17. The system according to claim 15, wherein The digital decoder at the counter receiving end decodes the encoded transmitting end time count string to generate a decoded receiving end time count string.
18. The system according to claim 15, wherein The bit compensation module fills Q zero bits into the decoded receiving end time count string to generate a receiving end time count compensation string, and the bit length of the receiving end time count compensation string is equal to that of the transmitting end time count string.
19. The system according to claim 15, characterized in that, The timing error of the counter receiving end in each cycle is a positive timing error or a negative timing error, and the maximum absolute timing error of the counter receiving end in each cycle is less than 2 Q , the cumulative error of the counter receiving end in M cycles is zero, and M is greater than 2.
20. The system according to claim 15, wherein The digital encoder is a Gray code encoder, and the digital decoder is a Gray code decoder.