Memory management method and device, electronic equipment, chip and storage medium

Abstract

The invention relates to a memory management method and device, electronic equipment, a chip and a storage medium. The method comprises the steps of obtaining sampling data of at least one sensor; selecting an idle available storage block from the at least one memory buffer pool as a target storage block; storing the sampling data to a target storage block; in response to the situation that the data volume of the sampling data stored in the target storage block reaches a set data volume threshold value, putting the target storage block into a data buffer; and waking up a central processing unit of the electronic equipment in response to the fact that the number of the storage blocks in the data buffer reaches a set number threshold value. According to the method, idle available storage blocks in a memory buffer pool are used for storing sampling data of each sensor, and after the number of the storage blocks in a data buffer reaches a certain threshold, a central processing unit (CPU) is awakened to process the sampling data, so that the aim of reducing the power consumption of the electronic equipment is fulfilled by reducing the awakening times of the CPU.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a memory management method, apparatus, electronic device, chip, and storage medium. Background Art

[0002] Wearable electronic devices such as electronic watches and bracelets are equipped with many sensors to continuously monitor human health data throughout the day. Most of the time, the electronic devices are in the screen-off standby scenario. Usually, the central processing unit (CPU) in the electronic device is awakened by a general-purpose input / output (GPIO) interrupt or a timer (Timer) interrupt, and then the sampled data of the sensors is obtained for processing. However, the sampled data of most sensors is only a few bytes, and the amount of data processed by the CPU after being awakened is relatively small. In addition, the number of times the CPU is awakened is related to the number of sensors and the sampling frequency of the sensors. The more sensors and the higher the sampling frequency, the more frequently the CPU is awakened, resulting in higher power consumption of the electronic device. Summary of the Invention

[0003] The present disclosure provides a memory management method, apparatus, electronic device, chip, and storage medium. The present disclosure uses idle and available storage blocks in the memory buffer pool to store the sampled data of each sensor, and wakes up the CPU to process the sampled data after the number of storage blocks in the data buffer reaches a certain threshold, so as to reduce the power consumption of the electronic device by reducing the number of times the CPU is awakened. The technical solutions of the present disclosure are as follows:

[0004] According to a first aspect of an embodiment of the present disclosure, a memory management method is provided, including:

[0005] Obtaining sampled data of at least one sensor;

[0006] Selecting an idle and available storage block from at least one memory buffer pool as a target storage block;

[0007] Storing the sampled data into the target storage block;

[0008] In response to the amount of the sampled data stored in the target storage block reaching a set data volume threshold, putting the target storage block into a data buffer;

[0009] In response to the number of storage blocks in the data buffer reaching a set number threshold, waking up the central processor of the electronic device.

[0010] In one embodiment of the present disclosure, before selecting an idle and available storage block from at least one memory buffer pool as the target storage block, the following steps are further included:

[0011] Obtain the data volume of the sampling data of each of the sensors;

[0012] Select at least one target memory buffer pool from at least one memory buffer pool according to the data volume of the sampling data of each of the sensors.

[0013] In one embodiment of the present disclosure, the step of selecting an idle and available storage block from at least one memory buffer pool as the target storage block includes:

[0014] Obtain the number of sensors from which the sampling data of each of the sensors is sourced;

[0015] Select the corresponding number of idle and available storage blocks from at least one of the target memory buffer pools as the target storage block according to the number of sensors from which the sampling data of each of the sensors is sourced.

[0016] In one embodiment of the present disclosure, the step of storing the sampling data in the target storage block includes:

[0017] Obtain the content length, timestamp, and valid data of the sampling data;

[0018] Generate a data packet according to the content length, timestamp, and valid data;

[0019] Store the data packet in the target storage block in the order of acquisition time.

[0020] In one embodiment of the present disclosure, after generating the data packet according to the content length, timestamp, and valid data, the following steps are further included:

[0021] Determine whether the packet length of the data packet reaches a set number of bytes;

[0022] In response to the packet length of the data packet not reaching the set number of bytes, add padding data after the valid data in the data packet according to the packet length of the data packet and the set number of bytes until the packet length of the data packet reaches the set number of bytes.

[0023] In one embodiment of the present disclosure, the content length and timestamp of the sampling data are 4 bytes.

[0024] In one embodiment of the present disclosure, the step of putting the target storage block into the data buffer includes:

[0025] Obtain the attribute information of the target storage block; wherein, the attribute information of the target storage block includes whether there is valid data in the target storage block, the sensor number for obtaining the sampled data, the address of the target storage block, and the content length of the valid data in the target storage block.

[0026] Put the target storage block carrying the attribute information into the data buffer.

[0027] According to the second aspect of the embodiments of the present disclosure, a memory management device is proposed, including:

[0028] An acquisition module, configured to acquire sampled data of at least one sensor;

[0029] A selection module, configured to select an idle and available storage block from at least one memory buffer pool as the target storage block;

[0030] A storage module, configured to store the sampled data into the target storage block;

[0031] A cache module, configured to, in response to the data volume of the sampled data stored in the target storage block reaching a set data volume threshold, put the target storage block into the data buffer;

[0032] A wake-up module, configured to, in response to the number of storage blocks stored in the data buffer reaching a set number threshold, wake up the central processing unit of the electronic device.

[0033] In an embodiment of the present disclosure, before the selection module is configured to select an idle and available storage block from at least one memory buffer pool as the target storage block, it is further configured to:

[0034] Obtain the data volume of the sampled data of each sensor, and select at least one target memory buffer pool from at least one memory buffer pool according to the data volume of the sampled data of each sensor.

[0035] In an embodiment of the present disclosure, when the selection module is configured to select an idle and available storage block from at least one memory buffer pool as the target storage block, it includes:

[0036] Obtain the number of sensors from which the sampled data of each sensor is sourced;

[0037] Select the corresponding number of idle and available storage blocks from at least one of the target memory buffer pools as the target storage block according to the number of sensors from which the sampled data of each sensor is sourced.

[0038] In an embodiment of the present disclosure, when the storage module is configured to store the sampled data into the target storage block, it includes:

[0039] Obtain the content length, timestamp, and valid data of the sampled data, generate a data packet based on the content length, timestamp, and valid data, and store the data packet in the target storage block in the order of acquisition time.

[0040] In an embodiment of the present disclosure, after the storage module is used to generate a data packet according to the content length, timestamp, and valid data, it is further used to:

[0041] Determine whether the packet length of the data packet reaches a set number of bytes;

[0042] In response to the packet length of the data packet not reaching the set number of bytes, add padding data after the valid data in the data packet according to the packet length of the data packet and the set number of bytes until the packet length of the data packet reaches the set number of bytes.

[0043] In an embodiment of the present disclosure, the content length and timestamp of the sampled data have 4 bytes.

[0044] In an embodiment of the present disclosure, when the cache module is used to put the target storage block into the data buffer, it includes:

[0045] Obtain the attribute information of the target storage block, and put the target storage block carrying the attribute information into the data buffer;

[0046] Wherein, the attribute information of the target storage block includes whether the target storage block contains valid data, the sensor number for obtaining the sampled data, the address of the target storage block, and the content length of the valid data contained in the target storage block.

[0047] According to the third aspect of the embodiments of the present disclosure, an electronic device is provided, including:

[0048] A processor;

[0049] A memory for storing instructions executable by the processor;

[0050] Wherein, the processor is configured to:

[0051] Implement the steps of the above memory management method.

[0052] According to the fourth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the program instructions are executed by a processor, the steps of the above memory management method are implemented.

[0053] According to a fifth aspect of the embodiments of the present disclosure, a chip is provided, which includes a processor and an interface circuit; the processor is configured to read instructions to execute the steps of the above-mentioned memory management method.

[0054] The technical solutions provided by the embodiments of the present disclosure at least bring the following beneficial effects:

[0055] Through the embodiments of the present disclosure, sampling data of at least one sensor is first obtained, and an idle and available storage block is selected from at least one memory buffer pool as the target storage block. Then, the sampling data is stored in the target storage block. When the data volume of the sampling data stored in the target storage block reaches a set data volume threshold, the target storage block is placed in a data buffer. Then, when the number of storage blocks in the data buffer reaches a set number threshold, the central processing unit of the electronic device is woken up. The present disclosure uses the idle and available storage blocks in the memory buffer pool to save the sampling data of each sensor, and wakes up the central processing unit CPU to process the sampling data only after the number of storage blocks in the data buffer reaches a certain threshold, so as to reduce the power consumption of the electronic device by reducing the number of times the central processing unit CPU is woken up.

[0056] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.

[0058] Figure 1 is a flowchart of the memory management method according to the embodiments of the present disclosure;

[0059] Figure 2 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0060] Figure 3 is a schematic diagram of a memory buffer pool according to an embodiment of the present disclosure;

[0061] Figure 4 is a schematic diagram of the format of the sampling data stored in the target storage block according to an embodiment of the present disclosure;

[0062] Figure 5 is a schematic diagram of the storage of the sampling data of each sensor into the target storage module according to an embodiment of the present disclosure;

[0063] Figure 6 is a schematic diagram of the format of the storage block in the data buffer according to an embodiment of the present disclosure;

[0064] Figure 7 It is a block diagram of a memory management device according to an embodiment of the present disclosure. Detailed implementation manners

[0065] In order to enable those of ordinary skill in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0066] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0067] The memory management method, device, electronic device, chip, and storage medium according to the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0068] Figure 1 It is a flowchart of the memory management method according to the embodiments of the present disclosure. The memory management method according to the embodiments of the present disclosure can be applied to an electronic device or a system on a chip, such as a microprocessor Micro.

[0069] The schematic diagram of the electronic device according to the embodiments of the present disclosure is as Figure 2As shown in the figure, it includes at least one sensor, a transmission interface GPIO, a microprocessor Micro, multiple memory buffer pools, a data buffer, and a central processing unit CPU. At least one sensor is connected to the microprocessor Micro through the transmission interface GPIO, and the microprocessor Micro is respectively connected to multiple memory buffer pools, the data buffer, and the central processing unit CPU. Among them, at least one sensor may include: EEG (Electroencephalogram) sensor, PPG (Photo Plethysmo Graphy) sensor, SaO2 (Oxygen Saturation of Blood) sensor, blood pressure sensor, blood glucose sensor, electrocardiograph (ECG) sensor, body composition sensor, skin electrical activity sensor, body temperature sensor, etc. The specific type of the sensor is not limited in the embodiments of the present disclosure. The transmission interface GPIO may be a Serial Peripheral Interface (SPI) or an Inter-Integrated Circuit (I2C) interface, and specific settings need to be made according to actual needs. The type of the transmission interface is not specifically limited in the embodiments of the present disclosure.

[0070] As Figure 1 shown, the memory management method of the embodiments of the present disclosure includes the following steps:

[0071] S101, Obtain the sampling data of at least one sensor.

[0072] In this step, referring to Figure 2 , the sampling data collected by at least one sensor (for example, a gravity acceleration sensor, a gyroscope, etc.) is transmitted to the microprocessor Micro through the transmission interface GPIO.

[0073] S102, Select an idle and available storage block from at least one memory buffer pool as the target storage block.

[0074] In the embodiments of the present disclosure, idle and available memory blocks are saved in the memory buffer pool. There may be multiple memory buffer pools of different sizes in the electronic device for saving memory blocks of different sizes. As Figure 3 shown, at least one memory buffer pool includes a first memory buffer pool and a second memory buffer pool; among them, the first memory buffer pool can save n + 1 data blocks, each data block has the same size, and the size of the data block is configurable. For example, the size of each data block is 256 Byte; the second memory buffer pool can save n + 1 data blocks, each data block has the same size, and the size of the data block is configurable. For example, the size of each data block is 1024 Byte.

[0075] As an implementable manner of step S102, after the microprocessor Micro receives the sampling data of at least one sensor transmitted through the transmission interface GPIO, it can select any available free storage block from any one of the memory buffer pools as the target storage block, so as to store the sampling data of at least one sensor through the target storage block.

[0076] As another implementable manner of step S102, referring to Figure 2 , after the microprocessor Micro receives the sampling data of at least one sensor transmitted through the transmission interface GPIO, it can first obtain the data volume of the sampling data of each sensor, and according to the data volume of the sampling data of each sensor, select at least one target memory buffer pool from at least one memory buffer pool. Then, it obtains the number of sensors from which the sampling data of each sensor is sourced, and according to the number of sensors from which the sampling data of each sensor is sourced, selects the corresponding number of available free storage blocks from at least one target memory buffer pool as the target storage block, so as to store the sampling data of at least one sensor through the target storage block.

[0077] S103, Store the sampling data into the target storage block.

[0078] In this step, referring to Figure 2 , after the microprocessor Micro determines the target storage block corresponding to the sampling data to be stored, it first obtains the content length, timestamp, and valid data of the sampling data, and generates a data packet according to the content length, timestamp, and valid data. Then, it stores the data packet into the target storage block in the order of acquisition time.

[0079] After generating the data packet according to the content length, timestamp, and valid data, it also determines whether the packet length of the data packet reaches the set number of bytes, and when the packet length of the data packet does not reach the set number of bytes, according to the packet length of the data packet and the set number of bytes, padding data is added after the valid data in the data packet until the packet length of the data packet reaches the set number of bytes.

[0080] As Figure 4 shown, the packet length of the data packet includes: the content length of 4 bytes of sampling data, the timestamp of 4 bytes, and the valid data, excluding the padding data.

[0081] Since the packet length of the data packet of the sampling data of the sensor may not be 4-byte aligned, in order to ensure 4-byte alignment, 1 to 4 bytes need to be supplemented later. For example, when the packet length of the data packet is equal to 9 bytes, then the length of the padding data is equal to 3 bytes.

[0082] The length of the valid data in the sampling data of the sensor is the packet length of the data packet minus 8, and the starting address starts from the 8th byte.

[0083] The data sampled by the sensor within a certain period of time can be sequentially placed into the target memory block according to the Figure 5 format shown, and the central processing unit CPU can read the sampled data according to this format.

[0084] S104, in response to the data volume of the sampled data stored in the target storage block reaching the set data volume threshold, put the target storage block into the data buffer.

[0085] Among them, the set data volume threshold is determined according to the data volume of the sampled data that the current target storage block allows to store. For example, there is a positive correlation between the set data volume and the data volume of the sampled data that the current target storage block allows to store.

[0086] In the present disclosure, the specific format of the data buffer is as Figure 6 shown, which can store multiple data blocks, and the size of each data block can be different. When reading, the principle of first in first out is followed. There are 4 elements in the data buffer representing the information of each data block:

[0087] Invalid: including whether the current data block contains valid data.

[0088] Sensor ID: indicating the number of the sensor from which the sampled data is sourced, and different sensors have different numbers.

[0089] Addr: indicating the address of the memory block.

[0090] Size: the content length of the valid data contained in the current memory block.

[0091] Therefore, in the process of putting the target storage block into the data buffer, it is necessary to obtain the attribute information of the target storage block; among them, the attribute information of the target storage block includes whether the target storage block contains valid data Invalid, the sensor number Sensor ID for obtaining the sampled data, the address Addr of the target storage block, and the content length Size of the valid data contained in the target storage block, and then put the target storage block carrying the attribute information into the data buffer.

[0092] S105, in response to the number of storage blocks in the data buffer reaching the set number threshold, wake up the central processing unit of the electronic device.

[0093] In this step, refer to Figure 2, the microprocessor Micro determines in real time whether the number of storage blocks stored in the data buffer reaches a set number threshold. If the number of storage blocks in the data buffer does not reach the set number threshold, the central processing unit of the electronic device is not awakened until the number of storage blocks in the data buffer reaches the set number threshold, and then the central processing unit of the electronic device is awakened.

[0094] Therefore, after obtaining the sampled data, the present disclosure needs to save the sampled data first. The sampled data of different sensors are saved using different memory blocks. One memory block can save the sampled data generated by the sensor multiple times. After the data volume in the memory block reaches the set data volume threshold, the memory block is stored in the data buffer. If the number of memory blocks in the data buffer reaches the set number threshold, the central processing unit CPU is awakened so that the central processing unit CPU can obtain the sampled data, thereby reducing the number of times the central processing unit CPU is awakened and achieving the purpose of reducing the power consumption of the central processing unit CPU.

[0095] In summary, according to the memory management method of the embodiments of the present disclosure, at least one sampled data of a sensor is obtained first, and an idle and available storage block is selected from at least one memory buffer pool as the target storage block, and then the sampled data is stored in the target storage block. When the data volume of the sampled data stored in the target storage block reaches the set data volume threshold, the target storage block is placed in the data buffer. Then, when the number of storage blocks in the data buffer reaches the set number threshold, the central processing unit of the electronic device is awakened. The present disclosure uses the idle and available storage blocks in the memory buffer pool to save the sampled data of each sensor, and wakes up the central processing unit CPU to process the sampled data after the number of storage blocks in the data buffer reaches a certain threshold, thereby reducing the power consumption of the electronic device by reducing the number of times the central processing unit CPU is awakened.

[0096] Figure 7 It is a block diagram of a memory management device according to an embodiment of the present disclosure.

[0097] As Figure 7 shown, the memory management device 700 of the embodiments of the present disclosure includes:

[0098] An acquisition module 710, configured to acquire at least one sampled data of a sensor;

[0099] A selection module 720, configured to select an idle and available storage block from at least one memory buffer pool as the target storage block;

[0100] A storage module 730, configured to store the sampled data in the target storage block;

[0101] A cache module 740, configured to put a target storage block into a data buffer in response to the data volume of the sampled data stored in the target storage block reaching a set data volume threshold;

[0102] A wake-up module 750, configured to wake up the central processing unit of the electronic device in response to the number of storage blocks stored in the data buffer reaching a set number threshold.

[0103] In an embodiment of the present disclosure, before selecting an idle and available storage block from at least one memory buffer pool as the target storage block, the selection module 720 is further configured to:

[0104] Obtain the data volumes of the sampled data of each sensor, and select at least one target memory buffer pool from at least one memory buffer pool according to the data volumes of the sampled data of each sensor.

[0105] In an embodiment of the present disclosure, when the selection module 720 selects an idle and available storage block from at least one memory buffer pool as the target storage block, it includes:

[0106] Obtain the number of sensors from which the sampled data of each sensor is sourced;

[0107] Select a corresponding number of idle and available storage blocks from at least one target memory buffer pool as the target storage block according to the number of sensors from which the sampled data of each sensor is sourced.

[0108] In an embodiment of the present disclosure, when the storage module 730 stores the sampled data into the target storage block, it includes:

[0109] Obtain the content length, timestamp, and valid data of the sampled data, generate a data packet according to the content length, timestamp, and valid data, and store the data packet into the target storage block in the order of acquisition time.

[0110] In an embodiment of the present disclosure, after the storage module 730 generates a data packet according to the content length, timestamp, and valid data, it is further configured to:

[0111] Judge whether the packet length of the data packet reaches a set number of bytes;

[0112] In response to the packet length of the data packet not reaching the set number of bytes, add padding data after the valid data in the data packet according to the packet length of the data packet and the set number of bytes until the packet length of the data packet reaches the set number of bytes.

[0113] In an embodiment of the present disclosure, the content length and timestamp of the sampled data have 4 bytes.

[0114] In one embodiment of the present disclosure, when the cache module 740 is used to place the target storage block into the data cache, it includes:

[0115] Obtain the attribute information of the target storage block, and place the target storage block carrying the attribute information into the data cache;

[0116] Among them, the attribute information of the target storage block includes whether the target storage block contains valid data, the sensor number for obtaining the sampled data, the address of the target storage block, and the content length of the valid data contained in the target storage block.

[0117] It should be noted that for the details not disclosed in the memory management device of the embodiments of the present disclosure, please refer to the details disclosed in the memory management method of the embodiments of the present disclosure, and specific details will not be elaborated here.

[0118] According to the memory management device of the embodiments of the present disclosure, the sampling data of at least one sensor is obtained through the obtaining module, the idle available storage block is selected from at least one memory buffer pool as the target storage block through the selection module, the sampling data is stored in the target storage block through the storage module, when the data volume of the sampling data stored in the target storage block reaches the set data volume threshold, the target storage block is placed into the data cache through the cache module, and when the number of storage blocks in the data cache reaches the set number threshold, the central processing unit of the electronic device is awakened through the wake-up module. Thus, the memory management device of the present disclosure uses the idle available storage blocks in the memory buffer pool to save the sampling data of each sensor, and waits until the number of storage blocks in the data cache reaches a certain threshold, and then wakes up the central processing unit CPU to process the sampling data, so as to reduce the power consumption of the electronic device by reducing the number of times the central processing unit CPU is awakened.

[0119] Based on the above embodiments, the present disclosure also proposes an electronic device.

[0120] The electronic device of the embodiments of the present disclosure includes: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to execute the instructions to implement the memory management method as described above.

[0121] The electronic device of the embodiments of the present disclosure, by executing the above memory management method, uses the idle available storage blocks in the memory buffer pool to save the sampling data of each sensor, and waits until the number of storage blocks in the data cache reaches a certain threshold, and then wakes up the central processing unit CPU to process the sampling data, so as to reduce the power consumption of the electronic device by reducing the number of times the central processing unit CPU is awakened.

[0122] Based on the above embodiments, the present disclosure also proposes a computer-readable storage medium.

[0123] When the instructions in the readable storage medium of the embodiments of the present disclosure are executed by a processor, the processor is enabled to execute the above-mentioned memory management method.

[0124] The computer-readable storage medium of the embodiments of the present disclosure, by executing the above-mentioned memory management method, uses the idle available storage blocks in the memory buffer pool to store the sampling data of each sensor. After the number of storage blocks in the data buffer reaches a certain threshold, the central processing unit (CPU) is then awakened to process the sampling data, thereby reducing the power consumption of the electronic device by reducing the number of times the central processing unit (CPU) is awakened.

[0125] Based on the above embodiments, the present disclosure also proposes a computer program product.

[0126] The computer program product of the embodiments of the present disclosure includes a computer program, and when the computer program is executed by a processor, it implements the above-mentioned memory management method.

[0127] The computer program product of the embodiments of the present disclosure, by executing the above-mentioned memory management method, uses the idle available storage blocks in the memory buffer pool to store the sampling data of each sensor. After the number of storage blocks in the data buffer reaches a certain threshold, the central processing unit (CPU) is then awakened to process the sampling data, thereby reducing the power consumption of the electronic device by reducing the number of times the central processing unit (CPU) is awakened.

[0128] Based on the above embodiments, the present disclosure also proposes a chip. The above chip includes a processor and an interface circuit, wherein the above processor is used to read instructions to execute a memory management method provided by the embodiments of the present disclosure.

[0129] The chip provided by the embodiments of the present disclosure is a system-on-chip. The above system-on-chip may include a microprocessor and an interface circuit, or may include a microprocessor, a central processing unit, and an interface circuit.

[0130] The chip of the embodiments of the present disclosure, by executing the above-mentioned memory management method, uses the idle available storage blocks in the memory buffer pool to store the sampling data of each sensor. After the number of storage blocks in the data buffer reaches a certain threshold, the central processing unit (CPU) is then awakened to process the sampling data, thereby reducing the power consumption of the electronic device by reducing the number of times the central processing unit (CPU) is awakened.

[0131] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0132] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0133] Any process or method description in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0134] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definitional sequence list of executable instructions for implementing logical functions, and can be embodied specifically in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or used in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0135] It should be understood that various parts of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0136] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method for implementing the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0137] In addition, each functional unit in various embodiments of the present disclosure may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0138] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A memory management method, characterized in that, including: Obtain the sampling data of at least one sensor; Select an idle and available storage block from at least one memory buffer pool as the target storage block; Store the sampling data into the target storage block; In response to the data volume of the sampling data stored in the target storage block reaching a set data volume threshold, put the target storage block into a data buffer; In response to the number of storage blocks stored in the data buffer reaching a set number threshold, wake up the central processing unit of the electronic device.

2. The method according to claim 1, wherein Before the step of selecting an idle and available storage block from at least one memory buffer pool as the target storage block, it further includes: Obtain the data volume of the sampling data of each sensor; According to the data volume of the sampling data of each sensor, select at least one target memory buffer pool from at least one memory buffer pool.

3. The method according to claim 2, wherein The step of selecting an idle and available storage block from at least one memory buffer pool as the target storage block includes: Obtain the number of sensors from which the sampling data of each sensor is sourced; According to the number of sensors from which the sampling data of each sensor is sourced, select the corresponding number of idle and available storage blocks from at least one of the target memory buffer pools as the target storage block.

4. The method according to claim 1, characterized in that, The step of storing the sampling data into the target storage block includes: Obtain the content length, timestamp and valid data of the sampling data; Generate a data packet according to the content length, timestamp and valid data; Store the data packet into the target storage block in the order of acquisition time.

5. The method according to claim 4, characterized in that, After generating the data packet according to the content length, timestamp and valid data, it further includes: Judge whether the packet length of the data packet reaches a set number of bytes; In response to the packet length of the data packet not reaching the set number of bytes, add padding data after the valid data in the data packet according to the packet length of the data packet and the set number of bytes until the packet length of the data packet reaches the set number of bytes.

6. The method according to claim 4, wherein The content length and timestamp of the sampling data have 4 bytes.

7. The method according to claim 1, characterized in that, The step of putting the target storage block into the data buffer includes: Obtain the attribute information of the target storage block; wherein, the attribute information of the target storage block includes whether the target storage block contains valid data, the sensor number from which the sampling data is obtained, the address of the target storage block, and the content length of the valid data contained in the target storage block; Put the target storage block carrying the attribute information into the data buffer.

8. A memory management device, characterized in that, including: An obtaining module, configured to obtain the sampling data of at least one sensor; A selecting module, configured to select an idle and available storage block from at least one memory buffer pool as the target storage block; A storing module, configured to store the sampling data into the target storage block; A caching module, configured to, in response to the data volume of the sampling data stored in the target storage block reaching a set data volume threshold, put the target storage block into a data buffer; A waking-up module, configured to, in response to the number of storage blocks stored in the data buffer reaching a set number threshold, wake up the central processing unit of the electronic device.

9. An electronic device, characterized in that, including: A processor; A memory for storing instructions executable by the processor; Wherein, the processor is configured to: Implement the steps of the memory management method according to any one of claims 1-7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, the steps of the memory management method according to any one of claims 1-7 are implemented.

11. A chip, characterized in that, Comprising a processor and an interface circuit; the processor is used to read instructions to execute the method according to any one of claims 1-7.

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