Fault analysis method and device in memory loading process, equipment and storage medium

Abstract

The invention relates to the technical field of memory fault diagnosis, in particular to a fault analysis method and device for a memory loading process, equipment and a storage medium. Erasing operation is executed on a target memory area, an erasing result is monitored in real time, meanwhile, memory state data is recorded, and when erasing fails, the memory loading process is completed. The method comprises the steps of extracting state data of abnormal blocks and reference blocks thereof in a preset time period, generating fault feature data through data comparison, performing multi-dimensional analysis in combination with a hardware environment, software configuration and a storage state, determining a fault source and executing targeted recovery operation, including self-adaptive retry erasing, bad block remapping or delayed erasing scheduling. According to the method, through multi-dimensional data monitoring and analysis, the reasons of the erasure faults are accurately recognized, misjudgment and invalid operation are effectively reduced, a differential erasure strategy and an intelligent recovery mechanism are combined, self-adaption to environment interference and automatic error correction can be achieved, and the automatic management capacity of the system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory fault diagnosis, and particularly to a fault analysis method, device, equipment and storage medium for the memory loading process. Background Art

[0002] In an automotive electronic control unit (ECU), the Bootloader software (boot loader) is a core component of the embedded system and undertakes the important responsibilities of booting and updating the application software. During the startup and update of the software system, the boot loader needs to perform memory self-check and erasure operations to ensure the normal operation of the memory and the update of data. However, due to various factors such as hardware failures, software defects or environmental interference, the memory erasure may fail, which in turn affects the normal operation of the ECU. Therefore, how to ensure the reliability of the boot loader during the self-check and memory erasure process has become an important issue in the automotive electronics field.

[0003] Currently, when the existing Bootloader software performs memory erasure, it mainly executes the corresponding erasure operation using a preset erasure algorithm, lacking the effective processing ability for abnormal situations. In terms of error detection, detailed error analysis is lacking. And in terms of the recovery mechanism, when the erasure fails, it often can only try to recover by restarting the system or reporting a simple error code, which makes the fault troubleshooting efficiency low and difficult to meet the reliability requirements in complex environments. In addition, the existing technology lacks a reliable fault analysis scheme and a fault solution for differential configuration according to different fault causes, further increasing the uncertainty of the erasure operation.

[0004] Therefore, how to improve the diagnosis and processing efficiency of the ECU's Bootloader software in the event of memory erasure failure in the existing technology has become a technical problem urgently to be solved in this industry. Summary of the Invention

[0005] The main purpose of the present invention is to provide a fault analysis method, device, equipment and storage medium for the memory loading process, aiming to solve the technical problem of how to improve the diagnosis and processing efficiency of the ECU's Bootloader software in the event of memory erasure failure in the existing technology.

[0006] To achieve the above object, the present invention provides a fault analysis method for the memory loading process, the method comprising the following steps: Divide a target memory area to obtain a plurality of memory blocks, and allocate an erasure algorithm to the plurality of memory blocks according to a preset rule; Execute the erasure operation on the memory blocks in batches, and record the memory state data and environmental state data of the memory blocks in real time; Divide the multiple memory blocks into erased abnormal blocks and reference memory blocks according to the result of the erasure operation; Obtain fault feature data according to the memory state data corresponding to the erased abnormal blocks and the memory state data corresponding to the reference memory area under the same erasure algorithm; Obtain the fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault.

[0007] Optionally, the dividing the target memory area to obtain multiple memory blocks and allocating erasure algorithms to the multiple memory blocks according to a preset rule includes: Determine the division quantity and the target specification of block division according to the specification parameters of the target memory area; Divide the target memory area according to the division quantity and the target specification of block division to obtain multiple memory blocks; Retrieve multiple erasure algorithms that meet the algorithm application conditions from a preset erasure algorithm database according to the division quantity of the memory blocks; Allocate the multiple erasure algorithms to the multiple memory blocks according to a preset rule, where the erasure algorithms allocated to physically adjacent memory blocks are different.

[0008] Optionally, the dividing the multiple memory blocks into erased abnormal blocks and reference memory blocks according to the result of the erasure operation includes: Take the memory blocks with an erasure failure result in the erasure operation result as the erased abnormal blocks; Take the memory blocks that use the same erasure algorithm as the erased abnormal blocks and have a successful erasure result among the memory blocks that have completed the erasure operation as the reference memory blocks corresponding to the erased abnormal blocks.

[0009] Optionally, before dividing the multiple memory blocks into erased abnormal blocks and reference memory blocks according to the result of the erasure operation, it further includes: During the execution of the erasure operation, obtain the erasure behavior verification information corresponding to each memory block that has completed the erasure operation in the target memory area in real time; Obtain the erasure operation result of the memory block according to the erasure behavior verification information corresponding to each memory block, where the erasure behavior verification information includes at least one of block register information, block level information, and block erasure log information.

[0010] Optionally, the obtaining fault feature data according to the memory state data corresponding to the erased abnormal blocks and the memory state data corresponding to the reference memory area under the same erasure algorithm includes: Compare the memory state data of the erased abnormal block item by item with the memory state data of the reference memory block, and determine the memory state data items whose data difference degree exceeds the data fluctuation threshold; Based on the fault correlation data item list, determine the key difference data items in the memory state data items; Use the memory state data corresponding to the key difference data items as the fault feature data.

[0011] Optionally, obtaining the fault cause analysis result according to the fault feature data and the corresponding environmental state data when the fault occurs includes: According to the fault feature data, obtain the software state features of the erased abnormal block, and the software state features include the erased block address, the erase algorithm parameters, and the erase interrupt status data; According to the fault feature data, obtain the hardware state features of the erased abnormal block, and the hardware state features include the power supply voltage data, the erase voltage data, and the memory controller status data; Perform a correlation analysis on the environmental state data, the software state features, and the hardware state features to obtain the fault cause analysis result, and the environmental state data includes environmental electromagnetic state information, environmental communication state information, and environmental temperature and humidity information.

[0012] Optionally, the fault analysis method for the memory loading process further includes: According to the fault cause analysis result, perform at least one of the following recovery operations on the memory block where the erase operation fails: Under the condition of meeting the block erase voltage threshold, perform a retry erase with adaptive erase parameters for a preset number of times; Perform address remapping on the bad block where the block recovery fails, and switch to the pre-divided redundant memory area; If it is determined to be a systematic environmental interference, delay the erase operation until the environmental parameters return to normal.

[0013] In addition, to achieve the above object, the present invention also proposes a fault analysis device for the memory loading process, and the fault analysis device for the memory loading process includes: A data processing module, configured to divide a target memory area to obtain a plurality of memory blocks, and allocate an erase algorithm to the plurality of memory blocks according to a preset rule; A data acquisition module, configured to perform an erase operation on the memory blocks in batches, and record the memory state data and the environmental state data of the memory blocks in real time; The data processing module is further configured to divide the plurality of memory blocks into erased abnormal blocks and reference memory blocks according to the erase operation result; A fault feature extraction module, configured to obtain fault feature data according to the memory state data corresponding to the erased abnormal block and the memory state data corresponding to the reference memory area under the same erasure algorithm; A fault analysis module, configured to obtain a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault.

[0014] In addition, to achieve the above object, the present invention also provides a fault analysis device for the memory loading process. The fault analysis device for the memory loading process includes: a memory, a processor, and a fault analysis program for the memory loading process stored on the memory and executable on the processor. The fault analysis program for the memory loading process is configured to implement the steps of the fault analysis method for the memory loading process as described above.

[0015] In addition, to achieve the above object, the present invention also provides a storage medium. A fault analysis program for the memory loading process is stored on the storage medium. When the fault analysis program for the memory loading process is executed by a processor, it implements the steps of the fault analysis method for the memory loading process as described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: By performing an erasure operation on the target memory area and monitoring the erasure result in real time, while recording the memory state data, when the erasure fails, the state data of the abnormal block and its reference block within a preset time period are extracted, and the fault feature data is generated through data comparison. Combined with the hardware environment, software configuration, and storage state for multi-dimensional analysis, the root cause of the fault is determined and targeted recovery operations are performed, including adaptive retry erasure, bad block remapping, or delayed erasure scheduling. This method accurately identifies the cause of the erasure fault through multi-dimensional data monitoring and analysis, effectively reduces misjudgment and ineffective operations, and combines a differential erasure strategy with an intelligent recovery mechanism to adapt to environmental interference and automatically correct errors, improving the automatic management ability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application and, together with the specification, are used to explain the principles of the present application.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required for describing the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic flowchart of the first embodiment of the fault analysis method for the memory loading process of the present invention; Figure 2 It is a schematic diagram of the overall process architecture of the first embodiment of the fault analysis method for the memory loading process of the present invention; Figure 3 It is a schematic flowchart of the second embodiment of the fault analysis method for the memory loading process of the present invention; Figure 4 It is a schematic flowchart of the third embodiment of the fault analysis method for the memory loading process of the present invention; Figure 5 It is a block diagram of the structure of the first embodiment of the fault analysis device for the memory loading process of the present invention; Figure 6 It is a schematic diagram of the structure of the fault analysis device for the memory loading process in the hardware operating environment involved in the solution of the embodiment of the present invention.

[0020] The realization, functional features and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Specific Embodiments

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0022] In order to better understand the technical solutions of the present application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific embodiments.

[0023] The main solution of the embodiments of the present application is: dividing the target memory area to obtain a plurality of memory blocks, and allocating an erasure algorithm to the plurality of memory blocks according to a preset rule; performing erasure operations on the memory blocks in batches, and recording the memory state data and environmental state data of the memory blocks in real time; according to the erasure operation results, dividing the plurality of memory blocks into erasure abnormal blocks and reference memory blocks; obtaining fault feature data according to the memory state data corresponding to the erasure abnormal blocks of the same erasure algorithm and the memory state data corresponding to the reference memory area; obtaining a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the time of fault occurrence.

[0024] Currently, when the existing Bootloader software performs memory erasure, it mainly uses a preset erasure algorithm to execute the corresponding erasure operation, lacking the ability to effectively handle abnormal situations. In terms of error detection, it lacks detailed error analysis. In the recovery mechanism, when the erasure fails, it often can only try to recover by restarting the system or reporting a simple error code, which makes the troubleshooting efficiency low and difficult to meet the reliability requirements in complex environments. In addition, the existing technology lacks a reliable fault analysis scheme and a fault solution for differential configuration according to different fault causes, further increasing the uncertainty of the erasure operation. Therefore, how to improve the diagnosis and processing efficiency of the ECU's Bootloader software in the existing technology when the memory erasure fails is a technical problem that urgently needs to be solved at present.

[0025] In this application, by performing an erasure operation on the target memory area and monitoring the erasure result in real time, while recording the memory state data, when the erasure fails, the state data of the abnormal block and its reference block within a preset time period are extracted, and the fault feature data is generated through data comparison. Combining the hardware environment, software configuration, and storage state for multi-dimensional analysis, the root cause of the fault is determined and targeted recovery operations are performed, including adaptive retry erasure, bad block remapping, or delayed erasure scheduling. This method can accurately identify the cause of the erasure fault through multi-dimensional data monitoring and analysis, effectively reduce misjudgment and ineffective operations, and combined with a differential erasure strategy and an intelligent recovery mechanism, can adapt to environmental interference and automatically correct errors, improving the system's automatic management ability.

[0026] It should be noted that the execution subject of the present invention can be a fault analysis device for the memory loading process, or a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a thermal management device of a fault analysis device for the memory loading process that can implement the above functions. This embodiment does not make specific limitations on this. Hereinafter, taking the fault analysis device for the memory loading process as the execution subject as an example, this embodiment and the following embodiments will be described.

[0027] Based on this, an embodiment of the present application provides a fault analysis method for the memory loading process, referring to Figure 1 , Figure 1 is a schematic flowchart of the first embodiment of the fault analysis method for the memory loading process of the present application.

[0028] In this embodiment, the fault analysis method for the memory loading process includes steps S10 to S50: Step S10: Divide the target memory area to obtain multiple memory blocks, and allocate an erasure algorithm to the multiple memory blocks according to a preset rule.

[0029] AsFigure 2 As shown Figure 2 This is a schematic diagram of the full - process architecture of the first embodiment of the fault analysis method for the memory loading process of the present invention.

[0030] It should be noted that the entire process starts with the initialization and self - check phase. The system checks its own hardware and software status to ensure everything is normal. The system determines whether the self - check passes. If it does not pass, the reason for the self - check failure will be stored and corresponding processing will be returned; if it passes, it enters the erasure phase. In the erasure phase, the system performs the erasure operation on the memory block. During the erasure process, it determines whether the erasure operation fails. If the erasure is successful, the process continues; if it fails, it enters the step of diagnosing the failure reason, and then analyzes the reason for the erasure failure. The specific failure reasons can be divided into abnormalities in three aspects: hardware status, software status, and environmental status. Finally, according to the diagnostic results, error handling and recovery operations are performed. The specific operations include attempting to re - erase multiple times, switching to an alternative memory area, reporting error messages, etc.

[0031] It can be understood that since there are multiple factors for the failure of memory erasure, specifically, it mainly includes three aspects: environment, software, and hardware. In terms of the environment, too high or too low temperature and humidity may affect the normal operation of the memory chip, resulting in erasure failure. The electromagnetic field in the surrounding environment may interfere with the signal transmission inside the memory, causing the erasure instruction to be unable to be executed accurately or data transmission to fail, resulting in erasure failure. At the software level, defects in the erasure algorithm itself, compatibility problems between software, and insufficient system resources may all lead to memory erasure failure. In terms of hardware factors, problems with the quality of the memory chip itself, unstable power supply voltage, and memory controller failures may all prevent the memory erasure operation from being completed normally.

[0032] It should be understood that, in addition to the above external factors, different memory regions may have different internal characteristics, such as storage density, access speed, physical location, etc. For a large memory region, after being divided into several small blocks, the erasure operation can be performed on each block separately. By adjusting the erasure parameters of each block, the influence of software, hardware, and environmental factors on the erasure result during the erasure process can be quantified. In addition, dividing the entire memory region into multiple blocks helps to more accurately track and analyze the state changes of each block during the erasure process. Moreover, different erasure algorithms are applicable to different types of memory blocks or different erasure environments. Retrieving multiple erasure algorithms that meet the algorithm application conditions from the preset erasure algorithm database can ensure that the selected algorithm can match the characteristics of each memory block, thereby improving the success rate and efficiency of the erasure operation. For example, some algorithms may perform better when dealing with high-density storage blocks, while others may be more suitable for erasure operations in low-voltage environments. Therefore, in order to better quantify the influence of software, hardware, and environmental factors on the erasure result, the memory is divided into multiple small blocks, and a suitable erasure algorithm is selected for each block. By controlling variables, the reasons for erasure failure can be tracked more accurately.

[0033] In a feasible implementation manner, step S10 may include steps A11 to A14: Step A11: Determine the number of divisions and the target specification for block division according to the specification parameters of the target memory region.

[0034] It should be noted that the specification parameters of the target memory region cover key information such as the size, storage density, access speed, and physical layout of the memory. By comprehensively considering these parameters, the number of divisions can be reasonably determined to ensure that each divided memory block can meet the specific requirements of subsequent erasure operations and effectively balance the complexity and efficiency of the overall operation. At the same time, clarifying the target specification for block division helps to provide a more operable basic unit for subsequent fault analysis and recovery operations.

[0035] Step A12: Divide the target memory region according to the number of divisions and the target specification for block division to obtain multiple memory blocks.

[0036] It can be understood that the specific division method is not limited to the physical segmentation of the entire memory region, but an orderly split based on the logical architecture of the memory and actual application requirements. Each obtained memory block is relatively independent in function but can work together under the overall memory management strategy. Such a division can perform differential processing according to the characteristics of different blocks in subsequent steps, facilitating quickly locating the specific block in case of a fault and determining the key factors affecting the erasure result according to the differential parameter configuration.

[0037] Step A13: According to the number of divisions of the memory block, retrieve multiple erasure algorithms that meet the algorithm application conditions from the preset erasure algorithm database.

[0038] It should be noted that the preset erasure algorithm database stores a variety of verified erasure algorithms. Generally speaking, for memory blocks with different configuration parameters, when different erasure algorithms are used, the erasure speed and result may be different. On the other hand, even for blocks using the same erasure algorithm, if there are differences in the external environmental state data or memory-related software and hardware data, it will also affect the erasure result. From this, two control groups can be obtained: The first control group is the performance of different memory blocks when using different erasure algorithms. By comparing the erasure speed and result of these blocks, the applicability and efficiency of various algorithms under different configurations can be evaluated. For example, two memory blocks with similar configurations can be selected, different erasure algorithms can be assigned to them respectively, and then the erasure operation can be performed under the same environmental conditions, and indicators such as the time required for erasure, success or failure, and data integrity after erasure can be recorded and compared; The second control group is the influence of the same erasure algorithm on the erasure result under different environmental states or software and hardware conditions. The same memory block or multiple blocks with the same configuration can be selected, the same erasure algorithm can be used, but the erasure operation can be performed under different environmental conditions (such as different temperature, humidity or electromagnetic interference intensity) or different software and hardware conditions (such as different power supply voltages, memory controller states or software versions), and the specific influence of these condition changes on the erasure effect can be analyzed. In this way, the interference mechanism of external factors on the erasure process can be better understood, so as to provide a basis for optimizing the erasure operation and ensuring ideal erasure effects in various actual application scenarios.

[0039] Step A14: Allocate the multiple erasure algorithms to the multiple memory blocks according to a preset rule, where the erasure algorithms allocated to physically adjacent memory blocks are different.

[0040] It should be noted that the main purpose of adopting this allocation method is to reduce or even avoid the possible mutual interference between physically adjacent blocks during the erasure operation. When adjacent memory blocks use different erasure algorithms, due to the differences in the working mechanisms, signal characteristics, etc. of each algorithm, the synchronous interference or mutual influence caused by the same algorithm can be reduced. For example, the superposition of electromagnetic interference generated when the same algorithm is executed simultaneously in adjacent blocks can be avoided, thereby affecting the erasure effect. In addition, different erasure algorithms have differences in processing memory data and erasure methods, which helps to more comprehensively evaluate the actual application effects of different algorithms in different regions and provides more dimensional comparison data for subsequent analysis of the reasons for erasure failure. Moreover, this allocation strategy can also serve as a fault tolerance mechanism. When an erasure failure occurs for a certain algorithm in a specific block, other algorithms in adjacent blocks may still work normally, thus ensuring that the erasure operation of the entire memory area will not completely fail and improving the reliability and stability of the entire memory erasure process.

[0041] Step S20: Execute the erasure operation on the memory blocks in batches, and record the memory state data and environmental state data of the memory blocks in real time.

[0042] It should be noted that executing the erasure operation in batches can reduce the risk of excessive system load that may be brought about by simultaneously erasing all memory blocks, and at the same time facilitate the timely discovery and handling of possible abnormal situations during the erasure process. Recording the memory state data and environmental state data in real time provides detailed information for subsequent fault analysis and helps to quickly locate the cause of the fault.

[0043] It can be understood that the data recorded in real time includes not only the memory state information in software aspects such as the erasure progress and data integrity of the memory blocks, but also the memory state information in hardware aspects such as the erasure voltage and erasure current of the memory blocks. In addition, it also covers environmental state information such as temperature, humidity, and electromagnetic interference. These data are crucial for analyzing the success or failure of the erasure operation.

[0044] It should be understood that the method of batch processing and real-time data recording can improve the reliability of the erasure operation. Even if a fault occurs during the erasure process of a certain batch, the strategy can be quickly adjusted according to the recorded data, and the erasure operation can be re-executed or other recovery measures can be taken to ensure the stability of the entire memory loading process and the integrity of the data.

[0045] Step S30: Divide the multiple memory blocks into erasure abnormal blocks and reference memory blocks according to the erasure operation results.

[0046] It should be noted that during the execution of the erasure operation, the erasure behavior verification information corresponding to each memory block that has completed the erasure operation in the target memory area is obtained in real time; according to the erasure behavior verification information corresponding to each memory block, the erasure operation result of the memory block is obtained, where the erasure behavior verification information includes at least one of block register information, block level information, and block erasure log information.

[0047] It can be understood that by obtaining this erasure behavior verification information in real time, the erasure status of each memory block can be judged timely and accurately. For example, the block register information can reflect the values of the control and status registers of the block during the erasure process, and these data can characterize whether the erasure operation is executed as expected; the block level information can provide whether the voltage level of the storage unit after erasure reaches the expected target, so as to judge whether the erasure is complete; the block erasure log information records the key events and error information of the erasure operation, which helps to track the abnormal situations during the erasure process. By synthesizing this information, it can be reliably determined which blocks are erased successfully and which blocks have abnormalities, and then effective classification management can be realized, providing a clear basis for subsequent fault analysis and recovery operations.

[0048] In one embodiment, the dividing the multiple memory blocks into erasure abnormal blocks and reference memory blocks according to the erasure operation result includes: taking the memory block with an erasure failure result as an erasure abnormal block; taking the memory blocks that have completed the erasure operation and use the same erasure algorithm as the erasure abnormal block and have an erasure success result as the reference memory blocks corresponding to the erasure abnormal blocks.

[0049] It can be understood that this division method can clearly identify which blocks have problems during the erasure process (i.e., erasure abnormal blocks), and at the same time provides a direct comparison object for these abnormal blocks (i.e., reference memory blocks).

[0050] Step S40: Obtain fault feature data according to the memory state data corresponding to the erasure abnormal block and the memory state data corresponding to the reference memory area under the same erasure algorithm.

[0051] It should be noted that selecting the reference memory blocks that use the same erasure algorithm as the erasure abnormal blocks for comparison helps to exclude the interference of the algorithm itself, making the fault analysis more targeted and scientific. In addition, this division also provides a basis for subsequent recovery operations. For example, the erasure parameters can be adjusted, the algorithm can be optimized, or other recovery measures can be taken according to the comparison results, so as to improve the overall reliability and efficiency of the memory system.

[0052] It can be understood that by comparing the successful and failed cases under the same erasure algorithm, the cause of the failure can be more accurately located, whether it is due to problems with the erasure algorithm itself or other factors specific to the abnormal block (such as hardware defects or environmental interference) that lead to the erasure failure.

[0053] Step S50: Obtain an analysis result of the cause of the failure based on the failure characteristic data and the environmental state data corresponding to the occurrence of the failure.

[0054] It can be understood that the failure characteristic data refers to the key data extracted from the memory state data of the erased abnormal block and the reference memory block during the memory erasure operation, which can reflect the abnormal performance of the memory block during the erasure operation. These data usually include: abnormal changes in the power supply voltage during the erasure process, abnormal time delays in completing the erasure operation, error codes generated during the erasure process or indicating specific failure modes, and the voltage levels of the storage units to determine whether the erasure target is reached.

[0055] It should be understood that by analyzing these data, it can be determined whether the cause of the erasure failure is a hardware problem with the memory block itself, the applicability of the erasure algorithm, or external environmental factors, thereby providing a scientific basis for subsequent recovery operations.

[0056] In some embodiments, the failure analysis method for the memory loading process further includes: performing at least one of the following recovery operations on the memory block with a failed erasure operation according to the analysis result of the cause of the failure: performing a retry erasure with adaptive erasure parameters for a preset number of times under the condition of meeting the block erasure voltage threshold; remapping the address of the bad block with a failed block recovery to switch to a pre-divided redundant memory area; if it is determined to be a systematic environmental interference, delaying the erasure operation until the environmental parameters return to normal.

[0057] It can be understood that the execution of these recovery operations needs to be selected and adjusted according to the specific cause of the failure and the system state to achieve the best recovery effect. For example, if the failure is caused by unstable power supply voltage, a retry can be attempted by adjusting the erasure parameters; if it is hardware damage, address remapping is required; and if it is environmental interference, the operation is delayed until the environment returns to normal.

[0058] In this embodiment, the target memory area is divided to obtain multiple memory blocks, and erasure algorithms are assigned to the multiple memory blocks according to a preset rule; the erasure operations on the memory blocks are executed in batches, and the memory state data and environmental state data of the memory blocks are recorded in real time; according to the erasure operation results, the multiple memory blocks are divided into erasure-abnormal blocks and reference memory blocks; according to the memory state data corresponding to the erasure-abnormal blocks of the same erasure algorithm and the memory state data corresponding to the reference memory area, fault feature data is obtained; according to the fault feature data and the environmental state data corresponding to the occurrence of the fault, a fault cause analysis result is obtained.

[0059] In summary, by dividing the memory area into multiple small blocks and assigning different erasure algorithms, this technical solution can effectively reduce the complexity of erasure operations, improve the pertinence and efficiency of operations. Recording the memory state and environmental state data in real time provides detailed information for fault analysis, which helps to quickly and accurately locate the cause of the fault. By comparing the data of erasure-abnormal blocks and reference memory blocks, algorithm interference can be excluded and the root cause of the fault can be accurately analyzed. In addition, the combined use of multiple recovery operations, such as retry erasure, address remapping, and delayed erasure, can effectively handle different types of faults, reduce the impact on system operation, and improve the reliability and fault tolerance of the memory system. This method not only optimizes memory management, but also enhances system stability and data integrity, reduces maintenance costs and downtime, and improves overall performance and user experience.

[0060] Based on the first embodiment of this application, in the second embodiment of this application, the same or similar content as the above-mentioned embodiment one can be referred to the above introduction and will not be elaborated hereinafter. On this basis, please refer to Figure 3 , in step S40 of the fault analysis method for the memory loading process, it includes steps S401 to S403: Step S401: Compare the memory state data of the erasure-abnormal block and the memory state data of the reference memory block item by item to determine the memory state data items whose data difference degree exceeds the data fluctuation threshold.

[0061] It should be noted that the memory state data usually includes multiple data items, such as power supply voltage, erasure time, error code, register state, and voltage levels of storage units. Comparing item by item can accurately identify which specific data items are abnormal.

[0062] It can be understood that setting the data fluctuation threshold is to distinguish normal data fluctuations from abnormal data changes. In this way, slight fluctuations caused by normal operations can be filtered out, thereby improving the accuracy of fault diagnosis.

[0063] It should be understood that the setting of the data fluctuation threshold should be based on a large amount of experimental data and actual operation experience to ensure its rationality and effectiveness.

[0064] Step S402: Based on the fault-associated data item list, determine the key difference data items in the memory status data items.

[0065] It can be understood that the fault-associated data item list is a predefined list that contains data items related to historical faults. These data items are obtained through the analysis and summary of a large number of fault cases and can help quickly identify the key data that may cause faults. By matching the item-by-item comparison results with the fault-associated data item list, it is possible to quickly locate which difference data items are key. This method can significantly reduce the amount of data that needs to be analyzed and improve the efficiency of fault diagnosis.

[0066] It should be understood that the fault-associated data item list needs to be continuously updated and optimized to adapt to new fault modes and system changes. At the same time, the matching process needs to consider the relevance and weight of the data items to ensure the accuracy and reliability of the key difference data items.

[0067] Step S403: Use the memory status data corresponding to the key difference data items as the fault feature data.

[0068] It can be understood that the fault feature data refers to the key data that can effectively characterize the erasure failure features. By extracting this data, it can provide a clear direction and basis for subsequent fault cause analysis. Therefore, using the memory status data corresponding to the key difference data items as the fault feature data can reduce the amount of data, highlight the key points, and make the subsequent fault analysis more efficient and accurate. These data are usually the information that best reflects the essence of the fault and can help quickly determine the root cause of the fault. In addition, the extraction process of the fault feature data can be used for further machine learning or artificial intelligence analysis to improve the automation level and accuracy of fault diagnosis.

[0069] In this embodiment, by comparing the memory status data of the erasure abnormal block and the reference block item by item, combined with the data fluctuation threshold, the abnormal data items are accurately located; based on the fault-associated data item list, the key difference data items are quickly determined; finally, the memory status data corresponding to these key difference data items is extracted as the fault feature data for subsequent fault analysis.

[0070] In summary, in this embodiment, the memory state data corresponding to the extracted key difference data items is used as the fault feature data, which not only reduces the data volume, highlights the analysis focus, but also provides a clear basis for subsequent fault cause analysis, making the fault analysis more efficient and accurate. In addition, these fault feature data can be used for machine learning or artificial intelligence analysis, further improving the automation level and accuracy of fault diagnosis, reducing manual intervention, lowering the maintenance cost, enhancing the reliability and stability of the system, ensuring the smooth progress of the memory erasure operation, and guaranteeing the overall performance and data integrity of the system.

[0071] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar content as in the above-mentioned first embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 4 , in step S50 of the fault analysis method for the memory loading process, it includes steps S501 to S503: Step S501: Obtain the software state characteristics of the erased abnormal block according to the fault feature data.

[0072] It should be noted that the software state characteristics mainly cover software-level information related to the erasure operation, such as the erasure block address, erasure algorithm parameters, and erasure interrupt status data, etc. These information can be extracted from the fault feature data for further analysis of software-level problems.

[0073] It can be understood that by analyzing the software state characteristics, it is possible to determine whether there are problems such as software configuration errors, inappropriate algorithm selection, or software failures. For example, unreasonable setting of erasure algorithm parameters may lead to erasure failure, or abnormal erasure interrupt status data may indicate that the software is accidentally interrupted during the erasure process.

[0074] It should be understood that the analysis of software state characteristics helps to quickly locate the fault cause at the software level, so as to take corresponding software repair or optimization measures. Specifically, through in-depth analysis of software state characteristics, potential software defects can be discovered and preventive maintenance can be carried out in advance. For example, if it is found that the erasure algorithm performs poorly in a specific environment, the algorithm can be optimized specifically in these scenarios, or a more stable erasure algorithm can be selected for this scenario; if the erasure interrupt status data is frequently abnormal, the software's exception handling mechanism can be strengthened to improve the software's fault response ability.

[0075] Step S502: Obtain the hardware state characteristics of the erased abnormal block according to the fault feature data.

[0076] It should be noted that the hardware status features mainly cover the hardware-level information related to the erasure operation, such as power supply voltage data, erasure voltage data, and memory controller status data, etc. These information are also extracted from the fault feature data and used to analyze problems at the hardware level.

[0077] It can be understood that by analyzing the hardware status features, it can be determined whether there are hardware faults. For example, abnormal power supply voltage data may cause the memory chip to malfunction, or abnormal memory controller status data may indicate that a fault occurs in the controller during the erasure process. The analysis of the hardware status features helps to quickly locate the cause of the fault at the hardware level, so as to take corresponding hardware repair or replacement measures, which can guide the subsequent fault recovery operation. In addition, the analysis of the hardware status features not only helps to identify the current hardware faults, but also can discover potential hardware problems, providing a basis for preventive maintenance. For example, a slight fluctuation in the power supply voltage may indicate the aging of the power supply module, and an occasional abnormality in the memory controller may indicate that the controller firmware needs to be updated. By continuously monitoring and analyzing the hardware status features, these problems can be discovered in advance and measures can be taken.

[0078] Step S503: Perform a correlation analysis on the environmental status data, software status features, and hardware status features to obtain the analysis result of the cause of the fault.

[0079] It should be noted that environmental, software, and hardware factors may interact with each other and jointly cause the erasure failure. For example, a high-temperature environment may cause a decline in hardware performance, thereby triggering an abnormal erasure; at the same time, incorrect software configuration may exacerbate this abnormality. Through correlation analysis, these complex relationships can be identified, and the main and secondary factors can be determined, so as to more accurately locate the cause of the fault.

[0080] It can be understood that correlation analysis is a comprehensive evaluation method that integrates data from three levels: environment, software, and hardware. The environmental status data reflects external conditions, such as temperature, humidity, and electromagnetic interference, etc.; the software status features cover software information related to the erasure operation, such as erasure algorithm parameters and interrupt status; the hardware status features involve power supply voltage, erasure voltage, and memory controller status, etc. Through this comprehensive analysis, the interaction between these factors can be comprehensively evaluated, and the root cause of the erasure failure can be found.

[0081] It should be understood that this comprehensive analysis method can provide more comprehensive and accurate analysis results of the cause of the fault, which helps to take targeted recovery measures and improve the reliability and stability of the system. It provides a scientific basis for subsequent recovery operations, guiding how to adjust environmental parameters, optimize software configurations or repair hardware faults to ensure the smooth progress of the memory erasure operation. In addition, this method helps to discover potential problems in system design and operation, providing valuable data support for future system optimization and fault prevention.

[0082] In this embodiment, by extracting the software state characteristics and hardware state characteristics of the erased abnormal blocks and performing correlation analysis with the environmental state data, the reasons for the memory erasure failure are comprehensively evaluated. Specifically, it includes: analyzing information at the software level (such as erased block address, algorithm parameters, interrupt status, etc.) to discover software configuration errors or faults; analyzing information at the hardware level (such as power supply voltage, erasure voltage, memory controller status, etc.) to identify hardware faults; and combining environmental factors (such as temperature, humidity, electromagnetic interference, etc.), comprehensively evaluating the interaction of these factors, and accurately locating the root cause of the fault.

[0083] To sum up, in this embodiment, by comprehensively analyzing environmental, software, and hardware factors, not only can the current cause of the fault be quickly located, but also potential problems can be discovered, providing a basis for preventive maintenance. For example, discovering and optimizing in advance the erasure algorithm that performs poorly in a specific environment, or timely updating the firmware of the memory controller that occasionally has abnormalities. In addition, this method reduces manual intervention, lowers the maintenance cost, shortens the fault troubleshooting and recovery time, improves the overall performance and data integrity of the system, ensures the smooth progress of the memory erasure operation, and guarantees the normal operation of the system.

[0084] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the fault analysis method for the memory loading process of this application. Based on this technical concept, more forms of simple transformations are within the protection scope of this application.

[0085] This application also provides a fault analysis device for the memory loading process. Please refer to Figure 5 , the fault analysis device for the memory loading process includes: A data processing module 10, configured to divide a target memory area to obtain a plurality of memory blocks, and assign an erasure algorithm to the plurality of memory blocks according to a preset rule; A data acquisition module 20, configured to perform erasure operations on the memory blocks in batches, and record in real time the memory state data and environmental state data of the memory blocks; The data processing module 10 is further configured to divide the plurality of memory blocks into erased abnormal blocks and reference memory blocks according to the erasure operation results; The fault feature extraction module 30 is configured to obtain fault feature data according to the memory state data corresponding to the erased abnormal block of the same erasure algorithm and the memory state data corresponding to the reference memory area; The fault analysis module 40 is configured to obtain a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault.

[0086] In one embodiment, the data processing module 10 is further configured to determine the number of partitions and the target partition specification of the block according to the specification parameters of the target memory area; divide the target memory area according to the number of partitions and the target partition specification of the block to obtain a plurality of memory blocks; according to the number of partitions of the memory blocks, retrieve a plurality of erasure algorithms that meet the algorithm application conditions from a preset erasure algorithm database; and allocate the plurality of erasure algorithms to the plurality of memory blocks according to a preset rule, wherein the erasure algorithms allocated to physically adjacent memory blocks are different.

[0087] In one embodiment, the data processing module 10 is further configured to use the memory block with an erasure operation result of erasure failure as an erased abnormal block; and use the memory block that uses the same erasure algorithm as the erased abnormal block and has an erasure result of erasure success among the memory blocks that have completed the erasure operation as the reference memory block corresponding to the erased abnormal block.

[0088] In one embodiment, the data acquisition module 20 is further configured to, during the execution of the erasure operation, obtain in real time the erasure behavior verification information corresponding to each memory block that has completed the erasure operation in the target memory area; and obtain the erasure operation result of the memory block according to the erasure behavior verification information corresponding to each memory block, wherein the erasure behavior verification information includes at least one of block register information, block level information, and block erasure log information.

[0089] In one embodiment, the fault feature extraction module 30 is further configured to compare the memory state data of the erased abnormal block with the memory state data of the reference memory block item by item to determine the memory state data items whose data difference degree exceeds the data fluctuation threshold; determine the key difference data items in the memory state data items based on the fault correlation data item list; and use the memory state data corresponding to the key difference data items as the fault feature data.

[0090] In one embodiment, the fault analysis module 40 is further configured to obtain software state characteristics of the erased abnormal block according to the fault feature data, where the software state characteristics include an erased block address, an erase algorithm parameter, and erase interrupt status data; obtain hardware state characteristics of the erased abnormal block according to the fault feature data, where the hardware state characteristics include power supply voltage data, erase voltage data, and memory controller status data; perform a correlation analysis on the environmental state data, the software state characteristics, and the hardware state characteristics to obtain a fault cause analysis result, where the environmental state data includes environmental electromagnetic state information, environmental communication state information, and environmental temperature and humidity information.

[0091] In one embodiment, the fault analysis module 40 is further configured to perform at least one of the following recovery operations on the memory block for which the erase operation fails according to the fault cause analysis result: perform a retry erase with adaptive erase parameters for a preset number of times under the condition of satisfying the block erase voltage threshold; perform an address remapping on the bad block for which the block recovery fails and switch to a pre-divided redundant memory area; if it is determined to be a systematic environmental interference, delay the erase operation until the environmental parameters return to normal.

[0092] In this embodiment, by performing an erase operation on the target memory area and monitoring the erase result in real time, and at the same time recording the memory state data, when the erase fails, the state data of the abnormal block and its reference block within a preset time period are extracted, and the fault feature data is generated through data comparison. Combining the hardware environment, software configuration, and storage state for multi-dimensional analysis, the root cause of the fault is determined and targeted recovery operations are performed, including adaptive retry erase, bad block remapping, or delayed erase scheduling. This method accurately identifies the cause of the erase fault through multi-dimensional data monitoring and analysis, effectively reduces misjudgment and invalid operations, and combines a differentiated erase strategy with an intelligent recovery mechanism to be able to adapt to environmental interference and automatically correct errors, improving the automatic management ability of the system.

[0093] The fault analysis device for the memory loading process provided by the present application adopts the fault analysis method for the memory loading process in the above embodiment, and can solve the technical problem of how to improve the diagnostic and processing efficiency of the ECU's Bootloader software when the memory erase fails in the prior art. Compared with the prior art, the beneficial effects of the fault analysis device for the memory loading process provided by the present application are the same as those of the fault analysis method for the memory loading process provided by the above embodiment, and other technical features in the fault analysis device for the memory loading process are the same as those disclosed in the above embodiment method, and will not be elaborated here.

[0094] The present application provides a fault analysis device for the memory loading process. The fault analysis device for the memory loading process includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the fault analysis method for the memory loading process in the first embodiment above.

[0095] Reference is made below Figure 6 , which shows a schematic structural diagram of a fault analysis device for the memory loading process suitable for implementing the embodiments of the present application. The fault analysis device for the memory loading process in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions: tablet computers), PMPs (Portable Media Players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The fault analysis device for the memory loading process shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0096] As Figure 6As shown, the fault analysis device for the memory loading process may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the fault analysis device for the memory loading process are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the fault analysis device for the memory loading process to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a fault analysis device for the memory loading process with various systems, it should be understood that it is not required to implement or have all the shown systems. More or fewer systems may be alternatively implemented or had.

[0097] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0098] The fault analysis device for the memory loading process provided by this application adopts the fault analysis method for the memory loading process in the above embodiments, and can solve the technical problem of how to improve the diagnosis and processing efficiency of the Bootloader software of the ECU in the prior art when the memory erasure fails. Compared with the prior art, the beneficial effects of the fault analysis device for the memory loading process provided by this application are the same as those of the fault analysis method for the memory loading process provided by the above embodiments, and other technical features in the fault analysis device for the memory loading process are the same as the features disclosed in the method of the previous embodiment, which will not be elaborated here.

[0099] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0100] As described above, only the specific implementation manners of this application are provided, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

[0101] This application provides a computer-readable storage medium with computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the fault analysis method for the memory loading process in the above embodiments.

[0102] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. The program code contained on the computer-readable storage medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0103] The above computer-readable storage medium can be included in the fault analysis device of the memory loading process; it can also exist independently and not be assembled into the fault analysis device of the memory loading process.

[0104] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by the fault analysis device of the memory loading process, the fault analysis device of the memory loading process is caused to: divide the target memory area to obtain multiple memory blocks, and allocate an erasure algorithm to the multiple memory blocks according to a preset rule; perform the erasure operation on the memory blocks in batches, and record the memory state data and environmental state data of the memory blocks in real time; according to the erasure operation results, divide the multiple memory blocks into erasure-abnormal blocks and reference memory blocks; obtain fault feature data according to the memory state data corresponding to the erasure-abnormal blocks of the same erasure algorithm and the memory state data corresponding to the reference memory area; and obtain a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault.

[0105] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN: Local Area Network) or a wide area network (WAN: Wide Area Network), or it can be connected to an external computer (for example, by connecting through the Internet using an Internet service provider).

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and this module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutively represented blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0107] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0108] The readable storage medium provided in this application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for performing the fault analysis method of the above-mentioned memory loading process, which can solve the technical problem of how to improve the diagnostic and processing efficiency of the ECU's Bootloader software in the case of memory erasure failure in the prior art. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the fault analysis method of the memory loading process provided in the above embodiments, and will not be elaborated here.

[0109] The computer program product provided by the present application can solve the technical problem of fault analysis in the memory loading process. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as those of the fault analysis method for the memory loading process provided in the above embodiments, and will not be elaborated herein.

[0110] The above are only partial embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A fault analysis method for a memory loading process, characterized in that The fault analysis method for the memory loading process includes: Dividing the target memory area to obtain multiple memory blocks, and allocating erasure algorithms to the multiple memory blocks according to a preset rule; Performing the erasure operation on the memory blocks in batches, and recording the memory state data and environmental state data of the memory blocks in real time; Dividing the multiple memory blocks into erasure abnormal blocks and reference memory blocks according to the erasure operation results; Obtaining fault feature data according to the memory state data corresponding to the erasure abnormal blocks with the same erasure algorithm and the memory state data corresponding to the reference memory area; Obtaining a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault.

2. The fault analysis method for the memory loading process according to claim 1, wherein The step of dividing the target memory area to obtain multiple memory blocks, and allocating erasure algorithms to the multiple memory blocks according to a preset rule includes: Determining the division quantity and the target specification of block division according to the specification parameters of the target memory area; Dividing the target memory area according to the division quantity and the target specification of block division to obtain multiple memory blocks; Retrieving multiple erasure algorithms that meet the algorithm application conditions from a preset erasure algorithm database according to the division quantity of the memory blocks; Allocating the multiple erasure algorithms to the multiple memory blocks according to a preset rule, wherein the erasure algorithms allocated to physically adjacent memory blocks are different.

3. The fault analysis method for the memory loading process according to claim 1, wherein The step of dividing the multiple memory blocks into erasure abnormal blocks and reference memory blocks according to the erasure operation results includes: Regarding the memory blocks with erasure operation results of erasure failure as erasure abnormal blocks; Regarding the memory blocks that use the same erasure algorithm as the erasure abnormal blocks and have erasure results of erasure success among the memory blocks that have completed the erasure operation as the reference memory blocks corresponding to the erasure abnormal blocks.

4. The fault analysis method for the memory loading process according to claim 3, wherein Before dividing the multiple memory blocks into erasure abnormal blocks and reference memory blocks according to the erasure operation results, it further includes: During the execution of the erasure operation, obtaining the erasure behavior verification information corresponding to each memory block that has completed the erasure operation in the target memory area in real time; Obtaining the erasure operation results of the memory blocks according to the erasure behavior verification information corresponding to each memory block, wherein the erasure behavior verification information includes at least one of block register information, block level information, and block erasure log information.

5. The fault analysis method for the memory loading process according to claim 1, wherein The step of obtaining fault feature data according to the memory state data corresponding to the erasure abnormal blocks with the same erasure algorithm and the memory state data corresponding to the reference memory area includes: Comparing the memory state data of the erasure abnormal blocks with the memory state data of the reference memory blocks item by item to determine the memory state data items whose data difference degree exceeds the data fluctuation threshold; Determining the key difference data items in the memory state data items based on the fault correlation data item list; Regarding the memory state data corresponding to the key difference data items as the fault feature data.

6. The fault analysis method for the memory loading process according to claim 1, wherein The step of obtaining a fault cause analysis result according to the fault feature data and the environmental state data corresponding to the occurrence of the fault includes: Based on the fault feature data, obtain the software status features of the erased abnormal block, where the software status features include the erased block address, the erasure algorithm parameters, and the erasure interrupt status data; Based on the fault feature data, obtain the hardware status features of the erased abnormal block, where the hardware status features include the power supply voltage data, the erasure voltage data, and the memory controller status data; Perform a correlation analysis on the environmental status data, the software status features, and the hardware status features to obtain the fault cause analysis result, where the environmental status data includes the environmental electromagnetic status information, the environmental communication status information, and the environmental temperature and humidity information.

7. The fault analysis method for the memory loading process according to any one of claims 1 to 6, characterized in that The fault analysis method for the memory loading process further includes: According to the fault cause analysis result, perform at least one of the following recovery operations on the memory block where the erasure operation fails: Under the condition of meeting the block erasure voltage threshold, perform a retry erasure with adaptive erasure parameters for a preset number of times; Perform an address remapping on the bad block where the block recovery fails, and switch to a pre-divided redundant memory area; If it is determined to be a systematic environmental interference, delay the erasure operation until the environmental parameters return to normal.

8. A fault analysis device for a memory loading process, characterized in that, The fault analysis device for the memory loading process includes: A data processing module, configured to divide a target memory area to obtain a plurality of memory blocks, and allocate an erasure algorithm to the plurality of memory blocks according to a preset rule; A data acquisition module, configured to perform erasure operations on the memory blocks in batches, and record the memory status data and the environmental status data of the memory blocks in real time; The data processing module is further configured to divide the plurality of memory blocks into erased abnormal blocks and reference memory blocks according to the erasure operation results; A fault feature extraction module, configured to obtain fault feature data according to the memory status data corresponding to the erased abnormal blocks with the same erasure algorithm and the memory status data corresponding to the reference memory area; A fault analysis module, configured to obtain a fault cause analysis result according to the fault feature data and the environmental status data corresponding to the occurrence of the fault.

9. A fault analysis device for a memory loading process, characterized in that, The fault analysis device for the memory loading process includes: a memory, a processor, and a fault analysis program for the memory loading process stored on the memory and executable on the processor, where the fault analysis program for the memory loading process is configured to implement the steps of the fault analysis method for the memory loading process according to any one of claims 1 to 7.

10. A storage medium, characterized in that, A fault analysis program for the memory loading process is stored on the storage medium, and when the fault analysis program for the memory loading process is executed by a processor, it implements the steps of the fault analysis method for the memory loading process according to any one of claims 1 to 7.

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