Testing method and testing device for IP interface circuit in GPU chip

Abstract

The invention provides a test method and a test device for an IP interface circuit in a GPU chip, and the method comprises the steps: extracting a read-write command, an address, data and time delay in a simulation task through an automatic script, and splicing the read-write command, the address, the data and the time delay into a data stream according to a specific structure; writing a test program on a test machine, reading a data stream, generating test excitation, and sending the test excitation to the IP interface circuit to be tested through an FTBus interface of the GPU chip; after the read is pulled up, reading the read data returned by the FTBus interface; and comparing the returned read data with expected data in the data stream, and judging whether the test is successful or failed according to a comparison result. According to the test method, a specific data flow structure is designed, a handshake mechanism of a bus protocol is introduced into a test program, a large amount of manual adjustment work is avoided, the problem of repeated simulation by using a VCD is also avoided, development of the test program is accelerated, and the judgment accuracy of the test program is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more particularly, to a testing method and a testing device for an IP interface circuit in a GPU chip. Background Art

[0002] Currently, the iteration of domestic GPU chip products is accelerating day by day. The GPU chip integrates high-speed interfaces such as PCIE, DDR, HDMI, DP, and display interfaces. To improve the testing efficiency of these IP interfaces, a custom unified testing interface FTBus is designed as the testing port for the IP interface circuit.

[0003] For these IP interface circuits, the flowchart of the conventional testing method can be seen in Figure 1 : First, use the EDA tool and the testing task of the IP interface for simulation to generate a VCD file; then use the vector format conversion tool to convert the VCD into a vector format that the testing machine can recognize; finally, conduct tests on the machine, compare the response and expectation of each testing cycle, and determine whether the test is pass or fail. Due to the inaccurate simulation model, the VCD generated by the simulation cannot completely correspond to the actual response one by one, and it is possible that the read data is advanced or delayed, as shown in Figure 2 . This will cause the testing machine to compare the response with the expectation and fail, resulting in misjudgment. For the test items with a small amount of test data, the comparison point can be adjusted manually, but for the test with a large amount of data, manual adjustment will consume a lot of time and delay the progress of the development of the testing program. Summary of the Invention

[0004] The present invention provides a testing method and a testing device for an IP interface circuit in a GPU chip aiming at the technical problems existing in the prior art, which can solve the misjudgment problem caused by the conventional VCD testing, and improve the accuracy of the testing program judgment and the development efficiency of the testing program.

[0005] According to a first aspect of the present invention, there is provided a testing method for an IP interface circuit in a GPU chip, including:

[0006] Extract the read and write commands, addresses, data, and delays in the simulation task through an automated script, and splice them into a data stream according to a specific structure;

[0007] Write a testing program on the testing machine, read the data stream, generate a test stimulus, and send the test stimulus to the IP interface circuit to be tested through the FTBus interface of the GPU chip;

[0008] After waiting for the ready signal to be pulled high, read the read data returned by the FTBus interface;

[0009] Compare the returned read data with the expected data in the data stream, and determine whether the test is successful or failed according to the comparison result.

[0010] Based on the above technical solutions, the present invention can also be improved as follows.

[0011] Optionally, the splicing into a data stream according to a specific structure includes:

[0012] Set corresponding identifiers before each piece of data according to the operation type to form a read-write data stream including delay information, where the identifier represents the operation performed on the subsequent piece of data, the write operation defaults to no identifier, the identifier for the read operation is -2, and the identifier for the delay operation is -1.

[0013] Optionally, the writing a test program on the test machine, reading the data stream, generating a test stimulus, and sending the test stimulus to the IP interface circuit under test through the FTBus interface of the GPU chip includes:

[0014] The test program reads the data stream and sequentially detects the identifiers in the data stream;

[0015] According to the detected identifier, sequentially execute the operations in the data stream, generate corresponding test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip.

[0016] Optionally, the according to the detected identifier, sequentially execute the operations in the data stream, generate corresponding test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip includes:

[0017] If the "-1" identifier in the data stream is detected, perform a delay operation, and after the delay operation ends, perform the next operation;

[0018] If the "-2" identifier in the data stream is detected, perform a read operation, generate an FTBus read operation timing sequence, send the read operation timing sequence to the IP interface circuit under test through the FTBus interface of the GPU chip, wait for ready to be pulled high, read the read data returned by the FTBus interface, compare the returned read data with the expected data in the data stream, and continue to perform the next operation;

[0019] If no identifier is detected, perform a write operation, generate an FTBus write operation timing sequence, send the write operation timing sequence to the IP interface circuit under test through the FTBus interface of the GPU chip, and continue to perform the next operation.

[0020] Optionally, comparing the read data to be returned with the expected data in the data stream, and determining whether the test is successful or failed according to the comparison result, includes:

[0021] After all read operations in the data stream are completed, when the read data returned through the FTBus interface is consistent with the expected data in the data stream, the IP interface circuit test is successful; otherwise, the IP interface circuit test fails.

[0022] According to a second aspect of the present invention, there is provided a test apparatus for an IP interface circuit in a GPU chip, including a test machine ATE and a GPU chip. The GPU chip includes a unified test FTBus interface and multiple IP interface circuits. A test program is deployed on the test machine ATE:

[0023] The test program is used to extract read and write commands, addresses, data, and delays in the simulation task through an automated script, and splice them into a data stream according to a specific structure; and is used to write a test program on the test machine, read the data stream, generate test stimuli, and send the test stimuli to the IP interface circuit to be tested through the FTBus interface of the GPU chip; and is further used to wait until ready is pulled high, read the read data returned by the FTBus interface, compare the returned read data with the expected data in the data stream, and determine whether the test is successful or failed according to the comparison result.

[0024] The test method and test apparatus for an IP interface circuit in a GPU chip provided by the present invention design a unique data stream structure, introduce the handshaking mechanism of the bus protocol into the test program, avoid a large amount of manual adjustment work, and when the ready signal is pulled high, compare the data to determine whether the test is successful, and also avoid the problem of repeatedly running the simulation using VCD, which is beneficial to accelerating the development of the test program and improving the accuracy of the test program judgment. Description of the Drawings

[0025] Figure 1 It is a flowchart of the VCD test method for the prior art;

[0026] Figure 2 It is a schematic diagram of misjudgment caused by inaccurate models in the prior art;

[0027] Figure 3 It is a flowchart of the test method for an IP interface circuit in a GPU chip provided by an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the data stream structure provided by an embodiment of the present invention;

[0029] Figure 5 It is a flowchart of the test stimulus generation program provided by an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of a test device for an IP interface circuit in a GPU chip provided by an embodiment of the present invention. Specific embodiments

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Additionally, the technical features in each embodiment or individual embodiment provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. This combination is not restricted by the order of steps and / or the structure composition mode, but must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0032] Figure 3 This is a flowchart of a test method for an IP interface circuit in a GPU chip provided by the present invention. As Figure 3 shown, the method includes:

[0033] Step 1: Extract read / write commands, addresses, data, and delays in the simulation task through an automated script, and splice them into a data stream according to a specific structure.

[0034] In an embodiment of the present invention, the splicing into a data stream according to a specific structure includes:

[0035] Set corresponding identifiers before each piece of data according to the operation type to form a read / write data stream including delay information, where the identifier represents the operation performed on the subsequent piece of data. The write operation defaults to no identifier, the identifier for the read operation is -2, and the identifier for the delay operation is -1.

[0036] It is understandable that when it is necessary to test the IP interface circuit in the GPU chip, a simulation task is obtained. The simulation task is provided by the IP manufacturer / written in advance for testing and is a file used for VCS simulation. An automated script is used to extract the read and write commands, addresses, data, and delays in the simulation task and splice them into a data stream according to a specific structure. Special identifiers are used in the data stream to distinguish read and write operations and delays. Since write operations are the most frequent in testing, the default is a write operation, that is, no identifier is set for write operations, "-2" represents that the next operation is a read operation, and "-1" represents a delay operation. This data stream structure simplifies the design of the test program. The structure of the spliced data stream is as Figure 4 shown.

[0037] Step 2: Write a test program on the test machine, read the data stream, generate test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip.

[0038] Step 3: After waiting for ready to be pulled high, read the read data returned by the FTBus interface;

[0039] Step 4: Compare the returned read data with the expected data in the data stream, and judge whether the test is successful or failed according to the comparison result.

[0040] It is understandable that a test program is written on the test machine, and test stimuli for the IP interface circuit are generated based on the test program. Specifically, refer to Figure 5 , the test program reads the data stream and detects the identifiers in the data stream, and sequentially executes the operations in the data stream. When "-1" is detected, a delay operation is executed. After the delay operation ends, the next operation is executed. When "-2" is detected, a read operation is executed, generating an FTBus read operation timing sequence. The stimulus (read operation timing sequence) is sent to the IP interface circuit under test through the unique FTBus interface of the GPU chip. After waiting for ready to be pulled high, the read data returned by the FTBus interface is read, and the returned read data is compared with the expected data in the data stream, and the next operation is continued. If no identifier is detected, a write operation is executed, generating an FTBus write operation timing sequence. The stimulus (write operation timing sequence) is sent to the IP interface circuit under test through the unique FTBus interface of the GPU chip, and the next operation is continued.

[0041] In an embodiment of the present invention, comparing the returned read data with the expected data in the data stream and judging whether the test is successful or failed according to the comparison result includes:

[0042] When all read operations in the data stream are completed and the read data returned through the FTBus interface is consistent with the expected data in the data stream, the IP interface circuit test is successful; otherwise, the IP interface circuit test fails.

[0043] It can be understood that after each operation in the data stream is completed, the read data returned by the FTBus interface after all read operations are completed is obtained, and the read data is compared with the expected data in the data stream. When all the returned read data is consistent with the expected data, the IP interface circuit test is successful; otherwise, the IP interface circuit test fails.

[0044] See Figure 6 , a test device for an IP interface circuit in a GPU chip provided by an embodiment of the present invention. The test device mainly includes a test machine ATE and a GPU chip. The GPU chip includes a unified test FTBus interface and multiple IP interface circuits to be tested, such as Figure 6 the HDMI interface, DP interface, PCIE interface, and DDR interface in , a test program is deployed on the test machine ATE, and the application program on the test machine ATE tests the IP interface circuit in the GPU chip.

[0045] Specifically, the test program is used to extract read and write commands, addresses, data, and delays in the simulation task through an automated script and splice them into a data stream according to a specific structure; and is used to write a test program on the test machine, read the data stream, generate a test stimulus, and send the test stimulus to the IP interface circuit to be tested through the FTBus interface of the GPU chip; and is also used to wait until ready is pulled high, read the read data returned by the FTBus interface, compare the returned read data with the expected data in the data stream, and judge whether the test is successful or failed according to the comparison result.

[0046] It can be understood that a test device for an IP interface circuit in a GPU chip provided by the present invention corresponds to the test method for an IP interface circuit in a GPU chip provided by the foregoing embodiments. The relevant technical features of the test device for an IP interface circuit in a GPU chip can refer to the relevant technical features of the test method for an IP interface circuit in a GPU chip, and will not be elaborated here.

[0047] A testing method and testing device for an IP interface circuit in a GPU chip provided by an embodiment of the present invention extract read and write commands, addresses, data, and delays in a simulation task through an automated script, and splice them into a data stream according to a specific structure; the data stream structure is a custom format, and the identifiers "-1" and "-2" are used to represent delays and read operations respectively; write a test program to sequentially read the array content and generate test stimuli, and give them to the IP interface circuit under test through the FTBus interface; perform tests on the test machine table, and after detecting that hready is pulled high, compare the response with the expectation. This method designs a unique data stream structure and introduces the handshake mechanism of the bus protocol into the test program, which is beneficial to accelerating the development of the test program and improving the accuracy of the test program judgment.

[0048] It should be noted that in the above embodiments, the descriptions of each embodiment have their own emphases. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0049] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0051] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable apparatus to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one process or a plurality of processes and / or boxes Figure 1 One process or a plurality of processes and / or boxes Figure 1 Or steps of the functions specified in a plurality of boxes.

[0053] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn of the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention.

[0054] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A test method for an IP interface circuit in a GPU chip, characterized in that, Including: Extract read and write commands, addresses, data, and delays in the simulation task through an automated script, and splice them into a data stream according to a specific structure; Write a test program on the test machine, read the data stream, generate test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip; After waiting for ready to be pulled high, read the read data returned by the FTBus interface; Compare the returned read data with the expected data in the data stream, and judge whether the test is successful or failed according to the comparison result.

2. The test method according to claim 1, characterized in that, The splicing into a data stream according to a specific structure includes: Set corresponding identifiers before each piece of data according to the operation type to form a read / write data stream including delay information, where the identifier represents the operation performed on the subsequent piece of data. The write operation defaults to no identifier, the identifier for the read operation is -2, and the identifier for the delay operation is -1.

3. The test method according to claim 2, wherein The writing of the test program on the test machine, reading the data stream, generating test stimuli, and sending the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip includes: The test program reads the data stream and sequentially detects the identifiers in the data stream; According to the detected identifiers, sequentially execute the operations in the data stream, generate corresponding test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip.

4. The testing method according to claim 3, wherein The sequentially executing the operations in the data stream according to the detected identifiers, generating corresponding test stimuli, and sending the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip includes: If the "-1" identifier in the data stream is detected, perform a delay operation. After the delay operation ends, perform the next operation; If the "-2" identifier in the data stream is detected, perform a read operation, generate an FTBus read operation timing sequence, send the read operation timing sequence to the IP interface circuit under test through the FTBus interface of the GPU chip. After waiting for ready to be pulled high, read the read data returned by the FTBus interface, compare the returned read data with the expected data in the data stream, and continue to perform the next operation; If no identifier is detected, perform a write operation, generate an FTBus write operation timing sequence, send the write operation timing sequence to the IP interface circuit under test through the FTBus interface of the GPU chip, and continue to perform the next operation.

5. The test method according to claim 4, wherein The comparing the returned read data with the expected data in the data stream and judging whether the test is successful or failed according to the comparison result includes: When all the read operations in the data stream are completed and the read data returned through the FTBus interface is consistent with the expected data in the data stream, the IP interface circuit test is successful; otherwise, the IP interface circuit test fails.

6. A test device for an IP interface circuit in a GPU chip, characterized in that, Including a test machine ATE and a GPU chip. The GPU chip includes a unified test FTBus interface and multiple IP interface circuits under test. A test program is deployed on the test machine ATE: The described test program is used to extract read and write commands, addresses, data, and delays in the simulation task through an automated script, and splice them into a data stream according to a specific structure; and is used to write a test program on a test machine, read the data stream, generate test stimuli, and send the test stimuli to the IP interface circuit under test through the FTBus interface of the GPU chip; It is also used to, after waiting for the ready signal to be pulled high, read the read data returned by the FTBus interface, compare the returned read data with the expected data in the data stream, and determine whether the test is successful or failed according to the comparison result.

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