Digital beam forming chip accompanying test logic system based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the field of chip testing, in particular to a digital beam forming chip accompanying test logic system based on an FPGA. Comprising a communication module, a command acquisition module, a command analysis module, a Serdes module and a read and write cache, when the command parsing module parses a write command, to-be-written data subsequently received by the command obtaining module is written into a write cache, and then the Serdes module is controlled to read the data from the write cache and send the data to the beam forming chip through the sending port; the receiving end of the Serdes module stores the effective content sent by the beam forming chip into a read cache; and when the command parsing module parses the read command, the content in the read cache is sent to the upper computer until the content in the read cache is empty. According to the accompanying test logic, the main data channel test of the chip can be completed through one FPGA, and the logic is high in expandability and can cope with various test environments and structures.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and particularly to a co-testing logic system for a digital beamforming chip based on FPGA. Background Art

[0002] The structural block diagram of the digital beamforming chip is as Figure 1 shown. The overall structure of the chip is designed symmetrically, divided into two optical fiber groups, with N optical fibers in each group. The data of each optical fiber is connected to external data through M Serdes, and after serial-to-parallel conversion, the data is unpacked, weighted, and the synthesized data of each optical fiber is transmitted to the middle processing module (Pro Mid). This module includes instruction parsing, weight management, and data extraction modules between optical fibers. Finally, all the data of the optical fibers within a single group is transmitted to the central module (Center). In this module, mainly the data between the two groups is beamformed again, and auxiliary modules such as instruction and parameter management are included. The original data goes through encoding and decoding, serial-to-parallel conversion, in-fiber beamforming, between-fiber beamforming, between-group beamforming, and finally is transmitted to the host computer through the network port to observe the data. The parameters used during the chip operation are read by the CPU from the external flash and then sent to the central module through the bus.

[0003] Since the digital beamforming chip uses the Serdes interface as the input end of the excitation data and the output end of the calculation result, although such an interface has high transmission efficiency, it cannot directly communicate with the host computer, so the calculation results cannot be compared in real time. Summary of the Invention

[0004] This patent details a co-testing logic architecture design based on FPGA for the code architecture of the digital beamforming chip, taking into account both the simplicity of the architecture and the comprehensiveness of the functions. It can be used for testing the FPGA prototype verification before tape-out and for testing the main data path of the chip after tape-out. In this way, before the chip is widely applied, its functions can be pre-tested to facilitate early discovery of potential problems.

[0005] The present invention provides a co-testing logic system for a digital beamforming chip based on FPGA, including:

[0006] A communication module obtained by configuring the communication interface of the FPGA: used for communicating with the host computer;

[0007] A command acquisition module obtained by configuring the FPGA: used for receiving the data obtained by the communication module for caching, or sending the data of this module to the host computer through the communication module;

[0008] The command parsing module obtained by configuring the FPGA: used to parse the content from the host computer cached in the command acquisition module to perform corresponding operations;

[0009] The Serdes module obtained by configuring the FPGA: used to communicate with the beamforming chip;

[0010] The write cache obtained by configuring the FPGA: used to cache the data from the command acquisition module;

[0011] The read cache obtained by configuring the FPGA: used to cache the data from the Serdes module;

[0012] Among them, the sending port of the Serdes module continuously sends the common code to the beamforming chip. When the command parsing module parses a write command, it writes the data to be written received by the command acquisition module subsequently into the write cache. After all the data to be written is stored in the write cache, it controls the Serdes module to read the data from the write cache and send it to the beamforming chip through the sending port;

[0013] The receiving end of the Serdes module continuously receives the data sent by the beamforming chip, filters the common code, and stores the valid content in the read cache;

[0014] When the command parsing module parses a read command, it writes the content in the read cache into the command acquisition module, and then sends it to the host computer through the communication module until the content in the read cache is emptied.

[0015] Preferably, the co-test logic system also has a self-loop function. The specific content is: when the command parsing module parses a self-loop command, it writes the subsequent data of the command acquisition module into the write cache. After writing is completed, it writes the data in the write cache into the read cache. After writing is completed, it writes the content in the read cache into the command acquisition module, and then sends it to the host computer through the communication module until the content in the read cache is emptied.

[0016] Preferably, the number of Serdes modules is more than two, and each Serdes module has a corresponding write cache and read cache.

[0017] Preferably, the communication interface is a serial port.

[0018] Preferably, the read cache and write cache are obtained by configuring the RAM of the FPGA.

[0019] Preferably, the number of channels of the Serdes module is the same as that of the corresponding digital beamforming chip.

[0020] Beneficial effects: The co-testing logic of the present invention can complete the testing of the main data channels of the chip through a single FPGA, and this logic has strong scalability and can handle various testing environments and structures. Description of the Drawings

[0021] Figure 1 It is a structural block diagram of a digital beamforming chip;

[0022] Figure 2 It is a structural diagram of the present invention;

[0023] Figure 3 It is a reference configuration diagram of the Serdes module in the embodiment; Detailed Embodiment

[0024] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0025] As Figure 2 shown, where the host computer is responsible for organizing commands and excitation data and recovering the calculation results for software comparison. The digital beamforming chip here can be a chip that has been taped out or a FPGA prototype verification before tape-out. The middle co-testing logic system is the system described in this patent, which is used to send the excitation data from the host computer to the digital beamforming chip and read back the results of the digital beamforming chip and send them to the host computer.

[0026] A co-testing logic system for a digital beamforming chip based on FPGA, comprising:

[0027] A communication module obtained by configuring the communication interface of the FPGA: used for communicating with the host computer;

[0028] The FPGA can communicate with the host computer through various interfaces. Commonly used ones include serial ports, USB, network ports, etc. If the excitation data has low requirements for real-time performance, a serial port can be used, which can simplify the debugging of the communication interface. If there are many types of excitation data and high real-time performance requirements, interfaces such as USB and network ports can be used; in this embodiment, the communication interface is a serial port;

[0029] A command acquisition module obtained by configuring the FPGA: used for receiving the data obtained by the communication module for caching, or sending the data of this module to the host computer through the communication module;

[0030] When the data bit width transmitted by a single clock is insufficient to support the expression of command information, multiple clocks are required to transmit data to form a command. Therefore, a command acquisition module is set up. In this embodiment, the serial port transmits 8-bit data each time, but a command has 40-bit data. Therefore, 40-bit data is cached in the command acquisition module for subsequent modules to parse. When sending data to the host computer, 40-bit data is also cached each time, and the serial port sends 8-bit data each time.

[0031] The command parsing module obtained by configuring the FPGA: used to parse the content from the host computer cached in the command acquisition module to perform corresponding operations;

[0032] The Serdes module obtained by configuring the FPGA: used to communicate with the beamforming chip;

[0033] In this embodiment, the Serdes interface of the beamforming chip has 8 channels; the FPGA is of the Virtex UltraScale series from Xilinx, and a Transceiver is used to generate an 8-lane, 1Gbps Serdes. Figure 3 It is a reference configuration diagram of the Serdes module.

[0034] The write buffer (Wrbuf) obtained by configuring the FPGA: used to cache data from the command acquisition module;

[0035] The read buffer (Rdbuf) obtained by configuring the FPGA: used to cache data from the Serdes module;

[0036] As Figure 2 shown, since the Serdes module is set to 8 lanes in this embodiment, the corresponding write buffer and read buffer also have 8 sub-buffers;

[0037] Among them, the sending port of the Serdes module continuously sends common codes to the beamforming chip. When the command parsing module parses a write command, it writes the data to be written received by the command acquisition module subsequently into the write buffer. After all the data to be written is stored in the write buffer, it controls the Serdes module to read the data from the write buffer and send it to the beamforming chip through the sending port;

[0038] The receiving end of the Serdes module continuously receives the data sent by the beamforming chip, filters the common codes, and stores the valid content in the read buffer;

[0039] When the command parsing module parses a read command, it writes the content in the read buffer into the command acquisition module, and then sends it to the host computer through the communication module until the content in the read buffer is emptied.

[0040] As a preferred embodiment, the co-test logic system further has a self-loop function, and the specific content is as follows: when the command parsing module parses a self-loop command, it writes the subsequent data of the command acquisition module into the write cache. After the writing is completed, it writes the data in the write cache into the read cache. After the writing is completed, it writes the content in the read cache into the command acquisition module and then sends it to the host computer until the content in the read cache is emptied, so as to realize the stability detection of the communication module, the read cache, and the write cache.

[0041] As a preferred embodiment, the number of Serdes modules is more than two, and each Serdes module has a corresponding write cache and read cache to realize multi-chip cascade testing.

[0042] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A co-test logic system for a digital beamforming chip based on FPGA, characterized in that, Including: A communication module obtained by configuring the communication interface of the FPGA: used for communicating with the host computer; A command acquisition module obtained by configuring the FPGA: used for receiving the data acquired by the communication module for caching, or sending the data of this module to the host computer through the communication module; A command parsing module obtained by configuring the FPGA: used for parsing the content from the host computer cached in the command acquisition module to execute corresponding operations; A Serdes module obtained by configuring the FPGA: used for communicating with the beamforming chip; A write cache obtained by configuring the FPGA: used for caching the data from the command acquisition module; A read cache obtained by configuring the FPGA: used for caching the data from the Serdes module; Among them, the sending port of the Serdes module continuously sends the common code to the beamforming chip. When the command parsing module parses the write command, it writes the data to be written received by the command acquisition module subsequently into the write cache. After all the data to be written are stored in the write cache, it controls the Serdes module to read the data from the write cache and send it to the beamforming chip through the sending port; The receiving end of the Serdes module continuously receives the data sent by the beamforming chip, and after filtering the common code, stores the valid content in the read cache; When the command parsing module parses the read command, it writes the content in the read cache into the command acquisition module, and then sends it to the host computer through the communication module until the content in the read cache is emptied.

2. The digital beamforming chip co-test logic system based on FPGA according to claim 1, characterized in that, The co-test logic system also has a self-loop function. The specific content is: when the command parsing module parses the self-loop command, it writes the subsequent data of the command acquisition module into the write cache. After writing is completed, it writes the data in the write cache into the read cache. After writing is completed, it writes the content in the read cache into the command acquisition module, and then sends it to the host computer through the communication module until the content in the read cache is emptied.

3. A co-test logic system for a digital beamforming chip based on FPGA according to claim 1, characterized in that, The number of the Serdes modules is more than two, and each Serdes module has a corresponding write cache and read cache.

4. A co-testing logic system for a digital beamforming chip based on FPGA according to claim 1, wherein, The communication interface is a serial port.

5. A co-test logic system for a digital beamforming chip based on FPGA according to claim 1, wherein The read cache and the write cache are obtained by configuring the RAM of the FPGA.

6. The co-test logic system of a digital beamforming chip based on FPGA according to claim 1, wherein The number of channels of the Serdes module is the same as that of the corresponding digital beamforming chip.

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