Multi-channel DDR4 storage device based on FPGA

Abstract

The invention relates to a multichannel DDR4 (Double Data Rate 4) storage device based on an FPGA (Field Programmable Gate Array). The device comprises an FPGA unit and a DDR4 memory, wherein the FPGA unit comprises an MIG module, a multi-channel scheduling module, a data buffer module, an on-chip memory and a dynamic address generation module; the MIG module is used for being connected with the DDR4 memory; the multi-channel scheduling module is connected with the MIG module, the data buffer module and the dynamic address generation module, and performs read-write operation on each channel in sequence in a time-sharing polling mode; the data buffering module is positioned between the multi-channel scheduling module and the on-chip memory and is used for buffering data read from the DDR4 memory; the on-chip memory is used for storing data read from the data buffer module; and the dynamic address generation module is used for generating an on-chip storage address of the data read from the data buffer module. The device provided by the invention can improve read-write efficiency, save storage resources and simplify data management.

Description

Technical Field

[0001] The present invention belongs to the technical field of data storage, and relates to a multi-channel DDR4 storage device based on FPGA. Background Art

[0002] FPGA (Field Programmable Gate Array) is a programmable integrated circuit, which is widely used in various electronic systems. The FPGA usually contains various storage resources inside, such as DRAM, BRAM, URAM, etc., for storing data and programs. However, the capacity of these internal storage resources is relatively limited. When the design requirements exceed the internal storage capacity, an external memory needs to be added to expand the storage capacity. As a high-performance DRAM memory, DDR4 is often used as the external storage resource of FPGA due to its characteristics such as high bandwidth and large capacity. The current FPGA external storage scheme generally adopts the "controller + scheduling module + independent FIFO" architecture, including the traditional single-channel storage architecture, and the connection mode between the FPGA and the DDR4 is usually single-channel. In this architecture, the FPGA interacts with the DDR4 through one channel. However, the single-channel architecture has obvious performance bottlenecks when processing a large number of different types of data or many data blocks of the same type, as shown in Figure 1.

[0003] To solve the performance bottleneck problem of the single-channel architecture, some studies have proposed a multi-channel DDR4 storage architecture. In this architecture, the FPGA interacts with the DDR4 through multiple channels, and each channel can perform read and write operations independently. However, the existing multi-channel DDR4 storage architectures still have some problems. First, when storing data, the existing multi-channel architectures do not effectively classify and store different types of data, resulting in a large amount of data screening and processing required when reading data, increasing the complexity and latency of the system. When processing a large amount of data, the existing multi-channel architectures still require a large number of FIFOs to cache the read data, consuming a large amount of FIFO resources and unable to effectively solve the problem of insufficient FIFO resources inside the FPGA, as Figure 2 shown. In addition, the dynamic refresh characteristic of the DDR4 causes that normal read and write operations cannot be performed during the refresh period, and the time delay from the read address to the data transmission changes dynamically, affecting the read and write efficiency. The precharge operation of the DDR4 will also cause a reduction in bandwidth, further affecting the data read and write efficiency. In terms of resource utilization, the fixed RAM partition leads to resource waste: using a BRAM space with a fixed size as the storage space causes the low-bandwidth channels (such as control signals) to occupy the entire BRAM block (36KB), wasting the BRAM space. Summary of the Invention

[0004] In view of the above-mentioned many problems existing in the prior art, the present invention provides a multi-channel DDR4 storage device based on FPGA.

[0005] The technical solution adopted by the present invention is: a multi-channel DDR4 storage device based on an FPGA unit, including an FPGA unit and a DDR4 memory. The FPGA unit includes: a MIG module, a multi-channel scheduling module, a data buffer module, an on-chip memory, and a dynamic address generation module; The MIG module is used to connect to the DDR4 memory to implement the conversion between the DDR4 physical interface and the AXI interface; The multi-channel scheduling module is connected to the MIG module, the data buffer module, and the dynamic address generation module, and is used to manage multiple DDR4 channels to implement time-sharing polling scheduling of multiple channels to ensure independent read and write operations for each channel; The data buffer module is located between the multi-channel scheduling module and the on-chip memory and is used to cache the data read from the DDR4 memory; The on-chip memory is used to store the data read from the data buffer module; The dynamic address generation module is used to generate the on-chip storage address of the data read from the data buffer module. Using the dynamic address sharding algorithm, the start address is dynamically divided according to the data bandwidth to generate the data dynamic storage address and store the data corresponding to different read and write channels.

[0006] Preferably, the multi-channel scheduling module distributes different types of data to different DDR4 channels according to the type and quantity of the data.

[0007] Preferably, the length of time occupied by the DDR4 storage device's read and write clock is calculated according to the amount of data, specifically: ; where is the number of time slots divided by the DDR4 storage device's read and write clock; is the preset weight of channel , is the preset weight of the real-time bandwidth demand factor, is the read and write clock of the DDR4 storage device.

[0008] Preferably, the dynamic address generation module stores in the manner of the row space size. For any access address, through mask operation, the row start address is aligned: ； where is the single-row capacity.

[0009] Preferably, reading and writing access the head address of each row of the cell array in the DDR4 memory; when reading data from the DDR4 memory, the data is first stored in the data buffer module, and then further stored in the on-chip memory according to the type and usage requirements of the data.

[0010] Preferably, the on-chip memory uses BRAM or URAM.

[0011] Compared with the prior art, the present invention has the following advantages: 1. Improve read and write efficiency: By multi-channel time-sharing polling scheduling and optimizing the DDR4 read and write address design, adopting the read and write head address alignment method, the impact of DDR4 dynamic refresh on read and write efficiency is effectively reduced, and the data read and write efficiency is improved.

[0012] 2. Save storage resources: Adopting a multi-level storage method and dynamic address sharding technology, the repeated instantiation of a large number of FIFOs is reduced, saving the internal storage resources of the FPGA.

[0013] 3. Simplify data management: By storing different types of data in different DDR4 channels, the data management process is simplified, and the complexity and latency of the system are reduced.

[0014] 4. Improve system performance: Through a multi-level storage method and a fast data access mechanism, the overall performance of the system is improved, meeting the requirements of large-scale data storage and processing. Description of the Drawings

[0015] Figure 1 Is a schematic diagram of single-channel DDR4 access in the prior art; Figure 2 Is a schematic diagram of multi-channel DDR4 access in the prior art; Figure 3 Is a schematic diagram of the multi-channel DDR4 storage device based on FPGA provided in the embodiment of the present invention. Detailed Embodiments

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings.

[0017] The multi-channel DDR4 storage device based on FPGA provided by the present invention, as Figure 3 shown, mainly consists of an FPGA unit and a DDR4 memory. DDR4 memory: As an external storage resource, it is used to store a large amount of data to meet the requirements of large-scale data storage.

[0018] The FPGA unit mainly includes the following parts: DDR4 MIG module 101: To simplify the design, FPGA manufacturers provide a general IP core for the memory interface, which can convert the DDR4 physical interface into an AXI interface.

[0019] Multi-channel scheduling module 102: Connected to the MIG module, it is responsible for managing multiple DDR4 channels, implementing time-division polling scheduling for multiple channels, and ensuring that each channel can perform read and write operations independently.

[0020] Data buffer module 103: Located between the multi-channel scheduling module and the on-chip memory, it is used to cache the data read from DDR4, reducing the impact of DDR4 read and write latency on system performance.

[0021] On-chip memory 104: Includes URAM, etc., and is used to store the data read from the buffer, enabling fast access and processing of data.

[0022] Dynamic address generation module 105: Used to generate the on-chip storage address of the data in the buffer, adopting a dynamic address sharding algorithm to achieve dynamic data sharding.

[0023] The multi-channel scheduling module adopts a multi-channel time-division polling scheduling strategy. According to the type and quantity of data, different types of data are allocated to different DDR4 channels. The multi-channel scheduling module performs read and write operations on each channel in turn through time-division polling. In each time slice, only one channel performs read and write operations, while other channels are in a waiting state. This can avoid multiple channels performing read and write operations on DDR4 simultaneously, thereby reducing the impact of DDR4 dynamic refresh on read and write efficiency.

[0024] Each read and write clock cycle of the DDR4 storage device can be divided into micro-slots, and the slot width is dynamically adjusted: ; Where: is the preset weight of channel , is the preset weight of the real-time bandwidth demand factor, is the read and write clock of the DDR4 storage device.

[0025] The slot width of different bandwidth data is calculated, that is, the length of time occupying the read and write clock of the DDR4 storage device is divided according to the amount of data.

[0026] Regarding the DDR4 dynamic refresh problem, the present invention proposes a storage method based on the row space size and designs the starting DDR4 addresses for multi-channel read and write data. Reading and writing access the head address of each row in the cell array of DDR4, which can reduce the bandwidth reduction problem caused by skipping DDR4 precharging and improve the data read and write efficiency. The specific methods include: the address generation rule of the dynamic address generation module: row start addressing, that is, for any access address ADDR, through mask operation, force row alignment.

[0027] ; Among them, is the single-row capacity.

[0028] When reading data from DDR4, the data is first stored in the buffer and then, according to the data type and usage requirements, further stored in the on-chip memory using a multi-level buffer. Implement row caching. In the buffer, extract the useful data in the row storage.

[0029] Dynamic allocation of on-chip storage resources: Through the way of a common memory pool, cascade the on-chip storage resources and, through the dynamic address generation module, achieve dynamic division of the starting address of on-chip resources according to the data bandwidth. Avoid excessive storage space occupied by low-bandwidth data streams.

Claims

1. A multi-channel DDR4 storage device based on FPGA units, comprising an FPGA unit and a DDR4 memory, characterized in that, The FPGA unit includes: a MIG module, a multi-channel scheduling module, a data buffer module, an on-chip memory, and a dynamic address generation module; The MIG module is used to connect to the DDR4 memory and convert the physical interface into an AXI interface; The multi-channel scheduling module is connected to the MIG module, the data buffer module, and the dynamic address generation module, and performs read and write operations on each channel in turn by means of time-sharing polling; The data buffer module is located between the multi-channel scheduling module and the on-chip memory and is used to cache the data read from the DDR4 memory; The on-chip memory is used to store the data read from the data buffer module; The dynamic address generation module is used to generate the on-chip storage address of the data read from the data buffer module. By using the dynamic address sharding algorithm, the start address is dynamically divided according to the data bandwidth to generate the data dynamic storage address and store the data corresponding to different read and write channels.

2. The multi-channel DDR4 storage device based on FPGA units according to claim 1, wherein The multi-channel scheduling module distributes different types of data to different DDR4 channels according to the type and quantity of the data.

3. The multi-channel DDR4 storage device based on FPGA units according to claim 2, characterized in that, Calculate the length of time occupied by the read and write clock of the DDR4 storage device according to the amount of data required bandwidth, specifically: ； Among them, is the number of time slots divided in one read / write clock cycle of the DDR4 storage device; is the channel 's preset weight, is the preset weight of the real-time bandwidth demand factor, is the read / write clock of the DDR4 storage device.

4. The multi-channel DDR4 storage device based on FPGA units according to claim 1, characterized in that, The dynamic address generation module stores in the manner of the row space size. For any access address, through mask operation, the row start address is aligned: ； Among them, is the single-line capacity.

5. The multi-channel DDR4 storage device based on FPGA units according to claim 1, wherein Read and write access the head address of each row of the cell array in the DDR4 memory; when reading data from the DDR4 memory, the data is first stored in the data buffer module, and then further stored in the on-chip memory according to the type and usage requirements of the data.

6. The multi-channel DDR4 storage device based on FPGA units according to any one of claims 1-5, characterized in that The on-chip memory described above uses BRAM or URAM.

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