An optimization method for merging D-type flip-flops

Abstract

The present invention belongs to the field of electronic design automation technology and specifically discloses a method for optimizing the merging of D-type flip-flops. The method comprises: obtaining and classifying D-type flip-flops in a circuit by type; selecting pairs of D-type flip-flops of the same type and determining whether their preset control signals are from the same source; if the control signals are from the same source, performing an iterative structural comparison of the driving logic cones of their data input terminals; the iterative comparison is performed by initializing a source instance container and comparing the number and type of source instances in the container layer by layer, as well as the sources of their input signals; if the iterative comparison results indicate that the logic cone structures are equivalent, the D-type flip-flop pairs are determined to be equivalent and the circuits are merged and updated. The present invention can effectively cover complex logic structures, improve operational efficiency, and handle loops, thereby more effectively reducing design area and power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic design automation, and in particular relates to an optimization method for merging D-type flip-flops. Background Art

[0002] In digital integrated circuit design, D-type flip-flops (DFFs) are the basic building blocks of sequential logic circuits. Their number and connection method directly affect the chip's area, power consumption, and performance. To optimize the design, logic synthesis tools often attempt to merge functionally equivalent DFFs.

[0003] Currently, the methods for merging DFFs mainly include homology optimization and equivalence verification.

[0004] The homologous source optimization method determines whether the input signals of two DFFs (such as data input D, clock CLOCK, set SET, reset RESET, enable ENABLE, etc.) all come from the same signal source. If all corresponding input signals come from the same source, the two DFFs are considered equivalent and can be merged. However, this method has limitations: when the data inputs (D terminals) of two DFFs are connected to structurally different but functionally equivalent combinational logic cones, the homologous source optimization method cannot determine the equivalence of the two DFFs due to the different direct drive signal sources of the D terminals, thus missing the optimization opportunity. For example, if the D inputs of two DFFs are driven by (A & B) and (B & A), respectively, despite logical equivalence, homologous source optimization cannot identify them.

[0005] The equivalence verification method is more complex. It first checks whether the control signals (such as CLOCK, SET, RESET, and ENABLE) of the two DFFs share the same source. If so, it further traverses the D inputs of the two DFFs to obtain their respective combinatorial logic cones. Then, a Boolean logic-based equivalence checking algorithm (such as one based on a SAT solver or BDD construction) is used to determine whether the two logic cones are functionally equivalent. If so, the DFFs are considered equivalent and can be merged. A drawback of this method is that when the combinatorial logic cones on the DFF data side are large, the computational complexity of the Boolean equivalence check increases dramatically, resulting in excessive runtime and low efficiency.

[0006] In addition, both of the above-mentioned existing methods have shortcomings when processing feedback loop circuit structures formed by DFFs and combinational logic, and it is difficult to effectively identify and merge equivalent DFFs in such structures.

[0007] Therefore, in terms of DFF merging optimization, existing technologies have problems such as insufficient ability to cover complex logic structures, low efficiency in processing large-scale logic cones, and difficulty in effectively processing loop structures. Summary of the Invention

[0008] Purpose of the invention: The purpose of the present invention is to provide a more efficient and comprehensive optimization method for merging D-type flip-flops to address the shortcomings of the DFF merging optimization method in the prior art when dealing with complex logic structures, large-scale logic cones and loop structures.

[0009] Technical solution: The optimization method for merging D-type flip-flops described in the present invention is applied to the design of a circuit including multiple D-type flip-flops. The method comprises the following steps:

[0010] S1: Select the first D flip-flop and the second D flip-flop of the same type in the circuit design as a pair to be compared;

[0011] S2: Determine whether the clock signals and the preset control signals of the first D flip-flop and the second D flip-flop are of the same source. If they are, proceed to S3; otherwise, determine that they are not equivalent.

[0012] S3: Determine whether the data signals of the first D flip-flop and the second D flip-flop have the same source, or both come from the output of their respective D flip-flops. If so, determine that they are equivalent. Otherwise, proceed to S4.

[0013] S4: iteratively performing a structured comparison on the logic cones driving the data signals of the first D flip-flop and the second D flip-flop, by comparing the types and numbers of source instances and sources of their input signals layer by layer, until determining whether they are equivalent or not;

[0014] S5: If it is determined to be equivalent, use the output of the first D flip-flop to connect the receiving instance of the second D flip-flop, and delete the second D flip-flop.

[0015] To further improve the above technical solution, the preset control signal in S2 includes a set signal, a reset signal and an enable signal.

[0016] Furthermore, the iterative structural comparison of the logic cones in step S4 includes:

[0017] S401: Traverse the logic cones of the data signals of the first D flip-flop and the second D flip-flop forward according to the hierarchical breadth, obtain source instances that directly drive the data signals, and store them in the first container and the second container respectively;

[0018] S402: Compare the number and type of source instances in the first container and the second container. If they are inconsistent, determine that they are not equivalent. Otherwise, proceed to S403.

[0019] S403: Traverse each pair of source instances at corresponding positions of the first container and the second container, and determine whether the input signals corresponding to the source instances have the same source or are derived from the outputs of their respective D flip-flops. If they have different sources and are not derived from the outputs of their respective D flip-flops, store the source instances corresponding to the input signals in the first temporary container and the second temporary container, respectively.

[0020] S404: After the traversal is completed, if the first temporary container and the second temporary container are both empty, then the process is determined to be equivalent, otherwise, the process proceeds to S405;

[0021] S405: Use the source instances in the first temporary container and the second temporary container to replace the contents in the first container and the second container respectively, empty the first temporary container and the second temporary container, and repeat steps S402 to S404 until it is determined to be equivalent or not equivalent.

[0022] Furthermore, the forward traversal by hierarchical breadth in step S401 includes: accessing source instances in the logic cone one by one by level until the top of the cone is reached or the traversal depth reaches a preset threshold, wherein the logic cone includes a top and a bottom, wherein the top of the cone is a register, a top-level output, or a black box input, and the bottom of the cone is a combinational logic circuit.

[0023] Furthermore, while deleting the second D flip-flop in step S5 , the logic cone that drives the data terminal of the second D flip-flop and is not shared by other logics is also deleted.

[0024] Furthermore, the source instance does not include a sequential device instance, a circuit top-level port instance, or a module instance.

[0025] Furthermore, the method is applicable to a circuit comprising a loop structure consisting of a D-type flip-flop and combinational logic, wherein the loop structure includes a circuit path in which the output of the D-type flip-flop is fed back to its data terminal through the combinational logic.

[0026] Beneficial effects: Compared with the existing technology, the advantages of the present invention are: Stronger complex logic coverage capability: By iteratively comparing the structure of the D input logic cone, the present invention can identify complex DFF merging scenarios with equivalent functions but different direct input sources, overcoming the limitations of traditional homologous optimization.

[0027] Higher operating efficiency: Compared with methods that rely on Boolean equivalence checks, the present invention adopts structured instance comparison and iterative backtracking to avoid complex Boolean operations. It can significantly reduce the running time for large-scale logic cones and improve the optimization efficiency.

[0028] Effectively handle loop structures: By explicitly considering whether the signal comes from the DFF's own output when comparing input signals, and combining iterative tracing mechanisms, the present invention can effectively handle the equivalent DFF merging problem in the feedback loop composed of DFF and combinational logic.

[0029] Comprehensive equivalence checking: From DFF type, control signal homology to structured comparison of D input logic cones, a comprehensive equivalence judgment process is formed.

[0030] Optimize design effects: By more effectively merging equivalent DFFs, the circuit design area can be further reduced, overall power consumption can be lowered, and design quality can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Figure 1 is a schematic diagram of a DFF (D-type flip-flop), showing its typical input and output signals.

[0032] Figure 2 Schematic diagram of DFF homology merging.

[0033] Figure 3 This is a schematic diagram of DFF equivalent merging, where the D input of DFF is connected to different logic cones.

[0034] Figure 4 FIG. 4 is a schematic diagram of a loop structure including a DFF.

[0035] Figure 5 It is a flow chart of an optimization method for merging DFFs of the present invention.

[0036] Figure 6 FIG2 is a schematic diagram of a specific circuit example in which the method of the present invention is applied, showing the iterative comparison process of a D-input logic cone. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the embodiments.

[0038] Example 1: Reference Figure 1 The DFF schematic diagram shown shows its typical input and output signals, including:

[0039] (1) D, ENABLE, SET, RESET, and CLOCK are input signals, and Q and QN are output signals;

[0040] (2) D is the data signal, CLOCK is the clock signal, ENABLE is the enable signal, SET is the set signal, RESET is the reset signal, Q and QN are inverse relations, and are the outputs of DFF;

[0041] (3) D and CLOCK are required input signals, while RESET, SET, and ENABLE are optional input signals.

[0042] like Figure 2As shown in the schematic diagram of homologous merging, the CLK and D signals of DFF1 and DFF2 are of the same source and can be merged. The circuit structure after merging is the Q driving logic circuit 2 of DFF1.

[0043] like Figure 3 As shown in the DFF equivalent schematic diagram, the CLK signals of DFF1 and DFF2 are of the same source, the D-end corresponds to logic cone 1 and logic cone 2, and DFF1 and DFF2 are merged. The Q of the merged circuit structure DFF1 drives logic circuit 2.

[0044] like Figure 4 The DFF loop structure diagram shown in the figure consists of four source instances: DFF, selector (MUX2), AND gate (AND), and OR gate (OR). The output Q of DFF passes through OR, AND, and MUX2 to reach D of DFF.

[0045] Reference Figure 5 As shown, the optimization method for merging D-type flip-flops provided by the present invention is specifically implemented in the following steps:

[0046] Step S1: Obtain all DFFs in the design netlist and classify them according to DFF type.

[0047] Step S2: From the classified DFFs of the same type, select a pair of DFFs, called DFF1 and DFF2, as merging objects.

[0048] Step S3: Determine whether the CLOCK signals of DFF1 and DFF2 have the same source. If the CLOCK signals do not have the same source, DFF1 and DFF2 are not equivalent, and the process terminates.

[0049] Step S4: Determine whether other control signals (such as RESET, SET, and ENABLE) of DFF1 and DFF2 have the same source. If any corresponding control signal does not have the same source, DFF1 and DFF2 are not equivalent, and the process terminates.

[0050] Step S5: Determine whether the data input D1 of DFF1 and the data input D2 of DFF2 are directly derived from the same source, or whether D1 is directly derived from the output of DFF1 and D2 is directly derived from the output of DFF2. If so, DFF1 and DFF2 are considered equivalent and the process proceeds directly to the subsequent circuit update step. If not, the process proceeds to the next step for logic cone comparison.

[0051] Step S6: If the previous control signal check passes and the fast D input check does not directly determine equivalence, the logic cone of data signal D for DFF1 and DFF2 is traversed forward in a hierarchical breadth-first manner based on the topological depth of the source instance. The logic cone includes the top and bottom. The top can be a register, top-level output, or black box input, while the bottom is the input part, mainly combinational logic circuits. Initialize two containers, vector1 and vector2; obtain the source instances of data signal D for DFF1 and DFF2, and store them in containers vector1 and vector2, respectively.

[0052] Step S7: Check whether the number of source instances stored in vector1 and vector2 is equal. If not, it is determined that DFF1 and DFF2 are not equivalent and the process terminates. Otherwise, it enters S8.

[0053] Step S8: If the number is equal, extract the source instances (instance1 and instance2) at the corresponding positions from vector1 and vector2 one by one and compare them to determine whether the types of instance1 and instance2 are consistent. If the types are inconsistent, DFF1 and DFF2 are determined to be unequal, and the process terminates.

[0054] Step S9: If the instance types are consistent, then further compare the corresponding input signals of the two instances. For each input of instance1 and the corresponding input of instance2:

[0055] Determine whether the corresponding input signal of the corresponding instance has the same source or comes from the output of the DFF. If they do not have the same source and are not from the output of the DFF, store the sourceinstance of the input signal in the temporary containers temp_vector1 and temp_vector2. The sourceinstance does not include the timing device, port, or module instance. Otherwise, it is not equivalent and exit; if they have the same source or come from the output of the DFF, do not process it and proceed to the next step.

[0056] The core of logic equivalence checking is static functional equivalence based on combinational logic. The core concept is to prove, through formal methods (such as Boolean algebra and binary decision diagrams), that the outputs of the combinational logic of two designs are identical under the same inputs. Key premises: Input signal changes are assumed to be instantaneous and synchronous, disregarding signal timing characteristics (such as clock period, setup / hold time, and delay). Sequential devices (such as registers, latches, and flip-flops) rely on clock signals and time sequences for their functionality, and their characteristics fundamentally conflict with the premise of logic equivalence checking, so sequential devices are not included. Ports, including input and output ports, are design boundaries, so ports are not included. A module instance is an instantiation of a module, which may contain sequential devices, so module instances are not included.

[0057] Step S10: After comparing all inputs of all instances in vector1 and vector2, check the temporary containers temp_vector1 and temp_vector2. If both temp_vector1 and temp_vector2 are empty, it indicates that all inputs at the current level have matched and there are no differences that require further tracing. In this case, DFF1 and DFF2 are considered equivalent.

[0058] If temp_vector1 or temp_vector2 (or both) are not empty, the contents of temp_vector1 are moved to vector1, the contents of temp_vector2 are moved to vector2, and the temporary container is cleared. Then, steps S7 to S9 are returned to perform the next round of iterative comparison on the instances in the new vector1 and vector2.

[0059] Step S11: If DFF1 and DFF2 are ultimately determined to be equivalent, a circuit update is performed. This typically involves reconnecting the fan-out logic originally connected to DFF2's Q (or QN) output to the corresponding Q (or QN) output of DFF1. DFF2 itself is then deleted, along with any combinatorial logic cones driving DFF2's D input that are not shared by other logic.

[0060] Example 2: The current mainstream method for logical equivalence verification: (1) The method based on binary decision diagram (BDD), the time complexity is , and BDD is extremely sensitive to the order of variables and cannot handle ultra-large-scale designs (such as million-gate circuits); (2) Based on the SAT (Boolean satisfiability) method, the SAT problem is NP-complete, and the theoretical time complexity is , the time complexity of the SAT solver actually used (such as MiniSat, Glucose) is The time complexity of the above two methods is nonlinear. The method provided by the present invention is to traverse the logic cones corresponding to the two DFFs, and the time complexity is linear, and the time complexity is n.

[0061] Compared with existing optimization methods, the present invention can cover complex circuit structures, such as a loop structure consisting of a DFF and multiple combinational logic units, and can comprehensively check equivalent DFFs. After merging the DFFs, it is equivalent to reducing one DFF and the combinational logic cone corresponding to the D end, reducing the number of devices used in the design. Accordingly, the design area will be reduced accordingly. Power consumption and area are positively correlated. After the area is reduced, power consumption will also be reduced accordingly. There is no need for a complex Boolean logic equivalence check algorithm, which reduces the running time and improves efficiency.

[0062] Reference Figure 6 , a specific application example is given according to the method provided in Example 1, and the specific steps are as follows:

[0063] (1) Assume that the CLK, SET, RESET and other signals of DFF1 and DFF2 have the same source.

[0064] (2) The D signal has different sources. Store the source instance of D into the containers vector1 = {ins0} and vector2 = {ins4}.

[0065] (3) The number of instances of vctor1 and vector2 is the same. Take out the corresponding ins0 and ins4 respectively, compare the types of ins0 and ins4 and whether the input signals are of the same source: select the signal S0 / S1 of the same source.

[0066] (4) Both ins0 and ins4 are MUX2 types, with equal quantity and the same type. Data inputs IN0 and IN1 have different sources and do not come from DFF outputs. Their driver instances are ins1 and ins5 (AND gates), and ins2 and ins6 (MUX2), respectively. These are combinational logic. Therefore, temp_vector1 = {ins1, ins2}, and temp_vector2 = {ins5, ins6}.

[0067] Clear containers vector1 and vector2, store the instances in temp_vector1 and temp_vector2 into containers vector1 and vector2, and update vector1 = {ins1, ins2} and vector2 = {ins5, ins6}.

[0068] (5) The number of instances of vctor1 and vector2 is the same. Take out the corresponding ins1, ins5, ins2, and ins6 respectively, and determine the types of ins1, ins5, ins2, and ins6 and whether the input signals are from the same source.

[0069] (6) Compare ins1 and ins5: Both are AND gates, one of which has the same input signal (signal a) and the other has a different input signal (from ins3 and ins7, both OR gates).

[0070] Store ins3 and ins7 into temp_vector1={ins3} and temp_vector2={ins7}; store the instances in temp_vector1 and temp_vector2 into containers vector1 and vector2.

[0071] (7) Compare ins2 and ins6: Both are MUX2 gates, with the same input, and no processing is done.

[0072] (8) The number of instances of vctor1 and vector2 is the same, temp_vector1 and temp_vector2 are not empty, and the corresponding ins3 and ins7 are taken out respectively. At this time, vector1 = {ins3}, vector2 = {ins7}.

[0073] (9) Compare ins3 and ins7: Both are OR gates. One input is from the same source (signal b); the other input comes from the Q output of DFF1 and the Q output of DFF2 (via signal c). This meets the loop matching condition and is not processed.

[0074] (10) At this time, the number of instances of vector1 and vector2 is 0, so DFF1 and DFF2 are determined to be equivalent, and DFF1 and DFF2 are merged.

[0075] Through the above iterative comparison, the present invention can effectively determine the equivalence between DFFs with complex input logic cones and process loop structures.

[0076] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes may be made to it in form and detail without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for optimizing a merged D-type flip-flop, applied to a circuit design including multiple D-type flip-flops, characterized in that: The following steps are involved: S1: Select the first D flip-flop and the second D flip-flop of the same type in the circuit design as a pair to be compared; S2: Determine whether the clock signals and the preset control signals of the first D flip-flop and the second D flip-flop are of the same source. If they are, proceed to S3; otherwise, determine that they are not equivalent. S3: Determine whether the data signals of the first D flip-flop and the second D flip-flop have the same source, or both come from the output of their respective D flip-flops. If so, determine that they are equivalent. Otherwise, proceed to S4. S4: iteratively performing a structured comparison on the logic cones driving the data signals of the first D flip-flop and the second D flip-flop, by comparing the types and numbers of source instances and sources of their input signals layer by layer, until determining whether they are equivalent or not; The iterative structured comparison of the logic cones in step S4 includes: S401: Traverse the logic cones of the data signals of the first D flip-flop and the second D flip-flop forward according to the hierarchical breadth, obtain source instances that directly drive the data signals, and store them in the first container and the second container respectively; S402: Compare the number and type of source instances in the first container and the second container. If they are inconsistent, determine that they are not equivalent. Otherwise, proceed to S403. S403: Traverse each pair of source instances at corresponding positions of the first container and the second container, and determine whether the input signals corresponding to the source instances have the same source or are derived from the outputs of their respective D flip-flops. If they have different sources and are not derived from the outputs of their respective D flip-flops, store the source instances corresponding to the input signals in the first temporary container and the second temporary container, respectively. S404: After the traversal is completed, if the first temporary container and the second temporary container are both empty, then the process is determined to be equivalent, otherwise, the process proceeds to S405; S405: Use the source instances in the first temporary container and the second temporary container to replace the contents in the first container and the second container respectively, empty the first temporary container and the second temporary container, and repeat steps S402 to S404 until it is determined to be equivalent or not equivalent; S5: If it is determined to be equivalent, use the output of the first D flip-flop to connect the receiving instance of the second D flip-flop, and delete the second D flip-flop.

2. The optimization method for merging D-type flip-flops according to claim 1, characterized in that: The preset control signals in S2 include a set signal, a reset signal and an enable signal.

3. The optimization method for merging D-type flip-flops according to claim 1, characterized in that: In step S401, the forward traversal by level breadth includes: accessing source instances in the logic cone one by one by level until the top of the cone is reached or the traversal depth reaches a preset threshold, wherein the logic cone includes a top and a bottom, wherein the top of the cone is a register, a top-level output, or a black box input, and the bottom of the cone is a combinational logic circuit.

4. The optimization method for merging D-type flip-flops according to claim 1, characterized in that: When deleting the second D flip-flop in step S5 , the logic cone that drives the data terminal of the second D flip-flop and is not shared by other logics is also deleted.

5. The optimization method for merging D-type flip-flops according to claim 1, characterized in that: The source instance does not include a sequential device instance, a circuit top-level port instance, or a module instance.

6. The optimization method for merging D-type flip-flops according to claim 1, characterized in that: The method is applicable to a circuit having a loop structure composed of a D-type flip-flop and combinational logic, wherein the loop structure includes a circuit path in which the output of the D-type flip-flop is fed back to its data terminal through the combinational logic.

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