Circuit schematic diagram generation method and system based on action mask and graph neural network

Abstract

The invention discloses a schematic circuit diagram generation method and system based on an action mask and a diagram neural network, and the method comprises the steps: 1, carrying out the preprocessing of a circuit netlist, and obtaining a circuit netlist topological matrix; 2, connecting a preset pin state and the number of the arranged units to obtain features after connection; 3, inputting a preset canvas state, the circuit netlist topological matrix and the connected features into the intelligent agent to obtain a layout and wiring result; and 4, constructing an action mask according to a layout wiring result, obtaining a predicted action by using the action mask, and generating a schematic circuit diagram according to the predicted action. According to the method, the schematic circuit diagram can be automatically generated, diagram information in a circuit netlist is concerned, and selection of invalid actions is avoided through action masks.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit schematic diagram generation, and particularly to a circuit schematic diagram generation method and system based on action masks and graph neural networks. Background Art

[0002] In modern electronic systems, the Printed Circuit Board (PCB) plays a crucial role and serves as an important foundation for the magnificent technological world. In recent years, with the continuous upgrading of people's pursuit of cutting-edge technology products, PCBs have become increasingly sophisticated and complex, and play an important role in more and more key industries. However, the three-dimensional structure of PCBs makes their working principles difficult to view, and it is very difficult to directly solve the above problems for PCB products.

[0003] PCB reverse schematic layout refers to the process of converting a PCB netlist into a circuit schematic diagram. Currently, this process mainly relies on manual layout by using Electronic Design Automation (EDA) tools. First, the designer imports the netlist into the EDA tool, and then, based on the connection relationship between the core chip and the peripheral components, infers the functional modules of the local circuit composition, and then performs manual disassembly, arrangement, and combination. Finally, a visual circuit schematic diagram is formed. During the process, depending on the scale of the PCB, designers often need several days to several months for layout, which consumes a great deal of time and labor costs.

[0004] Limited work has achieved the automatic generation of PCB schematics to a certain extent. They first solved the problem of the lack of objective indicators and gradually placed electronic components and wires on the canvas by training a reinforcement learning agent, initially realizing the automatic generation of PCB schematics. They perceived the global information in circuit generation through a convolutional neural network and a fully connected layer, and generated a PCB schematic that met the conditions according to the component placement order determined by depth-first search. However, this method ignores the graph structure information naturally existing in the circuit netlist, and this part of information is of great significance for the agent to perceive the topological relationship of the circuit netlist, optimize the component placement order in the schematic generation process, and thus improve the wiring quality in generation. In addition, the lack of restrictions on invalid actions leads to a large number of invalid explorations by the agent of this method during the training process, greatly limiting the improvement of training efficiency. Summary of the Invention

[0005] To at least partially solve the problems that existing indices cannot automatically generate a circuit schematic based on a circuit netlist, ignore the graph structure information in the circuit netlist when generating the circuit schematic, and lack restrictions on invalid actions, the present invention provides a circuit schematic generation method and system based on action masks and graph neural networks. The present invention incorporates a Graph Neural Network (GNN) to introduce the topological information of the circuit netlist, and the graph neural network has natural advantages in perceiving topological data. The topological features extracted by the graph neural network of the present invention are used to predict the component placement order during schematic generation to improve the wiring quality, thereby obtaining better overall schematic quality. In addition, the present invention adds action masks to mask invalid actions to improve the exploration efficiency of the reinforcement learning agent and optimize the network performance. The present invention overall realizes the process of automatically generating a circuit schematic based on a circuit netlist.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The first aspect of the present invention proposes a circuit schematic generation method based on action masks and graph neural networks, including:

[0008] Step 1: Preprocess the circuit netlist to obtain a circuit netlist topology matrix, which is convenient for extracting the topological information of the circuit netlist;

[0009] Step 2: Connect the preset pin states and the number of placed units to obtain the connected features, which are convenient for subsequent generation of the circuit schematic;

[0010] Step 3: Input the preset canvas state, the circuit netlist topology matrix, and the connected features into the agent to obtain the layout and routing results, which are convenient for obtaining the action mask;

[0011] Step 4: Construct an action mask based on the layout and routing results, obtain the predicted actions using the action mask, and generate the circuit schematic according to the predicted actions.

[0012] Further, the specific content of Step 1 includes:

[0013] Convert the circuit netlist into a netlist graph, where the connection points in the netlist graph are circuit units;

[0014] Input the netlist graph into two sequentially connected graph neural network units to obtain the circuit netlist topology matrix, which is convenient for extracting the topological information of the circuit netlist.

[0015] Further, the two graph neural network units have the same structure, and the graph neural network unit includes multiple graph convolutional network layers, ReLU activation layers, and dropout layers;

[0016] A plurality of the graph convolutional network layers are connected in sequence to perform graph convolution processing on the netlist graph, facilitating the capture of the physical connection relationships and fine-grained topological features among components in the circuit netlist;

[0017] The ReLU activation layer is used to enhance the output of the last graph convolutional network layer;

[0018] The dropout layer is used to randomly discard part of the output of the ReLU activation layer.

[0019] Further, the agent specifically includes a fully connected layer, a connection layer, a first multi-layer perceptron unit, a second multi-layer perceptron unit, and an execution layer;

[0020] The fully connected layer is used to perform a fully connected process on the flattened circuit netlist topology matrix and the preset canvas state, facilitating the fusion of the flattened circuit netlist topology matrix and the preset canvas state;

[0021] The connection layer is used to connect the output of the fully connected layer and the connected features;

[0022] The first multi-layer perceptron unit is used to process the flattened circuit netlist topology matrix to obtain the placement order of circuit components; wherein, the first multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function, the multi-layer perceptron is used to obtain the placement data of circuit components according to the flattened circuit netlist topology matrix, and the maximum index function is used to find the maximum value in the output of the multi-layer perceptron to obtain the placement order;

[0023] The second multi-layer perceptron unit is used to process the output of the connection layer to obtain an action;

[0024] The execution layer is used to select components according to the placement order and execute the action to obtain a layout and routing result.

[0025] Further, the second multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function;

[0026] The multi-layer perceptron is used to process the output of the connection layer according to the multi-layer perceptron;

[0027] The maximum index function is used to find the maximum value of the feature obtained by element-wise multiplication of the output of the multi-layer perceptron and the connection points to obtain an action, facilitating the generation of a circuit schematic diagram.

[0028] Further, constructing an action mask according to the layout and routing result specifically includes:

[0029] Mapping the layout and routing result to a grid to obtain corresponding coordinates;

[0030] Set the actions corresponding to the coordinates covered by the components in the coordinates to 0, and set the actions corresponding to the coordinates not covered to 1 to obtain an action mask, which is convenient for avoiding invalid action exploration.

[0031] Further, obtaining the predicted action using the action mask and generating a circuit schematic according to the predicted action specifically includes:

[0032] Perform a dot product of the action mask and the action, and then pass it through the maximum index function to obtain the predicted action, which is convenient for avoiding the agent from selecting invalid actions;

[0033] Connect the components according to the predicted action to generate a circuit schematic.

[0034] The second aspect of the present invention proposes a circuit schematic generation system based on an action mask and a graph neural network, including:

[0035] A preprocessing module for preprocessing the circuit netlist to obtain a circuit netlist topology matrix, which is convenient for extracting the topological information of the circuit netlist;

[0036] A connection module for connecting the preset pin states and the number of placed cells to obtain the connected features, which is convenient for subsequent generation of the circuit schematic;

[0037] An extraction module for inputting the preset canvas state, the circuit netlist topology matrix, and the connected features into the agent to obtain the placement and routing results, which is convenient for obtaining the action mask;

[0038] A generation module for constructing an action mask according to the placement and routing results, obtaining the predicted action using the action mask, and generating a circuit schematic according to the predicted action.

[0039] The third aspect of the present invention proposes an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the circuit schematic generation method based on an action mask and a graph neural network as described in the first aspect above.

[0040] The fourth aspect of the present invention proposes a computer-readable storage medium, where the storage medium includes a stored computer program. When the computer program runs, it controls the device where the storage medium is located to execute the circuit schematic generation method based on an action mask and a graph neural network as described in the first aspect above.

[0041] The beneficial effects of the present invention:

[0042] (1) The present invention designs a graph neural network unit. By introducing the topological information of the circuit netlist through the graph convolutional network in the graph neural network unit, it is used to predict the component placement order during schematic generation to improve the wiring quality, thereby obtaining better overall quality of the schematic. In addition, the present invention adds an action mask to mask invalid actions to improve the exploration efficiency of the reinforcement learning agent and optimize the network performance. The present invention can automatically generate circuit schematics, reducing labor costs and improving efficiency.

[0043] (2) The present invention first proposes a method of extracting topological features through a graph neural network (GNN, the graph convolutional network in the graph neural network unit belongs to GNN) to predict the component placement order, changing the sorting method based on depth-first search in previous work to improve the wiring quality, thereby promoting the ability of the agent to obtain the global optimal solution when generating the schematic.

[0044] (3) The present invention optimizes the automatic generation structure of the circuit schematic. After obtaining an action, an invalid action mask is added to make the agent reject exploring invalid actions during the exploration process, optimizing the agent's exploration process and improving the training speed and finality of the agent. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flowchart of the circuit schematic generation method based on action mask and graph neural network provided by an embodiment of the present invention.

[0046] Figure 2 It is a schematic diagram of the circuit schematic generation method based on action mask and graph neural network provided by an embodiment of the present invention.

[0047] Figure 3 It is a schematic diagram of the generation of the action mask provided by an embodiment of the present invention.

[0048] Figure 4 It is a schematic diagram of the circuit schematic generation provided by an embodiment of the present invention.

[0049] Figure 5 It is an architecture diagram of the circuit schematic generation system based on action mask and graph neural network provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] Embodiment 1

[0052] As Figure 1 and Figure 2 shown, a circuit schematic diagram generation method based on an action mask and a graph neural network includes:

[0053] S101: Preprocess the circuit netlist to obtain a circuit netlist topology matrix.

[0054] Specifically, before preprocessing the circuit netlist, it is also necessary to construct a simulation environment Sch-painter for reverse layout and wiring of a printed circuit board (PCB) schematic diagram. The PCB schematic diagram reverse layout and wiring simulation environment refers to a virtual environment that interacts with a reinforcement learning agent and simulates the layout and wiring process. This environment, based on the circuit netlist information, receives actions as the layout progresses, places components at the corresponding canvas positions and completes the wiring, and then returns the aesthetic reward obtained by executing the action and the new canvas state after executing the action. The present invention proposes and writes a schematic diagram generation environment for reinforcement learning, which is Sch-painter, and can gradually draw a reverse PCB schematic diagram on an empty canvas.

[0055] Convert the circuit netlist into a netlist graph, where the connection points in the netlist graph are circuit units. Input the netlist graph into two sequentially connected graph neural network units to obtain a circuit netlist topology matrix.

[0056] The two graph neural network units have the same structure. The graph neural network unit includes multiple graph convolutional network layers, a ReLU activation layer, and a dropout layer. The multiple graph convolutional network layers are sequentially connected to perform graph convolution processing on the netlist graph. The ReLU activation layer is used to enhance the output of the last graph convolutional network layer. The dropout layer is used to randomly discard part of the output of the ReLU activation layer.

[0057] S102: Connect the preset pin states and the number of placed units to obtain the connected features.

[0058] S103: Input the preset canvas state, the circuit netlist topology matrix, and the connected features into the agent to obtain the layout and wiring result.

[0059] Specifically, the agent specifically includes a fully connected layer, a connection layer, a first multi-layer perceptron unit, a second multi-layer perceptron unit, and an execution layer.

[0060] The fully connected layer is used to perform a fully connected process on the flattened circuit netlist topology matrix and the preset canvas state. The connection layer is used to connect the output of the fully connected layer and the connected features.

[0061] The first multi-layer perceptron unit is used to process the flattened circuit netlist topology matrix to obtain the placement order of circuit components. Among them, the first multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function. The multi-layer perceptron is used to obtain the placement data of circuit components according to the flattened circuit netlist topology matrix, and the maximum index function is used to find the maximum value in the output of the multi-layer perceptron to obtain the placement order;

[0062] The second multi-layer perceptron unit is used to process the output of the connection layer to obtain an action. The second multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function. The multi-layer perceptron is used to process the output of the connection layer according to the multi-layer perceptron. The maximum index function is used to find the maximum value of the feature obtained by element-wise multiplication of the output of the multi-layer perceptron and the connection points to obtain the action.

[0063] The execution layer is used to select components according to the placement order and execute actions to obtain the layout and routing result.

[0064] The present invention uses a graph neural network to capture the physical connection relationship and fine-grained topological features between components in the circuit netlist. Through this improvement, the present invention uses the topological output of the GNN to predict the placement order to improve the decision-making ability of the reinforcement learning agent for component placement, so as to explore more possibilities in the routing process and avoid local optimal solutions caused by fixed orders. In addition, the present invention also uses the topological output of the GNN as the input for agent action prediction, combines it with the placement position features and progress features, predicts the probability distribution of actions, increases the information dimension of the agent, and improves the quality of action prediction.

[0065] S104: Construct an action mask according to the layout and routing result, obtain the predicted action using the action mask, and generate a circuit schematic diagram according to the predicted action.

[0066] Specifically, when generating a circuit schematic diagram, components of different sizes occupy different spaces on the canvas, which may cause them to cover multiple placement points, and each placement point only allows one component to exist, otherwise it will cause overlap and make the generated schematic diagram difficult to view. The action mask is used to constrain the agent from placing multiple times at the same placement point to avoid invalid action exploration.

[0067] Specifically, as Figure 3 shown, map the layout and routing result to the grid to obtain the corresponding coordinates. Set the actions corresponding to the coordinates covered by the components in the coordinates to 0, and set the actions corresponding to the coordinates not covered to 1 to obtain the action mask to avoid the agent from selecting invalid actions. After multiplying the action mask and the action pointwise and passing through the maximum index function, the predicted action is obtained. As Figure 4As shown, components are connected according to the predicted actions to generate a circuit schematic diagram. First, place the components, and then perform wiring (actions). Repeat the process of placing components and wiring until the circuit schematic diagram is finally generated.

[0068] In the present invention, the circuit netlist is preprocessed by a graph neural network unit to obtain a circuit netlist topology matrix, which is convenient for extracting the topology information of the circuit netlist. Then, the preset canvas state, the circuit netlist topology matrix, and the connected features are input into the agent to obtain the placement and routing results. An action mask is obtained based on the placement and routing results, and the predicted actions are obtained based on the action mask, thereby completing the generation of the circuit schematic diagram. The present invention can automatically generate a circuit schematic diagram, pays attention to the graph information in the circuit netlist, and avoids the selection of invalid actions through the action mask.

[0069] Embodiment 2

[0070] Based on the above embodiment, the present invention proposes a training process for the agent, which specifically includes:

[0071] Train a reinforcement learning agent through Sch-painter with maximizing AEM as the objective function. Specifically, the training starts from an empty canvas. The reinforcement learning agent obtains the current canvas state, calculates the best decision action through a deep neural network, the action is perceived through a simulated layout environment, and placement and wiring are performed. This process is repeated. After all the components in the netlist are placed, the reinforcement learning agent maximizes AEM as the goal and optimizes the policy network based on the gradient to learn the optimal layout. The objective function is expressed by the following formula:

[0072]

[0073] Among them, AEM is the aesthetic evaluation index, R Li is the comprehensive score, D WBi and D NCi are the discount factors determined by the number of wiring bends and the number of network crossings respectively, m is the number of wirings, R bi is the reference score, which is affected by the component alignment method, α is the robustness factor of a single wiring, and P i is the penalty score for restricting the length of a single wiring within a specified range.

[0074] After multiple rounds of layout and learning, the reinforcement learning agent is trained. The trained agent can generate a high-quality PCB reverse schematic diagram with high efficiency.

[0075] Embodiment 3

[0076] Based on the above embodiment, as Figure 5 shown, the present invention proposes a circuit schematic diagram generation system based on an action mask and a graph neural network, including:

[0077] A preprocessing module, configured to preprocess a circuit netlist to obtain a circuit netlist topology matrix.

[0078] A connection module, configured to connect a preset pin status and the number of placed cells to obtain a connected feature.

[0079] An extraction module, configured to input a preset canvas status, a circuit netlist topology matrix, and the connected feature into an agent to obtain a placement and routing result.

[0080] A generation module, configured to construct an action mask according to the placement and routing result, obtain a predicted action by using the action mask, and generate a circuit schematic diagram according to the predicted action.

[0081] It should be noted that the circuit schematic diagram generation system based on an action mask and a graph neural network provided in the embodiments of the present invention is to implement the above-mentioned circuit schematic diagram generation method based on an action mask and a graph neural network. For specific functions, reference can be made to the above-mentioned method embodiments, which will not be elaborated here.

[0082] Embodiment 4

[0083] Based on the above embodiments, the present invention provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the method for generating a circuit schematic diagram based on an action mask and a graph neural network as described in the above embodiments is implemented.

[0084] The present invention provides a computer-readable storage medium, where the storage medium includes a stored computer program. When the computer program runs, the device where the storage medium is located is controlled to execute the method for generating a circuit schematic diagram based on an action mask and a graph neural network as described in the above embodiments.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a circuit schematic diagram based on action masks and graph neural networks, characterized in that Including: Step 1: Preprocess the circuit netlist to obtain a circuit netlist topology matrix; Step 2: Connect the preset pin states and the number of placed cells to obtain the connected features; Step 3: Input the preset canvas state, the circuit netlist topology matrix, and the connected features into the agent to obtain the placement and routing result; Step 4: Construct an action mask based on the placement and routing result, use the action mask to obtain the predicted action, and generate a circuit schematic according to the predicted action.

2. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 1, wherein The specific content of Step 1 includes: Convert the circuit netlist into a netlist graph, where the connection points in the netlist graph are circuit units; Input the netlist graph into two sequentially connected graph neural network units to obtain a circuit netlist topology matrix.

3. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 2, wherein The two graph neural network units have the same structure. The graph neural network unit includes multiple graph convolutional network layers, ReLU activation layers, and dropout layers; The multiple graph convolutional network layers are sequentially connected to perform graph convolution processing on the netlist graph; The ReLU activation layer is used to enhance the output of the last graph convolutional network layer; The dropout layer is used to randomly discard part of the output of the ReLU activation layer.

4. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 1, characterized in that The agent specifically includes a fully connected layer, a connection layer, a first multi-layer perceptron unit, a second multi-layer perceptron unit, and an execution layer; The fully connected layer is used to perform a fully connected process on the flattened circuit netlist topology matrix and the preset canvas state; The connection layer is used to connect the output of the fully connected layer and the connected features; The first multi-layer perceptron unit is used to process the flattened circuit netlist topology matrix to obtain the placement order of circuit components; among them, the first multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function. The multi-layer perceptron is used to obtain the placement data of circuit components according to the flattened circuit netlist topology matrix, and the maximum index function is used to find the maximum value in the output of the multi-layer perceptron to obtain the placement order; The second multi-layer perceptron unit is used to process the output of the connection layer to obtain an action; The execution layer is used to select components according to the placement order and execute actions to obtain the placement and routing result.

5. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 2 or 4, characterized in that, The second multi-layer perceptron unit includes a multi-layer perceptron and a maximum index function; The multi-layer perceptron is used to process the output of the connection layer according to the multi-layer perceptron; The maximum index function is used to find the maximum value of the feature obtained by element-wise multiplication of the output of the multi-layer perceptron and the connection points to obtain an action.

6. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 1, wherein The construction of the action mask according to the placement and routing result specifically includes: Map the placement and routing result to the grid to obtain the corresponding coordinates; Set the actions corresponding to the coordinates covered by components in the coordinates to 0, and set the actions corresponding to the coordinates not covered to 1 to obtain the action mask.

7. The method for generating a circuit schematic diagram based on an action mask and a graph neural network according to claim 1, wherein The use of the action mask to obtain the predicted action and generate a circuit schematic according to the predicted action specifically includes: Perform a dot product of the action mask and the action and then pass it through the maximum index function to obtain the predicted action; Connect the components according to the predicted action to generate a circuit schematic.

8. A circuit schematic generation system based on action masks and graph neural networks, characterized in that, Including: A preprocessing module for preprocessing the circuit netlist to obtain a circuit netlist topology matrix; A connection module for connecting the preset pin states and the number of placed cells to obtain the connected features; An extraction module, configured to input a preset canvas state, a circuit netlist topology matrix, and the connected features into an agent to obtain a placement and routing result; A generation module, configured to construct an action mask according to the placement and routing result, obtain a predicted action by using the action mask, and generate a circuit schematic diagram according to the predicted action.

9. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the circuit schematic diagram generation method based on an action mask and a graph neural network according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium includes a stored computer program, wherein when the computer program runs, it controls the device where the storage medium is located to execute the circuit schematic diagram generation method based on an action mask and a graph neural network according to any one of claims 1 to 7.

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