Display driving circuit and method, chip and display equipment

Abstract

The invention provides a display driving circuit and method, a chip and display equipment, which can be applied to the technical field of display. The display driving circuit comprises: an analysis sub-circuit configured to analyze received image information to obtain a frame trigger signal; a control sub-circuit configured to generate a write control signal and a read control signal in response to the frame trigger signal; the time sequence conversion sub-circuit is configured to analyze the received image information under the control of the write control signal to obtain image data and write the image data into an image register; and performing time sequence conversion on the read control signal to obtain a target read control signal, so that the display device reads and displays the image data from the image register under the control of the target read control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a display driving circuit, method, chip, and display device. Background Art

[0002] In some application scenarios, there is a need to replace the type of display screen. Therefore, in order to enable the replaced display screen to display image data normally, it is urgently necessary to re-develop a driving circuit suitable for the replaced display screen. Summary of the Invention

[0003] In view of this, the present disclosure provides a display driving circuit, method, chip, and display device.

[0004] According to one aspect of the present disclosure, there is provided a display driving circuit, including: a parsing sub-circuit configured to parse the received image information to obtain a frame trigger signal; a control sub-circuit configured to generate a write control signal and a read control signal in response to the frame trigger signal; a timing conversion sub-circuit configured to parse the received image information under the control of the write control signal to obtain image data, and write the image data into an image register; and perform timing conversion on the read control signal under the control of the read control signal to obtain a target read control signal, so that a display device reads and displays the image data from the image register under the control of the target read control signal.

[0005] For example, the control sub-circuit generating the write control signal and the read control signal in response to the frame trigger signal includes: comparing the number of transmitted frames with a preset number of frames in response to the frame trigger signal, and generating the write control signal when the number of transmitted frames is not equal to the preset number of frames, where the number of transmitted frames is obtained by counting a predetermined frame trigger signal before the frame trigger signal.

[0006] For example, the control sub-circuit is further configured to generate a first trigger signal when the number of transmitted frames is not equal to the preset number of frames; generate a second trigger signal when the number of transmitted frames is equal to the preset number of frames; the circuit further includes: a first counter configured to count the number of transmitted frames to obtain an updated number of transmitted frames under the trigger of the first trigger signal; and perform reset under the trigger of the second trigger signal.

[0007] For example, the above control sub - circuit generates a write control signal and a read control signal in response to the above frame trigger signal, including: comparing the number of written rows with a first preset number of rows in response to the above frame trigger signal, and generating the above read control signal when the number of written rows is equal to the first preset number of rows, where the number of written rows is obtained by counting the number of rows written by the above timing conversion sub - circuit to the above image register.

[0008] For example, the above control sub - circuit is further configured to: generate a third trigger signal when the number of written rows is not equal to the first preset number of rows; the circuit further includes: a second counter configured to count the number of written rows under the trigger of the third trigger signal to obtain an updated number of written rows.

[0009] For example, the above parsing sub - circuit is further configured to: parse the above image information to obtain a frame rate switching signal; determine a received frame rate according to the above frame rate switching signal; determine the above preset number of frames according to the above received frame rate and a preset frame rate conversion relationship, where the above preset frame rate conversion relationship represents the mapping relationship between the above received frame rate and the above preset number of frames, and the above preset number of frames is configured according to the above received frame rate and the display frame rate of the above display device.

[0010] For example, the above parsing sub - circuit is further configured to: parse the above image information to obtain a frame rate switching signal and a transmission mode signal; determine a received frame rate according to the above frame rate switching signal; when it is determined according to the above transmission mode signal that the image transmission mode is the command mode, determine the above first preset number of rows according to the above received frame rate and a first preset parameter conversion relationship, where the above first preset parameter conversion relationship represents the mapping relationship between the above received frame rate and the above first preset number of rows, and the above first preset number of rows is configured according to the above received frame rate and the display frame rate of the above display device.

[0011] For example, the above parsing sub - circuit is further configured to: parse the above image information to obtain a frame start signal, a transmission mode signal, a data valid signal, and a line synchronization signal; when it is determined according to the above transmission mode signal that the image transmission mode is the video mode, determine the number of input rows between the above frame start signal and the above data valid signal; determine the time difference between two adjacent line synchronization signals; determine the above first preset number of rows according to the above number of input rows, the above time difference, the time for the above display device to display one line of data, and the total number of display lines of the above display device.

[0012] For example, the above parsing sub - circuit is further configured to: parse the above image information to obtain a frame rate switching signal; determine a reception frame rate according to the above frame rate switching signal; determine a third preset number of rows according to the above reception frame rate and a second preset parameter conversion relationship, where the above second preset parameter conversion relationship represents a mapping relationship between the above reception frame rate and the above third preset number of rows; the above control sub - circuit is further configured to: generate a fourth trigger signal when the above number of written rows is equal to the above first preset number of rows; determine the display state of the above display device according to the number of display rows, a second preset number of rows, and the above third preset number of rows; the above second counter is further configured to: under the trigger of the above fourth trigger signal, count the above number of display rows to obtain an updated number of display rows.

[0013] For example, the above control sub - circuit determines the display state of the above display device according to the number of display rows, a second preset number of rows, and the above third preset number of rows, including: when the above number of display rows is equal to the above second preset number of rows, determining that the above display device has completed the display of one - frame image data and generating a fifth trigger signal; when the number of display waiting rows is not equal to the above third preset number of rows and the next frame trigger signal is received, returning the operation of generating a write control signal and a read control signal in response to the above frame trigger signal; the above second counter is further configured to: under the trigger of the above fifth trigger signal, count the above number of display waiting rows to obtain an updated number of display waiting rows.

[0014] For example, the above circuit further includes the above image register, which is configured to store the above image data.

[0015] According to another aspect of the present disclosure, there is provided a display driving method applied to the above - mentioned display driving circuit, including: parsing the received image information to obtain a frame trigger signal; generating a write control signal in response to the above frame trigger signal; under the control of the above write control signal, parsing the received above image information to obtain image data and writing the above image data into an image register; generating a read control signal in response to the above frame trigger signal; under the control of the above read control signal, performing timing conversion on the above read control signal to obtain a target read control signal, so that the display device reads and displays the above image data from the above image register under the control of the above target read control signal.

[0016] According to another aspect of the present disclosure, there is provided a chip including the above - mentioned display driving circuit.

[0017] According to another aspect of the present disclosure, there is provided a display device, including: a display device; and the above - mentioned display driving circuit.

[0018] According to the display driving circuit provided by the embodiments of the present disclosure, after parsing the received image information by using the parsing sub-circuit to obtain a frame trigger signal, the generation frequency of the write control signal is controlled based on the frame trigger signal by using the control sub-circuit to generate a write control signal in response to the frame trigger signal. Furthermore, when the timing conversion sub-circuit parses the received image information under the control of the write control signal to obtain image data and writes the image data into the image register, the frame rate of storing the image data by the timing conversion sub-circuit can be further controlled according to the generation frequency of the write control signal so that the frame rate is adapted to the display device. By using the control sub-circuit to generate a read control signal in response to the frame trigger signal, the timing conversion sub-circuit can generate a target read control signal adapted to the display device based on the read control signal under the control of the read control signal. Furthermore, when the display device reads and displays the image data from the image register under the control of the target read control signal, a frame of image data can be normally displayed. Description of the Drawings

[0019] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0020] Figure 1 Schematically shows a schematic structural diagram of a display driving circuit according to an embodiment of the present disclosure;

[0021] Figure 2A Schematically shows a schematic diagram of the relationship between the sending frame rate and the display frame rate according to an embodiment of the present disclosure;

[0022] Figure 2B Schematically shows a schematic diagram of the relationship between the sending frame rate and the display frame rate according to another embodiment of the present disclosure;

[0023] Figure 2C Schematically shows a schematic diagram of the relationship between the sending frame rate and the display frame rate according to another embodiment of the present disclosure;

[0024] Figure 3 Schematically shows a schematic structural diagram of a display driving circuit according to another embodiment of the present disclosure;

[0025] Figure 4A Schematically shows a schematic diagram of a display device in different display states according to an embodiment of the present disclosure;

[0026] Figure 4B Schematically shows a flowchart of operations performed by the control sub-circuit before and at the start of display of the display device according to an embodiment of the present disclosure;

[0027] Figure 4CSchematically shows a flowchart of a control sub - circuit for determining the display state of a display device according to an embodiment of the present disclosure;

[0028] Figure 5 Schematically shows a schematic diagram of a timing conversion sub - circuit for reading and writing an image register according to an embodiment of the present disclosure;

[0029] Figure 6 Schematically shows a structural schematic diagram of a display driving circuit according to another embodiment of the present disclosure;

[0030] Figure 7 Schematically shows a flowchart of a display driving method according to an embodiment of the present disclosure;

[0031] Figure 8 Schematically shows a structural schematic diagram of a chip according to an embodiment of the present disclosure; and

[0032] Figure 9 Schematically shows a structural schematic diagram of a display device according to an embodiment of the present disclosure. Detailed implementation manners

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0034] It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as any limitation to the present disclosure, but merely examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be of the ordinary meaning understood by those skilled in the art. The "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components.

[0036] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, these two components may be connected or coupled by wired or wireless means.

[0037] In some application scenarios, there is a need to replace an OLED (Organic Light-Emitting Diode) based display screen with an LCD (Liquid Crystal Display) based display screen. For example, after a problem occurs with the OLED based display screen, the OLED display screen can be replaced with an LCD based display screen. Or, the image data corresponding to the OLED based display screen is sent from the sending end of the OLED based display screen to the receiving end of the LCD based display screen, resulting in the replacement of the type of the display screen at the receiving end.

[0038] When the type of the display screen is replaced, various signals sent to the replaced display screen are no longer applicable to control the replaced display screen, causing the replaced display screen, such as an LCD based display screen, to display abnormally. Therefore, in order to enable the replaced LCD based display screen to display image data normally, it is urgent to re-develop a driving circuit suitable for the LCD based display screen.

[0039] Figure 1 A schematic structural diagram of a display driving circuit according to an embodiment of the present disclosure is schematically shown.

[0040] As Figure 1 shown, the display driving circuit 100 may include a parsing sub-circuit 110, a control sub-circuit 120, and a timing conversion sub-circuit 130.

[0041] The parsing sub-circuit 110 may be configured to parse the received image information to obtain a frame trigger signal.

[0042] For example, the parsing sub-circuit 110 may parse the received image information to obtain a frame start signal, and generate a frame trigger signal according to the frame start signal.

[0043] For example, in the case where the image transmission mode is the video mode, the vertical synchronization signal sent by the sending end may be determined as the frame start signal. After detecting the vertical synchronization signal, the parsing sub-circuit 110 generates a frame trigger signal.

[0044] For example, in the case where the image transmission mode is the command mode, the frame enable signal sent by the control sub-circuit 120 to the sending end may be determined as the frame start signal. After detecting the frame enable signal, the parsing sub-circuit 110 generates a frame trigger signal.

[0045] The control sub-circuit 120 may be configured to generate a write control signal and a read control signal in response to the frame trigger signal.

[0046] The timing conversion sub-circuit 130 can be configured to parse the received image information under the control of the write control signal, obtain image data, and write the image data into the image register 101. Under the control of the read control signal, perform timing conversion on the read control signal to obtain a target read control signal, so that the display device 102 reads and displays the image data from the image register 101 under the control of the target read control signal.

[0047] For example, the control sub-circuit 120 can respond to the frame trigger signal and generate a write control signal only for a fixed number of frames of image data. Furthermore, when the timing conversion sub-circuit 130 parses the received image information under the control of the write control signal, obtains image data, and writes the image data into the image register 101, the number of frames stored in the image register 101 by the timing conversion sub-circuit 130 is reduced, and the frame rate at which the timing conversion sub-circuit 130 receives image data is decreased, so that the frame rate adapts to the display frame rate of the display device 102.

[0048] For example, the control sub-circuit 120 can respond to the frame trigger signal and generate a read control signal according to the number of written rows written into the image register by the timing conversion sub-circuit 130 and the first preset number of rows, so that the timing conversion sub-circuit 130 can generate a target read control signal suitable for normal display of the display device 102 under the control of the read control signal based on the read control signal.

[0049] For example, the display device 102 can include a display panel and an original driving circuit for driving the display panel. The read control signal can be a start signal for controlling the display device 102 to start reading the image data in the image register 101. The target read control signal is a control signal for driving the original driving circuit in the display device 102. The original driving circuit can drive the display panel in the display device 102 to normally read and display the image data from the image register 101 under the control of the target read control signal. Among them, the original driving circuit and the display driving circuit 100 in the display device 102 can be integrated into one circuit to drive the display panel in the display device 102. The original driving circuit can be a source-level driving circuit.

[0050] For example, the timing conversion sub-circuit 130 can also start receiving image information under the control of the write control signal.

[0051] According to an embodiment of the present disclosure, the image signal included in the image information is suitable for controlling a display screen based on an OLED to perform normal display. The display device 102 may include a display screen based on an LCD and an original driving circuit for driving the display screen based on the LCD. When directly controlling the original driving circuit according to the image signal included in the image information and then using the original driving circuit to drive the display screen based on the LCD for display, the display screen based on the LCD displays abnormally. Therefore, according to the display driving circuit 100 provided by the embodiment of the present disclosure, after processing the image information, a target read control signal is generated, so that the original driving circuit can, under the control of the target read control signal, drive the display panel in the display device 102 to normally read and display image data from the image register 101. Among them, the image signal may include: a frame start signal, a frame rate switching signal, a transmission mode signal, a data valid signal, a line synchronization signal, etc.

[0052] According to the display driving circuit provided by the embodiment of the present disclosure, after using the parsing sub-circuit to parse the received image information to obtain a frame trigger signal, by using the control sub-circuit to generate a write control signal in response to the frame trigger signal, the generation frequency of the write control signal is controlled based on the frame trigger signal. Furthermore, when the timing conversion sub-circuit parses the received image information to obtain image data and writes the image data into the image register under the control of the write control signal, the frame rate of storing the image data by the timing conversion sub-circuit can be further controlled according to the generation frequency of the write control signal, so that the frame rate is adapted to the display device. By using the control sub-circuit to generate a read control signal in response to the frame trigger signal, the timing conversion sub-circuit can, under the control of the read control signal, generate a target read control signal adapted to the display device based on the read control signal. Furthermore, when the display device reads and displays image data from the image register under the control of the target read control signal, each frame of image data can be normally displayed.

[0053] The control sub-circuit 120 generating a write control signal and a read control signal in response to the frame trigger signal may include the following operations: comparing the number of transmitted frames with a preset number of frames in response to the frame trigger signal, and generating a write control signal when the number of transmitted frames is not equal to the preset number of frames, where the number of transmitted frames is obtained by counting the previous predetermined frame trigger signals before the current frame trigger signal. The predetermined frame trigger signal is the frame trigger signal output before the parsing sub-circuit 110 outputs the current frame trigger signal. The predetermined frame trigger signal may also be the frame trigger signal received by the control sub-circuit 120 before receiving the current frame trigger signal.

[0054] According to an embodiment of the present disclosure, the preset number of frames can be selected according to the actual situation and is not limited herein. For example, the preset number of frames can be 1, 2, or 3, etc.

[0055] According to an embodiment of the present disclosure, by using the control sub-circuit 120 to compare the number of transmitted frames with a preset number of frames in response to a frame trigger signal, and generating a write control signal when the number of transmitted frames is not equal to the preset number of frames, the control sub-circuit 120 is used to generate a write control signal only for the image data where the number of transmitted frames is not equal to the preset number of frames. Furthermore, the timing conversion sub-circuit can subsequently receive only the image data where the number of transmitted frames is not equal to the preset number of frames under the control of the write control signal, discard the image data where the number of transmitted frames is equal to the preset number of frames, and reduce the frame rate of the image data received by the timing conversion sub-circuit, so that the frame rate adapts to the display frame rate of the display device.

[0056] Figure 2A Schematically shows a schematic diagram of the relationship between the transmission frame rate and the display frame rate according to an embodiment of the present disclosure.

[0057] As Figure 2A shown, when the image data is sent to the display device 102 at a transmission frame rate of 120 fps at the sending end, in the t1 period, the first frame of data can be sent. In the t2 period, the second frame of data can be sent. In the t3 period, the third frame of data can be sent. In the t4 period, the fourth frame of data can be sent. Among them, each period can be a period of 8.333 ms for sending one frame of image data.

[0058] When the display device 102 displays at a display frame rate of 60 fps, in the period from t1 to t2, the first frame of image data can be read from and displayed on the image register 101. In the period from t3 to t4, the third frame of image data can be read from and displayed on the image register 101. Every two periods can be a period of 16.666 ms for the display device 102 to read and display one frame of image data.

[0059] It can be Figure 1 seen that the timing conversion sub-circuit 130 can perform timing conversion on the read control signal to obtain a target read control signal, so that the display device 102 reads and displays the image data from the image register under the control of the target read control signal. Therefore, in Figure 2AIn this case, the display device 102 can, under the control of the target read control signal, read and display one frame of image data from the image register 101 at a display frame rate of 60 fps. The moment when the display device 102 starts to read and display one frame of image data from the image register 101 can be controlled by the target read control signal. For example, the moment when the display device 102 starts to read and display one frame of image data from the image register 101 can be later than the moment when the sending end starts to send one frame of image data. The duration for which the display device 102 reads and displays one frame of image data from the image register 101 can be controlled by the target read control signal. For example, the duration for which the display device 102 reads and displays one frame of image data from the image register 101 can be greater than 8.333 ms.

[0060] It can be seen from Figure 2A that when the sending frame rate is 120 fps, the period is 8.333 ms, the display frame rate is 60 fps, and the period is 16.666 ms, the sending frame rate is twice the display frame rate. Therefore, the image data of the even frames sent by the sending end can be discarded to reduce the frame rate at which the timing conversion sub - circuit 130 receives the image data, so that this frame rate adapts to the display frame rate of the display device 102.

[0061] At this time, the preset number of frames can be set to 1. The control sub - circuit 120 can compare the transmission frame number 0 with the preset number of frames 1 for the first frame of image data, and since the transmission frame number 0 is not equal to the preset number of frames 1, generate a write control signal. The control sub - circuit 120 can compare the transmission frame number 1 with the preset number of frames 1 for the second frame of image data, and since the transmission frame number 1 is equal to the preset number of frames 1, does not generate a write control signal, and at the same time sets the transmission frame number to 0. Among them, the transmission frame number 1 is obtained by counting the frame trigger signal corresponding to the first frame of image data, and the frame trigger signal corresponding to the first frame of image data is a predetermined frame trigger signal.

[0062] The control sub - circuit 120 can compare the transmission frame number 0 with the preset number of frames 1 for the third frame of image data, and since the transmission frame number 0 is not equal to the preset number of frames 1, generate a write control signal. The control sub - circuit 120 can compare the transmission frame number 1 with the preset number of frames 1 for the fourth frame of image data, and since the transmission frame number 1 is equal to the preset number of frames 1, does not generate a write control signal, and at the same time sets the transmission frame number to 0. Among them, the transmission frame number 1 is obtained by counting the frame trigger signal corresponding to the third frame of image data, and the frame trigger signal corresponding to the third frame of image data is a predetermined frame trigger signal.

[0063] And so on, the control sub - circuit 120 is configured to generate a write control signal only when the number of transmitted frames is not equal to the preset number of frames 1. Subsequently, the control timing conversion sub - circuit 130 can, under the action of the write control signal, write the image data into the image register 101 only when the number of transmitted frames is not equal to the preset number of frames 1, thereby realizing discarding the image data of the even - numbered frames sent by the sending end.

[0064] Figure 2B Schematically shows a schematic diagram of the relationship between the sending frame rate and the display frame rate according to another embodiment of the present disclosure.

[0065] As Figure 2B shown, when the sending end sends image data to the display device 102 at a sending frame rate of 90 fps, in the t1 period, the first - frame data can be sent. In the t2 and t3 periods, the second - frame data can be sent. In the t4 period, the third - frame data can be sent. Both the t1 period and the t4 period can be respectively a period of 11.111 ms for sending one - frame image data, and the t2 period and the t3 period are a period of 11.111 ms for sending one - frame image data.

[0066] When the display device 102 displays at a display frame rate of 60 fps, in the period from t1 to t2, the first - frame image data can be read from and displayed on the image register 101. In the period from t3 to t4, the second - frame image data can be read from and displayed on the image register 101. Subsequently, in the period from t5 to t6 ( Figure 2B not shown), the fourth - frame image data can be read from and displayed on the image register 101. Every two periods can be a period of 16.666 ms for the display device 102 to read and display one - frame image data.

[0067] It can be Figure 1 seen that the timing conversion sub - circuit 130 can perform timing conversion on the read control signal to obtain a target read control signal, so that the display device 102 reads and displays the image data from the image register under the control of the target read control signal. Therefore, in Figure 2B , the display device 102 can read and display one - frame image data from the image register 101 at a display frame rate of 60 fps under the control of the target read control signal. The moment when the display device 102 starts to read and display one - frame image data from the image register 101 can be controlled by the target read control signal.

[0068] For example, the moment when the display device 102 starts to read and display a frame of image data from the image register 101 can be later than the moment when the sending end starts to send a frame of image data. The duration for the display device 102 to read and display a frame of image data from the image register 101 can be controlled by a target read control signal. For example, the duration for the display device 102 to read and display a frame of image data from the image register 101 can be greater than 8.333 ms.

[0069] It can be seen that Figure 2B when the sending frame rate is 90 fps, the period is 11.111 ms, the display frame rate is 60 fps, and the period is 16.666 ms, the sending frame rate is 3 / 2 times the display frame rate. Therefore, the image data of the 3n (n = 1, 2, 3,...)th frame sent by the sending end can be discarded to reduce the frame rate at which the timing conversion sub-circuit 130 receives the image data, so that the frame rate adapts to the display frame rate of the display device 102. Here, n is a positive integer.

[0070] At this time, the preset number of frames can be set to 2. The control sub-circuit 120 can compare the transmission frame number 0 with the preset number of frames 2 for the first frame of image data, and since the transmission frame number 0 is not equal to the preset number of frames 2, generate a write control signal. The control sub-circuit 120 can compare the transmission frame number 1 with the preset number of frames 2 for the second frame of image data, and since the transmission frame number 1 is not equal to the preset number of frames 2, generate a write control signal. Here, the transmission frame number 1 is obtained by counting the frame trigger signal corresponding to the first frame of image data, and the frame trigger signal corresponding to the first frame of image data is a predetermined frame trigger signal.

[0071] The control sub-circuit 120 can compare the transmission frame number 2 with the preset number of frames 2 for the third frame of image data, and since the transmission frame number 2 is equal to the preset number of frames 2, not generate a write control signal, and at the same time set the transmission frame number to 0. Here, the transmission frame number 2 is obtained by counting the frame trigger signal corresponding to the first frame of image data and the frame trigger signal corresponding to the second frame of image data, and both the frame trigger signal corresponding to the first frame of image data and the frame trigger signal corresponding to the second frame of image data are predetermined frame trigger signals.

[0072] And so on, the control sub-circuit 120 realizes generating a write control signal only when the transmission frame number is not equal to the preset number of frames 2. Thus, subsequently, the control timing conversion sub-circuit 130 can, under the action of the write control signal, write the image data into the image register 101 only when the transmission frame number is not equal to the preset number of frames 2, realizing discarding the image data of the 3n (n = 1, 2, 3,...)th frame sent by the sending end.

[0073] Figure 2CSchematically shows a schematic diagram of the relationship between the sending frame rate and the display frame rate according to another embodiment of the present disclosure.

[0074] As Figure 2C shown, when the image data is sent to the display device 102 at a sending frame rate of 60 fps at the sending end, in the time period t1, the first frame of data can be sent. In the time period t2, the second frame of data can be sent. Each time period can be a cycle of 16.666 ms for sending one frame of image data.

[0075] When the display device 102 displays at a display frame rate of 60 fps, in the time period t1, the first frame of image data can be read from and displayed by the image register 101. In the time period t2, the second frame of image data can be read from and displayed by the image register 101. Each time period can be a cycle of 16.666 ms for the display device 102 to read and display one frame of image data.

[0076] It can be seen from Figure 1 that the timing conversion sub-circuit 130 can perform timing conversion on the read control signal to obtain a target read control signal, so that the display device 102 reads and displays the image data from the image register under the control of the target read control signal. Therefore, in Figure 2C , the display device 102 can read and display one frame of image data from the image register 101 at a display frame rate of 60 fps under the control of the target read control signal. The moment when the display device 102 starts to read and display one frame of image data from the image register 101 can be controlled by the target read control signal. For example, the moment when the display device 102 starts to read and display one frame of image data from the image register 101 can be later than the moment when the sending end starts to send one frame of image data. The duration for the display device 102 to read and display one frame of image data from the image register 101 can be controlled by the target read control signal. For example, the duration for the display device 102 to read and display one frame of image data from the image register 101 can be greater than 8.333 ms.

[0077] It can be seen from Figure 2C that when the sending frame rate is 60 fps, the period is 16.666 ms, the display frame rate is 60 fps, and the period is 16.666 ms, the sending frame rate is the same as the display frame rate. Therefore, no frame of image data needs to be discarded.

[0078] At this time, the preset number of frames can be set to a decimal number. For example, 0.1. The control sub-circuit 120 can compare the transmission number of frames 0 with the preset number of frames 0.1 for the first frame of image data, and generate a write control signal because the transmission number of frames 0 is not equal to the preset number of frames 0.1. The control sub-circuit 120 can compare the transmission number of frames 1 with the preset number of frames 0.1 for the second frame of image data, and generate a write control signal because the transmission number of frames 1 is not equal to the preset number of frames 0.1. Here, the transmission number of frames 1 is obtained by counting the frame trigger signal corresponding to the first frame of image data, and the frame trigger signal corresponding to the first frame of image data is a predetermined frame trigger signal.

[0079] And so on, the control sub-circuit 120 realizes generating a write control signal when the transmission number of frames is not equal to the preset number of frames 0.1. Since the transmission number of frames is a positive integer and there is no decimal number, there is no case where the transmission number of frames is equal to the preset number of frames 0.1. The control sub-circuit 120 can generate a write control signal for each frame. Thus, subsequently, the control timing conversion sub-circuit 130 can write each frame of image data sent by the sending end into the image register 101 under the action of the write control signal.

[0080] The parsing sub-circuit 110 can also be configured to parse the image information to obtain a frame rate switching signal. According to the frame rate switching signal, determine the received frame rate. According to the received frame rate and the preset frame rate conversion relationship, determine the preset number of frames, where the preset frame rate conversion relationship represents the mapping relationship between the received frame rate and the preset number of frames. The preset number of frames is configured according to the received frame rate and the display frame rate of the display device 102.

[0081] For example, according to the frame rate switching signal, the sending frame rate of the sending end can be determined, and the sending frame rate of the sending end can be determined as the received frame rate of the parsing sub-circuit 110. Here, the received frame rate of the parsing sub-circuit 110 is equal to the sending frame rate of the sending end.

[0082] For example, the preset frame rate conversion relationship can be: when the received frame rate is 120fps and the corresponding display frame rate is 60fps, the preset number of frames is set to 1. When the received frame rate is 90fps and the corresponding display frame rate is 60fps, the preset number of frames is set to 2. When the received frame rate is 60fps and the corresponding display frame rate is 60fps, the preset number of frames is set to 0.1.

[0083] According to an embodiment of the present disclosure, by using an analysis sub-circuit to analyze image information, a frame rate switching signal is obtained. According to the frame rate switching signal, the received frame rate is determined. According to the received frame rate and a preset frame rate conversion relationship, a preset number of frames is determined. The preset number of frames is configured according to the received frame rate and the display frame rate of the display device. By means of the above technical means, the analysis sub-circuit is used to convert the received frame rate into a corresponding preset number of frames according to the difference between the received frame rate and the display frame rate of the display device. Furthermore, when the control sub-circuit executes an operation of generating a write control signal for image data with a transmission number of frames not equal to the preset number of frames, a reference value of the preset number of frames can be provided for it, so that it only generates a write control signal for image data with a fixed number of frames, reducing the frame rate at which the timing conversion sub-circuit receives image data under the control of the write control signal, so as to solve the problem of frame loss when the received frame rate is greater than the display frame rate of the display device. Furthermore, the received frame rate is converted into the display frame rate according to the preset number of frames.

[0084] Figure 3 Schematically shows a structural diagram of a display driving circuit according to another embodiment of the present disclosure.

[0085] As Figure 3 shown, the display driving circuit 300 may include an analysis sub-circuit 310, a control sub-circuit 320, a timing conversion sub-circuit 330, a first counter 340, and a second counter 350. Among them, the timing conversion sub-circuit 330 has a similar structure and function to the timing conversion sub-circuit 130. For simplicity, it will not be described in detail here.

[0086] The control sub-circuit 320 can implement the functions of the control sub-circuit 120. At the same time, the control sub-circuit 320 can also be configured to generate a first trigger signal when the transmission number of frames is not equal to the preset number of frames. When the transmission number of frames is equal to the preset number of frames, a second trigger signal can be generated.

[0087] The first counter 340 can be configured to count the transmission number of frames under the trigger of the first trigger signal to obtain an updated transmission number of frames. And under the trigger of the second trigger signal, perform a reset. Among them, the initial value of the transmission number of frames is 0.

[0088] For example, when the transmission frame rate at the sending end is 120 fps, that is, the receiving frame rate of the parsing sub-circuit 110 is 120 fps, the display frame rate is 60 fps, and the preset number of frames is 1, the control sub-circuit 320 can determine that the transmission frame number 0 is not equal to the preset frame number 1 for the first frame of image data, and generate a write control signal and a first trigger signal. The first counter 340 can count the transmission frame number 0 under the trigger of the first trigger signal to obtain the updated transmission frame number 1. The control sub-circuit 320 can determine that the transmission frame number 1 is equal to the preset frame number 1 for the second frame of image data, and generate a second trigger signal. The first counter 340 can perform a reset under the trigger of the second trigger signal to reset the transmission frame number to 0 again.

[0089] And so on, the control sub-circuit 320 can determine that the transmission frame number 0 is not equal to the preset frame number 1 for each odd-numbered frame of image data, and generate a write control signal and a first trigger signal. The first counter 340 can count the transmission frame number 0 under the trigger of each first trigger signal to obtain the updated transmission frame number 1. The control sub-circuit 320 can determine that the transmission frame number 1 is equal to the preset frame number 1 for each even-numbered frame of image data, and generate a second trigger signal. The first counter 340 can perform a reset under the trigger of each second trigger signal to reset the transmission frame number to 0 again. Thus, subsequently, the control timing conversion sub-circuit 330 can write the image data into the image register 301 only when the transmission frame number is not equal to the preset frame number 1 under the action of the write control signal, so as to discard the image data of the even frames sent by the sending end.

[0090] According to an embodiment of the present disclosure, by using the technical means that the control sub-circuit generates a write control signal and a first trigger signal when the transmission frame number is not equal to the preset frame number, and generates a second trigger signal when the transmission frame number is equal to the preset frame number, and using the first counter to count the transmission frame number under the trigger of the first trigger signal to obtain the updated transmission frame number, and performing a reset under the trigger of the second trigger signal, the control sub-circuit can generate a write control signal only when the transmission frame number is not equal to the preset frame number. Furthermore, the timing conversion sub-circuit can subsequently receive only the image data with the transmission frame number not equal to the preset frame number and discard the image data with the transmission frame number equal to the preset frame number under the control of the write control signal, reducing the frame rate of the image data received by the timing conversion sub-circuit so that the frame rate adapts to the display frame rate of the display device.

[0091] That the control sub-circuit 320 generates a write control signal and a read control signal in response to a frame trigger signal may include: in response to the frame trigger signal, comparing the number of written rows with a first preset number of rows, and generating a read control signal when the number of written rows is equal to the first preset number of rows, where the number of written rows is obtained by counting the number of rows written by the timing conversion sub-circuit into the image register.

[0092] For example, the first preset number of lines can be the VBP (vback-porch) parameter.

[0093] According to an embodiment of the present disclosure, by using the technical means that the control sub-circuit compares the number of written lines with the first preset number of lines in response to the frame trigger signal and generates a read control signal when the number of written lines is equal to the first preset number of lines, it is realized that the control sub-circuit generates a read control signal only when the number of written lines is equal to the first preset number of lines. Furthermore, when the timing conversion sub-circuit subsequently performs timing conversion on the read control signal to obtain the target read control signal, a timing conversion reference can be provided for it, and the target read control signal adapted to the display device can be obtained. Furthermore, when the display device reads and displays image data from the image register under the control of the target read control signal, each frame of image data can be normally displayed.

[0094] The control sub-circuit 320 can also be configured to: generate a third trigger signal when the number of written lines is not equal to the first preset number of lines.

[0095] The second counter 350 can be configured to count the number of written lines under the trigger of the third trigger signal to obtain the updated number of written lines. Wherein, the initial value of the number of written lines can be 0.

[0096] According to an embodiment of the present disclosure, when the number of written lines is not equal to the first preset number of lines, it indicates that the device is in the VBP state. When just entering the VBP state, the count value of the second counter 350 is updated to 0, and at the same time, the second counter 350 starts to count the number of written lines under the trigger of the third trigger signal.

[0097] In the case of being in the VBP state, the timing conversion sub-circuit 330 writes the image data into the image register 301 under the control of the write control signal. The display device 302 does not read the image data from the image register 301. At the same time, the control sub-circuit 320 determines whether to enter the next state according to the number of written lines and the first preset number of lines. The second counter 350 cyclically counts the number of written lines under the trigger of the third trigger signal generated by the control sub-circuit 320 to obtain the updated number of written lines.

[0098] The control sub-circuit 320 can also be configured to: generate a fourth trigger signal when the number of written lines is equal to the first preset number of lines.

[0099] The second counter 350 can also be configured to: count the number of display lines under the trigger of the fourth trigger signal to obtain the updated number of display lines. Wherein, the initial value of the number of display lines can be 0. The second counter 350 can also be configured to: update the number of written lines to 0 under the trigger of the fourth trigger signal.

[0100] The control sub - circuit 320 can also be configured to: determine the display state of the display device according to the number of display lines, the second preset number of lines, and the third preset number of lines.

[0101] For example, the second preset number of lines can be the VACTL (Vertical Active Line) parameter. The third preset number of lines can be the VFP (Vertical Front Porch) parameter.

[0102] According to an embodiment of the present disclosure, when the number of written lines is equal to the first preset number of lines, it represents the start of entering the ACTIVE state. When initially entering the ACTIVE state, the count value of the second counter 350 is updated to 0, and at the same time, the second counter 350 starts to count the number of display lines under the trigger of the fourth trigger signal. When the number of display lines is not equal to the second preset number of lines, it represents the ACTIVE state.

[0103] When in the ACTIVE state, the timing conversion sub - circuit 330 writes the image data into the image register 301 under the control of the write control signal. The display device 302 starts to read the image data from the image register 301 under the control of the target read control signal until a frame of image data is completely displayed. At the same time, the control sub - circuit 320 determines whether the display device 302 has completed the display of a frame of image data according to the number of display lines and the configured second preset number of lines, and further determines whether to enter the next state. The second counter 350 cyclically counts the number of display lines under the trigger of the fourth trigger signal generated by the control sub - circuit 320 to obtain the updated number of display lines.

[0104] The control sub - circuit 320 determining the display state of the display device according to the number of display lines, the second preset number of lines, and the third preset number of lines can include: when the number of display lines is equal to the second preset number of lines, determining that the display device 302 has completed the display of a frame of image data and generating a fifth trigger signal. When the number of display waiting lines is not equal to the third preset number of lines and the next frame trigger signal is received, return to the operation of generating the write control signal and the read control signal in response to the frame trigger signal.

[0105] The second counter 350 is also configured to: count the number of display waiting lines under the trigger of the fifth trigger signal to obtain the updated number of display waiting lines. Wherein, the initial value of the number of display waiting lines can be 0. The second counter 350 can also be configured to: update the number of display lines to 0 under the trigger of the fifth trigger signal.

[0106] According to an embodiment of the present disclosure, when the number of displayed lines is equal to a second preset number of lines, it is indicated that the VFP state is started to enter. When just entering the VFP state, the count value of the second counter 350 is updated to 0, and at the same time, the second counter 350 starts to count the number of displayed waiting lines under the trigger of the fifth trigger signal. When the number of displayed waiting lines is not equal to a third preset number of lines, it is indicated that the device is in the VFP state.

[0107] When in the VFP state, the timing conversion sub-circuit 330 no longer performs the operation of writing image data into the image register 301. The display device 302 does not read image data from the image register 301. At the same time, the control sub-circuit 320 determines whether to return the operation of generating a write control signal and a read control signal in response to the frame trigger signal or return to the default state, that is, the initial state of the control sub-circuit 320, according to the number of displayed waiting lines and the third preset number of lines. The second counter 350 is triggered by the fifth trigger signal generated by the control sub-circuit 320 to cyclically count the number of displayed waiting lines to obtain the updated number of displayed waiting lines.

[0108] The following is based on Figure 4A to further describe the display state of the display device. According to Figure 4B to further describe the operations performed by the control sub-circuit before and at the start of the display of the display device. According to Figure 4C to further describe the operation of the control sub-circuit for determining the display state of the display device.

[0109] Figure 4A Schematically shows a schematic diagram of a display device in different display states according to an embodiment of the present disclosure.

[0110] As Figure 4A shown, when the transmission rate at the sending end is 120 fps, the period is 8.333 ms, the display frame rate of the display device is 60 fps, and the period is 16.666 ms, the display device is in different display states according to different conditions. Among them, the method of the display device in Figure 4A for reading and displaying a frame of image data from the image register is similar to the method of the display device in Figure 2A for reading and displaying a frame of image data from the image register. For the sake of simplicity, it will not be described in detail here.

[0111] As Figure 4AAs shown, during the period when the transmitting end starts to send a frame of image data to the display device and the display device starts to read and display the frame of image data from the image register, the display state of the display device is in the VBP state. When the display state of the display device is in the VBP state, the display device does not read and display image data from the image register. The second counter counts the number of written lines under the trigger of the third trigger signal. The total number of counted lines of the second counter in the VBP state is the first preset number of lines. The control sub-circuit determines whether the number of written lines is equal to the first preset number of lines, and determines that the display state of the display device is in the VBP state when the number of written lines ≠ the first preset number of lines.

[0112] During the period when the display device starts to read and display a frame of image data from the image register until it stops reading the frame of image data, the display state of the display device is in the ACTIVE state. When the display state of the display device is in the ACTIVE state, the display device reads and displays image data from the image register. The count value of the second counter is updated to 0, and at the same time, under the trigger of the fourth trigger signal, it counts the number of displayed lines. The total number of counted lines of the second counter in the ACTIVE state is the second preset number of lines. The control sub-circuit determines whether the number of displayed lines is equal to the second preset number of lines, and determines that the display state of the display device is in the ACTIVE state when the number of displayed lines ≠ the second preset number of lines.

[0113] During the period when the display device finishes reading a frame of image data and waits for the next frame of image data, the display state of the display device is in the VFP state. When the display state of the display device is in the VFP state, the display device does not read and display image data from the image register. The count value of the second counter is updated to 0, and at the same time, under the trigger of the fifth trigger signal, it counts the number of display waiting lines. The total number of counted lines of the second counter in the VFP state is the third preset number of lines. The control sub-circuit determines whether the number of display waiting lines is equal to the third preset number of lines, and determines that the display state of the display device is in the VFP state when the number of display waiting lines ≠ the third preset number of lines.

[0114] Figure 4B Schematically shows a flowchart of operations performed by the control sub-circuit according to an embodiment of the present disclosure before and at the start of display of the display device.

[0115] As Figure 4B shown, the operations performed by the control sub-circuit 320 before and at the start of display of the display device 302 may include operation S410 to operation S450.

[0116] In operation S410, the control sub-circuit 320 receives a frame trigger signal.

[0117] In operation S420, in response to the frame trigger signal, compare the number of written lines with the first preset number of lines.

[0118] In the case where the number of written lines is not equal to the first preset number of lines, confirm that the display state of the display device 302 is in the VBP state. In operation S430, generate a third trigger signal. Further, the second counter 350 can count the number of written lines under the trigger of the third trigger signal to obtain the updated number of written lines.

[0119] In the case where the number of written lines is equal to the first preset number of lines, confirm that the display state of the display device 302 starts to enter the ACTIVE state. In operation S440, generate a read control signal and a fourth trigger signal. Further, the second counter 350 can update the number of written lines to 0 under the trigger of the fourth trigger signal, count the number of display lines, and obtain the updated number of display lines.

[0120] In operation S450, determine the display state of the display device according to the number of display lines, the second preset number of lines, and the third preset number of lines.

[0121] Figure 4C Schematically shows a flowchart of the control sub - circuit determining the display state of the display device according to an embodiment of the present disclosure.

[0122] As Figure 4C shown, Figure 4B in operation S450 as shown, determining the display state of the display device according to the number of display lines, the second preset number of lines, and the third preset number of lines may include sub - operations S451 - S455.

[0123] In sub - operation S451, the control sub - circuit 320 compares the number of display lines with the second preset number of lines.

[0124] In the case where the number of display lines is not equal to the second preset number of lines, confirm that the display state of the display device 302 is in the ACTIVE state, and return to execute sub - operation S451.

[0125] In the case where the number of display lines is equal to the second preset number of lines, confirm that the display device 302 starts to enter the VFP state. In sub - operation S452, determine that the display device has completed the display of one - frame image data and generate a fifth trigger signal. Further, the second counter 350 can update the number of display lines to 0 under the trigger of the fifth trigger signal, count the number of display waiting lines, and obtain the updated number of display waiting lines.

[0126] In sub - operation S453, compare the number of display waiting lines with the third preset number of lines.

[0127] When the number of display waiting lines is not equal to the third preset number of lines, confirm that the display state of the display device 302 is in the VFP state.

[0128] When the number of display waiting lines is not equal to the third preset number of lines and the next frame trigger signal is received, in sub-operation S454, return the operation of generating a write control signal and a read control signal in response to the frame trigger signal. The timing conversion sub-circuit 330 returns the operation of parsing the received image information under the control of the write control signal to obtain image data, writing the image data into the image register 301, performing timing conversion on the read control signal to obtain a target read control signal, so that the display device 302 reads and displays the image data from the image register 301 under the control of the target read control signal. The control sub-circuit 320 also returns to operation S410 at the same time.

[0129] When the number of display waiting lines is equal to the third preset number of lines and the next frame trigger signal is not received, in sub-operation S455, return to the default state.

[0130] According to an embodiment of the present disclosure, when the number of display waiting lines is equal to the third preset number of lines and the next frame trigger signal is not received, the control sub-circuit returns to the default state, so that the control sub-circuit is always in the default state. Furthermore, when the image transmission mode is the video mode, the control sub-circuit can automatically extend the duration corresponding to the first preset number of lines according to the vertical synchronization signal sent by the sending end, and can solve the problem of changing the refresh rate by automatically inserting blank lines corresponding to the first preset number of lines in the video mode.

[0131] The parsing sub-circuit 310 can also be configured to: parse the image information to obtain a frame rate switching signal and a transmission mode signal. Determine the received frame rate according to the frame rate switching signal. When it is determined that the image transmission mode is the command mode according to the transmission mode signal, determine the first preset number of lines according to the received frame rate and the first preset parameter conversion relationship, where the first preset parameter conversion relationship represents the mapping relationship between the received frame rate and the first preset number of lines, and the first preset number of lines is configured according to the received frame rate and the display frame rate of the display device.

[0132] According to an embodiment of the present disclosure, by using an analysis sub-circuit to analyze image information, a frame rate switching signal and a transmission mode signal are obtained. According to the frame rate switching signal, the received frame rate is determined. When it is determined that the image transmission mode is the command mode according to the transmission mode signal, according to the conversion relationship between the received frame rate and the first preset parameter, the technical means of determining the first preset number of rows is used to convert the received frame rate into the corresponding first preset number of rows, and the problem of how to configure the first preset number of rows in the command mode is solved. At the same time, when the control sub-circuit executes the operation of generating a read control signal according to the written number of rows and the first preset number of rows, a reference value of the first preset number of rows can be provided for it to obtain a timing conversion reference adapted to the display device, that is, the read control signal.

[0133] The analysis sub-circuit 310 may further be configured to: analyze the image information to obtain a frame start signal, a transmission mode signal, a data valid signal, and a line synchronization signal. When it is determined that the image transmission mode is the video mode according to the transmission mode signal, determine the number of input rows between the frame start signal and the data valid signal; determine the time difference between two adjacent line synchronization signals; and determine the first preset number of rows according to the number of input rows, the time difference, the time for the display device to display one line of data, and the total number of display rows of the display device. Among them, the number of input rows between the frame start signal and the data valid signal is the VBP parameter corresponding to the sending end. The time difference between two adjacent line synchronization signals is the time for the sending end to send one line of data.

[0134] For example, the operation of determining the first preset number of rows according to the number of input rows, the time difference, the time for the display device to display one line of data, and the total number of display rows of the display device can be implemented according to the following formula (1).

[0135] (Vbp_i+r n )×line_t_i=(Vbp_x+r n )×line_t_o (1)

[0136] Wherein, Vbp_i represents the number of input rows, r n represents the total number of display rows of the display device, line_t_i represents the time difference, Vbp_x represents the first preset number of rows, and line_t_o represents the time for the display device to display one line of data.

[0137] According to an embodiment of the present disclosure, by parsing image information using a parsing sub - circuit, a frame start signal, a transmission mode signal, a data valid signal, and a line - sync signal are obtained. When it is determined that the image transmission mode is a video mode according to the transmission mode signal, the number of input lines between the frame start signal and the data valid signal is determined, the time difference between two adjacent line - sync signals is determined, and according to the number of input lines, the time difference, the time for the display device to display one line of data, and the total number of display lines of the display device, the technical means of determining a first preset number of lines is used to convert the number of input lines, the time difference, the time for the display device to display one line of data, and the total number of display lines of the display device into the corresponding first preset number of lines, solving the problem of how to configure the first preset number of lines in the video mode. At the same time, when the control sub - circuit executes the operation of generating a read control signal according to the number of written lines and the first preset number of lines, a reference value of the first preset number of lines can be provided for it to obtain a timing conversion reference adapted to the display device, that is, the read control signal.

[0138] The parsing sub - circuit 310 can also be configured to: parse the image information to obtain a frame rate switching signal. According to the frame rate switching signal, determine the received frame rate. According to the second preset parameter conversion relationship, determine the third preset number of lines. Wherein, the second preset parameter conversion relationship represents the mapping relationship between the received frame rate and the third preset number of lines.

[0139] For example, the third preset number of lines can also be determined according to the received frame rate, the image transmission mode, and the second preset parameter conversion relationship. At this time, the second preset parameter conversion relationship represents the mapping relationship between the received frame rate and the third preset number of lines in the corresponding image transmission mode.

[0140] According to an embodiment of the present disclosure, in different image transmission modes, the third preset number of lines can be the same or different.

[0141] For example, the second preset number of lines can be equal to the maximum number of image data lines that the display device can display.

[0142] For example, determining the third preset number of lines according to the received frame rate and the second preset parameter conversion relationship can include the following operations: determining the configured first preset number of lines according to the received frame rate and the image transmission mode; determining the third preset number of lines according to the configured first preset number of lines, the total number of display lines of the display device, the time for the display device to display one line of data, and the period for the display device to display one frame of data. Wherein, after adding the configured first preset number of lines, the total number of display lines of the display device, and the third preset number of lines, and then multiplying by the time for the display device to display one line of data, it is equal to the period for the display device to display one frame of data.

[0143] According to an embodiment of the present disclosure, by using an analysis sub-circuit to analyze image information to obtain a frame rate switching signal, determining a received frame rate according to the frame rate switching signal, and determining a second preset number of rows and a third preset number of rows according to the received frame rate and a second preset parameter conversion relationship, the technical means of converting the received frame rate into the corresponding second preset number of rows and third preset number of rows is realized, and the problem of how to configure the second preset number of rows and the third preset number of rows in each image transmission mode is solved. At the same time, when the control sub-circuit executes the operation of determining the display state of the display device according to the display number of rows, the second preset number of rows, and the third preset number of rows, a reference value of the second preset number of rows and a reference value of the third preset number of rows can be provided for it. Based on the reference value of the second preset number of rows and the reference value of the third preset number of rows, it can correctly identify the display state of the display device.

[0144] The timing conversion sub-circuit 330 analyzes the received image information under the control of the write control signal to obtain image data, and writing the image data into the image register 301 may include: synchronously writing the multiple image data received in multiple reception timings into the image register 301.

[0145] For example, the image data may include pixel data. A reception timing may receive a predetermined number of pixel data, and multiple reception timings may receive multiple predetermined numbers of pixel data. The multiple predetermined numbers of pixel data received in the multiple reception timings may be merged and then synchronously written into the image register 301 to realize synchronously writing the multiple image data received in the multiple reception timings into the image register 301.

[0146] According to an embodiment of the present disclosure, by using the timing conversion sub-circuit to synchronously write the multiple image data received in multiple reception timings into the image register, it is realized to expand the bit width of the image data input by the sending end according to the system architecture requirements, reduce the speed of writing the image data into the image register, and increase the duration of writing the image data into the image register. In order to ensure that the display device can display normally, the duration of writing and reading a row of image data from the image register should be equal. Therefore, the subsequent duration for the display device to read and display the image data from the image register is correspondingly increased so that the display device can perform other processing operations within the additionally increased duration.

[0147] Figure 5 Schematically shows a schematic diagram of the timing conversion sub-circuit reading and writing the image register according to an embodiment of the present disclosure.

[0148] As Figure 5As shown in the figure, the timing conversion sub-circuit 330 can first synchronously write multiple pieces of image data received at multiple current reception timings into the image register 301 and store them in the first storage unit 3011 of the image register 301. Then, under the control of the target read control signal, the display device 302 can read and display the image data from the first storage unit 3011 of the image register 301. At the same time, the timing conversion sub-circuit 330 can synchronously write multiple pieces of image data received at multiple subsequent reception timings into the image register 301 and store them in the second storage unit 3012 of the image register 301.

[0149] Next, under the control of the target read control signal, the display device 302 can read and display the image data from the second storage unit 3012 of the image register 301. At the same time, the timing conversion sub-circuit 330 can synchronously write multiple pieces of image data received at multiple subsequent reception timings into the image register 301 and store them in the first storage unit 3011 of the image register 301. Among them, both the first storage unit 3011 and the second storage unit 3012 have a capacity of at least one row.

[0150] And so on. While the display device 302 reads and displays the image data from a storage unit of the image register 301 under the control of the target read control signal, the timing conversion sub-circuit 330 can synchronously write multiple pieces of image data received at multiple subsequent reception timings into the image register 301 and store them in another storage unit of the image register 301.

[0151] From Figure 5 it can be seen that since the method of expanding the bit width is adopted when the timing conversion sub-circuit 330 writes the image data into the image register 301, the process of the timing conversion sub-circuit 330 writing the image data into the image register 301 is a discrete process. However, the process of the display device 302 reading and displaying the image data according to the target read control signal output by the timing conversion sub-circuit 330 from the image register 301 is a continuous process. Therefore, the speed of reading the image register 301 is faster than the speed of writing the image register 301. The time for the display device 302 to read and display the image data from the image register 301 is shorter than the time for the timing conversion sub-circuit 330 to write the image data into the image register 301.

[0152] In order to ensure that the display device 302 can display normally, the time taken to write and read a row of image data to and from the image register 301 should be equal. However, the time taken to read the image register 301 is shorter than the time taken to write to the image register 301. Therefore, in order to ensure that the time taken to write and read a row of image data to and from the image register 301 is equal, it is necessary to ensure that the line blanking duration corresponding to reading the image register 301 is greater than or equal to the line blanking duration corresponding to writing to the image register 301. Thus, the line blanking duration corresponding to reading the image register 301 is automatically increased, so that the display device 302 can perform other processing operations during the additionally increased line blanking duration, which is very helpful for some display devices 302 with a relatively long charge and discharge time.

[0153] Figure 6 Schematically shows a schematic structural diagram of a display driving circuit according to another embodiment of the present disclosure.

[0154] As Figure 6 shown, the display driving circuit 600 may include a parsing sub-circuit 610, a control sub-circuit 620, a timing conversion sub-circuit 630, a first counter 640, a second counter 650, an image register 660, and at least one register. Among them, Figure 6 the parsing sub-circuit 610, the control sub-circuit 620, the timing conversion sub-circuit 630, the first counter 640, and the second counter 650 in Figure 3 respectively have similar structures and functions to the parsing sub-circuit 310, the control sub-circuit 320, the timing conversion sub-circuit 330, the first counter 340, and the second counter 350 in

[0155] For example, the image register 660 may be configured to store image data.

[0156] According to an embodiment of the present disclosure, since the display driving circuit includes an image register, it is possible to store image data according to the image register included in the display driving circuit in the case where the driving circuit for driving the display device does not include an image register. Furthermore, it is possible to control the display device to normally display image data according to the display driving circuit provided by the embodiment of the present disclosure and the driving circuit for driving the display device.

[0157] The at least one register may be configured to store a preset number of frames, a first preset number of rows, a third preset number of rows, and a third preset number of rows. For example, the at least one register may include a first register 671, a second register 672, a third register 673, and a fourth register 674. The first register 671 may store the first preset number of rows. The second register 672 may store the second preset number of rows. The third register 673 may store the third preset number of rows. And the fourth register 674 may store the preset number of frames.

[0158] For example, the first register 671 may be a VBP register, the second register 672 may be an ACTIVE register, and the third register 673 may be a VFP register.

[0159] According to an embodiment of the present disclosure, since the display driving circuit 600 includes at least one register, when the original driving circuit for driving the display panel included in the display device 602 does not include a register, the preset frame number, the first preset row number, the third preset row number, and the third preset row number can be stored according to at least one register included in the display driving circuit 600. Then, according to the display driving circuit 600 provided by the embodiment of the present disclosure and the original driving circuit included in the display device 602, the display panel included in the display device 602 can be controlled to display image data normally. Among them, the display device 602 includes a display panel and an original driving circuit. The original driving circuit can be a source driving circuit.

[0160] Figure 7 The flowchart of the display driving method according to the embodiment of the present disclosure is schematically shown.

[0161] like Figure 7 As shown, the display driving method may include operations S710 to S750. Figure 7 The display driving method in can be applied to the above-mentioned display driving circuit.

[0162] In operation S710, the received image information is parsed to obtain a frame trigger signal.

[0163] In operation S720, a write control signal is generated in response to the frame trigger signal.

[0164] In operation S730, under the control of the write control signal, the received image information is parsed to obtain image data, and the image data is written into the image register.

[0165] In operation S740 , a read control signal is generated in response to the frame trigger signal.

[0166] In operation S750, under the control of the read control signal, the read control signal is time-converted to obtain a target read control signal, so that the display device reads and displays image data from the image register under the control of the target read control signal.

[0167] It should be noted that, unless it is explicitly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present disclosure, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order of multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0168] It should also be noted that the display driving method in the embodiments of the present disclosure corresponds to the display driving circuit part in the embodiments of the present disclosure, which will not be elaborated here.

[0169] Figure 8 Schematically shows a schematic structural diagram of a chip according to an embodiment of the present disclosure.

[0170] As Figure 8 shown, the chip 800 may include a display driving circuit 810.

[0171] For example, the chip 800 may be a source driving chip. The chip 800 may also include a source driving circuit. The source driving circuit may drive the display panel to normally read and display image data from the image register under the control of the target read control signal output by the display driving circuit 810. The display driving circuit 810 may be the display driving circuit 100, the display driving circuit 300, or the display driving circuit 600.

[0172] Figure 9 Schematically shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0173] As Figure 9 shown, the display device 900 may include a display driving circuit 910 and a display device 920.

[0174] For example, the display driving circuit 910 may be the display driving circuit 100, the display driving circuit 300, or the display driving circuit 600. The display device 920 may include a display panel and a primitive driving circuit. The primitive driving circuit may be a source driving circuit.

[0175] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0176] Those skilled in the art will understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0177] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A display driving circuit, comprising: A parsing sub - circuit configured to parse the received image information to obtain a frame trigger signal; A control sub - circuit configured to generate a write control signal and a read control signal in response to the frame trigger signal; A timing conversion sub - circuit configured to Under the control of the write control signal, parse the received image information to obtain image data, and write the image data into an image register; And Under the control of the read control signal, perform timing conversion on the read control signal to obtain a target read control signal, so that the display device reads and displays the image data from the image register under the control of the target read control signal.

2. The circuit according to claim 1, wherein, The control sub - circuit generating a write control signal and a read control signal in response to the frame trigger signal includes: In response to the frame trigger signal, compare the number of transmitted frames with a preset number of frames, and generate the write control signal when the number of transmitted frames is not equal to the preset number of frames, where the number of transmitted frames is obtained by counting a predetermined frame trigger signal before the frame trigger signal.

3. The circuit according to claim 2, wherein, The control sub - circuit is further configured to generate a first trigger signal when the number of transmitted frames is not equal to the preset number of frames; Generate a second trigger signal when the number of transmitted frames is equal to the preset number of frames; The circuit further includes: A first counter configured to count the number of transmitted frames under the trigger of the first trigger signal to obtain an updated number of transmitted frames; And perform reset under the trigger of the second trigger signal.

4. The circuit according to any one of claims 1 to 3, wherein, The control sub - circuit generating a write control signal and a read control signal in response to the frame trigger signal includes: In response to the frame trigger signal, compare the number of written rows with a first preset number of rows, and generate the read control signal when the number of written rows is equal to the first preset number of rows, where the number of written rows is obtained by counting the number of rows written by the timing conversion sub - circuit into the image register.

5. The circuit according to claim 4, wherein, The control sub - circuit is further configured to: generate a third trigger signal when the number of written rows is not equal to the first preset number of rows; The circuit further includes: A second counter configured to count the number of written rows under the trigger of the third trigger signal to obtain an updated number of written rows.

6. The circuit according to claim 2 or 3, wherein, The parsing sub - circuit is further configured to: parse the image information to obtain a frame rate switching signal; Determine the received frame rate according to the frame rate switching signal; Determine the preset number of frames according to the received frame rate and a preset frame rate conversion relationship, where the preset frame rate conversion relationship represents the mapping relationship between the received frame rate and the preset number of frames, and the preset number of frames is configured according to the received frame rate and the display frame rate of the display device.

7. The circuit according to claim 4, wherein The parsing sub - circuit is further configured to: parse the image information to obtain a frame rate switching signal and a transmission mode signal; Determine the received frame rate according to the frame rate switching signal; When it is determined that the image transmission mode is the command mode according to the transmission mode signal, the first preset number of rows is determined according to the received frame rate and the first preset parameter conversion relationship, where the first preset parameter conversion relationship represents the mapping relationship between the received frame rate and the first preset number of rows, and the first preset number of rows is configured according to the received frame rate and the display frame rate of the display device.

8. The circuit according to claim 4, wherein The parsing sub-circuit is further configured to: Parse the image information to obtain a frame start signal, a transmission mode signal, a data valid signal, and a line synchronization signal; When it is determined that the image transmission mode is the video mode according to the transmission mode signal, determine the number of input rows between the frame start signal and the data valid signal; determine the time difference between two adjacent line synchronization signals; and determine the first preset number of rows according to the number of input rows, the time difference, the time for the display device to display one line of data, and the total number of display rows of the display device.

9. The circuit according to claim 5, wherein, The parsing sub-circuit is further configured to: parse the image information to obtain a frame rate switching signal; determine the received frame rate according to the frame rate switching signal; and determine the third preset number of rows according to the received frame rate and the second preset parameter conversion relationship, where the second preset parameter conversion relationship represents the mapping relationship between the received frame rate and the third preset number of rows; The control sub-circuit is further configured to: generate a fourth trigger signal when the number of written rows is equal to the first preset number of rows; and determine the display state of the display device according to the number of display rows, the second preset number of rows, and the third preset number of rows; The second counter is further configured to: count the number of display rows under the trigger of the fourth trigger signal to obtain an updated number of display rows.

10. The circuit according to claim 9, wherein, The control sub-circuit determines the display state of the display device according to the number of display rows, the second preset number of rows, and the third preset number of rows, including: When the number of display rows is equal to the second preset number of rows, it is determined that the display device has completed the display of one frame of image data, and a fifth trigger signal is generated; When the number of display waiting rows is not equal to the third preset number of rows and the next frame trigger signal is received, return to the operation of generating a write control signal and a read control signal in response to the frame trigger signal; The second counter is further configured to: count the number of display waiting rows under the trigger of the fifth trigger signal to obtain an updated number of display waiting rows.

11. The circuit according to any one of claims 1 to 3, wherein, It further includes the image register, which is configured to store the image data.

12. A display driving method applied to the display driving circuit according to any one of claims 1 to 11, including: Parse the received image information to obtain a frame trigger signal; Generate a write control signal in response to the frame trigger signal; Under the control of the write control signal, parse the received image information to obtain image data, and write the image data into the image register; Generate a read control signal in response to the frame trigger signal; Under the control of the read control signal, perform timing conversion on the read control signal to obtain a target read control signal, so that the display device reads and displays the image data from the image register under the control of the target read control signal.

13. A chip, comprising the display driving circuit according to any one of claims 1 to 11.

14. A display device, comprising: A display device; And The display driving circuit according to any one of claims 1 to 11.

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