Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, and belongs to the technical field of display. The display panel comprises a substrate with a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. Wherein the display pixels can emit light under the driving of signals provided by the signal lines, and each signal line comprises a pull-up power line and a pull-down power line. The light-emitting control circuit can respond to a light-emitting control signal provided by the light-emitting control line and control connection and disconnection between the pull-up power line or the pull-down power line and the display pixels. Thus, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the conduction duration of the pull-up power line or the pull-down power line and the display pixel, and then the light-emitting duration of the display pixel is flexibly controlled. Therefore, in the display panel, the driving flexibility for the display pixels is relatively good.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly relates to a display panel, a driving method thereof, and a display device. Background Art

[0002] A display panel generally includes a plurality of pixels. Each pixel includes a pixel circuit and a light-emitting unit connected to each other. The pixel circuit can drive the light-emitting unit to emit light, so that the display panel displays an image.

[0003] In related technologies, a pixel circuit usually includes a data writing circuit and a light-emitting driving circuit. Among them, the data writing circuit is respectively connected to a gate line, a data line, and the light-emitting driving circuit, and is configured to control the data line to transmit a data signal to the light-emitting driving circuit in response to a gate driving signal provided by the gate line. The light-emitting driving circuit is also respectively connected to a pull-up power supply line and the light-emitting unit, and is configured to transmit a light-emitting driving signal to the light-emitting unit based on the data signal and a pull-up power supply signal provided by the pull-up power supply line. The light-emitting unit is also connected to a pull-down power supply line, and the light-emitting unit can emit light under the drive of the light-emitting driving signal and the pull-down power supply signal provided by the pull-down power supply line.

[0004] However, since both the pull-up power supply line and the pull-down power supply line continuously provide power supply signals, the pixel circuit in related technologies cannot flexibly control the light-emitting duration of the light-emitting unit, and the driving flexibility is poor. Summary of the Invention

[0005] A display panel, a driving method thereof, and a display device are provided, which can solve the problem that the pixel circuit in related technologies cannot flexibly control the light-emitting duration of the light-emitting unit, and the driving flexibility is poor.

[0006] The technical solution is as follows:

[0007] On the one hand, a display panel is provided, and the display panel includes:

[0008] A substrate having a display area and at least a part of a peripheral area surrounding the display area;

[0009] A plurality of display pixels arranged in an array, located in the display area. Each display pixel includes: a data writing circuit, a light-emitting driving circuit, an external compensation circuit, and a light-emitting unit. The data writing circuit is respectively connected to a gate line, a data line, and an input node. The external compensation circuit is respectively connected to a compensation line, a sensing line, and an output node. The light-emitting driving circuit is respectively connected to the input node, the output node, and a pull-up power supply line. The light-emitting unit is respectively connected to the output node and a pull-down power supply line;

[0010] A plurality of groups of light-emitting control circuits are located in the peripheral area, each group of the light-emitting control circuits corresponds to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponds to a different row of display pixels, and each group of the light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction, each of the light-emitting control circuits is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line, and is used to control the on-off of the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line;

[0011] Wherein, the target power line is the pull-down power line or the pull-up power line.

[0012] Optionally, each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

[0013] Optionally, each of the light emitting control circuits comprises: an active layer, a gate metal layer and a source-drain metal layer which are located on one side of the substrate and stacked in sequence;

[0014] Each of the light emitting control circuits is switched with the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light emitting control circuits is switched with two display pixels in the same column of the two adjacent rows of display pixels through the same switching via hole.

[0015] Optionally, the thickness and width of the source-drain metal layer satisfy: I_t / (t*b)≤a;

[0016] Among them, I_t refers to the sum of pixel currents of multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; and a refers to the maximum current density resistance of the portion of the source-drain metal layer located in the transfer via.

[0017] Optionally, each group of the light emitting control circuits includes: one light emitting control circuit located at each of two sides of the at least one row of display pixels in the row direction;

[0018] Furthermore, a light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

[0019] Optionally, the light emitting control circuit comprises: a light emitting control transistor;

[0020] The gate of the light-emitting control transistor is connected to the light-emitting control line, the first pole of the light-emitting control transistor is connected to the target power supply line, and the second pole of the light-emitting control transistor is connected to at least one row of display pixels.

[0021] Optionally, the light-emitting control transistor is an N-type transistor.

[0022] Optionally, the light-emitting control transistor is a double-gate transistor.

[0023] Optionally, the data writing circuit includes: a data writing transistor; the external compensation circuit includes: a compensation transistor; the light-emitting driving circuit includes: a driving transistor;

[0024] The gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the second pole of the data writing transistor is connected to the input node;

[0025] The gate of the compensation transistor is connected to the compensation line, the first pole of the compensation transistor is connected to the sensing line, and the second pole of the compensation transistor is connected to the output node;

[0026] When the target power supply line is the pull-up power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the transfer node, the second pole of the driving transistor is connected to the first pole of the light-emitting unit, and the second pole of the light-emitting unit is connected to the pull-down power supply line;

[0027] When the target power supply line is the pull-down power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the pull-up power supply line, the second pole of the driving transistor is connected to the first pole of the light-emitting unit, and the second pole of the light-emitting unit is connected to the transfer node;

[0028] The light-emitting control circuit is connected to the transfer node.

[0029] Optionally, any one of the data writing transistor, the compensation transistor, and the driving transistor is an N-type transistor and a P-type transistor.

[0030] Optionally, each display pixel further includes: a storage capacitor;

[0031] When the driving transistor is a P-type transistor, the target power supply line is the pull-down power supply line, and the storage capacitor is connected in series between the input node and the pull-up power supply line;

[0032] When the driving transistor is an N-type transistor, the target power supply line is the pull-up power supply line, and the storage capacitor is connected in series between the input node and the output node.

[0033] Optionally, the display panel further includes:

[0034] A plurality of dummy pixels, located in the display area and between the multi-row display pixels and the multi-group light-emitting control circuits.

[0035] On the other hand, a driving method for a display panel is provided for driving the display panel as described in the above-mentioned one aspect; the method includes:

[0036] In the writing stage, the potential of the light-emitting control signal provided by the light-emitting control line is the first potential, and the light-emitting control circuit responds to the light-emitting control signal of the first potential to control the disconnection of the target power supply line from the display pixel;

[0037] In the light-emitting stage, the potential of the light-emitting control signal provided by the light-emitting control line is the second potential, and the light-emitting control circuit responds to the light-emitting control signal of the second potential to control the conduction of the target power supply line and the display pixel;

[0038] Wherein, the target power supply line is the pull-up power supply line connected to the light-emitting driving circuit in the display pixel, or the target power supply line is the pull-down power supply line connected to the light-emitting unit in the display pixel.

[0039] In yet another aspect, a display device is provided, the display device includes: a light-emitting control driving circuit, and a display panel as described in the above-mentioned one aspect;

[0040] Wherein, the light-emitting control driving circuit is connected to a plurality of light-emitting control lines connected to a plurality of light-emitting control circuits in the display panel, and is configured to transmit light-emitting control signals to the plurality of light-emitting control lines.

[0041] Optionally, the light-emitting control driving circuit is located in the peripheral area of the substrate in the display panel, and the light-emitting control driving circuit includes a plurality of cascaded light-emitting control driving units, the plurality of light-emitting control driving units are connected to the plurality of light-emitting control lines in one-to-one correspondence, and are configured to sequentially transmit light-emitting control signals to the plurality of light-emitting control lines; or,

[0042] The light-emitting control driving circuit is independent of the display panel, and the light-emitting control driving circuit is configured to simultaneously transmit light-emitting control signals to the plurality of light-emitting control lines.

[0043] In summary, the beneficial effects brought by the technical solutions provided by the present disclosure can at least include:

[0044] A display panel, a driving method thereof, and a display device are provided. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light emission control circuit located in the peripheral area. Among them, the display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power supply line and a pull-down power supply line. The light emission control circuit can control the on-off of the pull-up power supply line or the pull-down power supply line and the display pixels in response to a light emission control signal provided by a light emission control line. In this way, by flexibly setting the light emission control signal, the light emission control circuit can flexibly control the conduction duration of the pull-up power supply line or the pull-down power supply line and the display pixels, and further flexibly control the light emission duration of the display pixels. It can be seen from this that in this display panel, the driving flexibility for the display pixels is relatively good. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0047] Figure 2 It is a schematic structural diagram of a display pixel and a light emission control circuit provided by an embodiment of the present disclosure;

[0048] Figure 3 It is a schematic structural diagram of another display pixel and a light emission control circuit provided by an embodiment of the present disclosure;

[0049] Figure 4 It is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0050] Figure 5 It is a schematic circuit diagram in a display panel provided by an embodiment of the present disclosure;

[0051] Figure 6 It is a schematic circuit diagram in another display panel provided by an embodiment of the present disclosure;

[0052] Figure 7 It is a schematic circuit diagram in yet another display panel provided by an embodiment of the present disclosure;

[0053] Figure 8 It is a schematic circuit diagram in still another display panel provided by an embodiment of the present disclosure;

[0054] Figure 9It is a schematic structural layout diagram of a display panel provided by an embodiment of the present disclosure;

[0055] Figure 10 It is a schematic structural layout diagram of another display panel provided by an embodiment of the present disclosure;

[0056] Figure 11 It is a schematic diagram of the characteristic curve of a light-emitting control circuit provided by an embodiment of the present disclosure;

[0057] Figure 12 It is a schematic diagram of the flow of a driving method for a display panel provided by an embodiment of the present disclosure;

[0058] Figure 13 It is a schematic diagram of signal timing in a display panel provided by an embodiment of the present disclosure;

[0059] Figure 14 It is a schematic diagram of signal timing in another display panel provided by an embodiment of the present disclosure;

[0060] Figure 15 It is a schematic diagram of signal timing in yet another display panel provided by an embodiment of the present disclosure;

[0061] Figure 16 It is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure;

[0062] Figure 17 It is a schematic diagram of the structure of another display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0063] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0064] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetric, their source and drain can be interchanged. The source is referred to as the first pole and the drain as the second pole, or the drain is referred to as the first pole and the source as the second pole. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. In addition, the transistors used in the embodiments of the present disclosure can include any one or a combination of P-type transistors and N-type transistors. Among them, the P-type transistor conducts when the gate is at a low voltage and cuts off when the gate is at a high voltage, and the N-type transistor conducts when the gate is at a high voltage and cuts off when the gate is at a low voltage. In addition, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent that the first potential or the second potential has a specific value.

[0065] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As Figure 1 shown, the display panel includes: a substrate 01, which has a display area AA and a peripheral area BB that at least partially surrounds the display area AA.

[0066] Exemplarily, Figure 1 the shown display area AA is rectangular, and the peripheral area BB is located on the left and right sides of the display area AA, partially surrounding the display area AA. Of course, in some other embodiments, the display area AA may also be in other shapes, such as circular; and, the peripheral area BB may be located on each side of the display area AA, that is, surrounding the display area AA.

[0067] It can be understood that the display area AA can display an image, the peripheral area BB cannot display an image, and the peripheral area BB can also be referred to as a non-display area. Also, the area of the display area AA is generally much larger than the area of the non-display area BB, and the drawings are only for illustrative purposes.

[0068] Continuing to refer to Figure 1 , the display panel further includes: a plurality of display pixels 02 arranged in an array, and the plurality of display pixels 02 are located in the display area AA. The array arrangement may refer to a row-column arrangement, that is, the display panel includes multiple rows and multiple columns of display pixels 02.

[0069] Based on Figure 1 , referring to Figure 2 it can be seen that each display pixel 02 includes: a data writing circuit 021, a light emitting driving circuit 022, an external compensation circuit 023, and a light emitting unit 024. The data writing circuit 021, the light emitting driving circuit 022, and the external compensation circuit 023 can be collectively referred to as a pixel circuit.

[0070] Among them, the data writing circuit 021 is respectively connected to a gate line Gate_A, a data line Data, and an input node N1, the external compensation circuit 023 is respectively connected to a compensation line Gate_B, a sensing line SENS, and an output node N2, the light emitting driving circuit 022 is respectively connected to the input node N1, the output node N2, and a pull-up power supply line VDD, and the light emitting unit 024 is respectively connected to the output node N2 and a pull-down power supply line VSS.

[0071] Optionally, the light emitting unit 024 may be an organic light-emitting diode (OLED). Also, in combination with Figure 2 , it may be that the first electrode (e.g., anode) of the light emitting unit 024 is connected to the output node N2, and the second electrode (e.g., cathode) of the light emitting unit 024 is connected to the pull-down power supply line VSS.

[0072] The data writing circuit 021 can control the connection and disconnection between the data line Data and the input node N1 in response to the gate driving signal provided by the gate line Gate_A. For example, the data writing circuit 021 can control the disconnection between the data line Data and the input node N1 when the potential of the gate driving signal is the first potential; and can control the conduction between the data line Data and the input node N1 when the potential of the gate driving signal is the second potential, so that the data signal provided by the data line Data can be transmitted to the input node N1.

[0073] The light emission driving circuit 022 can transmit a light emission driving signal (such as a pixel current) to the output node N2 based on the potential of the input node N1 and the pull-up power supply signal provided by the pull-up power supply line VDD, so that the light emitting unit 024 can emit light based on the light emission driving signal and the pull-down power supply signal provided by the pull-down power supply line VSS.

[0074] The external compensation circuit 023 can control the connection and disconnection between the sense line SENS and the output node N2 in response to the compensation signal provided by the compensation line Gate_B. And, referring to Figure 2 It can also be seen that the sense line SENS can be connected to the external compensation device 10. For example, the external compensation circuit 023 can control the disconnection between the sense line SENS and the output node N2 when the potential of the compensation signal is the first potential; and can control the conduction between the sense line SENS and the output node N2 when the potential of the compensation signal is the second potential, so that the sense line SENS transmits the reference signal provided by the external compensation device 10 to the output node N2 to reset the output node N2, or the sense line SENS collects the potential of the output node N2 and transmits it to the external compensation device 10, so that the external compensation device 10 extracts sensing signals such as the threshold voltage Vth of the driving transistor in the light emission driving circuit 022 and the pixel current transmitted from the light emission driving circuit 022 to the light emitting unit 024, and externally compensates the data signal provided by the data line Data based on the extracted sensing signals to ensure that the light emitting unit 024 can emit light reliably.

[0075] Continue to refer to Figure 1 , the display panel further includes: multiple groups of light emission control circuits 03Z, which are located in the peripheral area BB. Each group of light emission control circuits 03Z corresponds to at least one row of display pixels 02 in the multiple rows of display pixels 02, and each group of light emission control circuits 03Z corresponds to different rows of display pixels 02. And, each group of light emission control circuits 03Z includes: a light emission control circuit 03 located on at least one side of the corresponding at least one row of display pixels 02 in the row direction X. Each light emission control circuit 03 is connected between the target power supply line and at least one row of display pixels 02, and is also connected to the light emission control line EM, and is used to control the connection and disconnection between the target power supply line and at least one row of display pixels 02 in response to the light emission control signal provided by the light emission control line EM.

[0076] Exemplarily, each light-emitting control circuit 03 can control the target power supply line to be disconnected from at least one row of display pixels 02 when the potential of the light-emitting control signal provided by the light-emitting control line EM is the first potential; and can control the target power supply line to be conducted with at least one row of display pixels 02 when the potential of the light-emitting control signal is the second potential, so that the power supply signal provided by the target power supply line can be transmitted to the display pixels 02 to drive the display pixels 02 to emit light reliably. Wherein, the target power supply line is a pull-down power supply line VSS or a pull-up power supply line VDD. Figure 1 The shown target power supply line is the pull-up power supply line VDD.

[0077] That is, in combination with Figure 2 , in one implementation, the target power supply line is the pull-up power supply line VDD, that is, the light-emitting driving circuit 022 in the display pixel 02 can be indirectly connected to the pull-up power supply line VDD through the light-emitting control circuit 03, and the connection point is also called the transfer node N3. The light-emitting control circuit 03 can control the on / off of the pull-up power supply line VDD and the light-emitting driving circuit 022 under the control of the light-emitting control signal provided by the light-emitting control line EM. Combining the foregoing records, when the light-emitting control circuit 03 controls the pull-up power supply line VDD to be conducted with the light-emitting driving circuit 022, the light-emitting driving circuit 022 can transmit a light-emitting driving signal to the first pole of the light-emitting unit 024 based on the potential of the input node N1 and the pull-up power supply signal provided by the pull-up power supply line VDD, thereby driving the light-emitting unit 024 to emit light.

[0078] Or, in combination with Figure 3 , in another implementation, the target power supply line can be the pull-down power supply line VSS, that is, the second pole of the light-emitting unit 024 in the display pixel 02 can be indirectly connected to the pull-down power supply line VSS through the light-emitting control circuit 03, and the connection point is also called the transfer node N3. The light-emitting control circuit 03 can control the on / off of the pull-down power supply line VSS and the second pole of the light-emitting unit 024 under the control of the light-emitting control signal provided by the light-emitting control line EM. Combining the foregoing records, when the light-emitting control circuit 03 controls the pull-down power supply line VSS to be conducted with the second pole of the light-emitting unit 024, the light-emitting unit 024 can emit light based on the light-emitting driving signal transmitted by the light-emitting driving circuit 022 and the pull-down power supply signal provided by the pull-down power supply line VSS.

[0079] Thus, by flexibly setting the light-emitting control signal, the light-emitting control circuit 03 can flexibly control the duration of the power supply signal transmitted from the pull-up power supply line VDD or the pull-down power supply line VSS to the display pixels 02, and further achieve the purpose of flexibly controlling the duty ratio of the light-emitting duration of the light-emitting unit 024. On this basis, the display abnormality of smear can be effectively improved, and the display effect of the display panel can be ensured to be better.

[0080] In addition, in the embodiments of the present disclosure, for the display pixel 02 with an external compensation function, the light-emitting control circuit 03 is located in the peripheral area BB rather than the display area AA. That is, the light-emitting control circuit 03 is an external circuit relative to the pixel circuit included in the display pixel 02. Therefore, compared with the embodiment in which the display pixel 02 is further provided with a light-emitting control circuit located in the display area AA, the solution provided by the embodiments of the present disclosure will not increase the size of the display pixel 02 (i.e., pixel pitch), and thus will not cause a decrease in PPI of the display area AA. That is, it is also beneficial to the design of a high-PPI display panel. Here, PPI (pixels per inch) refers to the number of pixels that can be set in 1 inch of the display panel and is used to characterize the resolution.

[0081] Optionally, the first potential may refer to an invalid potential, the second potential may refer to a valid potential, and for the N-type transistors included in each circuit, the invalid potential may be a low potential relative to the valid potential; for the P-type transistors included in each circuit, the invalid potential may be a high potential relative to the valid potential.

[0082] In summary, the embodiments of the present disclosure provide a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. Among them, the display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power supply line and a pull-down power supply line. The light-emitting control circuit can control the on / off of the pull-up power supply line or the pull-down power supply line and the display pixel in response to a light-emitting control signal provided by the light-emitting control line. In this way, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the conduction duration of the pull-up power supply line or the pull-down power supply line and the display pixel, and further flexibly control the light-emitting duration of the display pixel. It can be seen that in this display panel, the driving flexibility of the display pixel is relatively good.

[0083] Optionally, Figure 4 is a schematic structural diagram of another display panel provided by the embodiments of the present disclosure. As Figure 4 shown, each group of light-emitting control circuits 03Z can correspond to every two adjacent rows of display pixels 02.

[0084] For example, referring to Figure 4 , from top to bottom, the adjacent first row of display pixels 02 and the second row of display pixels 02 can be connected to each light-emitting control circuit 03 included in the same group of light-emitting control circuits 03Z. The adjacent third row of display pixels 02 and the fourth row of display pixels 02 can be connected to each light-emitting control circuit 03 included in the same group of light-emitting control circuits 03Z. And so on. In this way, not only can the wiring be facilitated, but also only a small number of light-emitting control circuits 03 need to be provided, which is beneficial to the narrow border design of the display panel.

[0085] Optionally, referring to Figure 1 and Figure 4 It can also be seen that in the embodiments of the present disclosure, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on each side of at least one row of display pixels 02 in the row direction X. That is, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on the left side of the display area AA as shown in the figure, and another light-emitting control circuit 03 located on the right side of the display area AA as shown in the figure, a total of two light-emitting control circuits 03.

[0086] Moreover, one light-emitting control circuit 03 located on one side of the two sides may be connected to a part of the display pixels 02 of at least one row of display pixels 02, and another light-emitting control circuit 03 located on the other side of the two sides may be connected to another part of the display pixels 02 of at least one row of display pixels 02 except for a part of the display pixels 02.

[0087] In this way, in the row direction X, for the display pixels 02 close to the left side and the right side of the display area AA, the light-emitting control circuit 03 can timely control the on / off of the target power supply lines such as the pull-up power supply line VDD or the pull-down power supply line VSS and the display pixels 02. And since the longer the trace connecting the light-emitting control circuit 03 and the display pixels 02, the greater the impedance on it, which easily leads to worse reliability of the power supply signal transmitted from the target power supply line to the display pixels 02. Therefore, by arranging one light-emitting control circuit 03 on each of the left and right sides in the row direction X, the length of the trace connected to each light-emitting control circuit 03 can be reduced, thereby reducing the impedance on the trace and ensuring reliable transmission of the power supply signal provided by the target power supply line to the display pixels 02. In some embodiments, for scenarios with larger impedance, increasing the trace line width is also considered to reduce the impedance. However, by adopting the solution of the embodiments of the present disclosure, there is no need to increase the trace line width, which is beneficial to the high PPI design of the display panel.

[0088] Optionally, in combination with Figure 2 , Figure 5 shows a schematic diagram of a circuit structure in a display panel. Figure 6 shows a schematic diagram of a circuit structure in another display panel. In combination with Figure 3 , Figure 7 shows a schematic diagram of a circuit structure in yet another display panel. Figure 8 shows a schematic diagram of a circuit structure in still another display panel. Referring to Figures 5 to 8 It can be seen that the light-emitting control circuit 03 may include: a light-emitting control transistor M0.

[0089] The gate of the light-emitting control transistor M0 can be connected to the light-emitting control line EM, the first pole of the light-emitting control transistor M0 can be connected to the target power supply line, and the second pole of the light-emitting control transistor M0 can be connected to at least one row of display pixels 02, that is, connected to the transfer node N3. For example, Figure 5 and Figure 6 the target power supply line shown in is the pull-up power supply line VDD; Figure 7 and Figure 8 the target power supply line shown in is the pull-down power supply line VSS.

[0090] Optionally, as Figure 5 shown, the light-emitting control transistor M0 can be an N-type transistor. Of course, in some other embodiments, as Figures 6 to 8 shown, the light-emitting control transistor M0 can be a P-type transistor.

[0091] Optionally, in the embodiments of the present disclosure, the light-emitting control transistor M0 can also be a double-gate transistor. That is, the light-emitting control transistor M0 can have two gates.

[0092] Since the leakage current of the P-type transistor is generally large, when the light-emitting control transistor M0 is set as an N-type transistor, the leakage current of the light-emitting control transistor M0 can be reduced to ensure reliable transmission of the power signal to the display pixel 02. In addition, when the light-emitting control transistor M0 is set as a double-gate transistor, the threshold voltage Vth of the light-emitting control transistor M0 can be stabilized, further ensuring reliable transmission of the power signal to the display pixel 02.

[0093] Optionally, continuing to refer to Figures 5 to 8 it can be seen that the data writing circuit 021 can include: a data writing transistor M1. The external compensation circuit 023 can include: a compensation transistor M2. The light-emitting driving circuit 022 can include: a driving transistor M3.

[0094] The gate of the data writing transistor M1 can be connected to the gate line Gate_A, the first pole of the data writing transistor M1 can be connected to the data line Data, and the second pole of the data writing transistor M1 can be connected to the input node N1.

[0095] The gate of the compensation transistor M2 can be connected to the compensation line Gate_B, the first pole of the compensation transistor M2 can be connected to the sensing line SENS, and the second pole of the compensation transistor M2 can be connected to the output node N2.

[0096] When the target power supply line is the pull-up power supply line VDD, as Figure 5 and Figure 6As shown, the gate of driving transistor M3 can be connected to input node N1, the first pole of driving transistor M3 can be connected to transfer node N3, the second pole of driving transistor M3 can be connected to the first pole of light-emitting unit 024, and the second pole of light-emitting unit 024 can be connected to pull-down power supply line VSS.

[0097] When the target power supply line is pull-down power supply line VSS, as Figure 7 and Figure 8 shown, the gate of driving transistor M3 can be connected to input node N1, the first pole of driving transistor M3 can be connected to pull-up power supply line VDD, the second pole of driving transistor M3 can be connected to the first pole of light-emitting unit 024, and the second pole of light-emitting unit 024 can be connected to transfer node N3.

[0098] The light-emitting control circuit 03 can be connected to transfer node N3. That is, in combination with the foregoing description, the second pole of light-emitting control transistor M0 can be connected to display pixel 02 by connecting to this transfer node N3.

[0099] Optionally, any one of data writing transistor M1, compensation transistor M2, and driving transistor M3 can be an N-type transistor or a P-type transistor.

[0100] For example, referring to Figure 5 , in the circuit structure shown therein, data writing transistor M1, compensation transistor M2, and driving transistor M3 are all N-type transistors. Referring to Figure 6 , in the circuit structure shown therein, data writing transistor M1 is a P-type transistor, and compensation transistor M2 and driving transistor M3 are both N-type transistors. Referring to Figure 7 , in the circuit structure shown therein, data writing transistor M1 and driving transistor M3 are both P-type transistors, and compensation transistor M2 is an N-type transistor. Referring to Figure 8 , in the circuit structure shown therein, data writing transistor M1, compensation transistor M2, and driving transistor M3 are all P-type transistors.

[0101] Optionally, in the embodiments of the present disclosure, the material of the P-type transistor can be low-temperature poly-silicon (LTPS). The material of the N-type transistor can be oxide. On this basis, Figure 5 the circuit structure shown can be called a pixel circuit with an all-N-type oxide architecture. Figure 6 and Figure 7 the circuit structures shown can be called pixel circuits with a low-temperature poly-silicon oxide (LTPO) architecture including both P-type transistors and N-type transistors. Figure 8The circuit structure shown can be called a pixel circuit of an all-P-type LTPS architecture.

[0102] Among them, Figure 6 and Figure 7 For the LTPO architecture shown, while taking advantage of the low leakage current of the N-type transistors of the oxide and the mobility of the P-type transistors of the LTPS, the working reliability is relatively good.

[0103] Optionally, each transistor described in the embodiments of the present disclosure may be a metal oxide semiconductor (MOS) field effect transistor.

[0104] Optionally, referring to Figure 5 and Figure 8 It can also be seen that each display pixel 02 may further include: a storage capacitor Cst. The storage capacitor Cst can be used to store signals.

[0105] When the driving transistor M3 is a P-type transistor, as Figure 7 and Figure 8 shown, the target power supply line may be a pull-down power supply line VSS, that is, the first pole of the light-emitting control transistor M0 can be connected to the pull-down power supply line VSS, and the second pole of the light-emitting control transistor M0 can be transferred to the transfer node N3 through the second pole of the light-emitting unit 024. And the storage capacitor Cst can be connected in series between the input node N1 and the pull-up power supply line VDD.

[0106] When the driving transistor M3 is an N-type transistor, as Figure 5 and Figure 6 shown, the target power supply line may be a pull-up power supply line VDD, that is, the first pole of the light-emitting control transistor M0 can be connected to the pull-up power supply line VDD, and the second pole of the light-emitting control transistor M0 can be transferred to the transfer node N3 through the first pole of the driving transistor M3. And the storage capacitor Cst can be connected in series between the input node N1 and the output node N2.

[0107] For the embodiment where the driving transistor M3 is a P-type transistor, by setting the target power supply line as the pull-down power supply line VSS, that is, setting the light-emitting control transistor M0 to indirectly transfer the pull-down power supply line VSS to the second pole of the light-emitting unit 024, while flexibly controlling the light-emitting duration, it can also reduce the current difference caused by the voltage drop (IR drop) at the source of the driving transistor M3, ensuring that the driving transistor M3 can reliably transmit the light-emitting driving signal to the light-emitting unit 024 to drive the light-emitting unit 024 to emit light reliably.

[0108] It can be understood that Figures 5 to 8In the circuit structure shown, the pixel circuits included in the display pixel 02 can all be considered as 3T1C structure circuits including three transistors and one storage capacitor. Of course, in some other embodiments, it can also be a 2T1C structure circuit.

[0109] Optionally, referring to Figures 5 to 8 It can also be seen that the external compensation device 10 described above can further include: a switch K1 and a switch K2.

[0110] Among them, the switch K1 can be connected between the reference signal terminal V_REF and the sensing line SENS, and can be connected to the switch control terminal S_REF, and can be used to control the on / off of the reference signal terminal V_REF and the sensing line SENS in response to the switch control signal provided by the switch control terminal S_REF.

[0111] Exemplarily, the switch K1 can control the reference signal terminal V_REF and the sensing line SENS to conduct when the potential of the switch control signal provided by the switch control terminal S_REF is an effective potential, so that the reference signal terminal V_REF transmits the reference signal described above to the output node N2 through the sensing line SENS; and can control the reference signal terminal V_REF and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_REF is an invalid potential.

[0112] The switch K2 can be connected between the test terminal VSENS and the sensing line SENS, and can be connected to the switch control terminal S_SAMP, and can be used to control the on / off of the test terminal VSENS and the sensing line SENS in response to the switch control signal provided by the switch control terminal S_SAMP.

[0113] Exemplarily, the switch K2 can control the test terminal VSENS and the sensing line SENS to conduct when the potential of the switch control signal provided by the switch control terminal S_SAMP is an effective potential, so that the test terminal VSENS collects the sensing signal described above through the sensing line SENS; and can control the test terminal VSENS and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_SAMP is an invalid potential.

[0114] Optionally, as Figures 5 to 8 shown, the switch K1 and the switch K2 can both be single-pole single-throw switches. For any switch, it can be closed when the potential of the switch control signal it receives is an effective potential; it can be opened when the potential of the switch control signal it receives is an invalid potential. Of course, in some other embodiments, the switch K1 and / or the switch K2 can also be the transistors described above.

[0115] Optionally, in combination with Figure 4 the structure shown, Figure 9The structure of a display panel is shown. Figure 9 It can be seen that each light emitting control circuit 03 (ie, the light emitting control transistor M0 externally mounted in the peripheral area BB) may include: an active (ACT) layer ACT1, a gate metal layer GATE1 and a source & drain (SD) metal layer SD1 located on one side of the substrate 01 and stacked in sequence.

[0116] Each light-emitting control circuit 03 can be connected to at least one row of display pixels 02 through the source-drain metal layer SD1 and the connecting via K0. Moreover, each light-emitting control circuit 03 can be connected to two display pixels 02 located in the same column in two adjacent rows of display pixels 02 through the same connecting via K0. In this way, reliable connection between the light-emitting control circuit 03 and the display pixel 02 can be ensured, and the process can be simplified to reduce the cost.

[0117] For example, for an implementation in which the target power line is the pull-up power line VDD, that is, the light emitting control transistor M0 is connected to the first electrode of the driving transistor M3 in the display pixel 02, as shown in FIG. Figure 9 As shown, the source-drain metal layer SD1 of the light-emitting control transistor M0 can be switched to the active layer ACT1 of the driving transistor M3. That is, the active layer ACT1 of the driving transistor M3 in the adjacent up and down rows of display pixels can be switched to the source-drain metal layer SD1 of the light-emitting control transistor M0 through the same switching via K0.

[0118] For another example, for an implementation in which the target power line is the pull-down power line VSS, that is, the light-emitting control transistor M0 is connected to the second electrode of the light-emitting unit 024 in the display pixel 02, assuming that the second electrode of the light-emitting unit 024 is a cathode, it can be considered that the source-drain metal layer SD1 of the light-emitting control transistor M0 is switched to the cathode of the light-emitting unit 024. That is, the cathodes of the light-emitting units 024 in the adjacent upper and lower rows of display pixels can be switched to the source-drain metal layer SD1 of the light-emitting control transistor M0 through the same switching via K0.

[0119] In addition, reference Figure 9 It can also be seen that the light emission control transistor M0 shown therein has two gates, and is a double-gate transistor.

[0120] Optionally, refer to Figure 9 It can also be seen that the display panel may further include: a plurality of dummy pixels 04, which may be located in the display area AA and between the plurality of rows of display pixels 02 and the plurality of groups of light emitting control circuits 03Z (i.e., external light emitting control transistors M0). In this way, the etching uniformity during the preparation of the display panel may be ensured to be good. Optionally, in Figure 9 Based on the layout shown,Figure 10 The structure layout including multiple rows of display pixels 02 is also schematically shown.

[0121] It is understandable that since the pull-up power line VDD or the pull-down power line VSS is connected to multiple display pixels 02 through a light-emitting control transistor M0 to transmit power signals to multiple display pixels 02, it is known that the on-state current of the light-emitting control transistor M0 needs to be relatively large. It is further known that the width and film thickness of the metal wiring at the switching node N3 (i.e., the wiring formed by the source and drain metal layer SD1 of the light-emitting control transistor M0) need to meet the maximum current density corresponding to the large current to reduce the problem of wiring heating.

[0122] Thus, in the embodiment of the present disclosure, the thickness and width of the source-drain metal layer SD1 of the light emitting control transistor M0 may satisfy: I_t / (t*b)≤a.

[0123] Wherein, I_t may refer to the total pixel current of the plurality of display pixels 02 connected to each light emitting control circuit 03. t may refer to the thickness of the source-drain metal layer SD1. b may refer to the width of the source-drain metal layer SD1. a may refer to the maximum current density of the portion of the source-drain metal layer SD1 located at the transfer via K0 (i.e., the transfer node N3).

[0124] Assume that the unit of I_t is microampere (μA) and the unit of a is milliampere / square micrometer (mA / μm 2 ), the unit of b is μm, and the unit of t is μm. After converting the units, it can be deduced that the wiring width b formed by the source-drain metal layer SD1 can satisfy: b≥I_t / 1000 / (t*a).

[0125] Furthermore, it can be understood that the on-state current of the light emitting control transistor M0 should also be greater than or equal to I_t, that is, the sum of the maximum currents of all display pixels controlled. In some embodiments, the on-state current of the light emitting control transistor M0 can be made larger by increasing the width-to-length ratio W / L of the light emitting control transistor M0 or the source-to-drain current Vds of the light emitting control transistor M0.

[0126] For example, assuming that the pixel current of each display pixel is Id (μA), each light emitting control transistor M0 is connected to n rows of display pixels 02 to control the target power line to transmit a power signal to the n rows of display pixels 02, and each row of display pixels 02 includes m display pixels, then I_t can satisfy: I_t=Id*n*m.

[0127] Wherein, n is an integer greater than or equal to 1 and less than the number of rows of display pixels 02 , and m is an integer greater than 1 and less than the number of columns of display pixels 02 .

[0128] Taking an OLED display product as an example, assume that its horizontal resolution H = 2000, that is, the display panel includes 2000 columns of display pixels 02, Id = 150 nanoamperes (nA), and a group of light-emitting control circuits 03Z includes one light-emitting control circuit 03 on each of the left and right sides, and each light-emitting control circuit 03 is connected to a row of display pixels 02, that is, n = 1, n = H / 2 = 500, then it can be calculated that: I_t = 150 μA. That is to say, the on-state current of the light-emitting control transistor M0 in each light-emitting control circuit 03 needs to be at least equal to 150 μA.

[0129] Optionally, Figure 11 Schematically shows the characteristic curve diagrams of the light-emitting control transistor M0 under different on-state currents (such as 1, 2.1, 4.1, etc.). Among them, the abscissa refers to the current, and the ordinate refers to the voltage.

[0130] It can be understood that the light-emitting control transistor M0 described in the embodiments of the present disclosure is not only applicable to OLED display products with the light-emitting unit 024 being OLED, but also equally applicable to MLED display products with the light-emitting unit 024 being a micro light-emitting diode (mini LED, MLED). Since compared with OLED, the pixel current required by MLED is at the μA level, which is about 100 times larger than the pixel current required by OLED, it can be known that the aspect ratio W / L of the light-emitting control transistor M0 set in the MLED display product can be much larger than the aspect ratio W / L of the light-emitting control transistor M0 set in the OLED display product, and a larger current needs to be provided.

[0131] In summary, the embodiments of the present disclosure provide a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. Among them, the display pixels can emit light under the drive of signals provided by each signal line, and each signal line includes a pull-up power supply line and a pull-down power supply line. The light-emitting control circuit can control the on / off of the pull-up power supply line or the pull-down power supply line and the display pixels in response to the light-emitting control signal provided by the light-emitting control line. In this way, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the conduction duration of the pull-up power supply line or the pull-down power supply line and the display pixels, and further flexibly control the light-emitting duration of the display pixels. It can be seen that in this display panel, the driving flexibility for the display pixels is relatively good.

[0132] Figure 12 It is a flowchart of a driving method for a display panel provided by the embodiments of the present disclosure, and this method is used to drive the display panel described above. As Figure 12 shown, this method includes:

[0133] Step 1201, writing stage: The potential of the light emission control signal provided by the light emission control line is the first potential. In response to the light emission control signal with the first potential, the light emission control circuit controls the target power line to be disconnected from the display pixel.

[0134] Step 1202, light emission stage: The potential of the light emission control signal provided by the light emission control line is the second potential. In response to the light emission control signal with the second potential, the light emission control circuit controls the target power line to be connected to the display pixel.

[0135] Wherein, the target power line is the pull-up power line connected to the light emission driving circuit in the display pixel, or the target power line is the pull-down power line connected to the light emission unit in the display pixel.

[0136] Optionally, for multiple light emission control lines connected to multiple light emission control circuits, in one implementation, the required light emission control signals can be provided to each of the multiple light emission control lines one by one, or, in another implementation, the required light emission control signals can also be provided to the multiple light emission control lines uniformly. In these two implementations, with the Figure 5 shown structure, Figure 13 and Figure 14 respectively show a signal sequence diagram in a display panel. Referring to the timing diagram, it can be seen that one frame period can include a display stage T1 and a sensing stage T2 that are sequentially executed. The display stage T1 can include a writing stage T11 and a light emission stage T12 that are sequentially executed. The sensing stage T2 can include a reset stage T21, a compensation stage T22, and an extraction stage T23 that are sequentially executed.

[0137] Wherein, in the writing stage T11, the gate line Gate_A can provide a gate driving signal with a high potential, the compensation line Gate_B can provide a compensation signal with a high potential, and the light emission control line EM can provide a light emission control signal with a low potential. Figure 5 In the shown structure, the high potential is the effective potential and the low potential is the invalid potential. Correspondingly, the data writing transistor M1 and the compensation transistor M2 can both be turned on, and the light emission control transistor M0 can be turned off. Further, the data line Data can transmit a data signal to the input node N1 through the turned-on data writing transistor M1 to charge the input node N1; and the sensing line SENS can transmit a reference signal to the output node N2 through the turned-on compensation transistor M2 to reset the output node N2. The storage capacitor Cst can store the data signal transmitted to the input node N1.

[0138] During the light-emitting stage T12, the gate line Gate_A can provide a gate driving signal with a low potential, the compensation line Gate_B can provide a compensation signal with a low potential, and the light-emitting control line EM can provide a light-emitting control signal with a high potential. Correspondingly, the data writing transistor M1 and the compensation transistor M2 can both be turned off, and the light-emitting control transistor M0 can be turned on. Furthermore, the pull-up power supply line VDD can transmit a pull-up power signal to the transfer node N3 through the turned-on light-emitting control transistor M0, so that the light-emitting driving transistor M3 can transmit a light-emitting driving signal to the anode of the light-emitting unit 024 based on the pull-up power signal and the data signal at the input node N1, thereby enabling the light-emitting unit 024 to emit light based on the light-emitting driving signal and the pull-down power signal provided by the pull-down power supply line VSS connected to the cathode. The light-emitting duration is positively correlated with the duration of the light-emitting control signal with a high potential. That is, the longer the duration of the light-emitting control signal with a high potential, the longer the light-emitting duration of the light-emitting unit 024. Thus, flexible control of the light-emitting duration of the display pixel 02 can be achieved.

[0139] During the reset stage T21 to the extraction stage T23, the gate line Gate_A can provide a gate driving signal with a high potential, the compensation line Gate_B can provide a compensation signal with a high potential, and the light-emitting control line EM can provide a light-emitting control signal with a high potential. Correspondingly, the data writing transistor M1, the compensation transistor M2, and the light-emitting control transistor M0 can all be turned on.

[0140] Moreover, during the reset stage T21, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an effective potential (e.g., a low potential), and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal with an ineffective potential (e.g., a high potential), so that the switch K1 is turned on and the switch K2 is turned off. Furthermore, the reference signal terminal V_REF and the sensing line SENS can be conducted, and the reference signal can be transmitted to the output node N2 through the sensing line SENS and the turned-on compensation transistor M2 to reset the output node N2, that is, the anode of the light-emitting unit 024.

[0141] During the compensation stage T22, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an ineffective potential, and the switch control terminal S_SAMP connected to the switch K2 can also provide a switch control signal with an ineffective potential, so that both the switch K1 and the switch K2 are turned off.

[0142] In the extraction stage T23, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an invalid potential, and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal with a valid potential, so that the switch K1 is turned off and the switch K2 is turned on. Furthermore, the test terminal VSENS and the sensing line SENS can be conducted, and the sensing line SENS can extract the signal of the output node N2 as a sensing signal and transmit it to the test terminal VSENS for the external compensation device 10 to perform external compensation on the data signal based on the sensing signal.

[0143] It can be understood that referring to Figure 14 , multiple gate lines Gate_A connected to the multi-line display pixel 02 can provide a gate driving signal with a valid potential to the multi-line display pixel 02 line by line. Figure 13 In the shown timing, multiple switch control lines EM can provide a switch control signal with a valid potential line by line, that is, the light-emitting control transistors M0 connected to each row of display pixels 02 can be turned on line by line. Figure 14 In the shown timing, multiple switch control lines EM can be such that after the multiple gate lines Gate_A provide a gate driving signal with a valid potential to all row display pixels 02 and the data signal provided by the data line Data is written into all row display pixels 02, a light-emitting control signal with a valid potential is further uniformly provided, that is, the light-emitting control transistors M0 connected to each row of display pixels 02 can be turned on simultaneously. In addition, the same as the multiple gate lines Gate_A, as Figure 14 shown, multiple compensation lines Gate_B connected to the multi-line display pixel 02 can also provide a compensation signal with a valid potential to the multi-line display pixel 02 line by line. In the figure, it is illustrated by taking the display panel including n rows of display pixels 02 as an example.

[0144] Optionally, Figure 15 also taking the Figure 8 shown structure as an example, a signal sequence diagram in a display panel is shown. Comparing Figure 13 and Figure 14 it can be seen that different from the Figure 5 shown structure, since the data writing transistor M1, the compensation transistor M2, and the light-emitting control transistor M0 are all P-type transistors, the valid potential of the gate driving signal, the compensation signal, and the light-emitting control signal all become low potential, and at the same time, the invalid potential all becomes high potential.

[0145] It can be understood that since the driving method has basically the same technical effect as the foregoing display panel embodiment, for the sake of simplicity, the technical effect of the driving method is not described repeatedly here.

[0146] Figure 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As Figure 16As shown, the display device includes: a light-emitting control driving circuit 20 and a display panel 00 as described above.

[0147] Among them, combined with Figure 1 , the light-emitting control driving circuit 20 is connected to a plurality of light-emitting control lines EM connected to a plurality of light-emitting control circuits 03 in the display panel 00, and is used to transmit light-emitting control signals to the plurality of light-emitting control lines EM.

[0148] Optionally, as an alternative implementation, as Figure 16 shown, the light-emitting control driving circuit 20 and the display panel 00 can be independent of each other. The light-emitting control driving circuit 20 can be used to transmit light-emitting control signals to the plurality of light-emitting control lines EM simultaneously. That is, transmit light-emitting control signals that satisfy the timing as Figure 14 shown.

[0149] For example, the light-emitting control driving circuit 20 can be an external integrated circuit (IC).

[0150] It can be understood that Figure 16 schematically shows the display area AA in the display panel and the 3T1C pixel circuit + light-emitting unit located in the display area AA, the peripheral area BB and the light-emitting control circuit located in the peripheral area BB.

[0151] Optionally, as another alternative implementation, as Figure 17 shown, the light-emitting control driving circuit 20 can be located in the peripheral area BB of the substrate 01 in the display panel 00. For example, the light-emitting control driving circuit 20 can be arranged on the substrate 01 by using the gate driver on array (GOA) technology. Correspondingly, the light-emitting control driving circuit 20 can also be called an EMGOA circuit. And the light-emitting control driving circuit 20 can include a plurality of cascaded light-emitting control driving units EM GOA. The plurality of light-emitting control driving units EM GOA can be connected to the plurality of light-emitting control lines EM in one-to-one correspondence, and are used to sequentially transmit light-emitting control signals to the plurality of light-emitting control lines EM. That is, transmit light-emitting control signals that satisfy the timing as Figure 13 shown.

[0152] It can be understood that Figure 17Also schematically shown are multiple rows of display pixels 02 located in the display area AA, and each light-emitting control circuit 03 can be connected to one row of display pixels 02. Further, a power supply 30 is shown, which is respectively connected to the light-emitting control circuit 03 and the display pixels 02 and is used to supply power to the light-emitting control circuit 03 and the display pixels 02. In addition, the display device may further include: a gate driving circuit located in the peripheral area BB, that is, a Gate GOA circuit, for transmitting a gate driving signal to the gate line Gate_A. The provision of the compensation signal is the same and will not be elaborated here.

[0153] Optionally, the display device may be: any type of display device such as an OLED display device and an MLED display device. And, the display device includes: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, and virtual reality (VR). Among them, since the VR display device will produce a tail-like effect when moving at a relatively high speed or quickly changing the viewing angle, and two images are simultaneously reflected in the human brain, it will cause ghosting anomalies and affect the viewing effect. However, in the embodiments of the present disclosure, by flexibly controlling the light-emitting duration, the adverse effect of the ghosting anomaly can be effectively improved.

[0154] It should be understood that the terms used in the embodiments of the present disclosure are for the purpose of explaining the embodiments of the present disclosure, rather than aiming to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning understood by those of ordinary skill in the field to which the present disclosure belongs.

[0155] For example, in the embodiments of the present disclosure, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The term "connection" may refer to an electrical connection. The term "plurality" refers to two or more, unless otherwise clearly defined. Similarly, words such as "one" or "a" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. "Upper", "lower", "left" or "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0156] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that, The display panel comprises: A substrate having a display area and a peripheral area at least partially surrounding the display area; A plurality of display pixels arranged in an array are located in the display area, each of the display pixels comprises: a data writing circuit, a light emitting driving circuit, an external compensation circuit and a light emitting unit, the data writing circuit is respectively connected to a gate line, a data line and an input node, the external compensation circuit is respectively connected to a compensation line, a sensing line and an output node, the light emitting driving circuit is respectively connected to the input node, the output node and a pull-up power line, and the light emitting unit is respectively connected to the output node and the pull-down power line; A plurality of groups of light-emitting control circuits are located in the peripheral area, each group of the light-emitting control circuits corresponds to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponds to a different row of display pixels, and each group of the light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction, each of the light-emitting control circuits is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line, and is used to control the on-off of the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line; Wherein, the target power line is the pull-down power line or the pull-up power line.

2. The display panel according to claim 1, wherein Each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

3. The display panel according to claim 2, wherein Each of the light emitting control circuits comprises: an active layer, a gate metal layer and a source-drain metal layer which are located on one side of the substrate and are stacked in sequence; Each of the light emitting control circuits is switched with the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light emitting control circuits is switched with two display pixels in the same column of the two adjacent rows of display pixels through the same switching via hole.

4. The display panel according to claim 3, wherein The thickness and width of the source and drain metal layers satisfy: I_t / (t*b)≤a; Among them, I_t refers to the sum of pixel currents of multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; and a refers to the maximum current density resistance of the portion of the source-drain metal layer located in the transfer via.

5. The display panel according to any one of claims 1 to 4, characterized in that, Each group of the light emitting control circuits comprises: one light emitting control circuit located on each side of the at least one row of display pixels in the row direction; Furthermore, a light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

6. The display panel according to any one of claims 1 to 4, characterized in that, The light emitting control circuit comprises: a light emitting control transistor; A gate of the light emission control transistor is connected to the light emission control line, a first electrode of the light emission control transistor is connected to the target power supply line, and a second electrode of the light emission control transistor is connected to the at least one row of display pixels.

7. The display panel according to claim 6, wherein The light emission control transistor is an N-type transistor.

8. The display panel according to claim 6, characterized in that, The light emission control transistor is a dual-gate transistor.

9. The display panel according to any one of claims 1 to 4, characterized in that, The data writing circuit includes: a data writing transistor; the external compensation circuit includes: a compensation transistor; the light-emitting driving circuit includes: a driving transistor; The gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the second pole of the data writing transistor is connected to the input node; The gate of the compensation transistor is connected to the compensation line, the first pole of the compensation transistor is connected to the sensing line, and the second pole of the compensation transistor is connected to the output node; When the target power supply line is the pull-up power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the transfer node, the second pole of the driving transistor is connected to the first pole of the light-emitting unit, and the second pole of the light-emitting unit is connected to the pull-down power supply line; When the target power supply line is the pull-down power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the pull-up power supply line, the second pole of the driving transistor is connected to the first pole of the light-emitting unit, and the second pole of the light-emitting unit is connected to the transfer node; The light-emitting control circuit is connected to the transfer node.

10. The display panel according to claim 9, wherein, Any one of the data writing transistor, the compensation transistor, and the driving transistor is an N-type transistor or a P-type transistor.

11. The display panel according to claim 10, wherein Each of the display pixels further includes: a storage capacitor; When the driving transistor is a P-type transistor, the target power supply line is the pull-down power supply line, and the storage capacitor is connected in series between the input node and the pull-up power supply line; When the driving transistor is an N-type transistor, the target power supply line is the pull-up power supply line, and the storage capacitor is connected in series between the input node and the output node.

12. The display panel according to any one of claims 1 to 4, characterized in that, The display panel further includes: A plurality of dummy pixels, located in the display area and between the multiple rows of display pixels and the multiple groups of light-emitting control circuits.

13. A driving method for a display panel, characterized in that, For driving the display panel according to any one of claims 1 to 12; the method includes: In the writing stage, the potential of the light-emitting control signal provided by the light-emitting control line is the first potential, and the light-emitting control circuit responds to the light-emitting control signal of the first potential to control the disconnection of the target power supply line from the display pixel; In the light-emitting stage, the potential of the light-emitting control signal provided by the light-emitting control line is the second potential, and the light-emitting control circuit responds to the light-emitting control signal of the second potential to control the conduction of the target power supply line and the display pixel; Wherein, the target power supply line is the pull-up power supply line connected to the light-emitting driving circuit in the display pixel, or the target power supply line is the pull-down power supply line connected to the light-emitting unit in the display pixel.

14. A display device, characterized in that, The display device includes: a light-emitting control driving circuit, and the display panel according to any one of claims 1 to 12; Wherein, the light-emitting control driving circuit is connected to multiple light-emitting control lines connected to multiple light-emitting control circuits in the display panel and is used to transmit light-emitting control signals to the multiple light-emitting control lines.

15. The display device according to claim 14, wherein The light-emitting control driving circuit is located in the peripheral area of the substrate in the display panel, and the light-emitting control driving circuit includes a plurality of cascaded light-emitting control driving units. The plurality of light-emitting control driving units are connected to the plurality of light-emitting control lines in one-to-one correspondence and are configured to sequentially transmit light-emitting control signals to the plurality of light-emitting control lines; or, The light-emitting control driving circuit is independent of the display panel, and the light-emitting control driving circuit is configured to simultaneously transmit light-emitting control signals to the plurality of light-emitting control lines.

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