Electronic circuit and delay method thereof

Abstract

An electronic circuit suitable for communication between a controller and a memory array includes a timer and a delay lock loop, and a delay method thereof. The timer counts counting time to generate a first enable signal according to a selection signal generated by the controller. The delay lock loop delays an output clock signal generated by the memory array for a delay time according to a clock signal generated by the controller and a first enable signal to generate a delayed clock signal. When the controller performs a read operation on the memory array, the memory array outputs an output clock signal and a data signal. The controller samples the data signal using the delayed clock signal. According to the electronic circuit and the delay method thereof provided by the invention, the sampling accuracy of the controller is improved.

Description

Technical Field

[0001] The present invention relates to an electronic circuit applicable to a memory and a delay method for the memory, and more particularly to an electronic circuit for optimizing the timing of a clock signal and a data signal issued by a memory array and a delay method thereof. Background Art

[0002] In recent years, edge computing and artificial intelligence have gradually become the mainstream of the market. In addition to more powerful microprocessors (MCU / MPU), people's requirements for storage products have become more and more stringent. Compared with the traditional Pseudo SRAM (pSRAM), a new type of memory called HyperRAM has begun to flourish in the Internet of Things, consumer devices, automotive and industrial applications due to its characteristics such as ultra-low power consumption, simple design, and easy control.

[0003] HyperRAM uses a bus called HyperBus for transmission. HyperBus uses a high-speed 8-bit transmission interface for both addresses and data. In addition, differential clock signals, read / write latch signals, and chip select units are used for each memory element. HyperBus can support external flash memories and random access memories to be set on the same bus and is applicable to any microcontroller with a peripheral interface compatible with HyperBus.

[0004] When reading a memory array, the microprocessor latches the data of the data signal (i.e., DQ[7:0]) through the clock signal of the bidirectional read / write data strobe signal (i.e., the RWDS pin). Since HyperBus is a double data rate (DDR) transmission interface, it is necessary to delay the clock signal of the bidirectional read / write data strobe signal so that the rising edge and the falling edge of the clock signal are aligned with the midpoint of the data signal to facilitate obtaining a correct sampling value. Summary of the Invention

[0005] In view of this, the present invention proposes an electronic circuit and a delay method thereof. By the electronic circuit and the delay method proposed by the present invention, the midpoint of the data signal of the memory array is aligned with the rising edge or the falling edge of the output clock signal (i.e., RWDS) to improve the accuracy rate when the controller samples. In addition, the electronic circuit and the delay method proposed by the present invention also count a counting time. When the electronic circuit times out during operation, the electronic circuit enters a low power consumption state or even does not operate, thereby reducing the power loss to the greatest extent.

[0006] The present invention provides an electronic circuit applicable to communication between a controller and a memory array. The electronic circuit includes a timer and a delay locked loop. The timer counts a counting time according to a selection signal generated by the controller to generate a first enable signal. The delay locked loop delays an output clock signal generated by the memory array by a delay time according to a clock signal and the first enable signal generated by the controller to generate a delayed clock signal. When the controller performs a read operation on the memory array, the memory array outputs the output clock signal and a data signal. The controller samples the data signal by using the delayed clock signal.

[0007] According to an embodiment of the present invention, the delay locked loop includes a first logic unit, a loop filter, a charge pump, a phase comparator, and a first delay chain. The first logic unit outputs the clock signal as a reference clock signal based on the first enable signal being in an enabled state. The loop filter generates a control voltage. The charge pump charges and discharges the loop filter according to a control signal. The phase comparator compares the phases of the reference clock signal and a first internal delay signal to generate the control signal. The first delay chain has a predetermined number of delay units and delays the reference clock signal based on the control voltage to generate the first internal delay signal.

[0008] According to an embodiment of the present invention, the delay locked loop includes a second delay chain and a multiplexer. The second delay chain has the predetermined number of delay units and delays the output clock signal by the delay time based on the control voltage to generate a second internal delay signal. The multiplexer selects one of the output signals of the predetermined number of delay units as the delayed clock signal.

[0009] According to an embodiment of the present invention, the first delay chain delays the reference clock signal by the delay time to generate the first internal delay signal. The reference clock signal has a cycle time, and the delay time is equal to the cycle time.

[0010] According to an embodiment of the present invention, when the phase of the reference clock signal is equal to the phase of the first internal delay signal, the phase comparator generates a lock signal. The controller knows that the phase of the reference clock signal is equal to the phase of the first internal delay signal based on the lock signal, and samples the data signal according to the delayed clock signal.

[0011] According to an embodiment of the present invention, when the first enable signal is in a disabled state, the first logic unit does not output the reference clock signal. When the first enable signal is in the enabled state, the first logic unit outputs the clock signal as the reference clock signal.

[0012] According to an embodiment of the present invention, when the first enable signal is in the disabled state, power supply to the delay locked loop is stopped.

[0013] According to an embodiment of the present invention, when the selection signal transitions from a first logic level to a second logic level, communication begins between the controller and the memory array, the first enable signal is in the enabled state, and the timer resets the counting time.

[0014] According to an embodiment of the present invention, when the selection signal transitions from the second logic level to the first logic level, the timer stops counting the counting time. When the counting time reaches a first target time, the timer sets the first enable signal to a disabled state. The delay locked loop does not operate based on the first enable signal in the disabled state.

[0015] According to an embodiment of the present invention, the timer also counts the counting time according to an additional clock signal.

[0016] According to another embodiment of the present invention, the delay locked loop includes a second logic unit. The second logic unit performs a logic operation on the first enable signal and a second enable signal to generate a third enable signal. The first logic unit also generates the reference clock signal based on the third enable signal.

[0017] According to an embodiment of the present invention, when either the first enable signal or the second enable signal is in the enabled state, the first logic unit outputs the clock signal as the reference clock signal. When either the first enable signal or the second enable signal is in the disabled state, the first logic unit does not output the reference clock signal.

[0018] According to an embodiment of the present invention, the delay locked loop includes a third logic unit. The third logic unit generates a maintenance signal according to the first enable state and the second enable state. When the first enable signal is in the disabled state and the second enable signal is in the enabled state, the maintenance signal is in a non-conductive state. When both the first enable signal and the second enable signal are in the enabled state or both are in the disabled state, the maintenance signal is in a conductive state.

[0019] According to an embodiment of the present invention, the above-mentioned loop filter includes a resistor, a capacitor, and a switch. The above-mentioned resistor is coupled to the above-mentioned charge pump. The above-mentioned capacitor is coupled between the above-mentioned control voltage and a ground terminal. The above-mentioned switch is coupled between the above-mentioned resistor and the above-mentioned capacitor and is controlled by the above-mentioned hold signal.

[0020] According to an embodiment of the present invention, when the above-mentioned hold signal is in the above-mentioned non-conducting state, the above-mentioned switch is non-conducting, and the above-mentioned capacitor is used to maintain the above-mentioned control voltage. When the above-mentioned hold signal is in the above-mentioned conducting state, the above-mentioned switch is conducting.

[0021] The present invention also provides a delay method applicable to an electronic circuit. The above-mentioned electronic circuit is used to assist in the communication between a controller and a memory array. The above-mentioned delay method includes: determining whether a selection signal is in an enabling state or a disabling state; when the above-mentioned selection signal is in the above-mentioned enabling state, receiving an output clock signal of the above-mentioned memory array based on the above-mentioned selection signal in the above-mentioned enabling state; and delaying the above-mentioned output clock signal by a delay time using a delay-locked loop to generate a delayed clock signal. The data of a data signal is aligned with the rising edge and the falling edge of the above-mentioned delayed clock signal. The above-mentioned controller samples the above-mentioned data signal based on the above-mentioned delayed clock signal.

[0022] According to an embodiment of the present invention, the above-mentioned delay method further includes: when the above-mentioned selection signal is in the above-mentioned disabling state, counting a counting time; determining whether the above-mentioned counting time reaches a first target time; when the above-mentioned counting time reaches the above-mentioned first target time, stopping the output of the above-mentioned delayed clock signal and continuously determining whether the above-mentioned selection signal is in the above-mentioned enabling state or the above-mentioned disabling state; and when the above-mentioned counting time has not reached the above-mentioned first target time, continuing to count the above-mentioned counting time and continuing to use the above-mentioned delay-locked loop to delay the above-mentioned output clock signal by the above-mentioned delay time to generate the above-mentioned delayed clock signal.

[0023] According to an embodiment of the present invention, the above-mentioned delay method further includes: when the above-mentioned selection signal is in the above-mentioned enabling state, resetting the above-mentioned counting time.

[0024] According to another embodiment of the present invention, the above-mentioned delay-locked loop further includes a capacitor for storing a control voltage, wherein the above-mentioned delay-locked loop delays the above-mentioned output clock signal by the above-mentioned delay time based on the above-mentioned control voltage to generate the above-mentioned delayed clock signal.

[0025] According to an embodiment of the present invention, the above-mentioned delay method further includes: when the above-mentioned counting time reaches the above-mentioned first target time, maintaining the above-mentioned control voltage by using the above-mentioned capacitor to continuously output the above-mentioned delayed clock signal; and when the above-mentioned counting time reaches a second target time, discharging the above-mentioned capacitor and stopping the output of the above-mentioned delayed clock signal. The above-mentioned second target time is greater than the above-mentioned first target time. Description of the Drawings

[0026] Figure 1 is a schematic diagram showing an electronic device according to an embodiment of the present invention;

[0027] Figure 2 is a waveform diagram showing an electronic device according to an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram showing an electronic circuit according to an embodiment of the present invention;

[0029] Figure 4 is a schematic diagram showing an electronic circuit according to another embodiment of the present invention;

[0030] Figure 5 is a circuit diagram showing a loop filter according to an embodiment of the present invention;

[0031] Figure 6 is a flowchart showing a delay method according to an embodiment of the present invention;

[0032] Figure 7 is a flowchart showing a delay method according to an embodiment of the present invention;

[0033] Figure 8 is a flowchart showing a control method according to an embodiment of the present invention.

[0034] Description of the Reference Numerals:

[0035] 100: Electronic device

[0036] 110: Controller

[0037] 120: Memory array

[0038] 130, 300, 400: Electronic circuit

[0039] 310, 410: Timer

[0040] 320, 420: Delay locked loop

[0041] 321: Phase comparator

[0042] 322: Charge pump

[0043] 323,423,500: Loop filter

[0044] 600,700: Delay method

[0045] CS#: Selection signal

[0046] CK / CKB: Transmission clock signal

[0047] DV1: First drive circuit

[0048] DV2: Second drive circuit

[0049] DV3: Third drive circuit

[0050] DV4: Fourth drive circuit

[0051] DV5: Fifth drive circuit

[0052] RWDS: Output clock signal

[0053] RWDS_D: Delayed clock signal

[0054] DQ[7:0]: Data signal

[0055] CMD[47:0]: Operation instruction

[0056] LOCK: Locking signal

[0057] CLK: Clock signal

[0058] SEL: Delay selection signal

[0059] DT1: First data

[0060] DT2: Second data

[0061] DT3: Third data

[0062] DT4: Fourth data

[0063] TRST: Reset terminal

[0064] TCLK: Clock terminal

[0065] TOUT1: First output terminal

[0066] TOUT2: Second output terminal

[0067] CLK_TMR: Timing clock signal

[0068] CLKR: Reference clock signal

[0069] EN1: First enable signal

[0070] EN2: Second Enable Signal

[0071] EN3: Third Enable Signal

[0072] LG1: First Logic Unit

[0073] LG2: Second Logic Unit

[0074] LG3: Third Logic Unit

[0075] DL1: First Delay Chain

[0076] DL2: Second Delay Chain

[0077] MUX: Multiplexer

[0078] SDLY1: First Internal Delay Signal

[0079] SDLY2: Second Internal Delay Signal

[0080] SUP: Rising Signal

[0081] SDN: Falling Signal

[0082] LOCK: Locking Signal

[0083] VCTL: Control Voltage

[0084] DU1: First Delay Unit

[0085] DU2: Second Delay Unit

[0086] DU3: Third Delay Unit

[0087] DU4: Fourth Delay Unit

[0088] DU5: Fifth Delay Unit

[0089] DU6: Sixth Delay Unit

[0090] DU7: Seventh Delay Unit

[0091] DU8: Eighth Delay Unit

[0092] SEL: Delay Selection Signal

[0093] SO1: First Output Signal

[0094] SO2: Second Output Signal

[0095] SO3: Third Output Signal

[0096] HD: Hold Signal

[0097] R: Resistor

[0098] C: Capacitor

[0099] SW: Switch

[0100] GND: Ground terminal

[0101] S610 - S650, S710 - S770, S810 - S830: Step flow Detailed implementation manners

[0102] The following description is of the embodiments of the present application. Its purpose is to illustrate the general principles of the present application by way of example and should not be regarded as a limitation of the present application. The scope of the present application shall be defined by the claims.

[0103] It should be noted that the content disclosed below can provide multiple embodiments or examples for practicing different features of the present application. The specific element examples and arrangements described below are only used to briefly elaborate the spirit of the present application and are not used to limit the scope of the present application. In addition, the following description may reuse the same element symbols or words in multiple examples. However, the purpose of the reuse is only to provide a simplified and clear description and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0104] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present application, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present application.

[0105] Figure 1 is a schematic diagram showing an electronic device according to an embodiment of the present invention. As Figure 1 shown, the electronic device 100 includes a controller 110, a memory array 120, and an electronic circuit 130. According to an embodiment of the present invention, the controller 110 can be a microprocessor. According to some embodiments of the present invention, communication between the controller 110 and the memory array 120 is performed through a transmission interface of HyperBus.

[0106] According to an embodiment of the present invention, as Figure 1 shown, when the controller 110 performs a read operation on the memory array 120, the controller 110 provides a selection signal CS# and a transmission clock signal CK / CKB, and provides them to the memory array 120 via a first driving circuit DV1 and a second driving circuit DV2 respectively, where the selection signal CS# is used to select a corresponding memory address for the read operation.

[0107] When the memory array 120 receives the select signal CS# and the transmission clock signal CK / CKB, the memory array 120 issues the output clock signal RWDS and the data signal DQ[7:0] through the third driving circuit DV3 and the fourth driving circuit DV4. The controller 110 samples the data of the data signal DQ[7:0] according to the output clock signal RWDS. According to other embodiments of the present invention, the controller 110 also sends the operation instruction CMD[47:0] to the memory array 120 through the fifth driving circuit DV5.

[0108] Since there will be some misalignments in the output clock signal RWDS and the data signal DQ[7:0], the electronic circuit 130 is used to generate an accurate delay time so that the controller 110 can sample the correct data. As Figure 1 shown, the electronic circuit 130 is enabled according to the select signal CS#, and generates a lock signal LOCK to notify the controller 110 when the enabling of the electronic circuit 130 is completed. The electronic circuit 130 delays the output clock signal RWDS based on the clock signal CLK and the delay selection signal SEL provided by the controller 110 to generate a delayed clock signal RWDS_D, so that the controller 110 can accurately sample the data of the data signal DQ[7:0] using the delayed clock signal RWDS_D.

[0109] Figure 2 is a waveform diagram showing an electronic device according to an embodiment of the present invention. The following description of Figure 2 will be accompanied by Figure 1 for detailed explanation. The following will be described with the select signal CS# being enabled at a low logic level, and it is not limited in any form. As Figure 2 shown, when the select signal CS# transitions from a high logic level to a low logic level, the controller 110 selects a specific memory address of the memory array 120 for a read operation and enables the electronic circuit 130 at the same time.

[0110] When the electronic circuit 130 completes initialization, the electronic circuit 130 transitions the lock signal LOCK from a low logic level to a high logic level, and the controller 110 provides the transmission clock signal CK / CKB to the memory array 120 only after the lock signal LOCK is at a high logic level, and sends the operation instruction CMD[47:0] to the memory array 120 through the fifth driving circuit DV5. According to some embodiments of the present invention, as Figure 2As shown, the operation instruction CMD[47:0] and the data signal DQ[7:0] share the same pin. In other words, the controller 110 transmits the operation instruction CMD[47:0] to the memory array 120 through the data signal DQ[7:0], and the memory array 120 transmits the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4 through the data signal DQ[7:0].

[0111] As Figure 2 shown, the rising edge and the falling edge of the output clock signal RWDS output by the memory array 120 are respectively aligned with the start point and the end point of the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4. However, when the controller 110 samples the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4, the optimal sampling time point is located at the midpoint of the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4.

[0112] Therefore, the electronic circuit 130 delays the output clock signal RWDS output by the memory array 120 by a delay time to generate a delayed clock signal RWDS_D, so that the rising edge and the falling edge of the delayed clock signal RWDS_D are respectively aligned with the midpoint of the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4. Therefore, the controller 110 can accurately sample the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4 of the data signal DQ[7:0] based on the rising edge and the falling edge of the delayed clock signal RWDS_D.

[0113] According to some embodiments of the present invention, the electronic circuit 130 is used to adjust the delay time of the output clock signal RWDS so that the midpoints of the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4 are respectively aligned with the rising edge and the falling edge of the delayed clock signal RWDS_D. Hereinafter, how the electronic circuit 130 generates the delayed clock signal RWDS_D based on the output clock signal RWDS will be described in detail.

[0114] Figure 3 is a schematic diagram showing an electronic circuit according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 1 the electronic circuit 130 corresponds to the electronic circuit 300. As Figure 3 shown, the electronic circuit 300 includes a timer 310 and a delay locked loop 320.

[0115] The timer 310 is used to count a counting time, and includes a reset terminal TRST, a clock terminal TCLK, and a first output terminal TOUT1. The reset terminal TRST receives a selection signal CS#, the clock terminal TCLK receives Figure 1 the additional timing clock signal CLK_TMR generated by the controller 110 ( Figure 1 not shown in the figure), and the first output terminal TOUT1 generates a first enable signal EN1.

[0116] When the selection signal CS# is at a low logic level, the controller 110 starts a read operation on the memory array 120. The timer 310 resets the counted counting time to zero based on the selection signal CS# at a low logic level, and outputs the first enable signal EN1 at a low logic level. When the selection signal CS# is at a high logic level, the controller 110 does not perform a read operation on the memory array 120.

[0117] Meanwhile, the timer 310 starts to count a counting time based on the period of the timing clock signal CLK_TMR based on the selection signal CS# at a high logic level. In other words, the timer 310 resets the counting time based on the selection signal CS# at a low logic level, and starts to count a counting time based on the selection signal CS# at a high logic level.

[0118] According to an embodiment of the present invention, when the counting time reaches the first target time, the first enable signal EN1 output by the timer 310 is at a high logic level. According to another embodiment of the present invention, when the counting time does not reach the first target time, the first enable signal EN1 output by the timer 310 is still at a low logic level.

[0119] The delay-locked loop 320, according to Figure 1 the clock signal CLK provided by the controller 110 and the first enable signal EN1 at a low logic level, delays the output clock signal RWDS generated by the memory array 120 by an appropriate delay time to generate a delayed clock signal RWDS_D, such that the start and end points of the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4 provided by the memory array 120 through the data signals DQ[7:0] are aligned with the rising edge and the falling edge of the delayed clock signal RWDS_D respectively.

[0120] As Figure 3 shown, the delay-locked loop 320 includes a first logic unit LG1, a phase comparator 321, a charge pump 322, a loop filter 323, a first delay chain DL1, a second delay chain DL2, and a multiplexer MUX. The first logic unit LG1, based on the first enable signal EN1 being in an enabled state, Figure 1The clock signal CLK output provided by the controller 110 is the reference clock signal CLKR. According to an embodiment of the present invention, since the description herein is based on enabling with a low logic level, the first logic unit LG1 is exemplified as an AND gate. When the electronic circuit 300 is enabled with a high logic level, the first logic unit LG1 can be a combination of other logic gates.

[0121] According to an embodiment of the present invention, when the first enable signal EN1 is at a low logic level, the enable delay locked loop 320 is enabled, such that the delay locked loop 320 operates in a high power consumption state. As Figure 3 shown, when the first enable signal EN1 is at a low logic level, the first logic unit LG1 outputs the clock signal CLK as the reference clock signal CLKR. When the first enable signal EN1 is at a high logic level, the first logic unit LG1 stops outputting the reference clock signal CLKR.

[0122] The phase comparator 321 compares the phase of the reference clock signal CLKR and the first internal delay signal SDLY1 based on the first enable signal EN1 being in an enabled state, and generates a rising signal SUP and a falling signal SDN. According to an embodiment of the present invention, the rising signal SUP and the falling signal SDN are combined to form a control signal. In addition, when the phase of the reference clock signal CLKR is equal to the phase of the first internal delay signal SDLY1, the phase comparator 321 outputs a lock signal LOCK, such that the controller 110 knows that the electronic circuit 300 has completed delay locking.

[0123] The charge pump 322 charges and discharges the loop filter 323 according to the control signal formed by combining the rising signal SUP and the falling signal SDN, and thereby generates a control voltage VCTL. According to an embodiment of the present invention, when the first enable signal EN1 is in a disabled state (i.e., at a high logic level in the Figure 3 embodiment), the phase comparator 321 is in a disabled state, and the charge pump 322 discharges the control voltage VCTL. According to an embodiment of the present invention, when the first enable signal EN1 is in a disabled state, the delay locked loop 320 operates in a first low power consumption state, and the delay locked loop 320 does not operate, wherein the power consumption of the delay locked loop 320 operating in the first low power consumption state is less than the power consumption of the delay locked loop 320 operating in the high power consumption state.

[0124] As Figure 3As shown, the first delay chain DL1 is formed by connecting in series a first delay unit DU1, a second delay unit DU2, a third delay unit DU3, and a fourth delay unit DU4. In addition, each of the first delay unit DU1, the second delay unit DU2, the third delay unit DU3, and the fourth delay unit DU4 generates a delay based on the control voltage VCTL, such that the first delay chain DL1 delays the reference clock signal CLKR to generate a first internal delay signal SDLY1. According to an embodiment of the present invention, when the phase comparator 321 generates a lock signal LOCK, the phase of the reference clock signal CLKR is equal to the phase of the first internal delay signal SDLY1, and the first internal delay signal SDLY1 is delayed by one cycle time of the reference clock signal CLKR with respect to the reference clock signal CLKR.

[0125] According to other embodiments of the present invention, the first delay chain DL1 may include any number of delay units. Here, 4 delay units are used for illustration and explanation, but it is not limited thereto in any form. In addition, when the first delay chain DL1 is composed of a larger number of delay units, the fineness of the generated delay time will be higher. According to some embodiments of the present invention, the first delay chain DL1 may be composed of 16 delay units. According to other embodiments of the present invention, the first delay chain DL1 may be composed of 64 delay units.

[0126] As Figure 3 shown, the second delay chain DL2 is formed by connecting in series a fifth delay unit DU5, a sixth delay unit DU6, a seventh delay unit DU7, and an eighth delay unit DU8. In addition, each of the fifth delay unit DU5, the sixth delay unit DU6, the seventh delay unit DU7, and the eighth delay unit DU8 generates a delay based on the control voltage VCTL, such that the second delay chain DL2 delays the output clock signal RWDS based on the control voltage VCTL to generate a second internal delay signal SDLY2.

[0127] According to some embodiments of the present invention, the number of delay units of the second delay chain DL2 is equal to the number of delay units of the first delay chain DL1, and the first delay unit DU1, the second delay unit DU2, the third delay unit DU3, the fourth delay unit DU4, the fifth delay unit DU5, the sixth delay unit DU6, the seventh delay unit DU7, and the eighth delay unit DU8 have the same circuit structure.

[0128] Since both the first delay chain DL1 and the second delay chain DL2 delay the reference clock signal CLKR and the output clock signal RWDS respectively based on the control voltage VCTL, and the first delay chain DL1 and the second delay chain DL2 have the same number and the same circuit structure of delay units, the delay time from the output clock signal RWDS to the second internal delay signal SDLY2 is equal to the delay time from the reference clock signal CLKR to the first internal delay signal SDLY1. In other words, the delay time of the first delay chain DL1 is copied to the second delay chain DL2.

[0129] As Figure 3 shown, the multiplexer MUX selects one of the first output signal SO1, the second output signal SO2, the third output signal SO3, and the second internal delay signal SDLY2 according to the delay selection signal SEL output by the controller 110 and outputs it as the delayed clock signal RWDS_D. In addition, the output signals of the fifth delay unit DU5, the sixth delay unit DU6, and the seventh delay unit DU7 are the first output signal SO1, the second output signal SO2, and the third output signal SO3 respectively.

[0130] According to an embodiment of the present invention, as Figure 2 shown, when the select signal CS# transitions from a high logic level to a low logic level, the first enable signal EN1 is at a low logic level to enable the electronic circuit 300 to delay the output clock signal RWDS by a delay time to generate a delayed clock signal RWDS_D, and the controller 110 selects an appropriate delay time through the delay selection signal SEL and outputs one of the first output signal SO1, the second output signal SO2, the third output signal SO3, and the second internal delay signal SDLY2 as the delayed clock signal RWDS_D.

[0131] In addition, when the select signal CS# transitions from a high logic level to a low logic level, the timer 310 resets the counting time. According to another embodiment of the present invention, when the select signal CS# transitions from a low logic level to a high logic level, the first enable signal EN1 switches to a high logic level, and the timer 310 starts counting a counting time. When the counting time reaches the first target time, the timer 310 outputs the first enable signal EN1 as a high logic level, so that the delay locked loop 320 does not operate to reduce power consumption. In other words, based on the high logic level select signal CS# lasting for a counting time, the electronic circuit 300 does not operate to reduce power consumption.

[0132] Figure 4 is a schematic diagram showing an electronic circuit according to another embodiment of the present invention. According to another embodiment of the present invention, Figure 1 the electronic circuit 130 corresponds to the electronic circuit 400. TheFigure 4 The electronic circuit 400 compared with Figure 3 the electronic circuit 300, the electronic circuit 400 further includes a second logic unit LG2 and a third logic unit LG3, and the timer 410 further includes a second output terminal TOUT2 for outputting a second enable signal EN2. In addition, Figure 4 the delay-locked loop 420 is the same as Figure 3 the delay-locked loop 320 except for the loop filter 423, and the detailed content will be described in detail below.

[0133] According to an embodiment of the present invention, as Figure 2 shown, when the select signal CS# transitions from a high logic level to a low logic level, the timer 410 resets the count time and sets the first enable signal EN1 and the second enable signal EN2 to the enabled state (i.e., low logic level in the Figure 4 embodiment). The second logic unit LG2 performs a logical OR operation on the first enable signal EN1 and the second enable signal EN2 to generate a third enable signal EN3, and the first logic unit LG1 outputs the clock signal CLK as the reference clock signal CLKR based on the enabled third enable signal EN3.

[0134] According to an embodiment of the present invention, when the select signal CS# is at a low logic level, the electronic circuit 400 operates in a high-power consumption state, the first enable signal EN1 and the second enable signal EN2 are both in the enabled state (i.e., low logic level in the Figure 4 embodiment), the second logic unit LG2 generates a third enable signal EN3 in the enabled state according to the first enable signal EN1 and the second enable signal EN2, the first logic unit LG1 outputs the clock signal CLK as the reference clock signal CLKR based on the enabled third enable signal EN3, and the third logic unit LG3 sets the hold signal HD to the conducting state according to the first enable signal EN1 and the second enable signal EN2. The delay-locked loop 420 operates in a high-power consumption state according to the enabled third enable signal EN3 and the reference clock signal CLKR and delays the output clock signal RWDS to the delayed clock signal RWDS_D. According to an embodiment of the present invention, the second logic unit LG2 is an OR gate here.

[0135] As Figure 2 shown, when the select signal CS# transitions from a low logic level to a high logic level, the timer 410 starts counting a count time. According to an embodiment of the present invention, before the count time reaches the first target time, the first enable signal EN1 and the second enable signal EN2 are both in the enabled state (i.e., in the Figure 4In the embodiment, it is a low logic level), the second logic unit LG2 generates a third enable signal EN3 in an enabled state according to the first enable signal EN1 and the second enable signal EN2, and the first logic unit LG1 outputs the clock signal CLK as the reference clock signal CLKR based on the enabled third enable signal EN3. The third logic unit LG3 sets the hold signal HD to an on state according to the first enable signal EN1 and the second enable signal EN2. The delay-locked loop 420 still operates in a high power consumption state according to the enabled third enable signal EN3 and the reference clock signal CLKR and delays the output clock signal RWDS to the delayed clock signal RWDS_D.

[0136] According to another embodiment of the present invention, when the counting time reaches the first target time, the timer 410 sets the first enable signal EN1 to a disabled state (i.e., in Figure 4 the embodiment, it is a high logic level), the second logic unit LG2 generates a third enable signal EN3 in a disabled state based on the first enable signal EN1 in a disabled state, so that the first logic unit LG1 stops generating the reference clock signal CLKR, and the delay-locked loop 420 operates in a second low power consumption state, where the power consumption of the delay-locked loop 420 operating in the second low power consumption state is between the power consumption of the delay-locked loop 420 operating in the high power consumption state and the first low power consumption state.

[0137] When the delay-locked loop 420 operates in the second low power consumption state, the phase comparator 321 and the charge pump 322 do not operate. The third logic unit LG3 sets the hold signal HD to a non-conducting state based on the first enable signal EN1 in a disabled state. According to an embodiment of the present invention, the third logic unit LG3 is an AND gate here, and when the hold signal HD is in a non-conducting state, the hold signal HD is a high logic level. The loop filter 423 maintains the control voltage VCTL based on the non-conducting hold signal HD, so that the first delay chain DL1 does not operate and the second delay chain DL2 still remains operating.

[0138] In other words, when the delay-locked loop 420 operates in the second low power consumption state, except that the second delay chain DL2 still remains operating, other elements of the delay-locked loop 420 are not operating to reduce power consumption. According to some embodiments of the present invention, since the loop filter 423 maintains the control voltage VCTL in the second low power consumption state and continuously generates the second internal delay signal SDLY2, the delay-locked loop 420 can recover quickly when it is enabled next time.

[0139] According to yet another embodiment of the present invention, when the counting time continues to count and reaches the second target time, the timer 410 also outputs the second enable signal EN2 as a disabled state (i.e., in Figure 4(in the embodiment, it is a high logic level), the third enable signal EN3 remains in the disabled state, while the hold signal HD is converted to the conducting state. According to an embodiment of the present invention, when the hold signal HD is in the conducting state, the hold signal HD is at a low logic level. Therefore, the charge pump 322 discharges the control voltage VCTL, and the second delay chain DL2 also does not operate, so that the delay locked loop 420 does not operate at all when operating in the first low power state. According to an embodiment of the present invention, the second target time is greater than the first target time.

[0140] According to some embodiments of the present invention, as Figure 2 shown, when the select signal CS# transitions from a low logic level to a high logic level, the timer 410 counts a counting time and the communication between the controller 110 and the memory array 120 stops, and the electronic circuit 400 operates in a first power consumption state (i.e., the delay locked loop 420 does not operate at all) or a second power consumption state (i.e., only the second delay chain DL2 of the delay locked loop 420 remains operating) based on the counting time.

[0141] Figure 5 is a circuit diagram showing a loop filter according to an embodiment of the present invention. According to an embodiment of the present invention, the loop filter 500 corresponds to Figure 4 the loop filter 423 of Figure 5 shown, the loop filter 500 includes a resistor R, a capacitor C, and a switch SW. The resistor R is coupled to the charge pump 322, and the capacitor C is coupled between the resistor R and the ground terminal GND. The switch SW is coupled between the resistor R and the capacitor C and is controlled to conduct or not conduct by the hold signal HD.

[0142] According to an embodiment of the present invention, when the hold signal HD is in the conducting state, the switch SW is conducting, so that the charge pump 322 can charge and discharge the capacitor C through the resistor R and the switch SW, thereby controlling the voltage level of the control voltage VCTL. According to another embodiment of the present invention, when the hold signal HD is in the non-conducting state, the switch SW is non-conducting, the capacitor C is electrically isolated from the charge pump 322, and is used to maintain the voltage level of the control voltage VCTL.

[0143] In other words, when the hold signal HD is in the conducting state, the switch SW is conducting, and the charge pump 322 charges and discharges the capacitor C through the resistor R. When the hold signal HD is in the non-conducting state, the phase comparator 321 and the charge pump 322 do not operate, and the capacitor C is electrically isolated from the charge pump 322 to maintain the voltage level of the control voltage VCTL, thereby maintaining the delay times of the first delay chain DL1 and the second delay chain DL2, and shortening the recovery time for the electronic circuit 400 to resume normal operation.

[0144] Figure 6 is a flowchart showing a delay method according to an embodiment of the present invention. The following description of the delay method 600 for Figure 6 will be described in conjunction with the Figure 3 electronic circuit 300.

[0145] First, the electronic circuit 300 determines the state of the select signal CS# (step S610). When the select signal CS# is in the enabled state (i.e., the Figure 2 low logic level shown), the timer 310 resets a count time (step S620). Then, the electronic circuit 300 receives the output clock signal RWDS from the memory array 120 (step S630). Subsequently, the electronic circuit 300 delays the output clock signal RWDS by an appropriate delay time according to the delay select signal SEL of the controller 110 to generate a delayed clock signal RWDS_D (step S640), such that the start and end points of the first data DT1, second data DT2, third data DT3, and fourth data DT4 of the data signal DQ[7:0] received by the controller 110 are aligned with the rising edge and falling edge of the delayed clock signal RWDS_D, respectively (as shown in Figure 2 ).

[0146] Returning to step S610, when the select signal CS# is in the disabled state (i.e., the Figure 2 high logic level shown), the timer 310 starts counting a count time (step S650) and determines whether the count time has reached a first target time (step S660). When the count time has not reached the first target time, the electronic circuit 300 operates normally (i.e., operates in a high power consumption state), and the timer 310 continues to count a count time (step S650).

[0147] According to some embodiments of the present invention, when the count time has not reached the first target time, the electronic circuit 300 continues to generate the delayed clock signal RWDS_D. When the count time reaches the first target time, the electronic circuit 300 stops generating the delayed clock signal RWDS_D (step S670) and operates in a first low power consumption state, and returns to step S610 to continue monitoring the change of the select signal CS#.

[0148] Figure 7 is a flowchart showing a delay method according to an embodiment of the present invention. The following description of the delay method 700 for Figure 7 will be described in conjunction with the Figure 4 electronic circuit 400.

[0149] As shown in Figure 7 , steps S710 to S760 are the same as those in Figure 6Steps S610 to S660 are the same as those described above and will not be repeated here. When it is determined in step S760 that the counting time has reached the first target time, the electronic circuit 400 operates in the second low-power state and maintains the control voltage VCTL using the capacitor C of the loop filter 423 (step S770).

[0150] After step S770, the timer 410 of the electronic circuit 400 further determines whether the counting time has reached the second target time (step S780). When it is determined in step S780 that the counting time has reached the second target time, the electronic circuit 400 stops generating the delayed clock signal RWDS_D (step S790), operates in the first low-power state, and returns to step S710 to continue monitoring the change of the selection signal CS#. When it is determined in step S780 that the counting time has not reached the second target time, the electronic circuit 400 returns to step S750 to continue counting a counting time.

[0151] According to some embodiments of the present invention, when in step S770 and the controller 110 receives the output clock signal RWDS and data signal DQ[7:0] sent by the memory array 120 again, the controller 110 can, through the selection signal CS#, cause the timer 410 to return to step S710, so that the electronic circuit 400 resets the counting time and resumes the normal working state to generate the delayed clock signal RWDS_D. Since the control voltage VCTL is maintained by the capacitor C, the recovery time for the electronic circuit 400 to recover from the second low-power state to the normal mode is shortened.

[0152] Figure 8 is a flowchart showing a control method according to an embodiment of the present invention. The following description of the control method 800 will be described in conjunction with Figure 1 the electronic device 100.

[0153] First, the controller 110 enables the selection signal CS# (step S810) and determines whether the lock signal LOCK generated by the phase comparator 321 is in an enabled state (step S820). According to an embodiment of the present invention, when the lock signal LOCK is in a disabled state, it means that Figure 3 the electronic circuit 300 and Figure 4 the electronic circuit 400 have not completed the delay lock, so the delayed clock signal RWDS_D is not yet available. Therefore, when it is determined in step S820 that the lock signal LOCK is in a disabled state, the controller 110 continuously determines whether the lock signal LOCK is in an enabled state.

[0154] According to another embodiment of the present invention, when the lock signal LOCK is in an enabled state, it means that Figure 3 the electronic circuit 300 and Figure 4The electronic circuit 400 has completed delay locking, so the delayed clock signal RWDS_D can be utilized. Therefore, when it is determined in step S820 that the lock signal LOCK is in the enabled state, the controller 110 samples the first data DT1, the second data DT2, the third data DT3, and the fourth data DT4 in the data signal DQ[7:0] by using the delayed clock signal RWDS_D (step S830).

[0155] The present invention proposes an electronic circuit and its delay method. By the electronic circuit and its delay method proposed by the present invention, the midpoint of the data signal of the memory array is aligned with the rising edge or the falling edge of the output clock signal (i.e., RWDS), so as to improve the accuracy rate when the controller samples. In addition, the electronic circuit and the delay method proposed by the present invention also count a counting time. When the electronic circuit operates overtime, the electronic circuit enters a low-power state or even does not operate, thereby reducing the power consumption to the greatest extent.

[0156] Although the embodiments of the present application and their advantages have been disclosed above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present application. The protection scope of the present application includes the above-mentioned processes, computers, manufacturing, compositions of matter, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present application also includes the combination of each claim and embodiment.

Claims

1. An electronic circuit, applicable to communication between a controller and a memory array, characterized in that, The electronic circuit includes: a timer that counts a counting time according to a selection signal generated by the controller to generate a first enable signal; and a delay locked loop that delays an output clock signal generated by the memory array by a delay time according to a clock signal and the first enable signal generated by the controller to generate a delayed clock signal; wherein when the controller performs a read operation on the memory array, the memory array outputs the output clock signal and a data signal; wherein the controller samples the data signal by using the delayed clock signal; wherein the delay locked loop switches different power consumption states according to the first enable signal.

2. The electronic circuit according to claim 1, characterized in that, The delay locked loop includes: a first logic unit that outputs the clock signal as a reference clock signal based on the first enable signal being in an enabled state; a loop filter that generates a control voltage; a charge pump that charges and discharges the loop filter according to a control signal; a phase comparator that compares the phase of the reference clock signal and a first internal delay signal to generate the control signal; a first delay chain having a predetermined number of delay units that delays the reference clock signal based on the control voltage to generate the first internal delay signal; a second delay chain having the predetermined number of delay units that delays the output clock signal by the delay time based on the control voltage to generate a second internal delay signal; and a multiplexer that selects one of the output signals of the predetermined number of delay units of the second delay chain as the delayed clock signal.

3. The electronic circuit according to claim 2, wherein The first delay chain delays the reference clock signal by the delay time to generate the first internal delay signal; wherein the reference clock signal has a cycle time; wherein the delay time is equal to the cycle time; wherein when the phase of the reference clock signal is equal to the phase of the first internal delay signal, the phase comparator generates a lock signal; wherein the controller knows that the phase of the reference clock signal is equal to the phase of the first internal delay signal based on the lock signal and samples the data signal according to the delayed clock signal.

4. The electronic circuit according to claim 2, wherein, When the first enable signal is in a disabled state, the first logic unit does not output the reference clock signal; wherein when the first enable signal is in the enabled state, the first logic unit outputs the clock signal as the reference clock signal; wherein the delay locked loop operates in a high power consumption state based on the first enable signal in the enabled state; wherein when the first enable signal is in the disabled state, power supply to the delay locked loop is stopped; wherein the delay locked loop operates in a first low power consumption state based on the first enable signal in the disabled state; wherein the power consumption of the delay locked loop operating in the high power consumption state is greater than the power consumption of the delay locked loop operating in the first low power consumption state; When the selection signal transitions from a first logic level to a second logic level, communication begins between the controller and the memory array, the first enable signal is in the enabled state, and the timer resets the counting time; When the selection signal transitions from the second logic level to the first logic level, the timer starts counting the counting time; When the counting time reaches a first target time, the timer sets the first enable signal to the disabled state; The delay locked loop does not operate based on the first enable signal in the disabled state.

5. The electronic circuit according to claim 4, characterized in that, The delay locked loop includes: A second logic unit that performs a logic operation on the first enable signal and a second enable signal to generate a third enable signal; The first logic unit further generates the reference clock signal based on the third enable signal; When either the first enable signal or the second enable signal is in the enabled state, the first logic unit outputs the clock signal as the reference clock signal; When either the first enable signal or the second enable signal is in the disabled state, the first logic unit does not output the reference clock signal.

6. The electronic circuit according to claim 5, wherein, The delay locked loop further includes: A third logic unit that generates a hold signal based on the first enable signal and the second enable signal; When the first enable signal is in the disabled state and the second enable signal is in the enabled state, the hold signal is in a non-conducting state; When both the first enable signal and the second enable signal are in the enabled state or both are in the disabled state, the hold signal is in a conducting state; The delay locked loop operates in a second low power state based on the non-conducting state of the hold signal; The power consumption of the delay locked loop operating in the second low power state is between the power consumption of the delay locked loop operating in the high power state and the first low power state.

7. The electronic circuit according to claim 6, wherein, The loop filter includes: A resistor coupled to the charge pump; A capacitor coupled between the control voltage and a ground terminal; and A switch coupled between the resistor and the capacitor and controlled by the hold signal; When the hold signal is in the non-conducting state, the switch is non-conducting and the capacitor is used to maintain the control voltage; When the hold signal is in the conducting state, the switch is conducting.

8. A delay method, applicable to an electronic circuit, characterized in that, The electronic circuit is used to assist communication between a controller and a memory array, and the delay method includes: Determining whether a selection signal is in an enabled state or a disabled state; When the selection signal is in the enabled state, receiving an output clock signal of the memory array based on the selection signal in the enabled state; and Delaying the output clock signal by a delay time using a delay locked loop to generate a delayed clock signal; The data of a data signal is aligned with the rising edge and the falling edge of the delayed clock signal; Wherein the controller samples the data signal based on the delayed clock signal.

9. The delay method according to claim 8, wherein Further included are: When the selection signal is in the disabled state, counting a counting time; Judging whether the counting time reaches a first target time; When the counting time reaches the first target time, stopping the output of the delayed clock signal and continuously judging whether the selection signal is in the enabled state or the disabled state; When the counting time has not reached the first target time, continuing to count the counting time and continuing to use the delay locked loop to delay the output clock signal by the delay time to generate the delayed clock signal; When the selection signal is in the enabled state, resetting the counting time.

10. The delay method according to claim 9, wherein The delay locked loop further includes a capacitor for storing a control voltage, wherein the delay locked loop delays the output clock signal by the delay time based on the control voltage to generate the delayed clock signal; Wherein the delay method further includes: When the counting time reaches the first target time, using the capacitor to maintain the control voltage to continuously output the delayed clock signal and reduce power consumption; and When the counting time reaches a second target time, discharging the capacitor and stopping the output of the delayed clock signal; Wherein the second target time is greater than the first target time.

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