Apparatus, system and method for non-target on-die terminal adjustment in power-off state

Abstract

The present disclosure relates to devices, systems, and methods for non-target terminal on die (NT-ODT adjustment) in a power-off state. In one embodiment, a memory device has NT-ODT power down logic that couples a specified pin of a command address terminal to an ODT control circuit when the memory device is in a power down state, thereby bypassing a command decoder. An NT-ODT adjustment command received along the specified pin causes the ODT control circuit to change a resistance of a termination circuit of the memory when the memory is in the power-off state.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor memory devices. Specifically, the present disclosure relates to volatile memories such as dynamic random access memories (DRAMs). Background Art

[0002] Information can be stored as a physical signal (e.g., charge on a capacitive element) on individual memory cells of a memory. During a read operation, the physical signal (e.g., charge) can be coupled to a conductive element to cause a voltage change. That voltage change can be amplified and read out to the input / output terminals of the device. A write operation can reverse the process, thereby receiving a signal at the terminals and providing a voltage to the memory cell (e.g., to charge a capacitor).

[0003] Since voltages can be applied to the terminals quickly, it can be important to prevent stray voltages from being reflected at the terminals where the memory interfaces with external devices. The memory can have multiple optional termination branches for impedance matching. Tuning the resistance of the termination resistor can be important. Summary of the Invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: a plurality of command address pins including a designated pin; an on-die termination (ODT) control circuit; and a termination circuit, wherein the ODT control circuit is configured to change the resistance of the termination circuit in response to a signal received along the designated pin when the apparatus is in a power-off state.

[0005] In another aspect, the present disclosure provides a system comprising: a first memory device including a first termination circuit; a second memory device including a second termination circuit; and a controller configured to perform a write operation on the first memory device and provide a non-target on-die termination (NT-ODT) adjustment command to the second memory device, wherein the second memory device is configured to change the resistance of the second termination circuit in response to the NT-ODT adjustment command when the second memory device is in a power-off state.

[0006] In yet another aspect, the present disclosure provides a method comprising: coupling a designated pin of a plurality of command address pins of a memory device to an on-die termination (ODT) control circuit when the memory device is in a power-off state; receiving a non-target ODT (NT-ODT) adjustment command along the designated pin when the device is in the power-off state; and changing a termination resistance of the memory device in response to the NT-ODS adjustment command. Brief Description of the Drawings

[0007] Figure 1It is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 It is a block diagram of a memory system according to some embodiments of the present disclosure.

[0009] Figure 3 It is a block diagram of a part of a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 It is a timing diagram of NT-ODT adjustment according to some embodiments of the present disclosure.

[0011] Figure 5 It is a timing diagram of NT-ODT adjustment according to some embodiments of the present disclosure.

[0012] Figure 6 It is a flowchart of a method for performing non-target die termination adjustment in a power-off state according to some embodiments of the present disclosure. Detailed Description

[0013] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings which form a part hereof and which show, by way of illustration, specific embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Additionally, for clarity purposes, when certain features will be apparent to those skilled in the art, detailed descriptions of such features will not be set forth so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the following detailed description should not be construed in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0014] Information in a memory device is stored in a memory array. The information is delivered as voltages along various internal signal lines. For example, a first voltage may represent a logic high, while a second voltage may represent a logic low. During access operations (such as read and write operations), signals may be passed to and from the device between the device's data terminals (DQ terminals) and a data bus (DQ bus) that couples the device to a controller. The memory includes input / output (IO) circuitry that couples internal signals to the DQ terminals and the DQ bus. The IO circuitry includes termination circuitry that includes one or more selectable resistor branches, each of which includes a tunable resistor. The resistor branches may be coupled in parallel, and a number of active resistor branches (e.g., a number of tunable resistors coupled in parallel) may determine the total impedance of the termination circuitry. This in turn ensures that the impedance along a line (e.g., the DQ bus) matches the impedance of the terminals (e.g., as set by the termination circuitry) to help ensure that there are no voltage reflections at the DQ terminals. This may be particularly important in a memory module where multiple memory devices may share the same DQ terminals.

[0015] During operation, a controller may direct commands to one or more 'target' memory devices on a module, while 'non-target' memories remain idle. A controller of a memory module may send commands to adjust the resistance of the termination circuitry of non-target memories. For example, the controller may send a command to a memory device that includes a first signal indicating that the termination resistance should change and a second signal indicating a burst length (e.g., the number of serial bits received at each data terminal during a read or write operation). The burst length information may be used to help manage the timing of the memory device. In some example memory devices, two different burst lengths (e.g., 16 bits and 32 bits) may be used. Thus, a conventional termination resistance command may require two pins, one for each signal.

[0016] To conserve power, certain non-target memory devices on a module may be placed in a powered-down state. When a device is in the powered-down state, it draws less power than when powered on. When in the powered-down state, the device may generally not respond to any commands (e.g., along a shared command / address bus of the module) other than a command that causes the powered-down device to exit the powered-down state. However, it may still be useful to be able to adjust the termination resistance value of non-target memories that are in the powered-down state without having to power up the memory again.

[0017] The present disclosure relates to a non-target die terminal in a power-off state. A non-target memory device may receive a command to change a terminal resistance when it is in the power-off state. For example, a single command pin may be designated, and when a signal (e.g., a voltage at an active level) is received along that command pin, the power-off memory device may change a resistance level in the terminal circuit without exiting the power-off state. The circuit of the memory device may receive the signal along the command pin and, when the device is in the power-off state, provide that signal as a non-target ODT (NT-ODT) adjustment command. In this way, the power-off device may enjoy the advantages of being in the power-off state (e.g., reduced power consumption) while still responding to commands that cause it to change the terminal resistance.

[0018] In some embodiments, the terminal circuit may change one step within a cycle of possible resistance values (e.g., low, medium, high, low, etc.) in response to an NT-ODT adjustment command when the device is in the power-off state. In some embodiments, the signal along the designated pin may cause the terminal circuit to switch between preselected values (e.g., a value when performing a read operation on a target memory and a value when performing a write operation on a target memory). The designated pin may use serial pulses of the signal for timing purposes instead of using two pins to determine a burst length. For example, a single pulse may indicate a change in a module using a first burst length (e.g., 16), and two pulses may indicate a change in a module using a second burst length (e.g., 32).

[0019] In an example embodiment, the memory device includes a multiplexer that couples the designated command pin to a command decoder when the device is powered on and couples the designated command pin to the terminal circuit when the device is powered off. In this way, the designated pin may be used as part of the normal command / address bus when the device is powered on and used for NT-ODT adjustment when the device is powered off.

[0020] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0021] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of banks. In Figure 1In an embodiment, the memory array 118 is shown as including eight banks BANK0 to BANK7. The memory array 118 in other embodiments may include more or fewer banks. For example, the memory may include 4, 16, 32, more or fewer banks. Each bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersection of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL is performed by the row decoder 108, and the selection of the bit lines BL and / BL is performed by the column decoder 110. In Figure 1 an embodiment, the row decoder 108 includes a corresponding row decoder for each bank, and the column decoder 110 includes a corresponding column decoder for each bank. The bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMP). The read data from the bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through complementary local data lines (LIOT / B), a transfer gate (TG), and complementary main data lines (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL or / BL.

[0022] The semiconductor device 100 may employ a plurality of external terminals, the external terminals including command and address (C / A) terminals coupled to a command and address bus to receive commands, addresses, and a CS signal, clock terminals for receiving clocks CK and / CK, data terminals DQ for providing data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may be coupled to a controller 140, and the controller 140 may operate the memory by providing various signals to the external terminals.

[0023] The controller 140 provides the external clocks CK and / CK to the clock terminals, and the external clocks CK and / CK are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the clocks CK and / CK. The clock ICLK is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the clock ICLK. The clock LCLK can be used to time the operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operations of the circuits included in the input / output circuit 122, for example, provided to a data receiver to time the reception of write data.

[0024] The controller 140 provides commands and memory addresses to the C / A terminals. There may be a command / address bus coupling the controller 140 to the C / A terminals of the memory device 100. For example, there may be a set of C / A terminals or pins each coupled to a conductive element of the C / A bus.

[0025] The memory addresses supplied to the C / A terminals are transmitted via the command / address input circuit 102 to the address decoder 104. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply the decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD.

[0026] The controller 140 may provide commands to the C / A terminals. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access commands may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the (s) memory cells to be accessed. The controller may send commands to place the device 100 in a power-off state and commands to wake up the device 100 and place it in a power-on state. As described in more detail herein, when the memory 100 is powered on or off, the controller 140 may also transmit NT-ODT adjustment commands. In some embodiments, when in the power-off state, the device 100 may respond only to NT-ODT adjustment commands and commands to power on the device.

[0027] When the device is powered on, control commands may be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line. The command decoder 106 also provides activation and precharge signals to different banks of the memory. The activation signal ACT may indicate which word lines in that bank should be activated, while the precharge signal Pre may indicate that the word lines should be precharged (e.g., turned off) in anticipation of the next activation command. In some embodiments, the ACT and Pre signals may share signal lines.

[0028] Device 100 may receive commands and addresses from controller 140 as part of an access operation (e.g., a read operation). As part of the access operation, a row address and a bank address are received together with an activate command. As part of the access operation, a column address and a bank address are received together with a read command. In response to the read operation, read data is read from the memory cells in memory array 118 corresponding to the row address and the column address. The command associated with the read operation is received by command decoder 106, and command decoder 106 provides internal commands such that the read data from memory array 118 is provided to read / write amplifier 120. In response to the activate command, row decoder 108 activates the word line associated with the row address. When the row is active, the memory cells along that row are coupled to sense amplifiers activated by column decoder 110 in response to the read command to read out data along the LIOT / B lines. The read data is output from data terminal DQ to the outside via input / output circuit 122. Command decoder 106 may then provide a precharge command, which may 'turn off' the active row.

[0029] Device 100 may receive commands and addresses from controller 140 as part of an access operation (e.g., a write operation). As part of the write operation, a row address and a bank address are received together with an activated command, and a column address and a bank address are received together with write data and a write command. In response to the write operation, the write data supplied to data terminal DQ is written to the memory cells in memory array 118 corresponding to the row address and the column address. The command associated with the write operation is received by command decoder 106, and command decoder 106 provides internal commands such that the write data is received by the data receiver in input / output circuit 122. In response to the activate command, row decoder 108 activates the word line associated with the row address. When the row is active, the memory cells along that row are coupled to sense amplifiers activated by column decoder 110 in response to the write command to receive the write data. A write clock may also be provided to an external clock terminal to time the reception of the write data by the data receiver in input / output circuit 122. The write data is supplied to read / write amplifier 120 via input / output circuit 122, and is supplied to memory array 118 through read / write amplifier 120 to be written to memory cell MC. Command decoder 106 may then provide a precharge command, which may 'turn off' the active row.

[0030] Device 100 may also perform a refresh operation. The refresh operation may be performed as part of an auto-refresh operation (where the controller 140 issues an auto-refresh command), or as part of a self-refresh operation (where the memory refreshes itself based on an internal command). The refresh control circuit 116 supplies a refresh row address RXADD to the row decoder 108, and the row decoder 108 may refresh one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, the refresh address RXADD may represent a single word line. In some embodiments, the refresh address RXADD may represent multiple word lines, which may be refreshed sequentially or simultaneously by the row decoder 108. In some embodiments, the number of word lines represented by the refresh address RXADD may vary with the refresh address. The refresh control circuit 116 may be controlled to vary details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or may operate based on internal logic.

[0031] The IO circuit 122 includes a termination circuit 123. The termination circuit 123 provides a calibrated impedance value to the DQ terminals, for example to match the impedance of the DQ terminals to the line impedance of the DQ bus between the DQ terminals and the controller 140. The termination circuit 123 includes a number of tunable resistors that may be selectively coupled to the DQ terminals to provide a selected impedance. The selected impedance may be a setting based on the nature of the controller and / or the DQ bus. For example, the termination circuit 123 includes a number of selectable resistor branches, each selectable resistor branch having a tunable resistor of NΩ. If X of the tunable branches are active, then the total value may be (N / X)Ω. For example, if a 240Ω resistor is used, then total values such as 60Ω (four active branches), 40Ω (six active branches), and 30Ω (seven active branches) may be selected. Other values of resistors and other numbers of branches may be used in other exemplary embodiments.

[0032] Each of the tunable resistors may be adjustable to ensure that the impedance can be matched to a nominal value (e.g., to ensure that each tunable resistor matches a value of 240Ω). The memory may access a reference resistor ZQ ( Figure 1 not shown in the figure) having a nominal value. The reference resistor ZQ may be a resistor manufactured with a very narrow tolerance (e.g., 5%, 1%, or 0.1%, etc.). As part of a calibration operation, the resistance of each of the tunable resistors of the termination circuit 123 is adjusted to match the resistance of the reference resistor ZQ.

[0033] There may be a situation where the controller 140 changes the impedance provided by the termination circuit 123. The controller 140 includes an NT-ODT control circuit 142, and the NT-ODT control circuit 142 can determine when to change the termination impedance of the memory 100. For example, the termination circuit 123 can generally be set to a value used when the controller executes a read command on some other memory device on the module. If the controller 140 is performing a write operation on another memory device, then the NT-ODT control circuit 142 can send a command to the memory 100 to change the termination impedance to a level suitable for the write operation for a period of time.

[0034] For example, when the device 100 is powered on, the NT-ODT control circuit 142 can send a two-bit command to two C / A pins. The first signal (e.g., the first bit) of the command can indicate that the termination impedance should change, and the second signal (e.g., the second bit) of the command can indicate how long the change should be effective (e.g., based on the burst length). When powered on, the command is passed to the command decoder 106, and the command decoder 106 can generate an internal signal indicating that the ODT control circuit 150 adjusts the termination impedance. For example, the ODT control circuit 150 can change the number of active branches of the variable resistor in the termination circuit 123.

[0035] When the device 100 is powered off, the command decoder is generally inactive. However, the NT-ODT control circuit 142 of the controller 140 can still send an NT-ODT adjustment command and the device 100 can still respond to the NT-ODT adjustment command without exiting the powered-off state. When the device 100 is in the power-off mode, the NT-ODT power-off logic circuit 152 can bypass the command decoder 106 and couple the C / A pins to the ODT control circuit 150. When the memory 100 is in the power-off mode, the NT-ODT control circuit 142 provides the NT-ODT adjustment command along a single designated C / A pin that bypasses the command decoder. A single C / A pin can be used to send both the first and second signals. For example, a single pulse along the designated pin can cause the ODT control circuit 150 to change the termination impedance within a first time period (e.g., a 16-bit burst length), while two pulses along the designated pin can cause the ODT control circuit 150 to change the termination impedance within a second time period (e.g., a 32-bit burst length).

[0036] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0037] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 such that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0038] Figure 2 is a block diagram of a memory system according to some embodiments of the present disclosure. Figure 2 An example shows an embodiment in which multiple memories are packaged together into a memory module 202. In this embodiment, the termination circuitry may be particularly important because some memory dies may share external DQ terminals. Thus, when accessing one (target) memory device coupled to a shared terminal, reflections at the terminal may cause signals to be improperly sent to another non-target memory coupled to that terminal. However, it should be understood that embodiments of the present disclosure may work both in standalone memories and in memories packaged together into modules.

[0039] The memory system 200 includes a module 202 and a controller 240. The memory module 202 includes several memory dies 212, 216, 232, and 236. In some embodiments, each of the memory dies 212, 216, 232, and 236 may be implemented by Figure 1 the memory device 100. The memory module 202 includes module logic 220 that manages access to the memory dies on the module 202. For example, the module logic 220 may include an input / output circuit 222 that may act as a buffer to provide signals between the terminals of the memory dies and the external terminals of the module 202. The external terminals of the module 202 interface with the controller 240. The module 202 also includes a reference resistor 204 used in calibration operations.

[0040] The memory module includes several memory dies organized into channels. Memory dies 212 and 216 are shown as part of the first channel 210, and memory dies 232 and 236 are shown as part of the second channel 230. Each channel may have several memory dies. For example, each channel may have 5 memory dies. In other example embodiments, more or fewer dies may be used per channel. Similarly, module 202 may have more or fewer channels. For example, Figure 2 Two channels 210 and 230 are shown, on either side of module logic 220. There may be additional channels (and additional memory dies) on the back side of the physical module chip, for a total of 4 channels. In other example embodiments, more or fewer than 4 channels may be used. Some channels may share the external DQ terminals of the module with each other and may be referred to as 'banks'.

[0041] Since the memory dies are generally similar, the operation of a single example memory die will be discussed only with respect to the operation of module 202. Module 202 is coupled to controller 240 along a set of terminals. Example command / address (CA) terminals are shown along with several sets of data input / output (DQ) terminals, although in other example embodiments there may be additional terminals and connections. During an example read operation, controller 240 provides a read command along with die identification information that specifies the channel (and / or individual die) to be accessed along with the row address, column address, and bank address to be accessed in the memory. Module logic 220 routes the C / A signal to the memory die, and the specified die (die 0 212 in this example) responds. The specified die reads data from the specified row, bank, and column, and provides that data along internal signal lines to module IO circuit 222 via IO circuit 215 (e.g., Figure 1 122) which routes the data to the external data terminals.

[0042] Each die on module 202 is associated with a set of external DQ terminals. The external DQ terminals may be shared by multiple dies. For example, memory die 0 212 has 16 DQ terminals, each of which corresponds to one of the 16 external die 0 DQ terminals on the module. Those 16 external die 0 DQ terminals may also be used by another die (e.g., located on the back side of module 202) that is part of a different channel. When sharing external DQ terminals, one of the dies sharing the DQ terminals may be the target die for a given operation, while the other dies are non-target dies. In other example embodiments, other arrangements of DQ terminal sharing may be used.

[0043] During operation, the controller may calibrate one or more of the memory dies (e.g., by sending commands to the target die and sending / receiving data to / from the target die), while other dies may not be calibrated. Some non-target dies may be powered on or in a powered-up state, while other dies may be powered off. The powered-off dies may operate in a low-power mode where certain components (e.g., command decoder, row and column decoders) do not receive power (or receive minimal power) and do not perform normal operations until the device is placed back in the powered-up state. When in the powered-off state, the memory devices (212, 216, 232, and / or 236) may typically only respond to a power-on command or an NT-ODT adjustment command.

[0044] The controller 240 may send an NT-ODT adjustment command to change the termination resistance in the IO circuit of the non-target memory device (e.g., how many resistor branches are active). For explanatory purposes, an access operation will be discussed where die M 232 is the target die and die 0 212 is the non-target die. The NT-ODT control circuit of the controller 240 (e.g., Figure 1 of 150) may send an NT-ODT adjustment command to the non-target memory die 212 via the CA bus. For example, the NT-ODT command may be sent along with information identifying die 0 as the non-target die to be adjusted. In response to the NT-ODT adjustment command, the non-target memory die 212 may change the termination circuit (e.g., Figure 1 of 123) in the IO circuit 215. For example, the number of tunable resistors coupled to the DQ terminals may change.

[0045] The controller 240 may monitor whether the non-target die 212 is powered on or off. If the non-target die 212 is powered on, then a first type of NT-ODT adjustment command may be sent. If the non-target die 212 is powered off, then a second type of NT-ODT adjustment command may be sent. The first type of NT-ODT adjustment command may be sent along a first number of CA terminals, while the second type of NT-ODT adjustment command may be sent along a second number of CA terminals that is less than the first number. For example, when the non-target device is powered on, the NT-ODT adjustment command may be sent along two lines of the CA bus (e.g., two parallel signals), and when the non-target device is powered off, the NT-ODT adjustment command may be sent along a single line of the CA bus. When the device is powered off, a specific designated CA pin or several specific designated CA pins may be used.

[0046] Each memory die (e.g., non-target die 212) includes power-down logic circuitry (e.g., Figure 1152). If the device is powered on, the power-off logic circuit 213 can route all signals along the CA pin to the command decoder 214, and the command decoder 214 can generate one or more internal signals to cause an adjustment to the termination resistor / impedance. If the device is powered off, the power-off logic circuit 213 can route signals from one or more designated CA pins to bypass the command decoder and directly reach the ODT control circuit (e.g., shown as part of the IO circuit 215 in Figure 2 150). Figure 1

[0047] In an example application, the controller 240 can send an NT-ODT adjustment command as part of performing a write operation on the target die 232. For example, the termination impedance value in the IO circuit 215 can typically be set based on the value for performing a read operation on the target memory die. However, a different impedance can be used for the write operation on the target die. Thus, when performing a write operation on the target die 232, an NT-ODT adjustment command can be sent to the non-target die 212, the NT-ODT adjustment command indicating that an adjustment should be performed and also indicating how long the adjustment should be made (e.g., by indicating the burst length of the write command).

[0048] The controller 240 provides a write command along with information identifying the target die 232 along the CA bus. The controller 240 starts transmitting data along the DQ terminals associated with the target die. The NT-ODT control circuit 242 of the controller 240 also sends an NT-ODT adjustment command along with information identifying the non-target die 212 along the CA bus. If the die 212 is powered on, the NT-ODT control circuit provides two signals along multiple lines of the CA bus, one signal identifying that an ODT adjustment should be performed and one signal indicating the burst length. In this example application, two binary signals can be used, one signal identifying that the termination impedance should change from a preset read value to a preset write value and one signal indicating whether the burst length being used is 16 or 32.

[0049] If the die 212 is powered off, the NT-ODT control circuit 242 can send a single signal along fewer CA pins. In this example, the NT-ODT control circuit 242 can use a single CA pin carrying a binary signal indicating a change in the termination impedance (e.g., from a read value to a write value) over a set period of time. The period of time can correspond to the burst length 16, and if the burst length 32 is used, the NT-ODT circuit 242 can send the signal twice so that the change is maintained for twice as long (e.g., burst length of 32).

[0050] ​In a subsequent operation, if the controller 240 performs an access operation (e.g., a write operation) on the memory 212, then the memory 212 may become the target die. When the memory 212 is the target die, the controller 240 may issue an NT-ODT adjustment command to one or more non-target memory devices (e.g., device 232). The device 232 may be powered off and may operate in a manner similar to that described when the device 212 is a non-target device.

[0051] Figure 3 is a block diagram of a portion of a memory device in accordance with some embodiments of the present disclosure. In some embodiments, the memory device 300 may implement Figure 1 a portion of the memory device 100 of Figure 2 and / or Figure 3 any one of the memory devices 212, 216, 232, and / or 236 of Figures 1 to 2 The memory device 300 shows a memory device in a powered-off state, where components that are inactive in the powered-off state are represented by dashed boxes and components that remain active in the powered-off state are represented by solid boxes. Similarly, dashed lines represent signal paths that are inactive in the powered-off state, while solid lines are active signal paths. For the sake of brevity, some components, signals, and operations that have been described in detail with respect to

[0052] The memory device 300 includes a memory array 304 (e.g., Figure 1 118 of Figure 1 ), along with sense amplifiers 306 and associated row and column decoders 330 and 332 (e.g., Figure 1 108 and 110 of Figure 1 ). The memory 300 also includes a command decoder 320 (e.g., Figure 1 106 of Figure 1 114 of Figure 1 and / or Figure 2 213, 217, 233, and / or 237 of Figure 3In an example embodiment, the NT-ODT power-down logic circuit 316 is implemented by a multiplexer circuit.

[0053] The command bus carries N + 1 signals designated as command 0 to command N, and each of the signals is received at a corresponding pin of the memory device. The command decoder 320 receives signals from all pins except one pin (e.g., command 1 to command N). The designated pin (here the first pin command 0) is instead provided to the NT-ODT power-down logic circuit 316. The NT-ODT power-down logic circuit receives the signal command 0 and routes it to the command decoder 320 or directly to the ODT control circuit 314 based on the power-down state. The power-down state may be indicated by a power-down state signal, which may be provided by the power-down control circuit 312. When the power-down state indicates that the device is powered on, the signal command 0 is provided to the command decoder 320 together with the remaining command signals. When the power-down state indicates that the device is powered off, the signal command 0 is provided to the ODT control circuit 314.

[0054] The clock generator 302 receives an external clock signal CK_t / c (e.g., Figure 1 CK and / CK of

[0055] and provides one or more internal clocks to the control logic 310. The chip select signal CS is also provided to the control logic 310. The CS signal may indicate that the memory device 300 has been selected by the controller to receive a command. For example, even if the device is a non-target device, the CS signal may still be used to indicate that the NT-ODT adjustment command is intended for the device 300. The ODT control circuit 314 may use the clock signal CK_t / c to manage the timing of various operations.

[0056] Figure 4 is a timing diagram of NT-ODT adjustment according to some embodiments of the present disclosure. In some embodiments, the timing diagram 400 may represent the operation of one or more devices and systems described herein. For example, the timing diagram may represent the operation of a target memory device and a non-target memory device (e.g., any one of which may be byFigure 2 memory devices 100, 212, 216, 232 and / or 236, and / or Figure 3 memory device 300 is implemented). Figure 4 Embodiments using a 16-bit burst length are shown.

[0057] Timing diagram 400 shows operations in a target memory device on which a controller is performing a write operation and operations in non-target memory devices in the same memory module. The target memory device may be the first bank (labeled bank 0 here) and the second bank (labeled bank 1 here) of the memory module, for example Figure 2 channels 210 and 230. The two banks may share DQ terminals with each other.

[0058] Timing diagram 400 shows complementary clock signals CK_t and CK_c, chip select and command bus (e.g., CA bus) signals for the two banks, information along the DQ bus, and representations of termination values for the two banks.

[0059] At an initial time t0, the controller issues a write command to the target memory by sending a chip select signal CS to bank 1 and sending a write command along the CA bus to the target bank. At t0, the controller also sends a CS signal to non-target bank 1 and sends an NT-ODT adjustment signal along the CA bus to that bank. For example, the signal may be sent along a designated pin (e.g., Figure 3 command 0). At the initial time, since neither bank is banked, the termination circuits in both banks may default to the NT-ODT_R or NT-ODT read value.

[0060] At a first time t1, in response to the write command and the NT-ODT adjustment command, the two banks may begin to transition their respective termination impedance values. At time t2, the termination circuit of bank 0 reaches the target ODT value, which is based on bank 0 being the target bank. At the same time, the termination circuit of bank 1 reaches the value NT-ODT_W or NT-ODT write value. The values NT-ODT_R, NT-ODT_W, and the target ODT may be settings of the memory and may be based on a training process. They may be the same as or different from each other. Times t1 and t2 may be separated by the ODT activation time tODTon. At time t3, the data terminals of the target bank may begin to receive data. In Figure 4 an example, 16 serial bits are received as part of the burst length. The time from the end of receiving the write command (and the NT-ODT adjustment command) to time t1 may be the ODT activation delay period ODTLon. The time between receiving the write command (after t0) and the start of the burst length is the write latency time WL.

[0061] At time t4 after the burst length has ended, the ODT values in the two banks can start to change again. During the ODT deactivation period tODToff, the respective banks change. After time tODToff, at time t5, the two banks have returned to the default value (NT-ODT_R). The time between receiving the write and NT-ODT adjustment commands and the second transition period (e.g., the end of adjusting the ODT value) can be the ODT deactivation delay time ODTLoff. The difference between the time ODTLoff and ODTLon plus tODTon can represent the time length for adjusting the ODT value in response to the write command and the NT-ODT adjustment command.

[0062] Figure 5 is a timing diagram of NT-ODT adjustment according to some embodiments of the present disclosure. In some embodiments, the timing diagram 500 can represent the operation of one or more devices and systems described herein. For example, the timing diagram can represent the operation of a target memory device and a non-target memory device (e.g., any one of which can be implemented by Figure 2 memory devices 100, 212, 216, 232, and / or 236, and / or Figure 3 memory device 300). Figure 5 The timing diagram 500 shows an embodiment in which a burst length of 32 is used. Since the timing diagram 500 is generally similar to Figure 4 the timing diagram 400, the details already explained with respect to Figure 5 the timing diagram 400 will not be repeated.

[0063] Similar to the timing diagram 400, at the initial time t0 in the timing diagram 500, the controller issues a write command to bank 0 and an NT-ODT adjustment command to bank 1. However, since this is an embodiment with a burst length of 32, at time t1, the controller issues a second NT-ODT adjustment command to bank 1. Thus, at t2, the two banks start to change (in response to the write command and the first NT-ODT adjustment command) and at t3, the two ODT circuits reach their adjusted values (target ODT and NT-ODT_W respectively). At time t4, the burst length of 16 is reached. However, in response to the second NT-ODT adjustment command received at time t1, a second period of NT-ODT adjustment can start. At time t5, after the 32-bit burst length ends, the two banks can start to change back to their default values (NT-ODT_R).

[0064] Figure 6 is a flowchart of a method for performing non-target die termination adjustment in a power-off state according to some embodiments of the present disclosure. In some embodiments, the method 600 can be performed by any device or system described herein (e.g., Figure 1 and 3memory device 100 and / or 300, and / or Figure 2 memory module 202) is executed.

[0065] Method 600 generally may begin at block 610, which describes coupling a designated pin among a plurality of command address pins of the memory device to an ODT control circuit when the memory device is in a power-off state. For example, when the memory is in a power-off mode, one of the CA pins (e.g., Figure 3 command 0) may be coupled to an NT-ODT power-off logic circuit that bypasses a command decoder (e.g., Figure 1 152 of Figure 2 213 of Figure 3 316 of ). When the device is in a power-on mode, method 600 may include coupling the designated pin to a command decoder. Method 600 may include receiving an NT-ODT adjustment command along a plurality of the command address pins when the memory is in a powered-on state.

[0066] After block 610 generally may be block 620, which describes receiving an NT-ODT adjustment command along the designated pin when the device is in a power-off state. For example, when a controller is performing an access operation on another memory device that is part of a different memory bank of a module (e.g., Figure 2 202), an NT-ODT adjustment command may be received from the controller.

[0067] After block 620 generally may be block 630, which describes changing a termination resistance of the memory device in response to the NT-ODT adjustment command. Method 600 may include changing the termination resistance within a set amount of time corresponding to a first burst length. Method 600 may include receiving two NT-ODT adjustment commands and changing the termination resistance within a different set amount of time corresponding to a second burst length (e.g., as Figure 5 shown). Method 600 may include changing the termination resistance from an NT-ODT read value to an NT-ODT write value. Method 600 may include changing the termination resistance while the device remains in a power-off mode.

[0068] As used herein, activation of a signal may refer to any portion of a signal waveform to which a circuit responds. For example, if a circuit responds to a rising edge, then an activatable signal switches from a low level to a high level. One example type of activation is a pulse, where the signal switches from a low level to a high level within a certain time period and then returns to the low level. This may trigger a circuit that responds to a rising edge, a falling edge, and / or a signal at a high logic level. Those skilled in the art will understand that although embodiments may be described with respect to a particular type of activation (e.g., high-level active) used by a particular circuit, other embodiments may use other types of activation (e.g., low-level active).

[0069] Of course, it should be understood that any example, embodiment, or process described herein can be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in a separate device or device part according to the present system, apparatus, and method.

[0070] Finally, the foregoing discussion is intended to merely illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments may be devised by those of ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense and not as limiting the scope of the appended claims.

Claims

1. An apparatus, comprising: A plurality of command address pins, including a designated pin; On-die termination ODT control circuitry; And Termination circuitry, wherein the ODT control circuitry is configured to change a resistance of the termination circuitry in response to a signal received along the designated pin when the apparatus is in a power-off state.

2. The apparatus according to claim 1, further comprising: A command decoder; And Non-target ODT NT-ODT power-off logic circuitry configured to couple the designated pin to the ODT control circuitry when the apparatus is in the power-off state and to couple the designated pin to the command decoder when the apparatus is in a power-on state.

3. The apparatus according to claim 2, wherein the command decoder is configured to receive an NT-ODT command along a plurality of the plurality of command address pins when the apparatus is in the power-on state, and wherein in response to the NT-ODT command received by the command decoder, the ODT control circuitry is configured to change the resistance of the termination circuitry.

4. The apparatus according to claim 1, wherein the signal is a binary signal, and wherein in response to the signal, the ODT control circuitry is configured to change the resistance of the termination circuitry from a first value to a second value.

5. The apparatus according to claim 4, wherein the first value is an NT-ODT read value and the second value is an NT-ODT write value.

6. The apparatus according to claim 4, wherein in response to the signal, the ODT control circuitry is configured to change the resistance of the termination circuitry within a set time period.

7. The apparatus according to claim 2, wherein the command decoder is configured to receive a signal along a plurality of the CA pins when in the power-on state.

8. A system, comprising: A first memory device including a first termination circuit; A second memory device including a second termination circuit; And A controller configured to perform a write operation on the first memory device and provide a non-target on-die termination NT-ODT adjustment command to the second memory device, wherein the second memory device is configured to change a resistance of the second termination circuit in response to the NT-ODT adjustment command when the second memory device is in a power-off state.

9. The system according to claim 8, wherein the second memory device includes: A command decoder; On-die termination ODT control circuitry; NT-ODT power-off logic circuitry configured to couple a designated pin of a plurality of command address pins to the on-die termination ODT control circuitry when the device is in the power-off state, wherein the ODT control circuitry is configured to change the resistance of the second termination circuit along the designated pin in response to the command.

10. The system according to claim 9, wherein the controller is configured to provide the NT-ODT adjustment command to the second memory device along the designated pin when the second memory device is in the power-off state or along multiple ones of the command address pins when the second memory device is in the power-on state.

11. The system according to claim 8, wherein the first termination circuit is configured to change from a value read from a corresponding NT-ODT to a target ODT value in response to the write operation, and wherein the second termination circuit is configured to change from a value read from a corresponding NT-ODT to an NT-ODT write value in response to the NT-ODT adjustment command.

12. The system according to claim 8, wherein the controller is configured to provide data of a burst length to the first memory device as part of the write operation, wherein the controller is further configured to provide one NT-ODT adjustment command having a first value for the burst length and two NT-ODT adjustment commands having a second value for the burst length.

13. The system according to claim 8, wherein the controller is configured to perform a second write operation on the second memory device and provide a second NT-ODT adjustment command to the first memory device, wherein the first memory device is configured to change the resistance of the first termination circuit in response to the second NT-ODT adjustment command when the first memory device is in the power-off state.

14. The system according to claim 8, wherein the first memory device and the second memory device are in different ranks of a memory module.

15. A method, comprising: coupling a designated pin among a plurality of command address pins of a memory device to an on-die termination ODT control circuit when the memory device is in a power-off state; receiving a non-target ODT NT-ODT adjustment command along the designated pin when the memory device is in the power-off state; and changing a termination resistance of the memory device in response to the NT-ODT adjustment command.

16. The method according to claim 15, further comprising changing the termination resistance within a set amount of time corresponding to a first burst length.

17. The method according to claim 16, further comprising: receiving two NT-ODT adjustment commands and changing the termination resistance within a different set amount of time corresponding to a second burst length.

18. The method according to claim 15, further comprising coupling the designated pin to a command decoder of the memory device when the memory device is in a powered-on state.

19. The method according to claim 18, further comprising receiving the NT-ODT adjustment command along multiple ones of the plurality of command address pins when the memory device is in the powered-on state.

20. The method according to claim 15, further comprising changing the termination resistance from an NT-ODT read value to an NT-ODT write value.

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