Memory device and operating method thereof

Abstract

The invention provides a memory device and an operating method thereof. The memory includes a first memory cell to store a first data bit. The first memory cell includes a channel structure, a source structure, a drain structure, and a charge trap layer. When the first data bit has a first logic value and the voltage signal applied to the charge trap layer has a first voltage level, the current signal flowing through the channel structure has a first current level. When the first data bit has a first logic value and the voltage signal has a second voltage level, the current signal has a second current level. When the first data bit has a second logic value and the voltage signal has a first voltage level, the current signal has a second current level. The current signal has a first current level when the first data bit has a second logic value and the voltage signal has a second voltage level.

Description

Technical Field

[0001] The present disclosure relates to a memory technology, and more particularly to a memory device and an operation method thereof. Background Art

[0002] Memory devices can perform database searches, in-memory data processing, and neuromorphic computing through ternary content addressable memory (TCAM). However, in the architecture of static random-access memory (SRAM), multiple transistors are required to form a single TCAM cell. As a result, the required area is large and the power consumption is high. Therefore, how to design to solve the above problems is an important topic in this field. Summary of the Invention

[0003] Embodiments of the present disclosure include a memory device. The memory device includes a first memory cell for storing a first data bit. The first memory cell includes a channel structure, a source structure, a drain structure, and a charge trap layer. The source structure contacts a first side of the channel structure. The drain structure contacts a second side of the channel structure. The charge trap layer contacts a third side of the channel structure. When the first data bit has a first logic value and the voltage signal applied to the charge trap layer has a first voltage level, the current signal flowing through the channel structure has a first current level. When the first data bit has a first logic value and the voltage signal has a second voltage level different from the first voltage level, the current signal has a second current level different from the first current level. When the first data bit has a second logic value different from the first logic value and the voltage signal has the first voltage level, the current signal has the second current level. When the first data bit has the second logic value and the voltage signal has the second voltage level, the current signal has the first current level.

[0004] In some embodiments, the memory device further includes an upper electrode. The upper electrode is used to apply a voltage signal to the charge trap layer. In a first direction, the charge trap layer is located between the upper electrode and the channel structure.

[0005] In some embodiments, in a second direction perpendicular to the first direction, the first side and the second side are opposite to each other.

[0006] In some embodiments, when the channel structure has a first device length, in response to the voltage signal having a first search voltage level, the current level of the current signal is greater than a mismatch current level; when the channel structure has a second device length, in response to the voltage signal having the first search voltage level, the current level of the current signal is less than a match current level, the first device length is less than the second device length, and the match current level is less than the mismatch current level.

[0007] In some embodiments, when the channel structure has a first device length, in response to the voltage signal having a second search voltage level, the current level of the current signal is equal to the match current level; and when the channel structure has a second device length, in response to the voltage signal having the second search voltage level, the current level of the current signal is less than the match current level.

[0008] In some embodiments, when the channel structure has a first device length, in response to the voltage signal having a third search voltage level, the current level of the current signal is greater than the mismatch current level; and when the channel structure has a second device length, in response to the voltage signal having the third search voltage level, the current level of the current signal is equal to the mismatch current level.

[0009] In some embodiments, when a drain bias signal applied to the drain structure has a first drain bias voltage level, in response to the voltage signal having a first search voltage level, the current level of the current signal is greater than a mismatch current level; when the drain bias signal has a second drain bias voltage level, in response to the voltage signal having the first search voltage level, the current level of the current signal is less than a match current level, the first drain bias level is greater than the drain bias level, and the match current level is less than the mismatch current level.

[0010] In some embodiments, when the drain bias signal has a first drain bias voltage level, in response to the voltage signal having a second search voltage level, the current level of the current signal is equal to the match current level; and when the drain bias signal has a second drain bias voltage level, in response to the voltage signal having the second search voltage level, the current level of the current signal is less than the match current level.

[0011] In some embodiments, when the drain bias signal has a first drain bias voltage level, in response to the voltage signal having a third search voltage level, the current level of the current signal is greater than the mismatch current level; and when the drain bias signal has a second drain bias voltage level, in response to the voltage signal having the third search voltage level, the current level of the current signal is equal to the mismatch current level.

[0012] An embodiment of the present disclosure includes a method of operating a memory device. The method of operation includes: storing first data in a first memory cell; applying a first voltage signal carrying a first search bit to the first memory cell; comparing a first data bit and the first search bit to generate a current signal flowing through the first memory cell, wherein when each of the first data bit and the first search bit has a first logical value, the current signal has a first current level, when the first data bit has the first logical value and the first search bit has a second logical value, the current signal has a second current level greater than the first current level, when the first data bit has the first logical value and the first search bit has a third logical value, the current signal has the second current level, and a difference between the first logical value and the second logical value is equal to a difference between the third logical value and the first logical value.

[0013] In some embodiments, when the first data bit has the second logical value and the first search bit has the second logical value, the current signal has the first current level.

[0014] In some embodiments, when the first data bit has the third logical value and the first search bit has the third logical value, the current signal has the first current level.

[0015] In some embodiments, when the first data bit has the second logical value and the first search bit has the third logical value, the current signal has a third current level greater than the second current level.

[0016] In some embodiments, when the first data bit has the third logical value and the first search bit has the second logical value, the current signal has the third current level.

[0017] In some embodiments, when the first data bit has a fourth logical value and the first search bit has the second logical value, the current signal has a fourth current level greater than the third current level, and the fourth logical value is greater than the third logical value.

[0018] In some embodiments, when the first data bit has the second logical value and the first search bit has the fourth logical value, the current signal has the fourth current level.

[0019] In some embodiments, when the first data bit has the fourth logical value and the first search bit has the fourth logical value, the current signal has the first current level.

[0020] An operation method of a memory device according to an embodiment of the present disclosure. The operation method includes: setting a first threshold voltage of a first memory cell to store first data in the first memory cell; applying a first voltage signal carrying a first search bit to the first memory cell; generating a current signal based on the first search bit and the first threshold voltage, wherein when the first threshold voltage has a first threshold voltage level, the first data bit has a first logical value, when the first threshold voltage has a second threshold voltage level, the first data bit has a second logical value different from the first logical value, when each of the first data bit and the first search bit has the first logical value, the current signal has a first current level, when the first data bit has the second logical value and the first search bit has the first logical value, the current signal has a second current level greater than the first current level, and when the first threshold voltage has a third threshold voltage level between the first threshold voltage level and the second threshold voltage level, the current signal has the first current level.

[0021] In some embodiments, when each of the first data bit and the first search bit has the second logical value, the current signal has the first current level.

[0022] In some embodiments, when the first data bit has the first logical value and the first search bit has the second logical value, the current signal has the second current level. Description of the Drawings

[0023] Figure 1 A schematic diagram of a part of a memory device illustrated according to some embodiments of the present disclosure.

[0024] Figure 2A A relationship diagram of a current signal and a voltage signal illustrated according to some embodiments of the present disclosure.

[0025] Figure 2B A schematic diagram of various scenarios of a search operation performed on a memory cell illustrated according to some embodiments of the present disclosure.

[0026] Figure 3A A relationship diagram of a current signal and a voltage signal illustrated according to some embodiments of the present disclosure.

[0027] Figure 3B A schematic diagram of various scenarios of a search operation performed on a memory cell illustrated according to some embodiments of the present disclosure.

[0028] Figure 4A A relationship diagram of a current signal and a voltage signal illustrated according to some embodiments of the present disclosure.

[0029] Figure 4B A schematic diagram of various scenarios of a search operation performed on a memory cell illustrated according to some embodiments of the present disclosure.

[0030] Figure 5A A diagram showing the relationship between current signals and voltage signals according to some embodiments of the present disclosure.

[0031] Figure 5B A schematic diagram showing various scenarios of a search operation for a memory cell according to some embodiments of the present disclosure.

[0032] Figure 6 A diagram showing the relationship between current signals and voltage signals according to some embodiments of the present disclosure.

[0033] Figure 7A A diagram showing the relationship between current signals and voltage signals according to some embodiments of the present disclosure.

[0034] Figure 7B Corresponding to according to some embodiments of the present disclosure Figure 7A energy band schematic diagram of the memory device.

[0035] Figure 8 A schematic diagram of a memory system according to some embodiments of the present disclosure.

[0036] Description of reference numerals

[0037] 100: Memory device

[0038] 110: Memory cell

[0039] 111: Source structure

[0040] 112: Drain structure

[0041] 113: Channel structure

[0042] 114: Charge trap layer

[0043] 115: Upper electrode

[0044] 116: Current signal

[0045] VG: Voltage signal

[0046] 200A, 300A, 400A, 500A, 600, 700: Diagrams

[0047] CV21~CV22, CV31~CV33, CV41~CV44, CV51~CV58, CV61, CV62, CV71, CV72, SCV1~SCV3, LCV1~LCV3: Curves

[0048] LVSL, HVSL: Voltage levels

[0049] IL21, IL22, IL31, IL32, IL1 - IL8, IL61, IL62, IL71, IL72: Current level

[0050] LVT, HVT, MVT, VT1 - VT8: Threshold voltage level

[0051] VSEARCH1 - VSEARCH3: Search voltage level

[0052] AP6, AP7: Analog point

[0053] AR6, AR7: Analog range

[0054] 700B: Energy band schematic diagram

[0055] 800: Memory system

[0056] 810: Search encoder

[0057] 820: Memory array

[0058] 830: Page buffer

[0059] 840: Combining and sorting device

[0060] SW1: Search character

[0061] WL1, WL2, WLn: Word line signal

[0062] CL1, CL2, CLm: Memory row

[0063] DW1, DW2, DWm: Data character

[0064] I1, I2, Im: Current signal

[0065] T1_1, T2_1, T1_n, T2_n, Tm_n: Transistor Detailed implementation manners

[0066] In this article, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this article to describe different elements, these terms are only used to distinguish elements or operations described by the same technical terms. Unless the context clearly indicates, these terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present disclosure.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0068] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence and / or components of the stated features, regions, wholes, steps, operations, elements, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or combinations thereof.

[0069] Multiple embodiments of the present disclosure will be provided below with reference to the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not used to limit the present disclosure. That is, in some embodiments of the present disclosure content, these practical details are not necessary. In addition, for the sake of simplifying the drawings, the structures and elements of some prior art will be illustrated in a simple schematic manner in the drawings.

[0070] Figure 1 A schematic diagram of a part of a memory device 100 illustrated according to some embodiments of the present disclosure. The memory device 100 includes memory cells 110. In various embodiments, the memory device 100 may include various numbers of memory cells.

[0071] As Figure 1 shown, the memory cell 110 includes a source structure 111, a drain structure 112, a channel structure 113, a charge trap layer 114, and a top electrode 115. In the horizontal direction, the source structure 111 contacts one side of the channel structure 113, and the drain structure 112 contacts the other side of the channel structure 113. In the vertical direction, the charge trap layer 114 is located above the channel structure 113 and contacts the channel structure 113, and the top electrode 115 is located above the charge trap layer 114 and contacts the charge trap layer 114. In some embodiments, in the horizontal direction, the length of the charge trap layer 114 is approximately equal to the length of the channel structure 113.

[0072] In some embodiments, the source structure 111 may be formed of a P-rich material. The drain structure 112 may be formed of an N-rich material. The channel structure 113 may be formed of intrinsic silicon, intrinsic polysilicon, or other intrinsic channel materials. The charge trap layer 114 may be formed of a nitride (such as oxide-nitride-oxide (ONO)) or other charge trap materials (such as a ferroelectric layer). The upper electrode 115 may be formed of a conductor (such as a metal). In some embodiments, the memory cell 110 may be implemented by a bipolar silicon-oxide-nitride-oxide-silicon (SONOS) channel tunneling field effect transistor (TEFT).

[0073] In some embodiments, the charge trap layer 114 can store charges. In response to different amounts of charge in the charge trap layer 114, the memory cell 110 has different threshold voltage levels. Through the different threshold voltage levels, the memory cell 110 can correspond to different logical values of the data bit DT1. In other words, the memory cell 110 stores the logical value of the data bit DT1 by the charge trap layer 114.

[0074] In some embodiments, the upper electrode 115 is used to receive a voltage signal VG and apply the voltage signal VG to the charge trap layer 114. The voltage signal VG may carry a search bit SB1. During a search operation, the memory cell 110 generates a current signal 116 flowing through the memory cell 110 according to the voltage signal VG and the threshold voltage level of the memory cell 110. In other words, the current level of the current signal 116 corresponds to the matching result of the search bit SB1 and the data bit DT1. In some embodiments, the current signal 116 is referred to as a matching current signal.

[0075] In some approaches, the memory device performs database search, in-memory data processing, and neuromorphic-like operations through a Ternary Content Addressable Memory (TCAM). However, in the architecture of a Static Random-Access Memory (SRAM), multiple transistors are required to form a single TCAM cell. As a result, the required area is large and the power consumption is high.

[0076] Compared with the above approach, in the embodiments of the present disclosure, the memory cell 110 is implemented by SONOS TFET for in-memory computing, such that one TFET is used to form the memory cell 110. Correspondingly, the area efficiency is improved and the energy consumption is lower.

[0077] Figure 2A FIG. 200A is a graph showing the relationship between the current signal 116 and the voltage signal VG according to some embodiments of the present disclosure. The horizontal axis of the graph 200A represents the voltage level of the voltage signal VG. The vertical axis of the graph 200A represents the current level of the current signal 116 and is represented in a logarithmic scale.

[0078] As Figure 2A shown, the graph 200A includes curves CV21 to CV22. The curves CV21 to CV22 represent two states of the memory cell 110 corresponding to the current signal 116. In the state corresponding to the curve CV21, the data bit DT1 stored in the memory cell 110 has a logical value of 0. In the state corresponding to the curve CV22, the data bit DT1 stored in the memory cell 110 has a logical value of 1.

[0079] In some embodiments, when the search bit SB1 has a logical value of 0, the voltage signal VG has a voltage level LVSL. Correspondingly, the curves CV21 and CV22 have current levels IL21 and IL22 respectively. When the search bit SB1 has a logical value of 1, the voltage signal VG has a voltage level HVSL. Correspondingly, the curves CV21 and CV22 have current levels IL22 and IL21 respectively. In some embodiments, the current level IL22 is greater than the current level IL21.

[0080] Figure 2B FIG. is a schematic diagram showing various scenarios of the memory cell 110 performing a search operation according to some embodiments of the present disclosure. During the search operation, the memory cell 110 can compare the logical value of the stored data bit DT1 and the logical value of the search bit SB1 carried by the voltage signal VG to generate a corresponding current signal 116. As Figure 2B shown, the memory cell 110 can operate in four scenarios. The four scenarios are arranged in two rows and two columns.

[0081] In the scenarios of the first row, the search bit SB1 has a logical value of 0, such that the voltage signal VG has a voltage level LVSL. In the scenarios of the second row, the search bit SB1 has a logical value of 1, such that the voltage signal VG has a voltage level HVSL.

[0082] In some embodiments, data bit DT1 can be stored in memory cell 110 by setting the threshold voltage of memory cell 110. In the context of the first column, data bit DT1 has a logic value of 0, such that memory cell 110 has a threshold voltage level LVT. In the context of the second column, data bit DT1 has a logic value of 1, such that memory cell 110 has a threshold voltage level HVT. In some embodiments, the threshold voltage level HVT is greater than the threshold voltage level LVT.

[0083] In some embodiments, the amount of charge in charge trap layer 114 is proportional to the threshold voltage level of memory cell 110. In other words, for charge trap layer 114, the amount of charge in the context of the first column is less than the amount of charge in the context of the second column.

[0084] As Figure 2B shown, in the context of the first row and the second column and the context of the second row and the first column, in response to the different logic values of data bit DT1 and search bit SB1, current signal 116 has a current level IL21. In the context of the first row and the first column and the second row and the second column, in response to the same logic values of data bit DT1 and search bit SB1, current signal 116 has a current level IL22. In some embodiments, the operation of memory cell 110 corresponds to the XNOR logic function.

[0085] Figure 3A FIG. 300A is a relationship diagram of current signal 116 and voltage signal VG according to some embodiments of the present disclosure. The horizontal axis of relationship diagram 300A represents the voltage level of voltage signal VG. The vertical axis of relationship diagram 300A represents the current level of current signal 116 and is represented in a logarithmic scale.

[0086] As Figure 3A shown, relationship diagram 300A includes curves CV31 to CV33. Curves CV31 to CV33 represent three states of memory cell 110 corresponding to current signal 116. In the state corresponding to curve CV31, the data bit DT1 stored in memory cell 110 has a logic value of 0. In the state corresponding to curve CV32, the data bit DT1 stored in memory cell 110 has a logic value of X. In the state corresponding to curve CV33, the data bit DT1 stored in memory cell 110 has a logic value of 1.

[0087] In some embodiments, the logic value X represents a don't care logic value. The logic value X can correspond to either logic value 0 or logic value 1 in a search operation.

[0088] As Figure 3AAs shown, when the voltage signal VG has a voltage level LVSL, each of the curves CV31 and CV32 has a current level IL31, and the curve CV33 has a current level IL32. When the voltage signal VG has a voltage level HVSL, each of the curves CV33 and CV32 has a current level IL31, and the curve CV31 has a current level IL32. In some embodiments, the current level IL32 is greater than the current level IL31. In some embodiments, the voltage levels LVSL and HVSL are 1.4 volts and 1.9 volts, respectively.

[0089] Figure 3B FIG. is a schematic diagram of various scenarios for performing a search operation on the memory cell 110 according to some embodiments of the present disclosure. As Figure 3B shown, the memory cell 110 can operate in six scenarios. The six scenarios are arranged in two rows and three columns.

[0090] In the scenarios of the first row, the search bit SB1 has a logical value of 0, such that the voltage signal VG has a voltage level LVSL. In the scenarios of the second row, the search bit SB1 has a logical value of 1, such that the voltage signal VG has a voltage level HVSL.

[0091] In the scenarios of the first column, the data bit DT1 has a logical value of 0, such that the memory cell 110 has a threshold voltage level LVT. In the scenarios of the second column, the data bit DT1 has a logical value of 1, such that the memory cell 110 has a threshold voltage level HVT. In the scenarios of the third column, the data bit DT1 has a logical value of X, such that the memory cell 110 has a threshold voltage level MVT. In some embodiments, the threshold voltage level MVT is greater than the threshold voltage level LVT and less than the threshold voltage level HVT.

[0092] As Figure 3B shown, in the scenarios of the first row and the second column and the second row and the first column, in response to the logical values of the data bit DT1 and the search bit SB1 being different, the current signal 116 has a current level IL31. In the scenarios of the first row and the first column, the second row and the second column, and the third column, in response to the logical values of the data bit DT1 and the search bit SB1 being the same, the current signal 116 has a current level IL32.

[0093] Figure 4A FIG. 400A is a relationship diagram of the current signal 116 and the voltage signal VG according to some embodiments of the present disclosure. The horizontal axis of the relationship diagram 400A represents the voltage level of the voltage signal VG. The vertical axis of the relationship diagram 400A represents the current level of the current signal 116, and is represented in a logarithmic scale.

[0094] As Figure 4AAs shown, the relationship diagram 400A includes curves CV41 to CV44. Curves CV41 to CV44 represent four states of the memory cell 110 corresponding to the current signal 116. In the state corresponding to curve CV41, the data bit DT1 stored in the memory cell 110 has a logical value of 00. In the state corresponding to curve CV42, the data bit DT1 stored in the memory cell 110 has a logical value of 01. In the state corresponding to curve CV43, the data bit DT1 stored in the memory cell 110 has a logical value of 10. In the state corresponding to curve CV44, the data bit DT1 stored in the memory cell 110 has a logical value of 11. In decimal representation, the above logical values 00, 01, 10, and 11 correspond to logical values 0, 1, 2, and 3 respectively.

[0095] As Figure 4A shown, when the voltage signal VG has a voltage level VSL1, curves CV41 to CV44 have current levels IL1 to IL4 respectively. When the voltage signal VG has a voltage level VSL2, curves CV41 to CV44 have current levels IL2, IL1, IL2, and IL3 respectively. When the voltage signal VG has a voltage level VSL3, curves CV41 to CV44 have current levels IL3, IL2, IL1, and IL2 respectively. When the voltage signal VG has a voltage level VSL4, curves CV41 to CV44 have current levels IL4, IL3, IL2, and IL1 respectively.

[0096] In some embodiments, the current level IL4 is greater than the current level IL3, the current level IL3 is greater than the current level IL2, and the current level IL2 is greater than the current level IL1.

[0097] Figure 4B A schematic diagram of various scenarios for performing a search operation on the memory cell 110 illustrated according to some embodiments of the present disclosure. As Figure 4B shown, the memory cell 110 can operate in sixteen scenarios. The sixteen scenarios are arranged in four rows and four columns.

[0098] In the scenarios of the first row, the search bit SB1 has a logical value of 00, such that the voltage signal VG has a voltage level VSL1. In the scenarios of the second row, the search bit SB1 has a logical value of 01, such that the voltage signal VG has a voltage level VSL2. In the scenarios of the third row, the search bit SB1 has a logical value of 10, such that the voltage signal VG has a voltage level VSL3. In the scenarios of the fourth row, the search bit SB1 has a logical value of 11, such that the voltage signal VG has a voltage level VSL4.

[0099] In the context of the first column, the data bit DT1 has a logical value of 00, such that the memory cell 110 has a threshold voltage level VT1. In the context of the second column, the data bit DT1 has a logical value of 01, such that the memory cell 110 has a threshold voltage level VT2. In the context of the third column, the data bit DT1 has a logical value of 10, such that the memory cell 110 has a threshold voltage level VT3. In the context of the fourth column, the data bit DT1 has a logical value of 11, such that the memory cell 110 has a threshold voltage level VT4.

[0100] In some embodiments, the threshold voltage level VT4 is greater than the threshold voltage level VT3, the threshold voltage level VT3 is greater than the threshold voltage level VT2, and the threshold voltage level VT2 is greater than the threshold voltage level VT1.

[0101] As Figure 4B shown, in the context of the first row and the first column, the second row and the second column, the third row and the third column, and the fourth row and the fourth column, in response to the logical values of the data bit DT1 and the search bit SB1 being the same, the current signal 116 has a current level IL1.

[0102] In the context of the first row and the second column, the second row and the first column, the second row and the third column, the third row and the second column, the third row and the fourth column, and the fourth row and the third column, in response to the difference between the logical values of the data bit DT1 and the search bit SB1 being 1 (for example, the difference between the logical values 00 and 01 is 1, and the difference between the logical values 10 and 11 is also 1), the current signal 116 has a current level IL2.

[0103] In the context of the first row and the third column, the second row and the fourth column, the third row and the first column, and the fourth row and the second column, in response to the difference between the logical values of the data bit DT1 and the search bit SB1 being 2 (for example, the difference between the logical values 00 and 10 is 2, and the difference between the logical values 01 and 11 is also 2), the current signal 116 has a current level IL3.

[0104] In the context of the first row and the fourth column and the fourth row and the first column, in response to the difference between the logical values of the data bit DT1 and the search bit SB1 being 3 (for example, the difference between the logical values 00 and 11 is 3), the current signal 116 has a current level IL3.

[0105] In summary, when the similarity between the data bit DT1 and the search bit SB1 is high, the current level of the current signal 116 is low. When the similarity between the data bit DT1 and the search bit SB1 is low, the current level of the current signal 116 is high. Correspondingly, the memory device can determine the similarity between the data bit DT1 and the search bit SB1 based on the current level of the current signal 116.

[0106] Figure 5A FIG. 500A is a graph showing the relationship between the current signal 116 and the voltage signal VG according to some embodiments of the present disclosure. The horizontal axis of graph 500A represents the voltage level of the voltage signal VG. The vertical axis of graph 500A represents the current level of the current signal 116 and is represented on a logarithmic scale.

[0107] As Figure 5A shown, graph 500A includes curves CV51 - CV58. Curves CV51 - CV58 represent eight states of the memory cell 110 corresponding to the current signal 116.

[0108] In the state corresponding to curve CV51, the data bit DT1 stored in the memory cell 110 has a logical value of 000. In the state corresponding to curve CV52, the data bit DT1 stored in the memory cell 110 has a logical value of 001. In the state corresponding to curve CV53, the data bit DT1 stored in the memory cell 110 has a logical value of 010. In the state corresponding to curve CV54, the data bit DT1 stored in the memory cell 110 has a logical value of 011. In the state corresponding to curve CV55, the data bit DT1 stored in the memory cell 110 has a logical value of 100. In the state corresponding to curve CV56, the data bit DT1 stored in the memory cell 110 has a logical value of 101. In the state corresponding to curve CV57, the data bit DT1 stored in the memory cell 110 has a logical value of 110. In the state corresponding to curve CV56, the data bit DT1 stored in the memory cell 110 has a logical value of 111. In decimal representation, the above logical values 000, 001, 010, 011, 100, 101, 110, 111 correspond to the logical values 0, 1, 2, 3, 4, 5, 6, and 7 respectively.

[0109] As Figure 5AAs shown, when the voltage signal VG has the voltage level VSL1, the curves CV51 to CV58 respectively have the current levels IL1 to IL8. When the voltage signal VG has the voltage level VSL2, the curves CV51 to CV58 respectively have the current levels IL2, IL1, and IL2 to IL7. When the voltage signal VG has the voltage level VSL3, the curves CV51 to CV58 respectively have the current levels IL3, IL2, IL1, and IL2 to IL6. When the voltage signal VG has the voltage level VSL4, the curves CV51 to CV58 respectively have the current levels IL4, IL3, IL2, IL1, and IL2 to IL5. When the voltage signal VG has the voltage level VSL5, the curves CV51 to CV58 respectively have the current levels IL5, IL4, IL3, IL2, IL1, and IL2 to IL4. When the voltage signal VG has the voltage level VSL6, the curves CV51 to CV58 respectively have the current levels IL6, IL5, IL4, IL3, IL2, IL1, IL2, and IL3. When the voltage signal VG has the voltage level VSL7, the curves CV51 to CV58 respectively have the current levels IL7, IL6, IL5, IL4, IL3, IL2, IL1, and IL2. When the voltage signal VG has the voltage level VSL8, the curves CV51 to CV58 respectively have the current levels IL8, IL7, IL6, IL5, IL4, IL3, IL2, and IL1.

[0110] In some embodiments, the current level IL8 is greater than the current level IL7, the current level IL7 is greater than the current level IL6, the current level IL6 is greater than the current level IL5, the current level IL5 is greater than the current level IL4, the current level IL4 is greater than the current level IL3, the current level IL3 is greater than the current level IL2, and the current level IL2 is greater than the current level IL1.

[0111] Figure 5B A schematic diagram of various scenarios for performing a search operation on the memory cell 110 illustrated according to some embodiments of the present disclosure. As Figure 5B shown, the memory cell 110 can operate in sixty-four scenarios. The sixty-four scenarios are arranged in eight rows and eight columns.

[0112] In the context of the first row, the search bit SB1 has a logical value of 000, such that the voltage signal VG has a voltage level VSL1. In the context of the second row, the search bit SB1 has a logical value of 001, such that the voltage signal VG has a voltage level VSL2. In the context of the third row, the search bit SB1 has a logical value of 010, such that the voltage signal VG has a voltage level VSL3. In the context of the fourth row, the search bit SB1 has a logical value of 011, such that the voltage signal VG has a voltage level VSL4. In the context of the fifth row, the search bit SB1 has a logical value of 100, such that the voltage signal VG has a voltage level VSL5. In the context of the sixth row, the search bit SB1 has a logical value of 101, such that the voltage signal VG has a voltage level VSL6. In the context of the seventh row, the search bit SB1 has a logical value of 110, such that the voltage signal VG has a voltage level VSL7. In the context of the eighth row, the search bit SB1 has a logical value of 111, such that the voltage signal VG has a voltage level VSL8.

[0113] In the context of the first column, the data bit DT1 has a logical value of 000, such that the memory cell 110 has a threshold voltage level VT1. In the context of the second column, the data bit DT1 has a logical value of 001, such that the memory cell 110 has a threshold voltage level VT2. In the context of the third column, the data bit DT1 has a logical value of 010, such that the memory cell 110 has a threshold voltage level VT3. In the context of the fourth column, the data bit DT1 has a logical value of 011, such that the memory cell 110 has a threshold voltage level VT4. In the context of the fifth column, the data bit DT1 has a logical value of 100, such that the memory cell 110 has a threshold voltage level VT5. In the context of the sixth column, the data bit DT1 has a logical value of 101, such that the memory cell 110 has a threshold voltage level VT6. In the context of the seventh column, the data bit DT1 has a logical value of 110, such that the memory cell 110 has a threshold voltage level VT7. In the context of the fourth column, the data bit DT1 has a logical value of 111, such that the memory cell 110 has a threshold voltage level VT8.

[0114] In some embodiments, the threshold voltage level VT8 is greater than the threshold voltage level VT7, the threshold voltage level VT7 is greater than the threshold voltage level VT6, the threshold voltage level VT6 is greater than the threshold voltage level VT5, the threshold voltage level VT5 is greater than the threshold voltage level VT4, the threshold voltage level VT4 is greater than the threshold voltage level VT3, the threshold voltage level VT3 is greater than the threshold voltage level VT2, and the threshold voltage level VT2 is greater than the threshold voltage level VT1.

[0115] As Figure 5BAs shown, in the scenarios of the first row and the first column, the second row and the second column, the third row and the third column, the fourth row and the fourth column, the fifth row and the fifth column, the sixth row and the sixth column, the seventh row and the seventh column, and the eighth row and the eighth column, in response to the data bit DT1 and the search bit SB1 having the same logical value, the current signal 116 has a current level IL1.

[0116] In the scenarios of the first row and the second column, the second row and the first column, the second row and the third column, the third row and the second column, the third row and the fourth column, the fourth row and the third column, the fourth row and the fifth column, the fifth row and the fourth column, the fifth row and the sixth column, the sixth row and the fifth column, the sixth row and the seventh column, the seventh row and the sixth column, the seventh row and the eighth column, and the eighth row and the seventh column, the difference between the logical values in response to the data bit DT1 and the search bit SB1 is 1 (for example, the difference between the logical values 010 and 011 is 1, and the difference between the logical values 110 and 111 is also 1), and the current signal 116 has a current level IL2.

[0117] In the scenarios of the first row and the third column, the second row and the fourth column, the third row and the first column, the third row and the fifth column, the fourth row and the second column, the fourth row and the sixth column, the fifth row and the third column, the fifth row and the seventh column, the sixth row and the fourth column, the sixth row and the eighth column, the seventh row and the fifth column, and the eighth row and the sixth column, the difference between the logical values in response to the data bit DT1 and the search bit SB1 is 2 (for example, the difference between the logical values 100 and 010 is 2, and the difference between the logical values 101 and 111 is also 2), and the current signal 116 has a current level IL3.

[0118] In the scenarios of the first row and the fourth column, the second row and the fifth column, the third row and the sixth column, the fourth row and the first column, the fourth row and the seventh column, the fifth row and the second column, the fifth row and the eighth column, the sixth row and the third column, the seventh row and the fourth column, and the eighth row and the fifth column, the difference between the logical values in response to the data bit DT1 and the search bit SB1 is 3 (for example, the difference between the logical values 100 and 001 is 3, and the difference between the logical values 100 and 111 is also 3), and the current signal 116 has a current level IL4.

[0119] In the scenarios of the first row and the fifth column, the second row and the sixth column, the third row and the seventh column, the fourth row and the eighth column, the fifth row and the first column, the sixth row and the second column, the seventh row and the third column, and the eighth row and the fourth column, the difference between the logical values in response to the data bit DT1 and the search bit SB1 is 4 (for example, the difference between the logical values 101 and 001 is 4, and the difference between the logical values 011 and 111 is also 4), and the current signal 116 has a current level IL5.

[0120] In the scenarios of the first row and the sixth column, the second row and the seventh column, the third row and the eighth column, the sixth row and the first column, the seventh row and the second column, and the eighth row and the third column, the difference between the logical values of the data bit DT1 and the search bit SB1 in response is 5 (for example, the difference between the logical values 101 and 000 is 5, and the difference between the logical values 010 and 111 is also 5), and the current signal 116 has a current level IL6.

[0121] In the scenarios of the first row and the seventh column, the second row and the eighth column, the seventh row and the first column, and the eighth row and the second column, the difference between the logical values of the data bit DT1 and the search bit SB1 in response is 6 (for example, the difference between the logical values 110 and 000 is 6, and the difference between the logical values 001 and 111 is also 6), and the current signal 116 has a current level IL7.

[0122] In the scenarios of the first row and the eighth column and the eighth row and the first column, the difference between the logical values of the data bit DT1 and the search bit SB1 in response is 7 (for example, the difference between the logical values 111 and 000 is 7), and the current signal 116 has a current level IL8.

[0123] In summary, in decimal notation, the data bit DT1 can have one of the logical values 0 to 7, and the search bit SB1 can also have one of the logical values 0 to 7. When performing a search operation, the current level of the current signal 116 is positively correlated with the difference between the data bit DT1 and the search bit SB1. In other words, the current level of the current signal 116 is negatively correlated with the similarity between the data bit DT1 and the search bit SB1.

[0124] Specifically, when the similarity between the data bit DT1 and the search bit SB1 is high, the current level of the current signal 116 is low. When the similarity between the data bit DT1 and the search bit SB1 is low, the current level of the current signal 116 is high. Correspondingly, the memory device can determine the similarity between the data bit DT1 and the search bit SB1 based on the current level of the current signal 116.

[0125] Figure 6 FIG. 600 is a relationship diagram of the current signal 116 and the voltage signal VG illustrated according to some embodiments of the present disclosure. The horizontal axis of the relationship diagram 600 represents the voltage level of the voltage signal VG. The vertical axis of the relationship diagram 600 represents the current level of the current signal 116 and is represented in a logarithmic scale. As Figure 6 shown, the relationship diagram 600 includes curves CV61 and CV62. The logical values of the data bit DT1 corresponding to the curves CV61 and CV62 are the same. The curves CV61 and CV62 respectively correspond to two different device lengths.

[0126] Please refer to Figure 6 and Figure 1, the device length corresponds to the length of the memory cell 110 in the horizontal direction. In some embodiments, the device length may correspond to the length of the channel structure 113 in the horizontal direction, or may correspond to the distance between the source structure 111 and the drain structure 112. The device length corresponding to the curve CV61 is less than the device length corresponding to the curve CV62.

[0127] In some embodiments, by applying voltage signals with different pulse widths or different voltage levels to the memory cell 110, the threshold voltage level of the memory cell 110 can be changed, causing the curves CV61 and CV62 to move horizontally. For example, referring to Figure 6 and Figure 5A , the curve CV61 can be adjusted to any one of the curves CV51 - CV58 by different voltage signals.

[0128] As Figure 6 shown, when the voltage signal VG has the search voltage level VSEARCH1, the current level of the curve CV62 is less than the current level IL61, and the current level of the curve CV61 is greater than the current level IL62. When the voltage signal VG has the search voltage level VSEARCH2, the current level of the curve CV62 is less than the current level IL61, and the curve CV61 has the current level IL61. When the voltage signal VG has the search voltage level VSEARCH3, the curve CV62 has the current level IL62, and the current level of the curve CV61 is greater than the current level IL62.

[0129] In some embodiments, the search voltage levels VSEARCH1, VSEARCH2, and VSEARCH3 respectively correspond to three different logical values of the search bit SB1. A current level greater than or equal to the current level IL62 represents that the search bit SB1 and the data bit DT1 do not match. A current level less than or equal to the current level IL61 represents that the search bit SB1 and the data bit DT1 match. In some embodiments, the current levels IL61 and IL62 are respectively referred to as the match current level and the non - match current level.

[0130] In other words, for the curve CV61, the logical values of the search voltage levels VSEARCH1 and VSEARCH3 do not match the logical value of the data bit DT1, and the logical value of the search voltage level VSEARCH2 matches the logical value of the data bit DT1. For the curve CV62, the logical values of the search voltage levels VSEARCH1 and VSEARCH2 match the logical value of the data bit DT1, and the logical value of the search voltage level VSEARCH1 does not match the logical value of the data bit DT1.

[0131] As Figure 6As shown, curve CV61 has an analog point AP6 corresponding to search voltage level VSEARCH2, and curve CV62 has an analog range AR6 that includes search voltage levels VSEARCH2 and VSEARCH1. In some embodiments, the device length of memory cell 110 can be adjusted to perform range search or point search.

[0132] Specifically, when the device length of memory cell 110 corresponds to curve CV62, the logic values corresponding to the voltage levels within analog range AR6 are considered to match the logic value of data bit DT1. When the device length of memory cell 110 corresponds to curve CV61, the logic value corresponding to search voltage level VSEARCH2 is considered to match the logic value of data bit DT1, and the logic value corresponding to search voltage level VSEARCH1 is considered not to match the logic value of data bit DT1.

[0133] In some embodiments, the above matching results can be determined based on the relationship between current signal 116 and current levels IL61 and IL62. For example, when the current level of current signal 116 is greater than current level IL62, search bit SB1 and data bit DT1 do not match. When the current level of current signal 116 is less than current level IL61, search bit SB1 and data bit DT1 match.

[0134] Figure 7A FIG. 700 is a graph showing the relationship between current signal 116 and voltage signal VG according to some embodiments of the present disclosure. The horizontal axis of graph 700 represents the voltage level of voltage signal VG. The vertical axis of graph 700 represents the current level of current signal 116, and is represented in a logarithmic scale. As Figure 7A shown, graph 700 includes curves CV71 and CV72. Curves CV71 and CV72 correspond to the same logic value of data bit DT1. Curves CV71 and CV72 correspond to two different drain bias signals respectively.

[0135] Please refer to Figure 7A and Figure 1 , the drain bias signal is a bias signal applied to drain structure 112. In some embodiments, the drain bias level of the drain bias signal corresponding to curve CV71 is greater than the drain bias level of the drain bias signal corresponding to curve CV72.

[0136] In some embodiments, the threshold voltage level of memory cell 110 can be changed by applying voltage signals with different pulse widths or different voltage levels to memory cell 110, such that curves CV71 and CV72 are shifted horizontally. For example, please refer to Figure 7A and Figure 5A, curve CV71 can be adjusted by different voltage signals to any one of curves CV51 - CV58.

[0137] As Figure 7A shown, when the voltage signal VG has a search voltage level VSEARCH1, the current level of curve CV72 is less than the current level IL71, and the current level of curve CV71 is greater than the current level IL72. When the voltage signal VG has a search voltage level VSEARCH2, the current level of curve CV72 is less than the current level IL71, and curve CV71 has the current level IL71. When the voltage signal VG has a search voltage level VSEARCH3, curve CV72 has the current level IL72, and the current level of curve CV71 is greater than the current level IL72.

[0138] In some embodiments, the search voltage levels VSEARCH1, VSEARCH2, and VSEARCH3 respectively correspond to three different logical values of the search bit SB1. A current level greater than or equal to the current level IL72 represents a mismatch between the search bit SB1 and the data bit DT1. A current level less than or equal to the current level IL71 represents a match between the search bit SB1 and the data bit DT1. In some embodiments, the current levels IL71 and IL72 are respectively referred to as the match current level and the mismatch current level.

[0139] In other words, for curve CV71, the logical values of the search voltage levels VSEARCH1 and VSEARCH3 do not match the logical value of the data bit DT1, and the logical value of the search voltage level VSEARCH2 matches the logical value of the data bit DT1. For curve CV72, the logical values of the search voltage levels VSEARCH1 and VSEARCH2 match the logical value of the data bit DT1, and the logical value of the search voltage level VSEARCH2 does not match the logical value of the data bit DT1.

[0140] As Figure 7A shown, curve CV71 has an analog point AP7 corresponding to the search voltage level VSEARCH2, and curve CV72 has an analog range AR7 including the search voltage levels VSEARCH2 and VSEARCH1. In some embodiments, the range search or point search can be performed by adjusting the drain bias signal of the memory cell 110.

[0141] Specifically, when the drain bias signal of the memory cell 110 corresponds to the curve CV72, the logic values corresponding to the voltage levels in the range from the search voltage level VSEARCH1 to the search voltage level VSEARCH2 are regarded as matching the logic value of the data bit DT1. When the drain bias signal of the memory cell 110 corresponds to the curve CV71, the logic value corresponding to the search voltage level VSEARCH2 is regarded as matching the logic value of the data bit DT1, and the logic value corresponding to the search voltage level VSEARCH1 is regarded as not matching the logic value of the data bit DT1.

[0142] In some embodiments, the above matching results can be determined by the relationship between the current signal 116 and the current levels IL71 and IL72. For example, when the current level of the current signal 116 is greater than the current level IL72, the search bit SB1 and the data bit DT1 do not match. When the current level of the current signal 116 is less than the current level IL71, the search bit SB1 and the data bit DT1 match. Please refer to Figure 6 and Figure 7A , in some embodiments, the current level IL71 is the same as IL61, and the current level IL72 is the same as IL62.

[0143] Figure 7B FIG. 700B is a band diagram of the memory device 110 corresponding to Figure 7A according to some embodiments of the present disclosure. The horizontal axis of the band diagram 700B corresponds to electron volts. The vertical axis of the band diagram 700B corresponds to the direction from the source structure 111 to the drain structure 112, for example Figure 1 the horizontal direction shown. In the embodiment shown in Figure 7B , the voltage level of the voltage signal VG is approximately equal to 0.

[0144] As shown in Figure 7B , the band diagram 700B includes energy levels SCV1~SCV3 and LCV1~LCV3. The energy levels SCV1 and LCV1 correspond to the conduction band. The energy levels SCV2 and LCV2 correspond to the Fermi-level. The energy levels SCV3 and LCV3 correspond to the valence band.

[0145] In some embodiments, the energy levels SCV1~SCV3 correspond to smaller drain bias signals, and the energy levels LCV1~LCV3 correspond to larger drain bias signals. Please refer to Figure 7B and Figure 7A, the drain bias signals corresponding to energy levels SCV1 - SCV3 are for the curve CV72, used to form a longer equivalent device length. The drain bias signals corresponding to energy levels LCV1 - LCV3 are for the curve CV71, used to form a shorter equivalent device length.

[0146] In other words, when the drain bias signal is adjusted from the voltage level corresponding to curve CV72 to the voltage level corresponding to curve CV71, the memory cell 110 is shifted from energy levels SCV1 - SCV3 to energy levels LCV1 - LCV3. When the drain bias signal is adjusted from the voltage level corresponding to curve CV71 to the voltage level corresponding to curve CV72, the memory cell 110 is shifted from energy levels LCV1 - LCV3 to curves SCV1 - SCV3. In some embodiments, the equivalent device length of the memory cell 110 can be changed by adjusting the drain bias signal of the memory cell 110 to perform range search or point search.

[0147] Figure 8 A schematic diagram of a memory system 800 illustrated according to some embodiments of the present disclosure. In some embodiments, the memory system 800 can be implemented by a TFET in - memory search system.

[0148] As Figure 8 shown, the memory system 800 includes a search encoder 810, a memory array 820, a page buffer 830, and a combining and sorting device 840. The search encoder 810 is used to generate word line signals WL1 - WLn carrying search characters SW1. The memory array 820 includes memory rows CL1 - CLm. The memory rows CL1 - CLm are respectively used to store data characters DW1 - DWm, and generate current signals I1 - Im according to the search character SW1 and the data characters DW1 - DWm. The page buffer 830 is used to receive the current signals I1 - Im and output them to the combining and sorting device 840. The combining and sorting device 840 is used to process the output of the page buffer 830 to generate a search result 850. In some embodiments, the page buffer 830 can include a plurality of sensing amplifiers.

[0149] In some embodiments, the processing performed by the combining and sorting device 840 on the output of the page buffer 830 includes AND logic, OR logic, or counting logic processing, and can also include a combined processing of the above three logics. Please refer to Figure 1 and Figure 8 , the combining and sorting device 840 can receive sensing results from the memory device 100 and / or the memory array 820, and control sorting (which can be serial or parallel) and combine the sensing results to generate an overall search result as the search result 850.

[0150] In some embodiments, the memory system 800 may be implemented on a single integrated circuit die, multiple integrated circuits, or as components of a System-On-a-Chip (SOC). As a specific example, the memory system 800 is implemented on a single integrated circuit die and is capable of performing search and combination logic operations within the single integrated circuit die.

[0151] As shown Figure 8 in the figure, memory row CL1 includes transistors T1_1 to T1_n. Memory row CL2 includes transistors T2_1 to T2_n, and so on. Memory row CLm includes transistors Tm_1 to Tm_n. The source terminals of transistors T1_1 to T1_n are coupled to each other. The source terminals of transistors T2_1 to T2_n are coupled to each other, and so on. The source terminals of transistors Tm_1 to Tm_n are coupled to each other. The drain terminals of transistors T1_1 to T1_n are coupled to each other and are used to output current signal I1. The drain terminals of transistors T2_1 to T2_n are coupled to each other and are used to output current signal I2, and so on. The drain terminals of transistors Tm_1 to Tm_n are coupled to each other and are used to output current signal Im.

[0152] On the other hand, the gate terminals of transistors T1_1 to Tm_1 are used to receive word line signal WL1. The gate terminals of transistors T1_2 to Tm_2 are used to receive word line signal WL2, and so on. The gate terminals of transistors T1_n to Tm_n are used to receive word line signal WLn.

[0153] Please refer to Figure 8 and Figure 1 , the memory array 820 may be implemented by the memory device 100. Each of transistors T1_1 to Tm_n may be implemented by a memory cell 110 and is used to store one corresponding data bit among data characters DW1 to DWm. Each of word line signals WL1 to WLn corresponds to a voltage signal VG and is used to carry one corresponding search bit among search characters SW1.

[0154] In some embodiments, word line signals WL1 to WLn respectively have voltage levels VSL_1 to VSL_n. In some embodiments, each of voltage levels VSL_1 to VSL_n may be Figure 5A any one of the voltage levels VSL1 to VSL8 shown in the figure to carry the corresponding logical value.

[0155] During a search operation, transistors T1_1 to T1_n compare a search character SW1 and data characters DW1, generate corresponding current signals 116, and add the current signals 116 to generate a current signal I1. Similarly, transistors T2_1 to T2_n compare the search character SW1 and data characters DW2, generate corresponding current signals 116, and add the current signals 116 to generate a current signal I2, and so on. Transistors Tm_1 to Tm_n compare the search character SW1 and data characters DWm, generate corresponding current signals 116, and add the current signals 116 to generate a current signal Im.

[0156] When the similarity between the search character SW1 and one of the data characters DW1 to DWm is high, the current level of the corresponding one of the current signals I1 to Im is low. When the similarity between the search character SW1 and one of the data characters DW1 to DWm is low, the current level of the corresponding one of the current signals I1 to Im is high. Correspondingly, the memory system 800 can determine the similarity between the search character SW1 and the data characters DW1 to DWm based on the current signals I1 to Im.

[0157] For example, in some embodiments, the current level of the current signal Im is greater than the current level of the current signal I2, and the current level of the current signal I2 is greater than the current level of the current signal I1. In the above embodiments, the memory system 800 can determine that the similarity between the search character SW1 and the data character DW1 is greater than the similarity between the search character SW1 and the data character DW2, and the similarity between the search character SW1 and the data character DW2 is greater than the similarity between the search character SW1 and the data character DWm.

[0158] Although the present disclosure has been disclosed as above with embodiments, it is not intended to limit the present disclosure. Any person skilled in the art, without departing from the spirit and scope of the present disclosure, may make some modifications and refinements. Therefore, the protection scope of the present disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A memory device (100) includes a first memory cell (110) for storing a first data bit, the first memory cell comprising: A channel structure (113); A source structure (111) contacting a first side of the channel structure; A drain structure (112) contacting a second side of the channel structure; A charge trap layer (114) contacting a third side of the channel structure, wherein when the first data bit has a first logic value and a voltage signal applied to the charge trap layer has a first voltage level, a current signal (116) flowing through the channel structure has a first current level, when the first data bit has the first logic value and the voltage signal has a second voltage level different from the first voltage level, the current signal has a second current level different from the first current level, when the first data bit has a second logic value different from the first logic value and the voltage signal has the first voltage level, the current signal has the second current level, and when the first data bit has the second logic value and the voltage signal has the second voltage level, the current signal has the first current level.

2. The memory device according to claim 1, further comprising: An upper electrode (115) for applying the voltage signal to the charge trap layer, wherein in a first direction, the charge trap layer is located between the upper electrode and the channel structure.

3. The memory device according to claim 2, wherein in a second direction perpendicular to the first direction, the first side and the second side are opposite to each other.

4. The memory device according to claim 1, wherein when the channel structure has a first device length, in response to the voltage signal having a first search voltage level, the current level of the current signal is greater than a mismatch current level, when the channel structure has a second device length, in response to the voltage signal having the first search voltage level, the current level of the current signal is less than a match current level, the first device length is less than the second device length, and the match current level is less than the mismatch current level.

5. The memory device according to claim 4, wherein when the channel structure has the first device length, in response to the voltage signal having a second search voltage level, the current level of the current signal is equal to the match current level, and when the channel structure has the second device length, in response to the voltage signal having the second search voltage level, the current level of the current signal is less than the match current level.

6. The memory device according to claim 5, wherein when the channel structure has the first device length, in response to the voltage signal having a third search voltage level, the current level of the current signal is greater than the mismatch current level, and when the channel structure has the second device length, in response to the voltage signal having the third search voltage level, the current level of the current signal is equal to the mismatch current level.

7. The memory device according to claim 1, wherein When a drain bias signal applied to the drain structure has a first drain bias voltage level, in response to the voltage signal having a first search voltage level, the current level of the current signal is greater than a mismatch current level. When the drain bias signal has a second drain bias voltage level, in response to the voltage signal having the first search voltage level, the current level of the current signal is less than a match current level. The first drain bias level is greater than the drain bias level, and The match current level is less than the mismatch current level.

8. The memory device according to claim 7, wherein When the drain bias signal has the first drain bias voltage level, in response to the voltage signal having a second search voltage level, the current level of the current signal is equal to the match current level, and When the drain bias signal has the second drain bias voltage level, in response to the voltage signal having the second search voltage level, the current level of the current signal is less than the match current level.

9. The memory device according to claim 8, wherein When the drain bias signal has the first drain bias voltage level, in response to the voltage signal having a third search voltage level, the current level of the current signal is greater than the mismatch current level, and When the drain bias signal has the second drain bias voltage level, in response to the voltage signal having the third search voltage level, the current level of the current signal is equal to the mismatch current level.

10. A method of operating a memory device, comprising: Storing a first data in a first memory cell (110); Applying a voltage signal carrying a first search bit to the first memory cell; Comparing the first data bit and the first search bit to generate a current signal (116) flowing through the first memory cell, Wherein when each of the first data bit and the first search bit has a first logic value, the current signal has a first current level, When the first data bit has the first logic value and the first search bit has a second logic value, the current signal has a second current level greater than the first current level, When the first data bit has the first logic value and the first search bit has a third logic value, the current signal has the second current level, and A difference between the first logic value and the second logic value is equal to a difference between the third logic value and the first logic value.

11. The method of operation according to claim 10, wherein when the first data bit has the second logic value and the first search bit has the second logic value, the current signal has the first current level.

12. The method of operation according to claim 11, wherein when the first data bit has the third logic value and the first search bit has the third logic value, the current signal has the first current level.

13. The method of operation according to claim 10, wherein when the first data bit has the second logic value and the first search bit has the third logic value, the current signal has a third current level greater than the second current level.

14. The operation method according to claim 13, wherein when the first data bit has the third logic value and the first search bit has the second logic value, the current signal has the third current level.

15. The operation method according to claim 13, wherein when the first data bit has a fourth logic value and the first search bit has the second logic value, the current signal has a fourth current level greater than the third current level, and the fourth logic value is greater than the third logic value.

16. The operation method according to claim 15, wherein when the first data bit has the second logic value and the first search bit has the fourth logic value, the current signal has the fourth current level.

17. The operation method according to claim 15, wherein when the first data bit has the fourth logic value and the first search bit has the fourth logic value, the current signal has the first current level.

18. An operation method of a memory device, comprising: setting a first threshold voltage of a first memory cell (110) to store a first data bit in the first memory cell; applying a voltage signal carrying a first search bit to the first memory cell; generating a current signal (116) according to the first search bit and the first threshold voltage, wherein when the first threshold voltage has a first threshold voltage level, the first data bit has a first logic value, when the first threshold voltage has a second threshold voltage level, the first data bit has a second logic value different from the first logic value, when each of the first data bit and the first search bit has the first logic value, the current signal has a first current level, when the first data bit has the second logic value and the first search bit has the first logic value, the current signal has a second current level greater than the first current level, and when the first threshold voltage has a third threshold voltage level between the first threshold voltage level and the second threshold voltage level, the current signal has the first current level.

19. The operation method according to claim 18, wherein when each of the first data bit and the first search bit has the second logic value, the current signal has the first current level.

20. The operation method according to claim 19, wherein when the first data bit has the first logic value and the first search bit has the second logic value, the current signal has the second current level.

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