Memory device for implementing read operations for bidirectional selector only memory SOM cells

Abstract

A memory device for implementing read operations of a bidirectional selector only memory (SOM) cell. The memory device includes a plurality of memory cells, each of the plurality of memory cells including a material film, an access circuit, and a sensing circuit. The logic state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state. The access circuit applies a first voltage to a first electrode of a selected memory cell among the plurality of memory cells, and applies a second voltage to a second electrode of the selected memory cell, and the sensing circuit determines a logic state of the selected memory cell based on an electrical response of a first sensing node and a second sensing node connected to the selected memory cell with respect to the first voltage and the second voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 007641, filed with the Korean Intellectual Property Office on January 17, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a semiconductor memory device, and more particularly, to a memory device for implementing a read operation of a bidirectional selector only memory cell. Background art

[0004] As non - volatile memory devices, resistive memory devices such as phase - change random access memory (PRAM), resistive RAM (RRAM), magnetic RAM (MRAM), etc. are known. A resistive memory device uses a variable resistor as a memory cell and stores data by changing its resistance state. By arranging such memory cells at the intersections of multiple bit lines and multiple word lines, a cross - point type resistive memory device is configured.

[0005] A resistive memory device can use an ovonic threshold switch (OTS) device to store data in a memory cell. The OTS device may include a semiconductor material in an amorphous state or a crystalline state disposed between a first electrode and a second electrode. The OTS device exhibits the following characteristics: when a positive (+) threshold voltage or a voltage higher than the positive (+) threshold voltage is applied between the first electrode and the second electrode, the current rapidly increases in a non - linear manner, and when a negative (-) threshold voltage or a voltage higher than the negative (-) threshold voltage is applied, the current rapidly increases in a non - linear manner (see Figure 4 ). The OTS element conducts in response to a positive (+) threshold voltage applied between the first electrode and the second electrode and also conducts in response to a negative (-) threshold voltage. In other words, the OTS device serves as a bidirectional selector device (sometimes called a bipolar device). The change in the voltage applied to the first electrode and the second electrode of the OTS device can be manifested as a current, thereby exhibiting a storage function. Such a bidirectional selector memory cell stores a logic "1" (sometimes called set data, crystalline state, or low - threshold voltage state) or a logic "0" (sometimes called reset data, amorphous state, or high - threshold voltage state) based on the threshold voltage of the bidirectional selector memory cell.

[0006] In a read operation of reading a logic state of a memory cell based on a resistance change of a two-way select memory cell, a sensing circuit of a resistive memory device may have asymmetry or a reduced sensing margin, resulting in a read error. Therefore, an operation method capable of reducing a read error of a resistive memory device and ensuring a sensing margin is needed. SUMMARY OF THE INVENTION

[0007] The inventive concept provides a memory device that performs a read operation of a two-way select memory cell.

[0008] According to an aspect of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film opposite to the first side, wherein a logic state of the material film is programmed based on whether the material film is in a crystalline state or a non-crystalline state; an access circuit configured to apply a first voltage to the first electrode of a selected memory cell among the plurality of memory cells and apply a second voltage to the second electrode of the selected memory cell; and a sensing circuit configured to determine a logic state of the selected memory cell based on an electrical response of a first sensing node and a second sensing node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sensing circuit includes: a switch configured to electrically connect the first sensing node to the second sensing node based on a read signal; a capacitor connected between the second sensing node and a sensing input node; a pre-charger configured to pre-charge the sensing input node with a pre-charge voltage based on a pre-charge control signal; and a comparison circuit configured to compare a voltage level of the sensing input node with a voltage level of a reference voltage and output a signal indicating a logic state of the selected memory cell.

[0009] According to another aspect of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein a logical state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state; an access circuit configured to apply a first voltage to the first electrode of a selected memory cell among the plurality of memory cells and to apply a second voltage to the second electrode of the selected memory cell; and a sensing circuit configured to determine a logical state of the selected memory cell based on electrical responses of a first sensing node and a second sensing node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sensing circuit includes: a capacitor connected between the first sensing node and the second sensing node; a pre-charger configured to pre-charge a first end of the capacitor to a voltage level of a pre-charge voltage; and a comparison circuit configured to compare a voltage level of the first end of the capacitor with a voltage level of a reference voltage and to output a signal indicating the logical state of the selected memory cell.

[0010] According to another aspect of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein a logical state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state; an access circuit configured to apply a first voltage to the first electrode of a selected memory cell among the plurality of memory cells and to apply a second voltage to the second electrode of the selected memory cell; and a sensing circuit configured to determine a logical state of the selected memory cell based on electrical responses of a first sensing node and a second sensing node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sensing circuit includes: a first capacitor connected between the first sensing node and a sensing input node; a second capacitor connected between the second sensing node and the sensing input node; a pre-charger configured to pre-charge the sensing input node with a pre-charge voltage based on a pre-charge control signal; and a comparison circuit configured to compare a voltage level of the sensing input node with a voltage level of a reference voltage and to output a signal indicating the logical state of the selected memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the inventive concept will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a diagram conceptually showing a memory device according to an exemplary embodiment;

[0013] Figure 2shows a Figure 1 configuration of a memory cell array according to an exemplary embodiment;

[0014] Figure 3 is a diagram showing the Figure 1 structure of a memory cell according to an exemplary embodiment;

[0015] Figure 4 is a diagram showing the Figure 3 characteristics of a memory cell according to an exemplary embodiment;

[0016] Figure 5A and Figure 5B is a diagram showing the write operation and read operation of a memory cell according to an exemplary embodiment; Figure 1 is a diagram for describing the read operation of a memory device according to an exemplary embodiment;

[0017] Figure 6 is a timing diagram showing the timing of signals associated with a sense circuit according to an exemplary embodiment;

[0018] Figure 7 shows a Figure 6 timing diagram of signals associated with a sense circuit according to an exemplary embodiment;

[0019] Figure 8 is a diagram showing a memory device including a sense circuit according to an exemplary embodiment;

[0020] Figure 9 shows a Figure 8 timing diagram of signals associated with a sense circuit according to an exemplary embodiment;

[0021] Figure 10 and Figure 11 is a diagram showing a memory device including a sense circuit according to an exemplary embodiment;

[0022] Figure 12 is a diagram showing a memory device including a sense circuit according to an exemplary embodiment; and

[0023] Figure 13 is a block diagram of a system of an electronic device including a memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0024] Figure 1 is a diagram conceptually showing a memory device according to an exemplary embodiment. Figure 2 shows a Figure 1 configuration of a memory cell array 110 according to an exemplary embodiment. Figure 3 is a diagram showing the Figure 1 structure of a memory cell 10 according to an exemplary embodiment. Figure 4 is a diagram showing theFigure 3 A diagram showing the characteristics of the memory cell 10. For ease of understanding, the use of terms such as top surface / bottom surface, top / bottom, above / below, etc. is based on the directions shown in the accompanying drawings. Accordingly, even the same surface can be referred to as the top surface or the bottom surface depending on the direction shown in the figure.

[0025] Referring to Figure 1 and Figure 2 , the memory device 100 may include a memory cell array 110, a first access circuit 120, a second access circuit 130, a sensing circuit 140, and a control circuit 150. According to an exemplary embodiment of the inventive concept, the memory device 100 may be a phase change RAM (PRAM), including a plurality of memory cells 10 (sometimes referred to as selector-only memories (SOM)) composed of two-way threshold switching devices, and hereinafter, the "memory device" refers to the PRAM. Figure 1 FIG. shows a memory device 100 implemented as a PRAM. It should be noted that Figure 1 the PRAM configuration shown is provided only as an example and is not necessarily the actual PRAM configuration. Similarly, Figure 1 the exemplary PRAM configuration shown in does not represent or imply a limitation to the inventive concept.

[0026] The memory cell array 110 may include a plurality of memory cells 10, and the plurality of memory cells 10 can be programmed by applying a voltage to the plurality of memory cells 10. The plurality of memory cells 10 may be arranged in a region where a plurality of first signal lines and a plurality of second signal lines intersect each other. According to an embodiment, the plurality of first signal lines may be a plurality of bit lines BL, and the plurality of second signal lines may be a plurality of word lines WL. According to another embodiment, the plurality of first signal lines may be a plurality of word lines WL, and the plurality of second signal lines may be a plurality of bit lines BL. For ease of explanation, the first signal line is referred to as the bit line BL, and the terms "first signal line" and "bit line BL" may be used interchangeably. The second signal line is referred to as the word line WL, and the terms "second signal line" and "word line WL" may be used interchangeably.

[0027] As Figure 2 shown, the memory cell array 110 may include word lines WL1 and WL2 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction (X direction). The memory cell array 110 may include bit lines BL1, BL2, BL3, and BL4 extending in the second direction (Y direction) and spaced apart from each other in the first direction (X direction). The bit lines BL1, BL2, BL3, and BL4 may be spaced apart from the word lines WL1 and WL2 in a third direction (Z direction). Although Figure 2Some components included therein (e.g., BL and WL) are marked with numerical symbols, but it can be understood that when other corresponding components are not marked, the other corresponding components are also the same or similar to BL and WL to increase the visibility and clarity of the features described in the accompanying drawings below.

[0028] According to some embodiments, the memory cell array 110 may include a first array of memory cells 10 connected to bit lines BL1, BL2, BL3, and BL4 and word lines WL1 and WL2. However, this is only an example for helping understanding and is not intended to limit the inventive concept. The memory cell array 110 may include a second memory cell array located above the first array. When the memory cell array 110 includes multiple layers, the memory cell array 110 may be a three-dimensional memory array.

[0029] As Figure 3 shown, the memory cell 10 may be electrically connected to the bit line BL and the word line WL. The memory cell 10 may include a first electrode 11 in contact with the bit line BL, a second electrode 12 in contact with the word line WL, and a selector / storage material 13 between the first electrode 11 and the second electrode 12. The first electrode 11 and the second electrode 12 may each include aluminum (Al), molybdenum (Mo), tungsten (W), titanium (Ti), platinum (Pt), chromium (Cr), silicon (Si), their metal nitrides, or their metal oxides. The material of the first electrode 11 constituting the memory cell 10 and the material of the second electrode 12 constituting the memory cell 10 may be the same as or different from each other. Additionally, the first electrode 11 or the second electrode 12 may each have a stacked structure of different materials among the above materials.

[0030] According to some embodiments, the first electrode 11 and the second electrode 12 may each include W, Ti, Ta, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, TiCSiN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, TiO, or a combination thereof.

[0031] The selector / storage material 13 of the memory cell 10 may include a chalcogenide material having OTS characteristics. For example, the selector / storage material 13 may include an amorphous chalcogenide-based semiconductor material that includes at least one element selected from among antimony (Sb), bismuth (Bi), arsenic (As), germanium (Ge), silicon (Si), tin (Sn), carbon (C), etc., at least one element selected from among gallium (Ga), aluminum (Al), indium (In), etc., nitrogen (N), and tellurium (Te). The amorphous chalcogenide-based semiconductor material is an excellent conductive phase change material and can achieve OTS characteristics.

[0032] According to some embodiments, the selector / storage material 13 can be formed as a single-layer film or a multi-layer film, including materials selected from binary materials (such as GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, Ysb, CeSb, DySb, and NdSb), ternary materials (such as GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, and NdSbS), quaternary materials (such as GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, GeSbTeIn, Ga, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, materials among ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, and NdGeSbS), and quinary materials (such as InSbTeAsSe, GeScSbSeTe, GeScSbTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSbSeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn, and GeSbSeZnSn, etc.).

[0033] According to some embodiments, the selector / storage material 13 may include a material selected from among the materials constituting the selector / storage material 13 exemplified above, and at least one additional element selected from B, C, N, O, P, Cd, W, Ti, Hf, and Zr.

[0034] Figure 3 and Figure 4FIG. 40 is shown, which shows the current for the memory cell 10 according to the voltage applied between the first electrode 11 and the second electrode 12. In the memory cell 10, cell data can be programmed (or written) into the selector / storage material 13 or read from the selector / storage material 13 according to the amplitude and polarity of the voltage applied between the first electrode 11 and the second electrode 12. The x-axis of FIGS. 400 and 410 of FIG. 40 represents the programming voltage applied to the memory cell 10, and the y-axis of FIGS. 400 and 410 of FIG. 40 represents the current flowing through the memory cell 10. The x-axis of FIGS. 401, 402, 411, and 412 of FIG. 40 represents the threshold voltage of the memory cell 10, and the y-axis of FIGS. 401, 402, 411, and 412 of FIG. 40 represents the distribution of the threshold voltage.

[0035] FIG. 40 shows FIGS. 410 and 400, in which, at a specific voltage VTS of the positive (+) programming voltage, the cell current rapidly increases in a non-linear manner, and in FIG. 400, at a specific voltage VTR of the negative (-) programming voltage, the cell current rapidly increases in a non-linear manner.

[0036] FIG. 40 shows FIG. 411 representing the switching characteristics to the logic "1" state and FIG. 412 representing the switching characteristics to the logic "0" state. FIG. 40 shows FIG. 401 representing the switching characteristics to the logic "0" state and FIG. 402 representing the switching characteristics to the logic "1" state. Thus, the memory cell 10 can perform a bidirectional switching storage function, where Figure 3 the change in the voltage applied between the first electrode 11 and the second electrode 12 is represented as a current.

[0037] Hereinafter, for ease of explanation, the positive programming voltage is referred to as the voltage for writing logic "1" to the memory cell 10, and the negative programming voltage is referred to as the voltage for writing logic "0" to the memory cell 10. Conversely, according to another embodiment, the negative programming voltage may be referred to as the voltage for writing logic "1" to the memory cell 10, and the positive programming voltage may be referred to as the voltage for writing logic "0" to the memory cell 10.

[0038] Figure 5A and Figure 5B are diagrams showing the Figure 1 write operation and read operation of the memory cell 10 according to an exemplary embodiment.

[0039] Referring to Figure 1 , Figure 3 and Figure 5A, the first access circuit 120 and the second access circuit 130 can access the bit line BL and the word line WL to program the memory cell 10 connected to the bit line BL and the word line WL or read the cell data therefrom. The terms "program" and "write" can be used interchangeably to describe the operation of storing data in the memory cell. The first access circuit 120 and the second access circuit 130 can apply a positive programming voltage pulse 510 between the bit line BL and the word line WL to write a logic "1" in the memory cell 10. The positive programming voltage pulse 510 can be set such that the voltage applied to the bit line BL is greater than the voltage applied to the word line WL.

[0040] According to some embodiments, the positive programming voltage pulse 510 can include, for example, a positive voltage applied to the bit line BL and a negative voltage applied to the word line WL. For example, a positive voltage can be applied to the bit line BL, and a ground voltage (e.g., VSS) can be applied to the word line WL. For example, when positive voltages are applied to both the bit line BL and the word line WL, the voltage applied to the bit line BL can be greater than the voltage applied to the word line WL. For example, when negative voltages are applied to both the bit line BL and the word line WL, the voltage applied to the bit line BL can be greater than the voltage applied to the word line WL.

[0041] The first access circuit 120 and the second access circuit 130 can apply a positive read voltage pulse 520 and a negative read voltage pulse 530 to the memory cell 10 to determine the logic state of the cell data. When the read voltage pulse has the same polarity as the programming voltage pulse, the memory cell 10 can exhibit a lower threshold voltage. When the read voltage pulse has a different polarity from the programming voltage pulse, the memory cell 10 can exhibit a higher threshold voltage.

[0042] The positive read voltage pulse 520 after the positive programming voltage pulse 510 causes a first low threshold voltage VTL1. It can be understood that the memory cell 10 has Figure 4 the threshold voltage distribution of diagram 411 in diagram 40. The negative read voltage pulse 530 after the positive programming voltage pulse 510 causes a first high threshold voltage VTH1. It can be understood that the memory cell 10 has Figure 4 the threshold voltage distribution of diagram 412 in diagram 40.

[0043] Referring to Figure 1 、 Figure 3 and Figure 5B , the first access circuit 120 and the second access circuit 130 can apply a negative programming voltage pulse 500 between the bit line BL and the word line WL to write a logic "0" in the memory cell 10. The negative programming voltage pulse 500 can be set such that the voltage applied to the bit line BL is less than the voltage applied to the word line WL.

[0044] According to some embodiments, the negative programming voltage pulse 500 may include, for example, a negative voltage applied to the bit line BL and a positive voltage applied to the word line WL. For example, a ground voltage VSS may be applied to the bit line BL, and a positive voltage may be applied to the word line WL. For example, when positive voltages are applied to both the bit line BL and the word line WL, the voltage applied to the bit line BL may be less than the voltage applied to the word line WL. For example, when negative voltages are applied to both the bit line BL and the word line WL, the voltage applied to the bit line BL may be less than the voltage applied to the word line WL.

[0045] The positive read voltage pulse 520 after the negative programming voltage pulse 500 causes the second high threshold voltage VTH2. It can be understood that the memory cell 10 has Figure 4 the threshold voltage distribution of the diagram 402 in the diagram 40 of. The negative read voltage pulse 530 after the positive read voltage pulse 520 causes the second low threshold voltage VTL2. It can be understood that the memory cell 10 has Figure 4 the threshold voltage distribution of the diagram 401 in the diagram 40 of.

[0046] According to some embodiments, the programming voltage pulse and the read voltage pulse may be set to box-shaped pulses (e.g., rectangular-shaped pulses or square-shaped pulses) having the same duration. However, this is only an example for ease of understanding and is not intended to limit the inventive concept. The first access circuit 120 and the second access circuit 130 may provide programming voltage pulses having various shapes (e.g., triangular pulses (e.g., ramp pulses) and / or trapezoidal pulses) and intervals sufficient to write the desired data into the memory cell 10. According to an embodiment, the first access circuit 120 and the second access circuit 130 may provide programming voltage pulses and read voltage pulses having different shapes from each other.

[0047] Referring again to Figure 1 , the first access circuit 120 and the second access circuit 130 may be connected to the sensing circuit 140 to distinguish the logic states of the cell data that occur in response to the positive read voltage pulse 520 and the negative read voltage pulse 530 applied to the memory cell 10. The sensing circuit 140 may determine whether the threshold voltage of the memory cell 10 is lower or higher than a reference voltage, detect the threshold voltage of the memory cell 10, and determine the logic state of the memory cell 10.

[0048] The control circuit 150 may generate control signals for controlling the operation timing and / or the storage operation of the memory device 100. The control circuit 150 may provide control signals to the circuits of the memory device 100. The control circuit 150 may control the memory device 100 by using the control signals to perform operations of writing cell data into the memory cell 10 and reading cell data from the memory cell 10.

[0049] Figure 6This is a diagram for describing the read operation of the storage device 100 according to an exemplary embodiment. Figure 7 It shows the Figure 6 timing diagram of signals associated with the sense circuit 140 according to an exemplary embodiment. In the timing diagram shown below, the horizontal axis and the vertical axis represent time and voltage level respectively, and they do not have to be drawn to scale.

[0050] Referring to Figure 1 、 Figure 5A 、 Figure 5B and Figure 6 , the storage device 100 may include a first driving circuit 610 and a second driving circuit 620 connected to the first access circuit 120 and the second access circuit 130. The first driving circuit 610 and the second driving circuit 620 may be controlled by the control circuit 150 and support the operations of the first access circuit 120 and the second access circuit 130 to write unit data to / read unit data from the storage unit 10. Although Figure 6 it shows that the first driving circuit 610 and the second driving circuit 620 are separate components from the control circuit 150, the first driving circuit 610, the second driving circuit 620 and the control circuit 150 may be implemented as an inseparable component.

[0051] The first driving circuit 610 may selectively provide the first voltage V1 of the storage device 100 to the first access circuit 120 or the second access circuit 130 according to the control of the control circuit 150. The first voltage V1 may be generated by a voltage generation circuit included in the storage device 100 and is set to have a positive voltage level. The voltage generation circuit may generate various internal voltages for the driving circuits of the storage device 100. The first voltage V1 is shown as a single voltage, but actually may include multiple positive voltages. For example, the voltage level of the first voltage V1 may be slightly higher than the level of the power supply voltage (e.g., VDD) of the storage device 100, or may be equal to the voltage level of a high voltage (e.g., VPP), and the voltage level of the high voltage (e.g., VPP) is significantly higher than the level of the power supply voltage (e.g., VDD) of the storage device 100. The first driving circuit 610 may provide the first voltage V1 to the line of the positive voltage VP connected to the first access circuit 120 and the second access circuit 130. The first driving circuit 610 may operate as a power supply circuit related to the operations of the first access circuit 120 and the second access circuit 130.

[0052] The second driving circuit 620 may selectively provide a second voltage V2 of the memory device 100 to the first access circuit 120 or the second access circuit 130 according to the control of the control circuit 150. The second voltage V2 may be generated by a voltage generation circuit included in the memory device 100 and is set to have a negative voltage level. According to an embodiment, the second voltage V2 may be provided at various negative voltage levels. The second driving circuit 620 may provide the second voltage V2 to a line of a negative voltage VN connected to the first access circuit 120 and the second access circuit 130. The second driving circuit 620 may operate as a power sink circuit related to the operations of the first access circuit 120 and the second access circuit 130.

[0053] The first access circuit 120 may include a first switch 121, a first selector 122, a second selector 123, and a second switch 124. The first switch 121 and the first selector 122 are connected in series between a line of a positive voltage VP and a bit line BL, and when the first switch 121 is turned on, a first voltage V1 of the line of the positive voltage VP may be provided to the bit line BL. The second selector 123 and the second switch 124 are connected in series between the bit line BL and a line of a negative voltage VN, and when the second switch 124 is turned on, a second voltage V2 of the line of the negative voltage VN may be provided to the bit line BL. The first switch 121 and the second switch 124 may be controlled by the control circuit 150 to operate in an opposite manner. For example, when the first switch 121 is turned on, the second switch 124 may be turned off. Conversely, when the second switch 124 is turned on, the first switch 121 may be turned off.

[0054] The first selector 122 and the second selector 123 of the first access circuit 120 may select a bit line BL corresponding to a column address of the memory cell 10 from among a plurality of bit lines of the memory cell array 110. The column address is divided into a column address of a most significant bit (MSB) group signal and a column address of a least significant bit (LSB) group signal, and the bit line BL of the memory cell 10 may be selected by a bit line selection signal generated by decoding the column address of the MSB group signal and the column address of the LSB group signal.

[0055] The second access circuit 130 may include a first switch 131, a first selector 132, a second selector 133, and a second switch 134. The first switch 131 and the first selector 132 are serially connected between the line of the positive voltage VP and the word line WL, and when the first switch 131 is turned on, a first voltage V1 of the line of the positive voltage VP may be provided to the word line WL. The second selector 133 and the second switch 134 are serially connected between the word line WL and the line of the negative voltage VN, and when the second switch 134 is turned on, a second voltage V2 of the line of the negative voltage VN may be provided to the word line WL. The first switch 131 and the second switch 134 may be controlled by the control circuit 150 to operate in an opposite manner. For example, when the first switch 131 is turned on, the second switch 134 may be turned off. Conversely, when the second switch 134 is turned on, the first switch 131 may be turned off.

[0056] The first selector 132 and the second selector 133 of the second access circuit 130 may select the word line WL corresponding to the row address of the memory cell 10 from among multiple word lines of the memory cell array 110. The row address is divided into a row address of the MSB group signal and a row address of the LSB group signal, and the word line WL of the memory cell 10 may be selected by a word line selection signal generated by decoding the row address of the MSB group signal and the row address of the LSB group signal.

[0057] The connection node between the second selector 123 and the second switch 124 of the first access circuit 120 may be connected to the sense circuit 140 as a first sense node SDL_NEG. The connection node between the second selector 133 and the second switch 134 of the second access circuit 130 may be connected to the sense circuit 140 as a second sense node SDL_POS. The sense circuit 140 may include: a first comparator 141 that compares the voltage level of a first reference voltage VREF_NEG with the voltage level of the first sense node SDL_NEG; and a second comparator 142 that compares the voltage level of a second reference voltage VREF_POS with the voltage level of the second sense node SDL_POS.

[0058] According to some embodiments, the memory device 100 may program the memory cell 10 to a logic "1" by using a first path 601, which includes a first driving circuit 610, a first switch 121 and a first selector 122 of the first access circuit 120, a bit line BL, the memory cell 10, the word line WL, a second selector 133 and a second switch 134 of the second access circuit 130, and a second driving circuit 620. This means that the positive programming voltage pulse 510 between the bit line BL and the word line WL described with reference to Figure 5A is applied through the first path 601.

[0059] According to some embodiments, the memory device 100 may program the memory cell 10 to a logic "0" by using a second path 600, which includes a first drive circuit 610, a first switch 131 and a first selector 132 of the second access circuit 130, a word line WL, a memory cell 10, a bit line BL, a second selector 123 and a second switch 124 of the first access circuit 120, and a second drive circuit 620. This means that the negative programming voltage pulse 500 between the bit line BL and the word line WL described with reference to Figure 5B is applied through the second path 600.

[0060] According to some embodiments, to read the cell data of the memory cell 10, the memory device 100 may apply a positive read voltage pulse 520 between the bit line BL and the word line WL as described above with reference to Figure 5A and Figure 5B by using a first path 601. The memory device 100 may apply a negative read voltage pulse 530 between the bit line BL and the word line WL as described with reference to Figure 5A and Figure 5B by using the second path 600.

[0061] With reference to Figure 5A , Figure 6 and Figure 7 , the sense circuit 140 may determine the logic state of the memory cell 10 programmed according to the programming voltage pulse by using the read voltage pulse. Assume that the memory cell 10 is programmed to a logic "1" state by the positive programming voltage pulse 510. It can be seen that through the positive read voltage pulse 520 after the positive programming voltage pulse 510, the voltage level 712 of the second sense node SDL_POS is higher than the second reference voltage VREF_POS, and through the negative read voltage pulse 530 after the positive programming voltage pulse 510, the voltage level 701 of the first sense node SDL_NEG is lower than the first reference voltage VREF_NEG.

[0062] During a pre-charge period tPCH from time point T0 to time point T1, the sense circuit 140 may pre-charge the first sense node SDL_NEG and the second sense node SDL_POS. Assume that the voltage level 700 of the first sense node SDL_NEG is higher than the voltage level 710 of the second sense node SDL_POS.

[0063] During a development period tDEV from time point T1 to time point T2, the voltage level 700 of the first sense node SDL_NEG develops into voltage levels 701 and 702 according to the logic state of the memory cell 10 and the read voltage pulse, and the voltage level 710 of the second sense node SDL_POS also develops into voltage levels 711 and 712 according to the logic state of the memory cell 10 and the read voltage pulse.

[0064] During the sensing period tSAOUT from time point T2 to time point T3, the sensing circuit 140 may output the result of comparing the voltage levels 701 and 702 of the first sensing node SDL_NEG with the voltage level of the first reference voltage VREF_NEG, and output the result of comparing the voltage levels 711 and 712 of the second sensing node SDL_POS with the voltage level of the second reference voltage VREF_POS.

[0065] During the pre-charge period tPCH, the first sensing node SDL_NEG may be pre-charged to the voltage level of the first pre-charge voltage VSDL_NEG_PCH, and the second sensing node SDL_POS may be pre-charged to the voltage level of the second pre-charge voltage VSDL_POS_PCH. For example, the voltage levels of the first pre-charge voltage VSDL_NEG_PCH and the second pre-charge voltage VSDL_POS_PCH may be negative voltages. When the load on the bit line BL connected to the memory cell 10 in the memory cell array 110 is different from the load on the word line WL connected to the memory cell 10 in the memory cell array 110, a voltage difference ΔV may occur between the first pre-charge voltage VSDL_NEG_PCH and the second pre-charge voltage VSDL_POS_PCH. The line load may include line resistance and / or line capacitance caused by the length and / or width of the line, the number of memory cells connected to the line, etc. In this embodiment, the voltage difference ΔV that occurs when the load on the bit line BL is greater than the load on the word line (WL) is described. According to another embodiment, even when the load on the word line WL is greater than the load on the bit line BL, a pre-charge voltage difference may occur between the first sensing node SDL_NEG and the second sensing node SDL_POS.

[0066] The voltage difference ΔV between the first sensing node SDL_NEG and the second sensing node SDL_POS can be understood as the offset voltage between the first sensing node SDL_NEG and the second sensing node SDL_POS according to the load on the bit line BL. Considering the offset voltage, the sensing circuit 140 can be designed such that a voltage difference ΔV equivalent to the offset voltage appears between the first reference voltage VREF_NEG and the second reference voltage VREF_POS that are respectively compared with the voltage levels of the first sensing node SDL_NEG and the second sensing node SDL_POS. In other words, in order to read the memory cell 10, considering the offset voltage between the first sensing node SDL_NEG and the second sensing node SDL_POS, two reference voltages VREF_NEG and VREF_POS are required, and two comparison circuits 141 and 142 that are respectively connected to each of the reference voltages VREF_NEG and VREF_POS are required. In other words, the sensing circuit 140 has asymmetry, where the comparison circuits 141 and 142 sense the memory cell 10 based on two different reference voltages VREF_NEG and VREF_POS respectively. The asymmetry of the sensing circuit 140 may cause bidirectional sensing mismatch of the memory cell 10 and reduce the sensing margin. Therefore, the sensing margin of the sensing circuit 140 may be reduced, thereby degrading the accuracy and performance of the memory device 100.

[0067] Before sensing the memory cell 10, when the offset voltage difference between the first sensing node SDL_NEG and the second sensing node SDL_POS can be compensated by the first sensing node SDL_NEG and the second sensing node SDL_POS together, the asymmetry of the sensing circuit 140 can be eliminated. Similarly, when the first sensing node SDL_NEG and the second sensing node SDL_POS are combined with each other through the sensing circuit 140, and the offset voltage difference is eliminated by the combined first sensing node SDL_NEG and second sensing node SDL_POS, the voltage levels of the combined first sensing node SDL_NEG and second sensing node SDL_POS can be sensed based on a single reference voltage (for example, Figure 8 VREF). This means that since the sensing circuit 140 senses the memory cell 10 by using one comparison circuit, the sensing accuracy can be improved, and since the number of comparison circuits is reduced, the area occupied by the sensing circuit 140 can be reduced. Therefore, the chip size of the memory device 100 can be reduced and the sensing accuracy of the sensing circuit 140 can be improved, and thus the operating performance of the memory device 100 can be improved.

[0068] The configuration and operation of the sensing circuit 140 will be described in detail with reference to various embodiments below.

[0069] Figure 8FIG. 0 is a diagram showing a memory device 100a including a sensing circuit 140a according to an exemplary embodiment. Figure 9 FIG. 1 shows the Figure 8 timing diagram of signals associated with the sensing circuit 140a according to an exemplary embodiment. In Figure 8 FIG. 1, the memory cell array 110, the first access circuit 120, the second access circuit 130, the first drive circuit 610, and the second drive circuit 620 of the memory device 100a are the same as those described with reference to Figure 6 FIG. 1, and thus the description same as that given above with reference to Figure 6 FIG. 1 is omitted. Hereinafter, subscripts (e.g., "a" in 100a and "a" in 140a) attached to the same reference numerals in different drawings are used to distinguish multiple circuits performing similar or identical functions.

[0070] Referring to Figure 1 FIG. 1 Figure 8 and

[0071] FIG. 2, the memory device 100a may include a sensing circuit 140a connected to a first sensing node SDL_NEG and a second sensing node SDL_POS. The sensing circuit 140a may include: a switch 841 connected between the first sensing node SDL_NEG and the second sensing node SDL_POS; a capacitor 842 connected between the second sensing node SDL_POS and a sensing input node SENSE_IN; a pre-charger 843 connected between a line of a pre-charge voltage VPCH and the sensing input node SENSE_IN; and a comparison circuit 844 that compares the voltage level of the sensing input node SENSE_IN with the voltage level of a reference voltage VREF. Figure 9 In the sensing circuit 140a, when the switch 841 is turned on, the first sensing node SDL_NEG and the second sensing node SDL_POS are combined with each other, and the voltage of the combined first sensing node SDL_NEG and second sensing node SDL_POS may be coupled and sent to the sensing input node SENSE_IN through the capacitor 842. For example, the first sensing node SDL_NEG and the second sensing node SDL_POS are electrically connected to each other through the turned-on switch 841. As Figure 7(ΔV). When the switch 841 is turned on, the voltage level of the second sense node SDL_POS can increase by half of the offset voltage difference by combining the first sense node SDL_NEG and the second sense node SDL_POS, and the voltage level of the first sense node SDL_NEG can decrease by half of the offset voltage difference. Therefore, the voltage level 900 of the sense input node SENSE_IN coupled through the capacitor 842 can be represented as a graph of the voltage level 920 of the first sense node SDL_NEG and a graph of the voltage level 910 of the second sense node SDL_POS.

[0072] According to some embodiments, the switch 841 can be implemented as a transmission gate responsive to the first read signal NEGRD and the second read signal nNEGRD. The first read signal NEGRD and the second read signal nNEGRD can have opposite logic levels to each other, the first read signal NEGRD can be connected to the PMOS transistor of the transmission gate, and the second read signal nNEGRD can be connected to the NMOS transistor of the transmission gate.

[0073] The pre-charger 843 can pre-charge the sense input node SENSE_IN to the voltage level of the pre-charge voltage VPCH based on the pre-charge control signal EN_PCH. The pre-charger 843 can be implemented as a transistor that turns on in response to the pre-charge control signal EN_PCH. The pre-charge control signal EN_PCH can be provided by the control circuit 150. The control circuit 150 can turn on the switch 841 in response to the first read signal NEGRD and the second read signal nNEGRD, and then activate the pre-charge control signal EN_PCH.

[0074] The comparison circuit 844 can compare the voltage level of the sense input node SENSE_IN with the voltage level of the reference voltage VREF and output a signal indicating the logic state of the memory cell 10. The voltage level of the reference voltage VREF can be set to an intermediate level between the voltage level of the first reference voltage VREF_NEG and the voltage level of the second reference voltage VREF_POS. When the voltage level of the sense input node SENSE_IN is higher than the voltage level of the reference voltage VREF, the logic state of the memory cell 10 can be determined to be a logic "1" state with a lower threshold voltage. When the voltage level of the sense input node SENSE_IN is lower than the voltage level of the reference voltage VREF, the logic state of the memory cell 10 can be determined to be a logic "0" state with a higher threshold voltage.

[0075] Refer to Figure 9, during a precharge period tPCH from time point T0 to time point T1, the sensing circuit 140a may precharge the sense input node SENSE_IN to the voltage level of a precharge voltage VPCH. During a development period tDEV from time point T1 to time point T2, the voltage level 900 of the sense input node SENSE_IN may develop into voltage levels 910 and 920 according to the logic state of the memory cell 10. It can be seen that the illustration of the voltage level 910 of the sense input node SENSE_IN has an intermediate level between the voltage level 702 of the first sense node SDL_NEG and the voltage level 712 of the second sense node SDL_POS described with reference to Figure 7 and the illustration of the voltage level 920 of the sense input node SENSE_IN has an intermediate level between the voltage level 701 of the first sense node SDL_NEG and the voltage level 711 of the second sense node SDL_POS described with reference to Figure 7 . During a sensing period tSAOUT from time point T2 to time point T3, the sensing circuit 140a may output a result of comparing the voltage levels 910 and 920 of the sense input node SENSE_IN with the voltage level of a reference voltage VREF.

[0076] Figure 10 and Figure 11 are diagrams showing a memory device including a sensing circuit according to an example embodiment. In Figure 10 and Figure 11 , the memory cell arrays 110, the first access circuits 120, the second access circuits 130, the first drive circuits 610, and the second drive circuits 620 of the memory devices 100b and 100c are the same as those described with reference to Figure 6 , and thus descriptions identical to those given above with reference to Figure 6 are omitted.

[0077] Referring to Figure 10, the memory device 100b may include a sensing circuit 140b connected to a first sensing node SDL_NEG and a second sensing node SDL_POS. The sensing circuit 140b may include: a capacitor 1041 connected between the first sensing node SDL_NEG and the second sensing node SDL_POS; a pre-charger 1042 connected between a line of a pre-charge voltage VPCH and the second sensing node SDL_POS; and a comparison circuit 1043 that compares the voltage level of the second sensing node SDL_POS with the voltage level of a reference voltage VREF. The voltage of the first sensing node SDL_NEG may be coupled and sent to the second sensing node SDL_POS through the capacitor 1041. The pre-charger 1042 may pre-charge the second sensing node SDL_POS to the voltage level of the pre-charge voltage VPCH in response to a pre-charge control signal EN_PCH provided from the control circuit 150. The comparison circuit 1043 may compare the voltage level of the second sensing node SDL_POS with the voltage level of the reference voltage VREF and output a signal indicating the logic state of the memory cell 10.

[0078] Referring to Figure 11 , the memory device 100c may include a sensing circuit 140c connected to a first sensing node SDL_NEG and a second sensing node SDL_POS. The sensing circuit 140c may include: a capacitor 1141 connected between the first sensing node SDL_NEG and the second sensing node SDL_POS; a pre-charger 1142 connected between a line of the pre-charge voltage VPCH and the first sensing node SDL_NEG; and a comparison circuit 1143 that compares the voltage level of the first sensing node SDL_NEG with the voltage level of the reference voltage VREF. The voltage of the second sensing node SDL_POS may be coupled and sent to the first sensing node SDL_NEG through the capacitor 1141. The pre-charger 1142 may pre-charge the first sensing node SDL_NEG to the voltage level of the pre-charge voltage VPCH in response to a pre-charge control signal EN_PCH provided from the control circuit 150. The comparison circuit 1143 may compare the voltage level of the first sensing node SDL_NEG with the voltage level of the reference voltage VREF and output a signal indicating the logic state of the memory cell 10.

[0079] Figure 12 is a diagram showing a memory device including a sensing circuit according to an exemplary embodiment. In Figure 12 , the memory cell array 110, the first access circuit 120, the second access circuit 130, the first drive circuit 610, and the second drive circuit 620 of the memory device 100d are the same as those described with reference to Figure 6 and thus descriptions identical to those given above with reference to Figure 6 are omitted.

[0080] Referring to Figure 12 Figure 12 , the memory device 100d may include a sensing circuit 140d connected to a first sensing node SDL_NEG and a second sensing node SDL_POS. The sensing circuit 140d includes a first capacitor 1241 and a second capacitor 1242 connected in series between the first sensing node SDL_NEG and the second sensing node SDL_POS, and a connection node between the first capacitor 1241 and the second capacitor 1242 becomes a sensing input node SENSE_IN. The sensing circuit 140d may further include: a pre-charger 1243 connected between a line of a pre-charge voltage VPCH and the sensing input node SENSE_IN; and a comparison circuit 1244 that compares a voltage level of the sensing input node SENSE_IN with a voltage level of a reference voltage VREF.

[0081] The voltage of the first sensing node SDL_NEG may be coupled and sent to the sensing input node SENSE_IN through the first capacitor 1241, and the voltage of the second sensing node SDL_POS may be coupled and sent to the sensing input node SENSE_IN through the second capacitor 1242. The pre-charger 1243 may pre-charge the sensing input node SENSE_IN to a voltage level of the pre-charge voltage VPCH in response to a pre-charge control signal EN_PCH provided from the control circuit 150. The comparison circuit 1244 may compare the voltage level of the sensing input node SENSE_IN with the voltage level of the reference voltage VREF and output a signal indicating a logic state of the memory cell 10.

[0082] Figure 13 is a block diagram of a system 2000 of an electronic device including a memory device according to an exemplary embodiment.

[0083] Referring to Figure 13 Figure 13 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, non-volatile memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented as a laptop, a mobile phone, a smartphone, a tablet, a wearable device, a healthcare device, or an Internet of Things (IoT) device. Similarly, the system 2000 may be implemented as a server or a PC.

[0084] The camera 2100 can capture still images or videos according to the user's control, and can store the captured image / video data or send the captured image / video data to the display 2200. The audio processor 2300 can process the audio data or network content included in the non-volatile memories 2600a and 2600b. The modem 2400 can send a modulation signal for wired / wireless data transmission / reception to the receiver, and the receiver can demodulate the modulation signal to recover the original signal. The I / O devices 2700a and 2700b can include devices providing digital input functions and / or digital output functions, such as universal serial bus (USB), storage devices, digital cameras, secure digital (SD) cards, digital versatile discs (DVDs), network adapters, touchscreens, etc.

[0085] The AP 2800 can control the overall operation of the system 2000. The AP 2800 can include a controller module 2810, an accelerator module or accelerator chip 2820, and an interface module 2830. The AP 2800 can control the display 2200 such that a part of the content stored in the non-volatile memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 can perform a control operation corresponding to the user input. The AP 2800 can include an accelerator module which is a circuit dedicated to computing artificial intelligence (AI) data, or can include an accelerator chip 2820 separated from the AP 2800. The DRAM 2500b can be additionally provided in the accelerator module or accelerator chip 2820. The accelerator module is a functional module that specifically executes a specific function of the AP 2800, and can include a GPU (a functional module dedicated to processing graphic data), a neural processing unit (NPU) (a module dedicated to AI computing and inference), and a data processing unit (DPU) (a module dedicated to data transmission).

[0086] The system 2000 may include multiple DRAMs 2500a and 2500b. The AP 2800 may set the DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to control the DRAMs 2500a and 2500b through command and mode register (MRS) settings compliant with Joint Electron Device Engineering Council (JEDEC) standards, or to use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a through an interface compliant with JEDEC standards such as LPDDR4, LPDDR5, etc., and the accelerator module or accelerator chip 2820 may set and use a new DRAM interface protocol to control the DRAM 2500b for an accelerator with a larger bandwidth than the DRAM 2500a.

[0087] Although Figure 13 only DRAMs 2500a and 2500b are shown, the inventive concept is not limited thereto. Any memory such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM may be used as long as the bandwidth, response speed, and voltage conditions of the AP 2800 or the accelerator chip 2820 are satisfied. The DRAMs 2500a and 2500b have relatively small latency and bandwidth compared to the I / O devices 2700a and 2700b or the non-volatile memories 2600a and 2600b. The DRAMs 2500a and 2500b are initialized when the system 2000 is powered on and the OS and application data are loaded, so the DRAMs 2500a and 2500b may be used as a temporary storage device for the OS and application data, or may be used as an execution space for various software codes.

[0088] In the DRAMs 2500a and 2500b, four arithmetic operations (i.e., addition, subtraction, multiplication, and division), vector calculations, address calculations, or fast Fourier transform (FFT) calculations may be performed. In addition, in the DRAMs 2500a and 2500b, functions for performing operations for inference may be performed. Here, an artificial neural network may be used for inference with a deep learning algorithm. The deep learning algorithm may include a training operation for learning a model through various data and an inference operation for identifying data using the trained model. According to an embodiment, an image captured by the camera 2100 by a user is signal-processed and stored in the DRAM 2500b, and the accelerator module or accelerator chip 2820 may perform AI data calculations for identifying data using the data stored in the DRAM 2500b and a function for inference.

[0089] System 2000 may include multiple storage devices or non-volatile memories 2600a and 2600b, which have a larger capacity than DRAMs 2500a and 2500b. The accelerator module or accelerator chip 2820 may perform training operations and AI data calculations using the non-volatile memories 2600a and 2600b. According to an embodiment, each of the non-volatile memories 2600a and 2600b may include a storage controller 2610 and a storage device 2620 (e.g., PRAM), and may more efficiently perform the training operations and inference AI data calculations performed by the AP 2800 and / or the accelerator chip 2820 by using the arithmetic unit included in the memory controller 2610. For example, the storage device 2620 may be a resistive storage device (RRAM) or an MRAM device. The non-volatile memories 2600a and 2600b may store images captured by the camera 2100 or data sent through the data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0090] In system 2000, the non-volatile memories 2600a and 2600b may include the storage devices described above with reference to Figures 1 to 4 , Figure 5A , Figure 5B , and Figures 6 to 12 . The storage device may program a material film in an amorphous state (e.g., logic "0") or a crystalline state (e.g., logic "1") between a first electrode and a second electrode of a storage cell by using a positive programming voltage pulse or a negative programming voltage pulse provided by an access circuit. The access circuit may provide a positive read voltage pulse and a negative read voltage pulse between the first electrode and the second electrode, and the sensing circuit may determine the logic state of the selected storage cell based on the electrical responses of a first sensing node and a second sensing node connected to the selected storage cell with respect to the positive read voltage pulse and the negative read voltage pulse. The sensing circuit may include: a switch that interconnects the first sensing node and the second sensing node; a capacitor connected to a sensing input node; a pre-charger; and a comparison circuit. The sensing circuit may include: a capacitor connected between the first sensing node and the second sensing node; a pre-charger connected to the first sensing node on one side of the capacitor; and a comparison circuit. The sensing circuit may include: a capacitor connected between the first sensing node and the second sensing node; a pre-charger connected to the second sensing node on one side of the capacitor; and a comparison circuit. The sensing circuit may include: a first capacitor connected between the first sensing node and the sensing input node; a second capacitor connected between the second sensing node and the sensing input node; a capacitor connected to the sensing input node; a pre-charger; and a comparison circuit. Therefore, the storage device may improve the accuracy of the read operation and reduce the chip size.

[0091] Although the concepts of the present invention have been specifically shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A storage device, comprising: A memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film opposite to the first side, wherein a logic state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state; An access circuit configured to apply a first voltage to a first electrode of a selected memory cell among the plurality of memory cells and apply a second voltage to a second electrode of the selected memory cell; and A sensing circuit configured to determine a logic state of the selected memory cell based on electrical responses of a first sensing node and a second sensing node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sensing circuit includes: A switch configured to electrically connect the first sensing node to the second sensing node based on a read signal; A capacitor connected between the second sensing node and a sensing input node; A pre-charger configured to pre-charge the sensing input node with a pre-charge voltage based on a pre-charge control signal; and A comparison circuit configured to compare a voltage level of the sensing input node with a voltage level of a reference voltage and output a signal indicating the logic state of the selected memory cell.

2. The storage device according to claim 1, wherein, The access circuit is further configured to: program the selected memory cell to logic "1" by using a positive programming voltage pulse that applies the first voltage having a first amplitude to the first electrode and applies the second voltage having a second amplitude less than the first amplitude to the second electrode.

3. The memory device according to claim 2, wherein, The access circuit is further configured to provide: A positive read voltage pulse for applying the first voltage having a third amplitude to the first electrode and applying the second voltage having a fourth amplitude less than the third amplitude to the second electrode, and A negative read voltage pulse for applying the first voltage having a fifth amplitude to the first electrode and applying the second voltage having a sixth amplitude greater than the fifth amplitude to the second electrode, and wherein the first sensing node indicates a lower threshold voltage due to the positive read voltage pulse and the second sensing node indicates a higher threshold voltage due to the negative read voltage pulse.

4. The storage device according to claim 1, wherein, The access circuit is further configured to: program the selected memory cell to logic "0" by using a negative programming voltage pulse that applies the first voltage having a first amplitude to the first electrode and applies the second voltage having a second amplitude greater than the first amplitude to the second electrode.

5. The storage device according to claim 4, wherein, The access circuit is further configured to provide: A positive read voltage pulse for applying the first voltage having a third amplitude to the first electrode and applying the second voltage having a fourth amplitude less than the third amplitude to the second electrode, and A negative read voltage pulse for applying the first voltage having a fifth amplitude to the first electrode and applying the second voltage having a sixth amplitude greater than the fifth amplitude to the second electrode, and wherein the first sense node indicates a higher threshold voltage due to the positive read voltage pulse and the second sense node indicates a lower threshold voltage due to the negative read voltage pulse.

6. The memory device according to claim 1, wherein, The plurality of memory cells includes phase change memory cells.

7. A memory device, comprising: A memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein the logical state of the material film is programmed based on whether the material film is in a crystalline state or a non-crystalline state; An access circuit configured to apply a first voltage to the first electrode of a selected memory cell among the plurality of memory cells and apply a second voltage to the second electrode of the selected memory cell; and A sense circuit configured to determine the logical state of the selected memory cell based on electrical responses of a first sense node and a second sense node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sense circuit includes: A capacitor connected between the first sense node and the second sense node; A pre-charger configured to pre-charge a first end of the capacitor to a voltage level of a pre-charge voltage; and A comparison circuit configured to compare a voltage level of the first end of the capacitor with a voltage level of a reference voltage and output a signal indicating the logical state of the selected memory cell.

8. The memory device according to claim 7, wherein, A second end of the capacitor is connected to the first sense node.

9. The memory device according to claim 7, wherein A second end of the capacitor is connected to the second sense node.

10. The memory device according to claim 7, wherein, The access circuit is further configured to: program the selected memory cell to a logical "1" by using a positive programming voltage pulse that applies the first voltage having a first amplitude to the first electrode and applies the second voltage having a second amplitude less than the first amplitude to the second electrode.

11. The memory device according to claim 10, wherein, The access circuit is further configured to provide: A positive read voltage pulse for applying the first voltage having a third amplitude to the first electrode and applying the second voltage having a fourth amplitude less than the third amplitude to the second electrode, and A negative read voltage pulse for applying the first voltage having a fifth amplitude to the first electrode and applying the second voltage having a sixth amplitude greater than the fifth amplitude to the second electrode, and wherein the first sense node indicates a lower threshold voltage due to the positive read voltage pulse and the second sense node indicates a higher threshold voltage due to the negative read voltage pulse.

12. The memory device according to claim 7, wherein, The access circuit is further configured to program the selected memory cell to a logic "0" by using a negative programming voltage pulse that applies the first voltage having a first magnitude to the first electrode and applies the second voltage having a second magnitude greater than the first magnitude to the second electrode.

13. The memory device according to claim 12, wherein, The access circuit is further configured to provide: a positive read voltage pulse for applying the first voltage having a third magnitude to the first electrode and applying the second voltage having a fourth magnitude less than the third magnitude to the second electrode, and a negative read voltage pulse for applying the first voltage having a fifth magnitude to the first electrode and applying the second voltage having a sixth magnitude greater than the fifth magnitude to the second electrode, and wherein the first sense node indicates a higher threshold voltage due to the positive read voltage pulse and the second sense node indicates a lower threshold voltage due to the negative read voltage pulse.

14. The storage device according to claim 7, wherein, The plurality of memory cells includes phase change memory cells.

15. A memory device, comprising: an array of memory cells including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein the logic state of the material film is programmed based on whether the material film is in a crystalline state or a non-crystalline state; an access circuit configured to apply a first voltage to a first electrode of a selected memory cell among the plurality of memory cells and apply a second voltage to a second electrode of the selected memory cell; and a sense circuit configured to determine a logic state of the selected memory cell based on electrical responses of a first sense node and a second sense node connected to the selected memory cell with respect to the first voltage and the second voltage, wherein the sense circuit includes: a first capacitor connected between the first sense node and a sense input node; a second capacitor connected between the second sense node and the sense input node; a pre-charger configured to pre-charge the sense input node with a pre-charge voltage based on a pre-charge control signal; and a comparison circuit configured to compare a voltage level of the sense input node with a voltage level of a reference voltage and output a signal indicating the logic state of the selected memory cell.

16. The memory device according to claim 15, wherein, The access circuit is further configured to program the selected memory cell to a logic "1" by using a positive programming voltage pulse that applies the first voltage having a first magnitude to the first electrode and applies the second voltage having a second magnitude less than the first magnitude to the second electrode.

17. The memory device according to claim 16, wherein, The access circuit is further configured to provide: a positive read voltage pulse for applying the first voltage having a third magnitude to the first electrode and applying the second voltage having a fourth magnitude less than the third magnitude to the second electrode, and A negative read voltage pulse for applying the first voltage having a fifth amplitude to the first electrode and applying the second voltage having a sixth amplitude greater than the fifth amplitude to the second electrode, and wherein the first sense node indicates a lower threshold voltage due to the positive read voltage pulse and the second sense node indicates a higher threshold voltage due to the negative read voltage pulse.

18. The memory device according to claim 15, wherein, The access circuit is further configured to program the selected memory cell to a logic "0" by using a negative programming voltage pulse that applies the first voltage having a first amplitude to the first electrode and applies the second voltage having a second amplitude greater than the first amplitude to the second electrode.

19. The storage device according to claim 18, wherein, The access circuit is further configured to provide: A positive read voltage pulse for applying the first voltage having a third amplitude to the first electrode and applying the second voltage having a fourth amplitude less than the third amplitude to the second electrode, and A negative read voltage pulse for applying the first voltage having a fifth amplitude to the first electrode and applying the second voltage having a sixth amplitude greater than the fifth amplitude to the second electrode, and wherein the first sense node indicates a higher threshold voltage due to the positive read voltage pulse and the second sense node indicates a lower threshold voltage due to the negative read voltage pulse.

20. The memory device according to claim 15, wherein, The plurality of memory cells includes phase change memory cells.

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